From 198f088c8f1a8f5ba2797fd3af8ce6302885eca8 Mon Sep 17 00:00:00 2001 From: Paulo Matos Date: Mon, 15 Apr 2024 14:44:06 +0200 Subject: [PATCH] Redesign x87 optimization framework --- FEXCore/Source/CMakeLists.txt | 1 + .../Core/Interpreter/Fallbacks/F80Fallbacks.h | 22 +- .../Fallbacks/InterpreterFallbacks.cpp | 8 +- .../Interface/Core/OpcodeDispatcher.cpp | 97 +- .../Source/Interface/Core/OpcodeDispatcher.h | 32 +- .../Core/OpcodeDispatcher/AVX_128.cpp | 4 +- .../Core/OpcodeDispatcher/Vector.cpp | 8 +- .../Interface/Core/OpcodeDispatcher/X87.cpp | 1402 +- .../Core/OpcodeDispatcher/X87F64.cpp | 710 +- FEXCore/Source/Interface/IR/IR.json | 312 +- FEXCore/Source/Interface/IR/PassManager.cpp | 1 + FEXCore/Source/Interface/IR/Passes.h | 1 + .../IR/Passes/x87StackOptimizationPass.cpp | 1892 + Source/Common/Config.cpp | 2 + docs/SourceOutline.md | 3 +- unittests/ASM/Known_Failures_host | 1 + unittests/ASM/X87/FXAM_Push.asm | 2 +- unittests/ASM/X87/FXAM_Push_2.asm | 2 +- unittests/ASM/X87/FXAM_Push_Simple.asm | 40 + unittests/ASM/X87/FXAM_Push_Simple_2.asm | 51 + unittests/ASM/X87/FXAM_Simple.asm | 49 + unittests/ASM/X87/Memcopy.asm | 21 + unittests/ASM/x87_stack.asm | 26 + unittests/FEXLinuxTests/Known_Failures_Host | 2 + .../FlagM/HotBlocks_32Bit.json | 823 +- .../FlagM/SecondaryGroup.json | 2 +- .../FlagM/x87-HalfLife.json | 6857 ++ .../FlagM/x87-Oblivion.json | 82038 +++++++++++++ .../FlagM/x87-Psychonauts.json | 98715 ++++++++++++++++ unittests/InstructionCountCI/FlagM/x87.json | 5447 +- .../InstructionCountCI/FlagM/x87_f64.json | 3830 +- unittests/InstructionCountCI/Primary.json | 8 + .../InstructionCountCI/SecondaryGroup.json | 2 +- unittests/InstructionCountCI/x87.json | 5445 +- unittests/InstructionCountCI/x87_f64.json | 3904 +- 35 files changed, 200297 insertions(+), 11463 deletions(-) create mode 100644 FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp create mode 100644 unittests/ASM/Known_Failures_host create mode 100644 unittests/ASM/X87/FXAM_Push_Simple.asm create mode 100644 unittests/ASM/X87/FXAM_Push_Simple_2.asm create mode 100644 unittests/ASM/X87/FXAM_Simple.asm create mode 100644 unittests/ASM/X87/Memcopy.asm create mode 100644 unittests/ASM/x87_stack.asm create mode 100644 unittests/InstructionCountCI/FlagM/x87-HalfLife.json create mode 100644 unittests/InstructionCountCI/FlagM/x87-Oblivion.json create mode 100644 unittests/InstructionCountCI/FlagM/x87-Psychonauts.json diff --git a/FEXCore/Source/CMakeLists.txt b/FEXCore/Source/CMakeLists.txt index d4f267b833..dace924f1f 100644 --- a/FEXCore/Source/CMakeLists.txt +++ b/FEXCore/Source/CMakeLists.txt @@ -145,6 +145,7 @@ set (SRCS Interface/IR/Passes/RedundantFlagCalculationElimination.cpp Interface/IR/Passes/DeadStoreElimination.cpp Interface/IR/Passes/RegisterAllocationPass.cpp + Interface/IR/Passes/x87StackOptimizationPass.cpp Utils/Telemetry.cpp Utils/Threads.cpp Utils/Profiler.cpp diff --git a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h index 9f03d2305e..f7f589c689 100644 --- a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h +++ b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h @@ -7,20 +7,22 @@ namespace FEXCore::CPU { FEXCORE_PRESERVE_ALL_ATTR static void LoadDeferredFCW(uint16_t NewFCW) { - auto PC = (NewFCW >> 8) & 3; + // This function is in a hot path in fex since many of the x87 fallback functions + // call it. + auto PC = NewFCW & 0x0300; switch (PC) { - case 0: extF80_roundingPrecision = 32; break; - case 2: extF80_roundingPrecision = 64; break; - case 3: extF80_roundingPrecision = 80; break; - case 1: LOGMAN_MSG_A_FMT("Invalid x87 precision mode, {}", PC); + case 0x0000: extF80_roundingPrecision = 32; break; + case 0x0200: extF80_roundingPrecision = 64; break; + case 0x0300: extF80_roundingPrecision = 80; break; + default: LOGMAN_MSG_A_FMT("Invalid x87 precision mode, {}", PC); } - auto RC = (NewFCW >> 10) & 3; + auto RC = NewFCW & 0x0C00; switch (RC) { - case 0: softfloat_roundingMode = softfloat_round_near_even; break; - case 1: softfloat_roundingMode = softfloat_round_min; break; - case 2: softfloat_roundingMode = softfloat_round_max; break; - case 3: softfloat_roundingMode = softfloat_round_minMag; break; + case 0x0000: softfloat_roundingMode = softfloat_round_near_even; break; + case 0x0400: softfloat_roundingMode = softfloat_round_min; break; + case 0x0800: softfloat_roundingMode = softfloat_round_max; break; + case 0x0C00: softfloat_roundingMode = softfloat_round_minMag; break; } } diff --git a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp index 06391bf6de..652cc4c347 100644 --- a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp +++ b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp @@ -89,7 +89,7 @@ bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::I uint8_t OpSize = IROp->Size; switch (IROp->Op) { case IR::OP_F80CVTTO: { - auto Op = IROp->C(); + const auto* Op = IROp->C(); switch (Op->SrcSize) { case 4: { @@ -119,7 +119,7 @@ bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::I break; } case IR::OP_F80CVTINT: { - auto Op = IROp->C(); + const auto* Op = IROp->C(); switch (OpSize) { case 2: { @@ -154,7 +154,7 @@ bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::I break; } case IR::OP_F80CMP: { - auto Op = IROp->C(); + const auto* Op = IROp->C(); static constexpr std::array handlers { &FEXCore::CPU::OpHandlers::handle<0>, &FEXCore::CPU::OpHandlers::handle<1>, @@ -169,7 +169,7 @@ bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::I } case IR::OP_F80CVTTOINT: { - auto Op = IROp->C(); + const auto* Op = IROp->C(); switch (Op->SrcSize) { case 2: { diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index c2a789b06d..509f46e5e2 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -3990,6 +3990,7 @@ void OpDispatchBuilder::BeginFunction(uint64_t RIP, const fextl::vectorBlocks = Block->Wrapped(DualListData.ListBegin()); + CurrentHeader = IRHeader.first; LOGMAN_THROW_A_FMT(IsDeferredFlagsStored(), "Something failed to calculate flags and now we began with invalid state"); } @@ -6181,11 +6182,11 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(0xD9, 0xD0), 1, &OpDispatchBuilder::NOPOp}, // FNOP // D1 = Invalid // D8 = Invalid - {OPD(0xD9, 0xE0), 1, &OpDispatchBuilder::FCHSF64}, - {OPD(0xD9, 0xE1), 1, &OpDispatchBuilder::FABSF64}, + {OPD(0xD9, 0xE0), 1, &OpDispatchBuilder::FCHS}, + {OPD(0xD9, 0xE1), 1, &OpDispatchBuilder::FABS}, // E2 = Invalid {OPD(0xD9, 0xE4), 1, &OpDispatchBuilder::FTSTF64}, - {OPD(0xD9, 0xE5), 1, &OpDispatchBuilder::X87FXAMF64}, + {OPD(0xD9, 0xE5), 1, &OpDispatchBuilder::X87FXAM}, // E6 = Invalid {OPD(0xD9, 0xE8), 1, &OpDispatchBuilder::FLDF64_Const<0x3FF0000000000000>}, // 1.0 {OPD(0xD9, 0xE9), 1, &OpDispatchBuilder::FLDF64_Const<0x400A934F0979A372>}, // log2l(10) @@ -6196,22 +6197,22 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(0xD9, 0xEE), 1, &OpDispatchBuilder::FLDF64_Const<0>}, // 0.0 // EF = Invalid - {OPD(0xD9, 0xF0), 1, &OpDispatchBuilder::X87UnaryOpF64}, + {OPD(0xD9, 0xF0), 1, &OpDispatchBuilder::F80F2XM1}, {OPD(0xD9, 0xF1), 1, &OpDispatchBuilder::X87FYL2XF64}, - {OPD(0xD9, 0xF2), 1, &OpDispatchBuilder::X87TANF64}, - {OPD(0xD9, 0xF3), 1, &OpDispatchBuilder::X87ATANF64}, - {OPD(0xD9, 0xF4), 1, &OpDispatchBuilder::FXTRACTF64}, - {OPD(0xD9, 0xF5), 1, &OpDispatchBuilder::X87BinaryOpF64}, + {OPD(0xD9, 0xF2), 1, &OpDispatchBuilder::X87TAN}, + {OPD(0xD9, 0xF3), 1, &OpDispatchBuilder::X87ATAN}, + {OPD(0xD9, 0xF4), 1, &OpDispatchBuilder::FXTRACT}, + {OPD(0xD9, 0xF5), 1, &OpDispatchBuilder::F80FPREM1}, {OPD(0xD9, 0xF6), 1, &OpDispatchBuilder::X87ModifySTP}, {OPD(0xD9, 0xF7), 1, &OpDispatchBuilder::X87ModifySTP}, - {OPD(0xD9, 0xF8), 1, &OpDispatchBuilder::X87BinaryOpF64}, + {OPD(0xD9, 0xF8), 1, &OpDispatchBuilder::F80FPREM}, {OPD(0xD9, 0xF9), 1, &OpDispatchBuilder::X87FYL2XF64}, - {OPD(0xD9, 0xFA), 1, &OpDispatchBuilder::FSQRTF64}, - {OPD(0xD9, 0xFB), 1, &OpDispatchBuilder::X87SinCosF64}, - {OPD(0xD9, 0xFC), 1, &OpDispatchBuilder::FRNDINTF64}, - {OPD(0xD9, 0xFD), 1, &OpDispatchBuilder::X87BinaryOpF64}, - {OPD(0xD9, 0xFE), 1, &OpDispatchBuilder::X87UnaryOpF64}, - {OPD(0xD9, 0xFF), 1, &OpDispatchBuilder::X87UnaryOpF64}, + {OPD(0xD9, 0xFA), 1, &OpDispatchBuilder::F80SQRT}, + {OPD(0xD9, 0xFB), 1, &OpDispatchBuilder::X87SinCos}, + {OPD(0xD9, 0xFC), 1, &OpDispatchBuilder::FRNDINT}, + {OPD(0xD9, 0xFD), 1, &OpDispatchBuilder::F80SCALE}, + {OPD(0xD9, 0xFE), 1, &OpDispatchBuilder::F80SIN}, + {OPD(0xD9, 0xFF), 1, &OpDispatchBuilder::F80COS}, {OPDReg(0xDA, 0) | 0x00, 8, &OpDispatchBuilder::FADDF64<32, true, OpDispatchBuilder::OpResult::RES_ST0>}, @@ -6288,10 +6289,10 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(0xDC, 0xC0), 8, &OpDispatchBuilder::FADDF64<80, false, OpDispatchBuilder::OpResult::RES_STI>}, {OPD(0xDC, 0xC8), 8, &OpDispatchBuilder::FMULF64<80, false, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDC, 0xE0), 8, &OpDispatchBuilder::FSUBF64<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDC, 0xE8), 8, &OpDispatchBuilder::FSUBF64<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDC, 0xF0), 8, &OpDispatchBuilder::FDIVF64<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDC, 0xF8), 8, &OpDispatchBuilder::FDIVF64<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDC, 0xE0), 8, &OpDispatchBuilder::FSUBF64<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDC, 0xE8), 8, &OpDispatchBuilder::FSUBF64<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDC, 0xF0), 8, &OpDispatchBuilder::FDIVF64<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDC, 0xF8), 8, &OpDispatchBuilder::FDIVF64<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, {OPDReg(0xDD, 0) | 0x00, 8, &OpDispatchBuilder::FLDF64<64>}, @@ -6334,10 +6335,10 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(0xDE, 0xC0), 8, &OpDispatchBuilder::FADDF64<80, false, OpDispatchBuilder::OpResult::RES_STI>}, {OPD(0xDE, 0xC8), 8, &OpDispatchBuilder::FMULF64<80, false, OpDispatchBuilder::OpResult::RES_STI>}, {OPD(0xDE, 0xD9), 1, &OpDispatchBuilder::FCOMIF64<80, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, true>}, - {OPD(0xDE, 0xE0), 8, &OpDispatchBuilder::FSUBF64<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDE, 0xE8), 8, &OpDispatchBuilder::FSUBF64<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDE, 0xF0), 8, &OpDispatchBuilder::FDIVF64<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDE, 0xF8), 8, &OpDispatchBuilder::FDIVF64<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDE, 0xE0), 8, &OpDispatchBuilder::FSUBF64<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDE, 0xE8), 8, &OpDispatchBuilder::FSUBF64<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDE, 0xF0), 8, &OpDispatchBuilder::FDIVF64<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDE, 0xF8), 8, &OpDispatchBuilder::FDIVF64<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, {OPDReg(0xDF, 0) | 0x00, 8, &OpDispatchBuilder::FILDF64}, @@ -6369,9 +6370,9 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPDReg(0xD8, 1) | 0x00, 8, &OpDispatchBuilder::FMUL<32, false, OpDispatchBuilder::OpResult::RES_ST0>}, - {OPDReg(0xD8, 2) | 0x00, 8, &OpDispatchBuilder::FCOMI<32, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, + {OPDReg(0xD8, 2) | 0x00, 8, &OpDispatchBuilder::FCOMI< 32, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, - {OPDReg(0xD8, 3) | 0x00, 8, &OpDispatchBuilder::FCOMI<32, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, + {OPDReg(0xD8, 3) | 0x00, 8, &OpDispatchBuilder::FCOMI< 32, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, {OPDReg(0xD8, 4) | 0x00, 8, &OpDispatchBuilder::FSUB<32, false, false, OpDispatchBuilder::OpResult::RES_ST0>}, @@ -6383,8 +6384,8 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(0xD8, 0xC0), 8, &OpDispatchBuilder::FADD<80, false, OpDispatchBuilder::OpResult::RES_ST0>}, {OPD(0xD8, 0xC8), 8, &OpDispatchBuilder::FMUL<80, false, OpDispatchBuilder::OpResult::RES_ST0>}, - {OPD(0xD8, 0xD0), 8, &OpDispatchBuilder::FCOMI<80, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, - {OPD(0xD8, 0xD8), 8, &OpDispatchBuilder::FCOMI<80, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, + {OPD(0xD8, 0xD0), 8, &OpDispatchBuilder::FCOMI< 80, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, + {OPD(0xD8, 0xD8), 8, &OpDispatchBuilder::FCOMI< 80, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, {OPD(0xD8, 0xE0), 8, &OpDispatchBuilder::FSUB<80, false, false, OpDispatchBuilder::OpResult::RES_ST0>}, {OPD(0xD8, 0xE8), 8, &OpDispatchBuilder::FSUB<80, false, true, OpDispatchBuilder::OpResult::RES_ST0>}, {OPD(0xD8, 0xF0), 8, &OpDispatchBuilder::FDIV<80, false, false, OpDispatchBuilder::OpResult::RES_ST0>}, @@ -6426,30 +6427,30 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(0xD9, 0xEE), 1, &OpDispatchBuilder::FLD_Const}, // 0.0 // EF = Invalid - {OPD(0xD9, 0xF0), 1, &OpDispatchBuilder::X87UnaryOp}, + {OPD(0xD9, 0xF0), 1, &OpDispatchBuilder::F80F2XM1}, {OPD(0xD9, 0xF1), 1, &OpDispatchBuilder::X87FYL2X}, {OPD(0xD9, 0xF2), 1, &OpDispatchBuilder::X87TAN}, {OPD(0xD9, 0xF3), 1, &OpDispatchBuilder::X87ATAN}, {OPD(0xD9, 0xF4), 1, &OpDispatchBuilder::FXTRACT}, - {OPD(0xD9, 0xF5), 1, &OpDispatchBuilder::X87BinaryOp}, + {OPD(0xD9, 0xF5), 1, &OpDispatchBuilder::F80FPREM1}, {OPD(0xD9, 0xF6), 1, &OpDispatchBuilder::X87ModifySTP}, {OPD(0xD9, 0xF7), 1, &OpDispatchBuilder::X87ModifySTP}, - {OPD(0xD9, 0xF8), 1, &OpDispatchBuilder::X87BinaryOp}, + {OPD(0xD9, 0xF8), 1, &OpDispatchBuilder::F80FPREM}, {OPD(0xD9, 0xF9), 1, &OpDispatchBuilder::X87FYL2X}, - {OPD(0xD9, 0xFA), 1, &OpDispatchBuilder::X87UnaryOp}, + {OPD(0xD9, 0xFA), 1, &OpDispatchBuilder::F80SQRT}, {OPD(0xD9, 0xFB), 1, &OpDispatchBuilder::X87SinCos}, {OPD(0xD9, 0xFC), 1, &OpDispatchBuilder::FRNDINT}, - {OPD(0xD9, 0xFD), 1, &OpDispatchBuilder::X87BinaryOp}, - {OPD(0xD9, 0xFE), 1, &OpDispatchBuilder::X87UnaryOp}, - {OPD(0xD9, 0xFF), 1, &OpDispatchBuilder::X87UnaryOp}, + {OPD(0xD9, 0xFD), 1, &OpDispatchBuilder::F80SCALE}, + {OPD(0xD9, 0xFE), 1, &OpDispatchBuilder::F80SIN}, + {OPD(0xD9, 0xFF), 1, &OpDispatchBuilder::F80COS}, {OPDReg(0xDA, 0) | 0x00, 8, &OpDispatchBuilder::FADD<32, true, OpDispatchBuilder::OpResult::RES_ST0>}, {OPDReg(0xDA, 1) | 0x00, 8, &OpDispatchBuilder::FMUL<32, true, OpDispatchBuilder::OpResult::RES_ST0>}, - {OPDReg(0xDA, 2) | 0x00, 8, &OpDispatchBuilder::FCOMI<32, true, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, + {OPDReg(0xDA, 2) | 0x00, 8, &OpDispatchBuilder::FCOMI< 32, true, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, - {OPDReg(0xDA, 3) | 0x00, 8, &OpDispatchBuilder::FCOMI<32, true, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, + {OPDReg(0xDA, 3) | 0x00, 8, &OpDispatchBuilder::FCOMI< 32, true, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, {OPDReg(0xDA, 4) | 0x00, 8, &OpDispatchBuilder::FSUB<32, true, false, OpDispatchBuilder::OpResult::RES_ST0>}, @@ -6504,9 +6505,9 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPDReg(0xDC, 1) | 0x00, 8, &OpDispatchBuilder::FMUL<64, false, OpDispatchBuilder::OpResult::RES_ST0>}, - {OPDReg(0xDC, 2) | 0x00, 8, &OpDispatchBuilder::FCOMI<64, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, + {OPDReg(0xDC, 2) | 0x00, 8, &OpDispatchBuilder::FCOMI< 64, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, - {OPDReg(0xDC, 3) | 0x00, 8, &OpDispatchBuilder::FCOMI<64, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, + {OPDReg(0xDC, 3) | 0x00, 8, &OpDispatchBuilder::FCOMI< 64, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, {OPDReg(0xDC, 4) | 0x00, 8, &OpDispatchBuilder::FSUB<64, false, false, OpDispatchBuilder::OpResult::RES_ST0>}, @@ -6518,10 +6519,10 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(0xDC, 0xC0), 8, &OpDispatchBuilder::FADD<80, false, OpDispatchBuilder::OpResult::RES_STI>}, {OPD(0xDC, 0xC8), 8, &OpDispatchBuilder::FMUL<80, false, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDC, 0xE0), 8, &OpDispatchBuilder::FSUB<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDC, 0xE8), 8, &OpDispatchBuilder::FSUB<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDC, 0xF0), 8, &OpDispatchBuilder::FDIV<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDC, 0xF8), 8, &OpDispatchBuilder::FDIV<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDC, 0xE0), 8, &OpDispatchBuilder::FSUB<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDC, 0xE8), 8, &OpDispatchBuilder::FSUB<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDC, 0xF0), 8, &OpDispatchBuilder::FDIV<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDC, 0xF8), 8, &OpDispatchBuilder::FDIV<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, {OPDReg(0xDD, 0) | 0x00, 8, &OpDispatchBuilder::FLD<64>}, @@ -6549,9 +6550,9 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPDReg(0xDE, 1) | 0x00, 8, &OpDispatchBuilder::FMUL<16, true, OpDispatchBuilder::OpResult::RES_ST0>}, - {OPDReg(0xDE, 2) | 0x00, 8, &OpDispatchBuilder::FCOMI<16, true, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, + {OPDReg(0xDE, 2) | 0x00, 8, &OpDispatchBuilder::FCOMI< 16, true, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, - {OPDReg(0xDE, 3) | 0x00, 8, &OpDispatchBuilder::FCOMI<16, true, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, + {OPDReg(0xDE, 3) | 0x00, 8, &OpDispatchBuilder::FCOMI< 16, true, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>}, {OPDReg(0xDE, 4) | 0x00, 8, &OpDispatchBuilder::FSUB<16, true, false, OpDispatchBuilder::OpResult::RES_ST0>}, @@ -6564,10 +6565,10 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(0xDE, 0xC0), 8, &OpDispatchBuilder::FADD<80, false, OpDispatchBuilder::OpResult::RES_STI>}, {OPD(0xDE, 0xC8), 8, &OpDispatchBuilder::FMUL<80, false, OpDispatchBuilder::OpResult::RES_STI>}, {OPD(0xDE, 0xD9), 1, &OpDispatchBuilder::FCOMI<80, false, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, true>}, - {OPD(0xDE, 0xE0), 8, &OpDispatchBuilder::FSUB<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDE, 0xE8), 8, &OpDispatchBuilder::FSUB<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDE, 0xF0), 8, &OpDispatchBuilder::FDIV<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, - {OPD(0xDE, 0xF8), 8, &OpDispatchBuilder::FDIV<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDE, 0xE0), 8, &OpDispatchBuilder::FSUB<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDE, 0xE8), 8, &OpDispatchBuilder::FSUB<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDE, 0xF0), 8, &OpDispatchBuilder::FDIV<80, false, true, OpDispatchBuilder::OpResult::RES_STI>}, + {OPD(0xDE, 0xF8), 8, &OpDispatchBuilder::FDIV<80, false, false, OpDispatchBuilder::OpResult::RES_STI>}, {OPDReg(0xDF, 0) | 0x00, 8, &OpDispatchBuilder::FILD}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 79843b77dd..85833cb4c8 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -739,9 +739,9 @@ class OpDispatchBuilder final : public IREmitter { void VZEROOp(OpcodeArgs); // X87 Ops - Ref ReconstructFSW(); + Ref ReconstructFSW_Helper(Ref T = nullptr); // Returns new x87 stack top from FSW. - Ref ReconstructX87StateFromFSW(Ref FSW); + Ref ReconstructX87StateFromFSW_Helper(Ref FSW); template void FLD(OpcodeArgs); template @@ -760,10 +760,14 @@ class OpDispatchBuilder final : public IREmitter { template void FIST(OpcodeArgs); + // OpResult is used for Stack operations, + // describes if the result of the operation is stored in ST(0) or ST(i), + // where ST(i) is one of the arguments to the operation. enum class OpResult { RES_ST0, RES_STI, }; + template void FADD(OpcodeArgs); template @@ -778,11 +782,14 @@ class OpDispatchBuilder final : public IREmitter { void FRNDINT(OpcodeArgs); void FXTRACT(OpcodeArgs); void FNINIT(OpcodeArgs); + void F80FPREM(OpcodeArgs); + void F80FPREM1(OpcodeArgs); + void F80SCALE(OpcodeArgs); + void F80SIN(OpcodeArgs); + void F80COS(OpcodeArgs); + void F80SQRT(OpcodeArgs); + void F80F2XM1(OpcodeArgs); - template - void X87UnaryOp(OpcodeArgs); - template - void X87BinaryOp(OpcodeArgs); template void X87ModifySTP(OpcodeArgs); void X87SinCos(OpcodeArgs); @@ -1131,6 +1138,8 @@ class OpDispatchBuilder final : public IREmitter { } private: + FEX_CONFIG_OPT(ReducedPrecisionMode, X87REDUCEDPRECISION); + struct JumpTargetInfo { Ref BlockEntry; bool HaveEmitted; @@ -1626,12 +1635,8 @@ class OpDispatchBuilder final : public IREmitter { return _AddShift(OpSize::i64Bit, X, _LoadDF(), ShiftType::LSL, Shift); } - // Compares two floats and sets flags for a COMISS instruction - void Comiss(size_t ElementSize, Ref Src1, Ref Src2, bool InvalidateAF = false) { - // First, set flags according to Arm FCMP. - HandleNZCVWrite(); - _FCmp(ElementSize, Src1, Src2); - + // Sets flags for a COMISS instruction + void ComissFlags(bool InvalidateAF = false) { // Now set COMISS flags by converts NZCV from the Arm representation to an // eXternal representation that's totally not a euphemism for x86, nuh-uh. if (CTX->HostFeatures.SupportsFlagM2) { @@ -2216,7 +2221,7 @@ class OpDispatchBuilder final : public IREmitter { Ref GetX87Tag(Ref Value, Ref AbridgedFTW); Ref GetX87Tag(Ref Value); void SetX87FTW(Ref FTW); - Ref GetX87FTW(); + Ref GetX87FTW_Helper(); void SetX87Top(Ref Value); bool DestIsLockedMem(FEXCore::X86Tables::DecodedOp Op) const { @@ -2232,6 +2237,7 @@ class OpDispatchBuilder final : public IREmitter { bool Multiblock {}; uint64_t Entry; + IROp_IRHeader* CurrentHeader {}; Ref _StoreMemAutoTSO(FEXCore::IR::RegisterClassType Class, uint8_t Size, Ref Addr, Ref Value, uint8_t Align = 1) { if (CTX->IsAtomicTSOEnabled()) { diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp index 760c743028..c9dbd4122f 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp @@ -966,7 +966,9 @@ void OpDispatchBuilder::AVX128_UCOMISx(OpcodeArgs) { Src2.Low = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], SrcSize, Op->Flags); } - Comiss(ElementSize, Src1.Low, Src2.Low); + HandleNZCVWrite(); + _FCmp(ElementSize, Src1.Low, Src2.Low); + ComissFlags(); } template diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 840db9d68e..5846e1899d 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2652,7 +2652,7 @@ void OpDispatchBuilder::SaveX87State(OpcodeArgs, Ref MemBase) { _StoreMem(GPRClass, 2, MemBase, FCW, 2); } - { _StoreMem(GPRClass, 2, ReconstructFSW(), MemBase, _Constant(2), 2, MEM_OFFSET_SXTX, 1); } + { _StoreMem(GPRClass, 2, ReconstructFSW_Helper(), MemBase, _Constant(2), 2, MEM_OFFSET_SXTX, 1); } { // Abridged FTW @@ -2827,7 +2827,7 @@ void OpDispatchBuilder::RestoreX87State(Ref MemBase) { { auto NewFSW = _LoadMem(GPRClass, 2, MemBase, _Constant(2), 2, MEM_OFFSET_SXTX, 1); - ReconstructX87StateFromFSW(NewFSW); + ReconstructX87StateFromFSW_Helper(NewFSW); } { @@ -2952,7 +2952,9 @@ void OpDispatchBuilder::UCOMISxOp(OpcodeArgs) { Ref Src1 = LoadSource_WithOpSize(FPRClass, Op, Op->Dest, GetGuestVectorLength(), Op->Flags); Ref Src2 = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], SrcSize, Op->Flags); - Comiss(ElementSize, Src1, Src2); + HandleNZCVWrite(); + _FCmp(ElementSize, Src1, Src2); + ComissFlags(); } template void OpDispatchBuilder::UCOMISxOp<4>(OpcodeArgs); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp index 3699c09251..d02363da40 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp @@ -8,6 +8,7 @@ desc: Handles x86/64 x87 to IR #include "Interface/Core/OpcodeDispatcher.h" #include "Interface/Core/X86Tables/X86Tables.h" +#include "Interface/IR/IR.h" #include #include @@ -20,9 +21,11 @@ desc: Handles x86/64 x87 to IR namespace FEXCore::IR { class OrderedNode; - #define OpcodeArgs [[maybe_unused]] FEXCore::X86Tables::DecodedOp Op +//////////////////////?????????<<<< TOREMOVE + + Ref OpDispatchBuilder::GetX87Top() { // Yes, we are storing 3 bits in a single flag register. // Deal with it @@ -73,134 +76,64 @@ void OpDispatchBuilder::SetX87FTW(Ref FTW) { _StoreContext(1, GPRClass, NewAbridgedFTW, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); } -Ref OpDispatchBuilder::GetX87FTW() { - Ref AbridgedFTW = _LoadContext(1, GPRClass, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); - Ref FTW = _Constant(0); - - for (int i = 0; i < 8; i++) { - const auto RegTag = GetX87Tag(_Constant(i), AbridgedFTW); - FTW = _Orlshl(OpSize::i32Bit, FTW, RegTag, i * 2); - } - - return FTW; -} - void OpDispatchBuilder::SetX87Top(Ref Value) { _StoreContext(1, GPRClass, Value, offsetof(FEXCore::Core::CPUState, flags) + FEXCore::X86State::X87FLAG_TOP_LOC); } +//////////////////////?????????<<<< TOREMOVE -Ref OpDispatchBuilder::ReconstructFSW() { - // We must construct the FSW from our various bits - Ref FSW = _Constant(0); - auto Top = GetX87Top(); - FSW = _Bfi(OpSize::i64Bit, 3, 11, FSW, Top); - - auto C0 = GetRFLAG(FEXCore::X86State::X87FLAG_C0_LOC); - auto C1 = GetRFLAG(FEXCore::X86State::X87FLAG_C1_LOC); - auto C2 = GetRFLAG(FEXCore::X86State::X87FLAG_C2_LOC); - auto C3 = GetRFLAG(FEXCore::X86State::X87FLAG_C3_LOC); - - FSW = _Orlshl(OpSize::i64Bit, FSW, C0, 8); - FSW = _Orlshl(OpSize::i64Bit, FSW, C1, 9); - FSW = _Orlshl(OpSize::i64Bit, FSW, C2, 10); - FSW = _Orlshl(OpSize::i64Bit, FSW, C3, 14); - return FSW; -} - -Ref OpDispatchBuilder::ReconstructX87StateFromFSW(Ref FSW) { - auto Top = _Bfe(OpSize::i32Bit, 3, 11, FSW); - SetX87Top(Top); - - auto C0 = _Bfe(OpSize::i32Bit, 1, 8, FSW); - auto C1 = _Bfe(OpSize::i32Bit, 1, 9, FSW); - auto C2 = _Bfe(OpSize::i32Bit, 1, 10, FSW); - auto C3 = _Bfe(OpSize::i32Bit, 1, 14, FSW); - - SetRFLAG(C0); - SetRFLAG(C1); - SetRFLAG(C2); - SetRFLAG(C3); - return Top; -} - +// Float LoaD operation template void OpDispatchBuilder::FLD(OpcodeArgs) { - // Update TOP - auto orig_top = GetX87Top(); - auto mask = _Constant(7); + static_assert(width == 32 || width == 64 || width == 80, "Unsupported FLD width"); + CurrentHeader->HasX87 = true; size_t read_width = (width == 80) ? 16 : width / 8; - Ref data {}; - if (!Op->Src[0].IsNone()) { + if (Op->Src[0].IsNone()) { + // Implicit arg + data = _ReadStackValue(Op->OP & 7); + } else { // Read from memory data = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], read_width, Op->Flags); - } else { - // Implicit arg - auto offset = _Constant(Op->OP & 7); - data = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, orig_top, offset), mask); - data = _LoadContextIndexed(data, 16, MMBaseOffset(), 16, FPRClass); - } - Ref converted = data; - // Convert to 80bit float - if constexpr (width == 32 || width == 64) { - converted = _F80CVTTo(data, width / 8); + // Convert to 80bit float + if constexpr (width == 32 || width == 64) { + data = _F80CVTTo(data, read_width); + } } - - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), mask); - SetX87ValidTag(top, true); - SetX87Top(top); - // Write to ST[TOP] - _StoreContextIndexed(converted, top, 16, MMBaseOffset(), 16, FPRClass); - //_StoreContext(converted, 16, offsetof(FEXCore::Core::CPUState, mm[7][0])); + _PushStack(data, OpSize::i128Bit, true, read_width); } template void OpDispatchBuilder::FLD<32>(OpcodeArgs); template void OpDispatchBuilder::FLD<64>(OpcodeArgs); template void OpDispatchBuilder::FLD<80>(OpcodeArgs); + void OpDispatchBuilder::FBLD(OpcodeArgs) { - // Update TOP - auto orig_top = GetX87Top(); - auto mask = _Constant(7); - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), mask); - SetX87ValidTag(top, true); - SetX87Top(top); + CurrentHeader->HasX87 = true; // Read from memory Ref data = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], 16, Op->Flags); Ref converted = _F80BCDLoad(data); - _StoreContextIndexed(converted, top, 16, MMBaseOffset(), 16, FPRClass); + _PushStack(converted, i128Bit, true, 16); } -void OpDispatchBuilder::FBSTP(OpcodeArgs) { - auto orig_top = GetX87Top(); - auto data = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass); - - Ref converted = _F80BCDStore(data); +void OpDispatchBuilder::FBSTP(OpcodeArgs) { + CurrentHeader->HasX87 = true; + Ref converted = _F80BCDStore(_ReadStackValue(0)); StoreResult_WithOpSize(FPRClass, Op, Op->Dest, converted, 10, 1); - // if we are popping then we must first mark this location as empty - SetX87ValidTag(orig_top, false); - auto top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87Top(top); + _PopStackDestroy(); } template void OpDispatchBuilder::FLD_Const(OpcodeArgs) { + CurrentHeader->HasX87 = true; // Update TOP - auto orig_top = GetX87Top(); - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87ValidTag(top, true); - SetX87Top(top); - Ref data = LoadAndCacheNamedVectorConstant(16, constant); - - // Write to ST[TOP] - _StoreContextIndexed(data, top, 16, MMBaseOffset(), 16, FPRClass); + _PushStack(data, OpSize::i128Bit, true, 16); } template void OpDispatchBuilder::FLD_Const(OpcodeArgs); // 1.0 @@ -211,17 +144,12 @@ template void OpDispatchBuilder::FLD_Const(OpcodeArgs); // log(2) template void OpDispatchBuilder::FLD_Const(OpcodeArgs); // 0.0 -void OpDispatchBuilder::FILD(OpcodeArgs) { - // Update TOP - auto orig_top = GetX87Top(); - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87ValidTag(top, true); - SetX87Top(top); +void OpDispatchBuilder::FILD(OpcodeArgs) { + CurrentHeader->HasX87 = true; size_t read_width = GetSrcSize(Op); - // Read from memory - auto data = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], read_width, Op->Flags); + auto* data = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], read_width, Op->Flags); auto zero = _Constant(0); @@ -233,12 +161,12 @@ void OpDispatchBuilder::FILD(OpcodeArgs) { // We're about to clobber flags to grab the sign, so save NZCV. SaveNZCV(); - // Extract sign and make interger absolute + // Extract sign and make integer absolute _SubNZCV(OpSize::i64Bit, data, zero); auto sign = _NZCVSelect(OpSize::i64Bit, CondClassType {COND_SLT}, _Constant(0x8000), zero); auto absolute = _Neg(OpSize::i64Bit, data, CondClassType {COND_MI}); - // left justify the absolute interger + // left justify the absolute integer auto shift = _Sub(OpSize::i64Bit, _Constant(63), _FindMSB(IR::OpSize::i64Bit, absolute)); auto shifted = _Lshl(OpSize::i64Bit, absolute, shift); @@ -249,28 +177,29 @@ void OpDispatchBuilder::FILD(OpcodeArgs) { Ref converted = _VCastFromGPR(16, 8, shifted); converted = _VInsElement(16, 8, 1, 0, converted, _VCastFromGPR(16, 8, upper)); - - // Write to ST[TOP] - _StoreContextIndexed(converted, top, 16, MMBaseOffset(), 16, FPRClass); + _PushStack(converted, OpSize::i128Bit, false, read_width); } + template void OpDispatchBuilder::FST(OpcodeArgs) { - auto orig_top = GetX87Top(); - auto data = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass); - if constexpr (width == 80) { - StoreResult_WithOpSize(FPRClass, Op, Op->Dest, data, 10, 1); - } else if constexpr (width == 32 || width == 64) { - auto result = _F80CVT(width / 8, data); - StoreResult_WithOpSize(FPRClass, Op, Op->Dest, result, width / 8, 1); - } + static_assert(width == 32 || width == 64 || width == 80, "Unsupported FST width"); + CurrentHeader->HasX87 = true; - if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(orig_top, false); - // Set the new top now - auto top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87Top(top); + if (Op->Src[0].IsNone()) { // Destination is stack + auto offset = Op->OP & 7; + _StoreStackToStack(offset); + } else { + // Destination is memory + Ref Mem = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.LoadData = false}); + if constexpr (width == 80) { + _StoreStackMemory(Mem, OpSize::i128Bit, true, 10); + } else if constexpr (width == 32 || width == 64) { + _StoreStackMemory(Mem, OpSize::i128Bit, true, width / 8); + } + } + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); } } @@ -278,72 +207,81 @@ template void OpDispatchBuilder::FST<32>(OpcodeArgs); template void OpDispatchBuilder::FST<64>(OpcodeArgs); template void OpDispatchBuilder::FST<80>(OpcodeArgs); + +void OpDispatchBuilder::FST(OpcodeArgs) { + CurrentHeader->HasX87 = true; + const uint8_t Offset = Op->OP & 7; + if (Offset != 0) { + _StoreStackToStack(Offset); + } else { + LogMan::Msg::DFmt("FST: _StoreStackToStack(0) is a nop.\n"); + } + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); + } +} + + +// Store integer to memory (possibly with truncation) template void OpDispatchBuilder::FIST(OpcodeArgs) { + CurrentHeader->HasX87 = true; auto Size = GetSrcSize(Op); + // FIXME(pmatos): is there any advantage of using STORESTACKMEMORY here? + // Do we need STORESTACKMEMORY at all? + Ref Data = _ReadStackValue(0); + Data = _F80CVTInt(Size, Data, Truncate); - auto orig_top = GetX87Top(); - Ref data = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass); - data = _F80CVTInt(Size, data, Truncate); - - StoreResult_WithOpSize(GPRClass, Op, Op->Dest, data, Size, 1); + StoreResult_WithOpSize(GPRClass, Op, Op->Dest, Data, Size, 1); if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(orig_top, false); - // Set the new top now - auto top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87Top(top); + _PopStackDestroy(); } } template void OpDispatchBuilder::FIST(OpcodeArgs); template void OpDispatchBuilder::FIST(OpcodeArgs); + template void OpDispatchBuilder::FADD(OpcodeArgs) { - auto top = GetX87Top(); - Ref StackLocation = top; - - Ref arg {}; - Ref b {}; + static_assert(width == 16 || width == 32 || width == 64 || width == 80, "Unsupported FADD width"); - auto mask = _Constant(7); + CurrentHeader->HasX87 = true; - if (!Op->Src[0].IsNone()) { - // Memory arg - if constexpr (width == 16 || width == 32 || width == 64) { - if constexpr (Integer) { - arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); - b = _F80CVTToInt(arg, width / 8); - } else { - arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - b = _F80CVTTo(arg, width / 8); - } - } - } else { - // Implicit arg - auto offset = _Constant(Op->OP & 7); - arg = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), mask); + if (Op->Src[0].IsNone()) { // Implicit argument case + auto offset = Op->OP & 7; + auto st0 = 0; if constexpr (ResInST0 == OpResult::RES_STI) { - StackLocation = arg; + _F80AddStack(offset, st0); + } else { + _F80AddStack(st0, offset); } - b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass); + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); + } + return; } - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); - auto result = _F80Add(a, b); + // We have one memory argument + Ref arg {}; - if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(top, false); - // Set the new top now - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87Top(top); + if constexpr (width == 16 || width == 32 || width == 64) { + if constexpr (Integer) { + arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); + arg = _F80CVTToInt(arg, width / 8); + } else { + arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); + arg = _F80CVTTo(arg, width / 8); + } } - // Write to ST[TOP] - _StoreContextIndexed(result, StackLocation, 16, MMBaseOffset(), 16, FPRClass); + // top of stack is at offset zero + _F80AddValue(0, arg); + + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); + } } template void OpDispatchBuilder::FADD<32, false, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); @@ -356,50 +294,42 @@ template void OpDispatchBuilder::FADD<32, true, OpDispatchBuilder::OpResult::RES template void OpDispatchBuilder::FMUL(OpcodeArgs) { - auto top = GetX87Top(); - Ref StackLocation = top; - Ref arg {}; - Ref b {}; - - auto mask = _Constant(7); + static_assert(width == 16 || width == 32 || width == 64 || width == 80, "Unsupported FMUL width"); - if (!Op->Src[0].IsNone()) { - // Memory arg - - if constexpr (width == 16 || width == 32 || width == 64) { - if constexpr (Integer) { - arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); - b = _F80CVTToInt(arg, width / 8); - } else { - arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - b = _F80CVTTo(arg, width / 8); - } - } - } else { - // Implicit arg - auto offset = _Constant(Op->OP & 7); - arg = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), mask); + CurrentHeader->HasX87 = true; + if (Op->Src[0].IsNone()) { // Implicit argument case + auto offset = Op->OP & 7; + auto st0 = 0; if constexpr (ResInST0 == OpResult::RES_STI) { - StackLocation = arg; + _F80MulStack(offset, st0); + } else { + _F80MulStack(st0, offset); } - - b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass); + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); + } + return; } - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); - - auto result = _F80Mul(a, b); + // We have one memory argument + Ref arg {}; - if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(top, false); - // Set the new top now - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87Top(top); + if constexpr (width == 16 || width == 32 || width == 64) { + if constexpr (Integer) { + arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); + arg = _F80CVTToInt(arg, width / 8); + } else { + arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); + arg = _F80CVTTo(arg, width / 8); + } } - // Write to ST[TOP] - _StoreContextIndexed(result, StackLocation, 16, MMBaseOffset(), 16, FPRClass); + // top of stack is at offset zero + _F80MulValue(0, arg); + + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); + } } template void OpDispatchBuilder::FMUL<32, false, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); @@ -412,55 +342,56 @@ template void OpDispatchBuilder::FMUL<32, true, OpDispatchBuilder::OpResult::RES template void OpDispatchBuilder::FDIV(OpcodeArgs) { - auto top = GetX87Top(); - Ref StackLocation = top; - Ref arg {}; - Ref b {}; - - auto mask = _Constant(7); + static_assert(width == 16 || width == 32 || width == 64 || width == 80, "Unsupported FDIV width"); + CurrentHeader->HasX87 = true; - if (!Op->Src[0].IsNone()) { - // Memory arg + if (Op->Src[0].IsNone()) { + const auto offset = Op->OP & 7; + const auto st0 = 0; - if constexpr (width == 16 || width == 32 || width == 64) { - if constexpr (Integer) { - arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); - b = _F80CVTToInt(arg, width / 8); + if constexpr (reverse) { + if constexpr (ResInST0 == OpResult::RES_STI) { + _F80DivStack(offset, st0, offset); } else { - arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - b = _F80CVTTo(arg, width / 8); + _F80DivStack(st0, offset, st0); + } + } else { + if constexpr (ResInST0 == OpResult::RES_STI) { + _F80DivStack(offset, offset, st0); + } else { + _F80DivStack(st0, st0, offset); } - } - } else { - // Implicit arg - auto offset = _Constant(Op->OP & 7); - arg = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), mask); - if constexpr (ResInST0 == OpResult::RES_STI) { - StackLocation = arg; } - b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass); + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); + } + return; } - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); + // We have one memory argument + Ref arg {}; + + if constexpr (width == 16 || width == 32 || width == 64) { + if constexpr (Integer) { + arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); + arg = _F80CVTToInt(arg, width / 8); + } else { + arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); + arg = _F80CVTTo(arg, width / 8); + } + } - Ref result {}; + // top of stack is at offset zero if constexpr (reverse) { - result = _F80Div(b, a); + _F80DivRValue(arg, 0); } else { - result = _F80Div(a, b); + _F80DivValue(0, arg); } - if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(top, false); - // Set the new top now - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87Top(top); + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); } - - // Write to ST[TOP] - _StoreContextIndexed(result, StackLocation, 16, MMBaseOffset(), 16, FPRClass); } template void OpDispatchBuilder::FDIV<32, false, false, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); @@ -481,57 +412,59 @@ template void OpDispatchBuilder::FDIV<16, true, true, OpDispatchBuilder::OpResul template void OpDispatchBuilder::FDIV<32, true, false, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); template void OpDispatchBuilder::FDIV<32, true, true, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); + template void OpDispatchBuilder::FSUB(OpcodeArgs) { - auto top = GetX87Top(); - Ref StackLocation = top; - Ref arg {}; - Ref b {}; - - auto mask = _Constant(7); + static_assert(width == 16 || width == 32 || width == 64 || width == 80, "Unsupported FSUB width"); + CurrentHeader->HasX87 = true; - if (!Op->Src[0].IsNone()) { - // Memory arg + if (Op->Src[0].IsNone()) { + const auto offset = Op->OP & 7; + const auto st0 = 0; - if constexpr (width == 16 || width == 32 || width == 64) { - if constexpr (Integer) { - arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); - b = _F80CVTToInt(arg, width / 8); + if constexpr (reverse) { + if constexpr (ResInST0 == OpResult::RES_STI) { + _F80SubStack(offset, st0, offset); } else { - arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - b = _F80CVTTo(arg, width / 8); + _F80SubStack(st0, offset, st0); + } + } else { + if constexpr (ResInST0 == OpResult::RES_STI) { + _F80SubStack(offset, offset, st0); + } else { + _F80SubStack(st0, st0, offset); } } - } else { - // Implicit arg - auto offset = _Constant(Op->OP & 7); - arg = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), mask); - if constexpr (ResInST0 == OpResult::RES_STI) { - StackLocation = arg; + + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); } - b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass); + return; } - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); + // We have one memory argument + Ref arg {}; + + if constexpr (width == 16 || width == 32 || width == 64) { + if constexpr (Integer) { + arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); + arg = _F80CVTToInt(arg, width / 8); + } else { + arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); + arg = _F80CVTTo(arg, width / 8); + } + } - Ref result {}; + // top of stack is at offset zero if constexpr (reverse) { - result = _F80Sub(b, a); + _F80SubRValue(arg, 0); } else { - result = _F80Sub(a, b); + _F80SubValue(0, arg); } - if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(top, false); - // Set the new top now - - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87Top(top); + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); } - - // Write to ST[TOP] - _StoreContextIndexed(result, StackLocation, 16, MMBaseOffset(), 16, FPRClass); } template void OpDispatchBuilder::FSUB<32, false, false, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); @@ -552,110 +485,336 @@ template void OpDispatchBuilder::FSUB<16, true, true, OpDispatchBuilder::OpResul template void OpDispatchBuilder::FSUB<32, true, false, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); template void OpDispatchBuilder::FSUB<32, true, true, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); -void OpDispatchBuilder::FCHS(OpcodeArgs) { - auto top = GetX87Top(); - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); - - auto low = _Constant(0); - auto high = _Constant(0b1'000'0000'0000'0000ULL); - Ref data = _VCastFromGPR(16, 8, low); - data = _VInsGPR(16, 8, 1, data, high); +Ref OpDispatchBuilder::GetX87FTW_Helper() { + Ref AbridgedFTW = _LoadContext(1, GPRClass, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + Ref FTW = _Constant(0); - auto result = _VXor(16, 1, a, data); + for (int i = 0; i < 8; i++) { + auto* const RegTag = GetX87Tag(_Constant(i), AbridgedFTW); + FTW = _Orlshl(OpSize::i32Bit, FTW, RegTag, i * 2); + } - // Write to ST[TOP] - _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass); + return FTW; } -void OpDispatchBuilder::FABS(OpcodeArgs) { - auto top = GetX87Top(); - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); +void OpDispatchBuilder::X87FNSTENV(OpcodeArgs) { + CurrentHeader->HasX87 = true; - auto low = _Constant(~0ULL); - auto high = _Constant(0b0'111'1111'1111'1111ULL); - Ref data = _VCastFromGPR(16, 8, low); - data = _VInsGPR(16, 8, 1, data, high); + // 14 bytes for 16bit + // 2 Bytes : FCW + // 2 Bytes : FSW + // 2 bytes : FTW + // 2 bytes : Instruction offset + // 2 bytes : Instruction CS selector + // 2 bytes : Data offset + // 2 bytes : Data selector - auto result = _VAnd(16, 1, a, data); + // 28 bytes for 32bit + // 4 bytes : FCW + // 4 bytes : FSW + // 4 bytes : FTW + // 4 bytes : Instruction pointer + // 2 bytes : Instruction pointer selector + // 2 bytes : Opcode + // 4 bytes : data pointer offset + // 4 bytes : data pointer selector - // Write to ST[TOP] - _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass); -} + // Before we store anything we need to sync our stack to the registers. + _SyncStackToSlow(); -void OpDispatchBuilder::FTST(OpcodeArgs) { - auto top = GetX87Top(); - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); + auto Size = GetDstSize(Op); + Ref Mem = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.LoadData = false}); + Mem = AppendSegmentOffset(Mem, Op->Flags); - auto low = _Constant(0); - Ref data = _VCastFromGPR(16, 8, low); + { + auto FCW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FCW)); + _StoreMem(GPRClass, Size, Mem, FCW, Size); + } - Ref Res = _F80Cmp(a, data, (1 << FCMP_FLAG_EQ) | (1 << FCMP_FLAG_LT) | (1 << FCMP_FLAG_UNORDERED)); + { + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1)); + _StoreMem(GPRClass, Size, MemLocation, ReconstructFSW_Helper(), Size); + } - Ref HostFlag_CF = _GetHostFlag(Res, FCMP_FLAG_LT); - Ref HostFlag_ZF = _GetHostFlag(Res, FCMP_FLAG_EQ); - Ref HostFlag_Unordered = _GetHostFlag(Res, FCMP_FLAG_UNORDERED); - HostFlag_CF = _Or(OpSize::i32Bit, HostFlag_CF, HostFlag_Unordered); - HostFlag_ZF = _Or(OpSize::i32Bit, HostFlag_ZF, HostFlag_Unordered); + auto ZeroConst = _Constant(0); - SetRFLAG(HostFlag_CF); - SetRFLAG(_Constant(0)); - SetRFLAG(HostFlag_Unordered); - SetRFLAG(HostFlag_ZF); -} + { + // FTW + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 2)); + _StoreMem(GPRClass, Size, MemLocation, GetX87FTW_Helper(), Size); + } -void OpDispatchBuilder::FRNDINT(OpcodeArgs) { - auto top = GetX87Top(); - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); + { + // Instruction Offset + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 3)); + _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size); + } - auto result = _F80Round(a); + { + // Instruction CS selector (+ Opcode) + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 4)); + _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size); + } - // Write to ST[TOP] - _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass); -} + { + // Data pointer offset + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 5)); + _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size); + } -void OpDispatchBuilder::FXTRACT(OpcodeArgs) { - auto orig_top = GetX87Top(); - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87ValidTag(top, true); - SetX87Top(top); + { + // Data pointer selector + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 6)); + _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size); + } +} - auto a = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass); +Ref OpDispatchBuilder::ReconstructX87StateFromFSW_Helper(Ref FSW) { + auto Top = _Bfe(OpSize::i32Bit, 3, 11, FSW); + SetX87Top(Top); - auto exp = _F80XTRACT_EXP(a); - auto sig = _F80XTRACT_SIG(a); + auto C0 = _Bfe(OpSize::i32Bit, 1, 8, FSW); + auto C1 = _Bfe(OpSize::i32Bit, 1, 9, FSW); + auto C2 = _Bfe(OpSize::i32Bit, 1, 10, FSW); + auto C3 = _Bfe(OpSize::i32Bit, 1, 14, FSW); - // Write to ST[TOP] - _StoreContextIndexed(exp, orig_top, 16, MMBaseOffset(), 16, FPRClass); - _StoreContextIndexed(sig, top, 16, MMBaseOffset(), 16, FPRClass); + SetRFLAG(C0); + SetRFLAG(C1); + SetRFLAG(C2); + SetRFLAG(C3); + return Top; } -void OpDispatchBuilder::FNINIT(OpcodeArgs) { - auto Zero = _Constant(0); - // Init FCW to 0x037F - auto NewFCW = _Constant(16, 0x037F); +void OpDispatchBuilder::X87LDENV(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _StackForceSlow(); + + auto Size = GetSrcSize(Op); + Ref Mem = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, {.LoadData = false}); + Mem = AppendSegmentOffset(Mem, Op->Flags); + + auto NewFCW = _LoadMem(GPRClass, 2, Mem, 2); _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); - // Init FSW to 0 - SetX87Top(Zero); + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1)); + auto NewFSW = _LoadMem(GPRClass, Size, MemLocation, Size); + ReconstructX87StateFromFSW_Helper(NewFSW); - SetRFLAG(Zero); - SetRFLAG(Zero); - SetRFLAG(Zero); - SetRFLAG(Zero); + { + // FTW + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 2)); + SetX87FTW(_LoadMem(GPRClass, Size, MemLocation, Size)); + } +} - // Tags all get marked as invalid - _StoreContext(1, GPRClass, Zero, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); +void OpDispatchBuilder::X87FNSAVE(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _SyncStackToSlow(); + // 14 bytes for 16bit + // 2 Bytes : FCW + // 2 Bytes : FSW + // 2 bytes : FTW + // 2 bytes : Instruction offset + // 2 bytes : Instruction CS selector + // 2 bytes : Data offset + // 2 bytes : Data selector + + // 28 bytes for 32bit + // 4 bytes : FCW + // 4 bytes : FSW + // 4 bytes : FTW + // 4 bytes : Instruction pointer + // 2 bytes : instruction pointer selector + // 2 bytes : Opcode + // 4 bytes : data pointer offset + // 4 bytes : data pointer selector + + const auto Size = GetDstSize(Op); + Ref Mem = MakeSegmentAddress(Op, Op->Dest); + Ref Top = GetX87Top(); + { + auto FCW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FCW)); + _StoreMem(GPRClass, Size, Mem, FCW, Size); + } + + { + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1)); + _StoreMem(GPRClass, Size, MemLocation, ReconstructFSW_Helper(), Size); + } + + auto ZeroConst = _Constant(0); + + { + // FTW + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 2)); + _StoreMem(GPRClass, Size, MemLocation, GetX87FTW_Helper(), Size); + } + + { + // Instruction Offset + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 3)); + _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size); + } + + { + // Instruction CS selector (+ Opcode) + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 4)); + _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size); + } + + { + // Data pointer offset + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 5)); + _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size); + } + + { + // Data pointer selector + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 6)); + _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size); + } + + Ref ST0Location = _Add(OpSize::i64Bit, Mem, _Constant(Size * 7)); + + auto OneConst = _Constant(1); + auto SevenConst = _Constant(7); + auto TenConst = _Constant(10); + for (int i = 0; i < 7; ++i) { + auto data = _LoadContextIndexed(Top, 16, MMBaseOffset(), 16, FPRClass); + _StoreMem(FPRClass, 16, ST0Location, data, 1); + ST0Location = _Add(OpSize::i64Bit, ST0Location, TenConst); + Top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, Top, OneConst), SevenConst); + } + + // The final st(7) needs a bit of special handling here + auto data = _LoadContextIndexed(Top, 16, MMBaseOffset(), 16, FPRClass); + // ST7 broken in to two parts + // Lower 64bits [63:0] + // upper 16 bits [79:64] + _StoreMem(FPRClass, 8, ST0Location, data, 1); + ST0Location = _Add(OpSize::i64Bit, ST0Location, _Constant(8)); + auto topBytes = _VDupElement(16, 2, data, 4); + _StoreMem(FPRClass, 2, ST0Location, topBytes, 1); + + // reset to default + FNINIT(Op); } +void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _StackForceSlow(); + const auto Size = GetSrcSize(Op); + Ref Mem = MakeSegmentAddress(Op, Op->Src[0]); + + auto NewFCW = _LoadMem(GPRClass, 2, Mem, 2); + _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); + + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1)); + auto NewFSW = _LoadMem(GPRClass, Size, MemLocation, Size); + Ref Top = ReconstructX87StateFromFSW_Helper(NewFSW); + { + // FTW + Ref MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 2)); + SetX87FTW(_LoadMem(GPRClass, Size, MemLocation, Size)); + } + + Ref ST0Location = _Add(OpSize::i64Bit, Mem, _Constant(Size * 7)); + + auto OneConst = _Constant(1); + auto SevenConst = _Constant(7); + auto TenConst = _Constant(10); + + auto low = _Constant(~0ULL); + auto high = _Constant(0xFFFF); + Ref Mask = _VCastFromGPR(16, 8, low); + Mask = _VInsGPR(16, 8, 1, Mask, high); + + for (int i = 0; i < 7; ++i) { + Ref Reg = _LoadMem(FPRClass, 16, ST0Location, 1); + // Mask off the top bits + Reg = _VAnd(16, 16, Reg, Mask); + + _StoreContextIndexed(Reg, Top, 16, MMBaseOffset(), 16, FPRClass); + + ST0Location = _Add(OpSize::i64Bit, ST0Location, TenConst); + Top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, Top, OneConst), SevenConst); + } + + // The final st(7) needs a bit of special handling here + // ST7 broken in to two parts + // Lower 64bits [63:0] + // upper 16 bits [79:64] + + Ref Reg = _LoadMem(FPRClass, 8, ST0Location, 1); + ST0Location = _Add(OpSize::i64Bit, ST0Location, _Constant(8)); + Ref RegHigh = _LoadMem(FPRClass, 2, ST0Location, 1); + Reg = _VInsElement(16, 2, 4, 0, Reg, RegHigh); + _StoreContextIndexed(Reg, Top, 16, MMBaseOffset(), 16, FPRClass); +} + +// Load / Store Control Word +void OpDispatchBuilder::X87FSTCW(OpcodeArgs) { + auto FCW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FCW)); + StoreResult(GPRClass, Op, FCW, -1); +} + + +void OpDispatchBuilder::X87FLDCW(OpcodeArgs) { + CurrentHeader->HasX87 = true; + // FIXME: Because loading control flags will affect several instructions in fast path, we might have + // to switch for now to slow mode whenever these are manually changed. + // Remove the next line and try DF_04.asm in fast path. + _StackForceSlow(); + Ref NewFCW = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); + _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); +} + + +void OpDispatchBuilder::FXCH(OpcodeArgs) { + CurrentHeader->HasX87 = true; + uint8_t Offset = Op->OP & 7; + // fxch st0, st0 is for us essentially a nop + if (Offset != 0) { + _F80StackXchange(Offset); + } + SetRFLAG(_Constant(0)); +} + +void OpDispatchBuilder::FCHS(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _F80StackChangeSign(); +} + +void OpDispatchBuilder::FABS(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _F80StackAbs(); +} + +void OpDispatchBuilder::X87FYL2X(OpcodeArgs) { + CurrentHeader->HasX87 = true; + + if (Op->OP == 0x01F9) { // fyl2xp1 + // create an add between top of stack and 1. + Ref f80one = LoadAndCacheNamedVectorConstant(16, NamedVectorConstant::NAMED_VECTOR_X87_ONE); + _F80AddValue(0, f80one); + } + + _F80StackFYL2X(); +} + + template void OpDispatchBuilder::FCOMI(OpcodeArgs) { - auto top = GetX87Top(); - auto mask = _Constant(7); - + CurrentHeader->HasX87 = true; Ref arg {}; Ref b {}; - if (!Op->Src[0].IsNone()) { + Ref Res = nullptr; + if (Op->Src[0].IsNone()) { + // Implicit arg + uint8_t offset = Op->OP & 7; + Res = _F80CmpStack(offset, (1 << FCMP_FLAG_EQ) | (1 << FCMP_FLAG_LT) | (1 << FCMP_FLAG_UNORDERED)); + } else { // Memory arg if constexpr (width == 16 || width == 32 || width == 64) { if constexpr (Integer) { @@ -666,17 +825,9 @@ void OpDispatchBuilder::FCOMI(OpcodeArgs) { b = _F80CVTTo(arg, width / 8); } } - } else { - // Implicit arg - auto offset = _Constant(Op->OP & 7); - arg = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), mask); - b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass); + Res = _F80CmpValue(b, (1 << FCMP_FLAG_EQ) | (1 << FCMP_FLAG_LT) | (1 << FCMP_FLAG_UNORDERED)); } - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); - - Ref Res = _F80Cmp(a, b, (1 << FCMP_FLAG_EQ) | (1 << FCMP_FLAG_LT) | (1 << FCMP_FLAG_UNORDERED)); - Ref HostFlag_CF = _GetHostFlag(Res, FCMP_FLAG_LT); Ref HostFlag_ZF = _GetHostFlag(Res, FCMP_FLAG_EQ); Ref HostFlag_Unordered = _GetHostFlag(Res, FCMP_FLAG_UNORDERED); @@ -703,19 +854,10 @@ void OpDispatchBuilder::FCOMI(OpcodeArgs) { } if constexpr (poptwice) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(top, false); - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87ValidTag(top, false); - // Set the new top now - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87Top(top); + _PopStackDestroy(); + _PopStackDestroy(); } else if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(top, false); - // Set the new top now - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87Top(top); + _PopStackDestroy(); } } @@ -732,431 +874,204 @@ template void OpDispatchBuilder::FCOMI<16, true, OpDispatchBuilder::FCOMIFlags:: template void OpDispatchBuilder::FCOMI<32, true, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>(OpcodeArgs); -void OpDispatchBuilder::FXCH(OpcodeArgs) { - auto top = GetX87Top(); - Ref arg; - - auto mask = _Constant(7); - - // Implicit arg - auto offset = _Constant(Op->OP & 7); - arg = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), mask); +void OpDispatchBuilder::FTST(OpcodeArgs) { + CurrentHeader->HasX87 = true; + Ref Res = _F80StackTest(0, (1 << FCMP_FLAG_EQ) | (1 << FCMP_FLAG_LT) | (1 << FCMP_FLAG_UNORDERED)); - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); - auto b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass); + Ref HostFlag_CF = _GetHostFlag(Res, FCMP_FLAG_LT); + Ref HostFlag_ZF = _GetHostFlag(Res, FCMP_FLAG_EQ); + Ref HostFlag_Unordered = _GetHostFlag(Res, FCMP_FLAG_UNORDERED); + HostFlag_CF = _Or(OpSize::i32Bit, HostFlag_CF, HostFlag_Unordered); + HostFlag_ZF = _Or(OpSize::i32Bit, HostFlag_ZF, HostFlag_Unordered); - // Set C1 to Zero + SetRFLAG(HostFlag_CF); SetRFLAG(_Constant(0)); - - // Write to ST[TOP] - _StoreContextIndexed(b, top, 16, MMBaseOffset(), 16, FPRClass); - _StoreContextIndexed(a, arg, 16, MMBaseOffset(), 16, FPRClass); + SetRFLAG(HostFlag_Unordered); + SetRFLAG(HostFlag_ZF); } -void OpDispatchBuilder::FST(OpcodeArgs) { - auto top = GetX87Top(); - auto mask = _Constant(7); - - // Implicit arg - auto offset = _Constant(Op->OP & 7); - Ref arg = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), mask); - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); - - // Write to ST[i] - _StoreContextIndexed(a, arg, 16, MMBaseOffset(), 16, FPRClass); - - // Set Tag for ST[i] - SetX87ValidTag(arg, true); - - if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(top, false); - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), _Constant(7)); - SetX87Top(top); - } +void OpDispatchBuilder::X87ATAN(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _F80ATANStack(); } -template -void OpDispatchBuilder::X87UnaryOp(OpcodeArgs) { - auto top = GetX87Top(); - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); - DeriveOp(result, IROp, _F80Round(a)); +void OpDispatchBuilder::FXTRACT(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _F80XTRACTStack(); +} - if constexpr (IROp == IR::OP_F80SIN || IROp == IR::OP_F80COS) { - // TODO: ACCURACY: should check source is in range –2^63 to +2^63 - SetRFLAG(_Constant(0)); +// TODO: The following 3 functions were dealt with by a single templatized +// X80BinaryOp<>. Can we redo it as a template? +void OpDispatchBuilder::F80FPREM(OpcodeArgs) { + CurrentHeader->HasX87 = true; + if (ReducedPrecisionMode && ImplicitFlagClobber(OP_F64FPREM)) { + SaveNZCV(); } - // Write to ST[TOP] - _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass); + _F80FPREMStack(); + // TODO: Set C0 to Q2, C3 to Q1, C1 to Q0 + SetRFLAG(_Constant(0)); } -template void OpDispatchBuilder::X87UnaryOp(OpcodeArgs); -template void OpDispatchBuilder::X87UnaryOp(OpcodeArgs); -template void OpDispatchBuilder::X87UnaryOp(OpcodeArgs); -template void OpDispatchBuilder::X87UnaryOp(OpcodeArgs); - -template -void OpDispatchBuilder::X87BinaryOp(OpcodeArgs) { - auto top = GetX87Top(); - - auto mask = _Constant(7); - Ref st1 = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); - st1 = _LoadContextIndexed(st1, 16, MMBaseOffset(), 16, FPRClass); +void OpDispatchBuilder::F80FPREM1(OpcodeArgs) { + CurrentHeader->HasX87 = true; + if (ReducedPrecisionMode && ImplicitFlagClobber(OP_F64FPREM1)) { + SaveNZCV(); + } - DeriveOp(result, IROp, _F80Add(a, st1)); + _F80FPREM1Stack(); + // TODO: Set C0 to Q2, C3 to Q1, C1 to Q0 + SetRFLAG(_Constant(0)); +} - if constexpr (IROp == IR::OP_F80FPREM || IROp == IR::OP_F80FPREM1) { - // TODO: Set C0 to Q2, C3 to Q1, C1 to Q0 - SetRFLAG(_Constant(0)); +void OpDispatchBuilder::F80SCALE(OpcodeArgs) { + CurrentHeader->HasX87 = true; + if (ReducedPrecisionMode && ImplicitFlagClobber(OP_F64SCALE)) { + SaveNZCV(); } - // Write to ST[TOP] - _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass); + _F80SCALEStack(); } -template void OpDispatchBuilder::X87BinaryOp(OpcodeArgs); -template void OpDispatchBuilder::X87BinaryOp(OpcodeArgs); -template void OpDispatchBuilder::X87BinaryOp(OpcodeArgs); - template void OpDispatchBuilder::X87ModifySTP(OpcodeArgs) { - auto orig_top = GetX87Top(); + CurrentHeader->HasX87 = true; if (Inc) { - auto top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87Top(top); + _IncStackTop(); } else { - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87Top(top); + _DecStackTop(); } } template void OpDispatchBuilder::X87ModifySTP(OpcodeArgs); template void OpDispatchBuilder::X87ModifySTP(OpcodeArgs); -void OpDispatchBuilder::X87SinCos(OpcodeArgs) { - auto orig_top = GetX87Top(); - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87ValidTag(top, true); - SetX87Top(top); - - auto a = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass); - - auto sin = _F80SIN(a); - auto cos = _F80COS(a); +// TODO(pmatos): the next 4 operations used to be abstracted into a UnaryOp templatized op. +// can we abstract it again? +void OpDispatchBuilder::F80SIN(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _F80SINStack(); // TODO: ACCURACY: should check source is in range –2^63 to +2^63 SetRFLAG(_Constant(0)); - - // Write to ST[TOP] - _StoreContextIndexed(sin, orig_top, 16, MMBaseOffset(), 16, FPRClass); - _StoreContextIndexed(cos, top, 16, MMBaseOffset(), 16, FPRClass); -} - -void OpDispatchBuilder::X87FYL2X(OpcodeArgs) { - bool Plus1 = Op->OP == 0x01F9; // FYL2XP - - auto orig_top = GetX87Top(); - // if we are popping then we must first mark this location as empty - SetX87ValidTag(orig_top, false); - auto top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87Top(top); - - Ref st0 = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass); - Ref st1 = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); - - if (Plus1) { - Ref data = LoadAndCacheNamedVectorConstant(16, NamedVectorConstant::NAMED_VECTOR_X87_ONE); - st0 = _F80Add(st0, data); - } - - auto result = _F80FYL2X(st0, st1); - - // Write to ST[TOP] - _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass); } -void OpDispatchBuilder::X87TAN(OpcodeArgs) { - auto orig_top = GetX87Top(); - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87ValidTag(top, true); - SetX87Top(top); - - auto a = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass); - - auto result = _F80TAN(a); - - Ref data = LoadAndCacheNamedVectorConstant(16, NamedVectorConstant::NAMED_VECTOR_X87_ONE); +void OpDispatchBuilder::F80COS(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _F80COSStack(); // TODO: ACCURACY: should check source is in range –2^63 to +2^63 SetRFLAG(_Constant(0)); - - // Write to ST[TOP] - _StoreContextIndexed(result, orig_top, 16, MMBaseOffset(), 16, FPRClass); - _StoreContextIndexed(data, top, 16, MMBaseOffset(), 16, FPRClass); } -void OpDispatchBuilder::X87ATAN(OpcodeArgs) { - auto orig_top = GetX87Top(); - // if we are popping then we must first mark this location as empty - SetX87ValidTag(orig_top, false); - auto top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87Top(top); - - auto a = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass); - Ref st1 = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); - - auto result = _F80ATAN(st1, a); - - // Write to ST[TOP] - _StoreContextIndexed(result, top, 16, MMBaseOffset(), 16, FPRClass); -} - -void OpDispatchBuilder::X87LDENV(OpcodeArgs) { - const auto Size = GetSrcSize(Op); - Ref Mem = MakeSegmentAddress(Op, Op->Src[0]); - - auto NewFCW = _LoadMem(GPRClass, 2, Mem, 2); - _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); - - auto NewFSW = _LoadMem(GPRClass, Size, Mem, _Constant(Size * 1), Size, MEM_OFFSET_SXTX, 1); - ReconstructX87StateFromFSW(NewFSW); - - { - // FTW - SetX87FTW(_LoadMem(GPRClass, Size, Mem, _Constant(Size * 2), Size, MEM_OFFSET_SXTX, 1)); - } -} - -void OpDispatchBuilder::X87FNSTENV(OpcodeArgs) { - // 14 bytes for 16bit - // 2 Bytes : FCW - // 2 Bytes : FSW - // 2 bytes : FTW - // 2 bytes : Instruction offset - // 2 bytes : Instruction CS selector - // 2 bytes : Data offset - // 2 bytes : Data selector - - // 28 bytes for 32bit - // 4 bytes : FCW - // 4 bytes : FSW - // 4 bytes : FTW - // 4 bytes : Instruction pointer - // 2 bytes : instruction pointer selector - // 2 bytes : Opcode - // 4 bytes : data pointer offset - // 4 bytes : data pointer selector - - const auto Size = GetDstSize(Op); - Ref Mem = MakeSegmentAddress(Op, Op->Dest); - - { - auto FCW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FCW)); - _StoreMem(GPRClass, Size, Mem, FCW, Size); - } - - { _StoreMem(GPRClass, Size, ReconstructFSW(), Mem, _Constant(Size * 1), Size, MEM_OFFSET_SXTX, 1); } - - auto ZeroConst = _Constant(0); - - { - // FTW - _StoreMem(GPRClass, Size, GetX87FTW(), Mem, _Constant(Size * 2), Size, MEM_OFFSET_SXTX, 1); - } - - { - // Instruction Offset - _StoreMem(GPRClass, Size, ZeroConst, Mem, _Constant(Size * 3), Size, MEM_OFFSET_SXTX, 1); - } - - { - // Instruction CS selector (+ Opcode) - _StoreMem(GPRClass, Size, ZeroConst, Mem, _Constant(Size * 4), Size, MEM_OFFSET_SXTX, 1); - } - - { - // Data pointer offset - _StoreMem(GPRClass, Size, ZeroConst, Mem, _Constant(Size * 5), Size, MEM_OFFSET_SXTX, 1); - } +void OpDispatchBuilder::X87SinCos(OpcodeArgs) { + CurrentHeader->HasX87 = true; - { - // Data pointer selector - _StoreMem(GPRClass, Size, ZeroConst, Mem, _Constant(Size * 6), Size, MEM_OFFSET_SXTX, 1); + // Compute the sine and cosine of ST(0); replace ST(0) with the approximate sine, and push the approximate cosine onto the register stack. + auto st0 = _ReadStackValue(0); + _F80SINStack(); + if (ReducedPrecisionMode) { + _PushStack(st0, i64Bit, true, 64); + } else { + _PushStack(st0, OpSize::i128Bit, true, 80); } -} + _F80COSStack(); -void OpDispatchBuilder::X87FLDCW(OpcodeArgs) { - Ref NewFCW = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); - _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); + // TODO: ACCURACY: should check source is in range –2^63 to +2^63 + SetRFLAG(_Constant(0)); } -void OpDispatchBuilder::X87FSTCW(OpcodeArgs) { - auto FCW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FCW)); - - StoreResult(GPRClass, Op, FCW, -1); +void OpDispatchBuilder::FRNDINT(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _F80RoundStack(); } -void OpDispatchBuilder::X87LDSW(OpcodeArgs) { - Ref NewFSW = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); - ReconstructX87StateFromFSW(NewFSW); +void OpDispatchBuilder::F80SQRT(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _F80SQRTStack(); } -void OpDispatchBuilder::X87FNSTSW(OpcodeArgs) { - StoreResult(GPRClass, Op, ReconstructFSW(), -1); +void OpDispatchBuilder::F80F2XM1(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _F80F2XM1Stack(); } -void OpDispatchBuilder::X87FNSAVE(OpcodeArgs) { - // 14 bytes for 16bit - // 2 Bytes : FCW - // 2 Bytes : FSW - // 2 bytes : FTW - // 2 bytes : Instruction offset - // 2 bytes : Instruction CS selector - // 2 bytes : Data offset - // 2 bytes : Data selector - - // 28 bytes for 32bit - // 4 bytes : FCW - // 4 bytes : FSW - // 4 bytes : FTW - // 4 bytes : Instruction pointer - // 2 bytes : instruction pointer selector - // 2 bytes : Opcode - // 4 bytes : data pointer offset - // 4 bytes : data pointer selector - - const auto Size = GetDstSize(Op); - Ref Mem = MakeSegmentAddress(Op, Op->Dest); - Ref Top = GetX87Top(); - { - auto FCW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FCW)); - _StoreMem(GPRClass, Size, Mem, FCW, Size); - } - - { _StoreMem(GPRClass, Size, ReconstructFSW(), Mem, _Constant(Size * 1), Size, MEM_OFFSET_SXTX, 1); } - - auto ZeroConst = _Constant(0); - - { - // FTW - _StoreMem(GPRClass, Size, GetX87FTW(), Mem, _Constant(Size * 2), Size, MEM_OFFSET_SXTX, 1); - } - - { - // Instruction Offset - _StoreMem(GPRClass, Size, ZeroConst, Mem, _Constant(Size * 3), Size, MEM_OFFSET_SXTX, 1); - } +// Operations dealing with loading and storing environment pieces - { - // Instruction CS selector (+ Opcode) - _StoreMem(GPRClass, Size, ZeroConst, Mem, _Constant(Size * 4), Size, MEM_OFFSET_SXTX, 1); - } - - { - // Data pointer offset - _StoreMem(GPRClass, Size, ZeroConst, Mem, _Constant(Size * 5), Size, MEM_OFFSET_SXTX, 1); - } - { - // Data pointer selector - _StoreMem(GPRClass, Size, ZeroConst, Mem, _Constant(Size * 6), Size, MEM_OFFSET_SXTX, 1); - } +// Reconstruct as a constant the Status Word of the FPU. +// We only track stack top and each of the code conditions (C flags) +// Top is 3 bits at bit 11. +// C0 is 1 bit at bit 8. +// C1 is 1 bit at bit 9. +// C2 is 1 bit at bit 10. +// C3 is 1 bit at bit 14. +// Optionally we can pass a pre calculated value for Top, otherwise we calculate it +// during the function runtime. +Ref OpDispatchBuilder::ReconstructFSW_Helper(Ref T) { + // We must construct the FSW from our various bits + Ref FSW = _Constant(0); + auto* Top = T ? T : GetX87Top(); + FSW = _Bfi(OpSize::i64Bit, 3, 11, FSW, Top); - auto OneConst = _Constant(1); - auto SevenConst = _Constant(7); - for (int i = 0; i < 7; ++i) { - auto data = _LoadContextIndexed(Top, 16, MMBaseOffset(), 16, FPRClass); - _StoreMem(FPRClass, 16, data, Mem, _Constant((Size * 7) + (10 * i)), 1, MEM_OFFSET_SXTX, 1); - Top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, Top, OneConst), SevenConst); - } + auto* C0 = GetRFLAG(FEXCore::X86State::X87FLAG_C0_LOC); + auto* C1 = GetRFLAG(FEXCore::X86State::X87FLAG_C1_LOC); + auto* C2 = GetRFLAG(FEXCore::X86State::X87FLAG_C2_LOC); + auto* C3 = GetRFLAG(FEXCore::X86State::X87FLAG_C3_LOC); - // The final st(7) needs a bit of special handling here - auto data = _LoadContextIndexed(Top, 16, MMBaseOffset(), 16, FPRClass); - // ST7 broken in to two parts - // Lower 64bits [63:0] - // upper 16 bits [79:64] - _StoreMem(FPRClass, 8, data, Mem, _Constant((Size * 7) + (7 * 10)), 1, MEM_OFFSET_SXTX, 1); - auto topBytes = _VDupElement(16, 2, data, 4); - _StoreMem(FPRClass, 2, topBytes, Mem, _Constant((Size * 7) + (7 * 10) + 8), 1, MEM_OFFSET_SXTX, 1); + FSW = _Orlshl(OpSize::i64Bit, FSW, C0, 8); + FSW = _Orlshl(OpSize::i64Bit, FSW, C1, 9); + FSW = _Orlshl(OpSize::i64Bit, FSW, C2, 10); + FSW = _Orlshl(OpSize::i64Bit, FSW, C3, 14); + return FSW; +} - // reset to default - FNINIT(Op); +// Store Status Word +// There's no load Status Word instruction +void OpDispatchBuilder::X87FNSTSW(OpcodeArgs) { + CurrentHeader->HasX87 = true; + Ref TopValue = _SyncStackToSlow(); + Ref StatusWord = ReconstructFSW_Helper(TopValue); + StoreResult(GPRClass, Op, StatusWord, -1); } -void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) { - const auto Size = GetSrcSize(Op); - Ref Mem = MakeSegmentAddress(Op, Op->Src[0]); +void OpDispatchBuilder::FNINIT(OpcodeArgs) { + CurrentHeader->HasX87 = true; + auto Zero = _Constant(0); - auto NewFCW = _LoadMem(GPRClass, 2, Mem, 2); + // Init FCW to 0x037F + auto NewFCW = _Constant(16, 0x037F); _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); - auto NewFSW = _LoadMem(GPRClass, Size, Mem, _Constant(Size * 1), Size, MEM_OFFSET_SXTX, 1); - auto Top = ReconstructX87StateFromFSW(NewFSW); - { - // FTW - SetX87FTW(_LoadMem(GPRClass, Size, Mem, _Constant(Size * 2), Size, MEM_OFFSET_SXTX, 1)); - } - - auto OneConst = _Constant(1); - auto SevenConst = _Constant(7); - - auto low = _Constant(~0ULL); - auto high = _Constant(0xFFFF); - Ref Mask = _VCastFromGPR(16, 8, low); - Mask = _VInsGPR(16, 8, 1, Mask, high); - - for (int i = 0; i < 7; ++i) { - Ref Reg = _LoadMem(FPRClass, 16, Mem, _Constant((Size * 7) + (10 * i)), 1, MEM_OFFSET_SXTX, 1); - // Mask off the top bits - Reg = _VAnd(16, 16, Reg, Mask); - - _StoreContextIndexed(Reg, Top, 16, MMBaseOffset(), 16, FPRClass); - - Top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, Top, OneConst), SevenConst); - } + // Set top to zero + SetX87Top(Zero); + // Tags all get marked as invalid + _StoreContext(1, GPRClass, Zero, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); - // The final st(7) needs a bit of special handling here - // ST7 broken in to two parts - // Lower 64bits [63:0] - // upper 16 bits [79:64] + // Reinits the simulated stack + _InitStack(); - Ref Reg = _LoadMem(FPRClass, 8, Mem, _Constant((Size * 7) + (10 * 7)), 1, MEM_OFFSET_SXTX, 1); - Ref RegHigh = _LoadMem(FPRClass, 2, Mem, _Constant((Size * 7) + (10 * 7) + 8), 1, MEM_OFFSET_SXTX, 1); - Reg = _VInsElement(16, 2, 4, 0, Reg, RegHigh); - _StoreContextIndexed(Reg, Top, 16, MMBaseOffset(), 16, FPRClass); + SetRFLAG(Zero); + SetRFLAG(Zero); + SetRFLAG(Zero); + SetRFLAG(Zero); } -void OpDispatchBuilder::X87FXAM(OpcodeArgs) { - auto top = GetX87Top(); - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); - Ref Result = _VExtractToGPR(16, 8, a, 1); - - // Extract the sign bit - Result = _Bfe(OpSize::i64Bit, 1, 15, Result); - SetRFLAG(Result); - - // Claim this is a normal number - // We don't support anything else - auto TopValid = GetX87ValidTag(top); - auto ZeroConst = _Constant(0); - auto OneConst = _Constant(1); - - // In the case of top being invalid then C3:C2:C0 is 0b101 - auto C3 = _Select(FEXCore::IR::COND_NEQ, TopValid, OneConst, OneConst, ZeroConst); +void OpDispatchBuilder::X87FFREE(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _InvalidateStack(Op->OP & 7); +} - auto C2 = TopValid; - auto C0 = C3; // Mirror C3 until something other than zero is supported - SetRFLAG(C0); - SetRFLAG(C2); - SetRFLAG(C3); +void OpDispatchBuilder::X87EMMS(OpcodeArgs) { + // Tags all get set to 0b11 + CurrentHeader->HasX87 = true; + _InvalidateStack(0xff); } void OpDispatchBuilder::X87FCMOV(OpcodeArgs) { + CurrentHeader->HasX87 = true; CalculateDeferredFlags(); uint16_t Opcode = Op->OP & 0b1111'1111'1000; @@ -1195,39 +1110,40 @@ void OpDispatchBuilder::X87FCMOV(OpcodeArgs) { Ref SrcCond = SelectCC(CC, OpSize::i64Bit, AllOneConst, ZeroConst); Ref VecCond = _VDupFromGPR(16, 8, SrcCond); + _F80VBSLStack(16, VecCond, Op->OP & 7, 0); +} - auto top = GetX87Top(); - Ref arg; +void OpDispatchBuilder::X87FXAM(OpcodeArgs) { + CurrentHeader->HasX87 = true; - auto mask = _Constant(7); + auto a = _ReadStackValue(0); + Ref Result = ReducedPrecisionMode ? _VExtractToGPR(8, 8, a, 0) : _VExtractToGPR(16, 8, a, 1); - // Implicit arg - auto offset = _Constant(Op->OP & 7); - arg = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), mask); + // Extract the sign bit + Result = ReducedPrecisionMode ? _Bfe(OpSize::i64Bit, 1, 63, Result) : _Bfe(OpSize::i64Bit, 1, 15, Result); + SetRFLAG(Result); - auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass); - auto b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass); - auto Result = _VBSL(16, VecCond, b, a); + // Claim this is a normal number + // We don't support anything else + auto TopValid = _StackValidTag(0); + auto ZeroConst = _Constant(0); + auto OneConst = _Constant(1); - // Write to ST[TOP] - _StoreContextIndexed(Result, top, 16, MMBaseOffset(), 16, FPRClass); -} + // In the case of top being invalid then C3:C2:C0 is 0b101 + auto C3 = _Select(FEXCore::IR::COND_NEQ, TopValid, OneConst, OneConst, ZeroConst); -void OpDispatchBuilder::X87EMMS(OpcodeArgs) { - // Tags all get set to 0b11 - _StoreContext(1, GPRClass, _Constant(0), offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + auto C2 = TopValid; + auto C0 = C3; // Mirror C3 until something other than zero is supported + SetRFLAG(C0); + SetRFLAG(C2); + SetRFLAG(C3); } -void OpDispatchBuilder::X87FFREE(OpcodeArgs) { - // Only sets the selected stack register's tag bits to EMPTY - Ref top = GetX87Top(); - - // Implicit arg - auto offset = _Constant(Op->OP & 7); - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), _Constant(7)); +void OpDispatchBuilder::X87TAN(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _F80PTANStack(); - // Set this argument's tag as empty now - SetX87ValidTag(top, false); + // TODO: ACCURACY: should check source is in range –2^63 to +2^63 + SetRFLAG(_Constant(0)); } - } // namespace FEXCore::IR diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp index 96d2f35773..6ba116133a 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp @@ -40,10 +40,13 @@ class OrderedNode; // FXCH // FCMOV // FST(register to register) +// FCHS // State loading duplicated from X87.cpp, setting host rounding mode // See issue void OpDispatchBuilder::FNINITF64(OpcodeArgs) { + // FIXME: almost a duplicate of x87 version. + CurrentHeader->HasX87 = true; // Init FCW to 0x037F auto NewFCW = _Constant(16, 0x037F); // Init host rounding mode to zero @@ -53,17 +56,21 @@ void OpDispatchBuilder::FNINITF64(OpcodeArgs) { // Init FSW to 0 SetX87Top(Zero); + // Tags all get marked as invalid + _StoreContext(1, GPRClass, Zero, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + + _InitStack(); SetRFLAG(Zero); SetRFLAG(Zero); SetRFLAG(Zero); SetRFLAG(Zero); - - // Tags all get marked as invalid - _StoreContext(1, GPRClass, Zero, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); } void OpDispatchBuilder::X87LDENVF64(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _StackForceSlow(); + const auto Size = GetSrcSize(Op); Ref Mem = MakeSegmentAddress(Op, Op->Src[0]); @@ -75,7 +82,7 @@ void OpDispatchBuilder::X87LDENVF64(OpcodeArgs) { _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); auto NewFSW = _LoadMem(GPRClass, Size, Mem, _Constant(Size * 1), Size, MEM_OFFSET_SXTX, 1); - ReconstructX87StateFromFSW(NewFSW); + ReconstructX87StateFromFSW_Helper(NewFSW); { // FTW @@ -85,6 +92,9 @@ void OpDispatchBuilder::X87LDENVF64(OpcodeArgs) { void OpDispatchBuilder::X87FLDCWF64(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _StackForceSlow(); + Ref NewFCW = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); // ignore the rounding precision, we're always 64-bit in F64. // extract rounding mode @@ -94,42 +104,29 @@ void OpDispatchBuilder::X87FLDCWF64(OpcodeArgs) { } // F64 ops - template void OpDispatchBuilder::FLDF64(OpcodeArgs) { - // Update TOP - auto orig_top = GetX87Top(); - auto mask = _Constant(7); + static_assert(width == 32 || width == 64 || width == 80, "Unsupported FLD width"); + CurrentHeader->HasX87 = true; size_t read_width = (width == 80) ? 16 : width / 8; - Ref data {}; - Ref converted {}; - if (!Op->Src[0].IsNone()) { + if (Op->Src[0].IsNone()) { + // Implicit arg + data = _ReadStackValue(Op->OP & 7); + } else { // Read from memory data = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], read_width, Op->Flags); - // Convert to 64bit float + + // Convert to 80bit float if constexpr (width == 32) { - converted = _Float_FToF(8, 4, data); + data = _Float_FToF(8, 4, data); } else if constexpr (width == 80) { - converted = _F80CVT(8, data); - } else { - converted = data; + data = _F80CVT(8, data); } - } else { - // Implicit arg (does this need to change with width?) - auto offset = _Constant(Op->OP & 7); - data = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, orig_top, offset), mask); - data = _LoadContextIndexed(data, 8, MMBaseOffset(), 16, FPRClass); - converted = data; - } - - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), mask); - SetX87ValidTag(top, true); - SetX87Top(top); - // Write to ST[TOP] - _StoreContextIndexed(converted, top, 8, MMBaseOffset(), 16, FPRClass); + } + _PushStack(data, OpSize::i64Bit, true, read_width); } template void OpDispatchBuilder::FLDF64<32>(OpcodeArgs); @@ -137,45 +134,28 @@ template void OpDispatchBuilder::FLDF64<64>(OpcodeArgs); template void OpDispatchBuilder::FLDF64<80>(OpcodeArgs); void OpDispatchBuilder::FBLDF64(OpcodeArgs) { - // Update TOP - auto orig_top = GetX87Top(); - auto mask = _Constant(7); - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), mask); - SetX87ValidTag(top, true); - SetX87Top(top); - + CurrentHeader->HasX87 = true; // Read from memory Ref data = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], 16, Op->Flags); Ref converted = _F80BCDLoad(data); converted = _F80CVT(8, converted); - _StoreContextIndexed(converted, top, 8, MMBaseOffset(), 16, FPRClass); + _PushStack(converted, i64Bit, true, 8); } void OpDispatchBuilder::FBSTPF64(OpcodeArgs) { - auto orig_top = GetX87Top(); - auto data = _LoadContextIndexed(orig_top, 8, MMBaseOffset(), 16, FPRClass); - - Ref converted = _F80CVTTo(data, 8); + CurrentHeader->HasX87 = true; + Ref converted = _F80CVTTo(_ReadStackValue(0), 8); converted = _F80BCDStore(converted); - StoreResult_WithOpSize(FPRClass, Op, Op->Dest, converted, 10, 1); - - // if we are popping then we must first mark this location as empty - SetX87ValidTag(orig_top, false); - auto top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87Top(top); + _PopStackDestroy(); } template void OpDispatchBuilder::FLDF64_Const(OpcodeArgs) { - // Update TOP - auto orig_top = GetX87Top(); - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87ValidTag(top, true); - SetX87Top(top); + CurrentHeader->HasX87 = true; + auto data = _VCastFromGPR(8, 8, _Constant(num)); - // Write to ST[TOP] - _StoreContextIndexed(data, top, 8, MMBaseOffset(), 16, FPRClass); + _PushStack(data, OpSize::i64Bit, true, 8); } template void OpDispatchBuilder::FLDF64_Const<0x3FF0000000000000>(OpcodeArgs); // 1.0 @@ -187,46 +167,35 @@ template void OpDispatchBuilder::FLDF64_Const<0x3FE62E42FEFA39EF>(OpcodeArgs); / template void OpDispatchBuilder::FLDF64_Const<0>(OpcodeArgs); // 0.0 void OpDispatchBuilder::FILDF64(OpcodeArgs) { - // Update TOP - auto orig_top = GetX87Top(); - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87ValidTag(top, true); - SetX87Top(top); - + CurrentHeader->HasX87 = true; size_t read_width = GetSrcSize(Op); + // Read from memory - auto data = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], read_width, Op->Flags); + Ref data = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], read_width, Op->Flags); if (read_width == 2) { data = _Sbfe(OpSize::i64Bit, read_width * 8, 0, data); } auto converted = _Float_FromGPR_S(8, read_width == 4 ? 4 : 8, data); - // Write to ST[TOP] - _StoreContextIndexed(converted, top, 8, MMBaseOffset(), 16, FPRClass); + _PushStack(converted, i64Bit, false, read_width); } template void OpDispatchBuilder::FSTF64(OpcodeArgs) { - auto orig_top = GetX87Top(); - auto data = _LoadContextIndexed(orig_top, 8, MMBaseOffset(), 16, FPRClass); - if constexpr (width == 64) { - // Store 64-bit float directly - StoreResult_WithOpSize(FPRClass, Op, Op->Dest, data, 8, 1); - } else if constexpr (width == 32) { - // Convert to 32-bit float and store - auto result = _Float_FToF(4, 8, data); - StoreResult_WithOpSize(FPRClass, Op, Op->Dest, result, 4, 1); - } else if constexpr (width == 80) { - // Convert to 80-bit float - auto result = _F80CVTTo(data, 8); - StoreResult_WithOpSize(FPRClass, Op, Op->Dest, result, 10, 1); + + static_assert(width == 32 || width == 64 || width == 80, "Unsupported FST width"); + CurrentHeader->HasX87 = true; + + if (Op->Src[0].IsNone()) { // Destination is stack + // FIXME: Why is this case not in x87f64 upstream code? + auto offset = Op->OP & 7; + _StoreStackToStack(offset); + } else { + Ref Mem = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.LoadData = false}); + _StoreStackMemory(Mem, OpSize::i64Bit, true, width / 8); } - if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(orig_top, false); - // Set the new top now - auto top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87Top(top); + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); } } @@ -236,10 +205,10 @@ template void OpDispatchBuilder::FSTF64<80>(OpcodeArgs); template void OpDispatchBuilder::FISTF64(OpcodeArgs) { + CurrentHeader->HasX87 = true; auto Size = GetSrcSize(Op); - auto orig_top = GetX87Top(); - Ref data = _LoadContextIndexed(orig_top, 8, MMBaseOffset(), 16, FPRClass); + Ref data = _ReadStackValue(0); if constexpr (Truncate) { data = _Float_ToGPR_ZS(Size == 4 ? 4 : 8, 8, data); } else { @@ -248,11 +217,7 @@ void OpDispatchBuilder::FISTF64(OpcodeArgs) { StoreResult_WithOpSize(GPRClass, Op, Op->Dest, data, Size, 1); if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(orig_top, false); - // Set the new top now - auto top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87Top(top); + _PopStackDestroy(); } } @@ -261,50 +226,46 @@ template void OpDispatchBuilder::FISTF64(OpcodeArgs); template void OpDispatchBuilder::FADDF64(OpcodeArgs) { - auto top = GetX87Top(); - Ref StackLocation = top; - - Ref arg {}; - Ref b {}; + static_assert(width == 16 || width == 32 || width == 64 || width == 80, "Unsupported FADD width"); - auto mask = _Constant(7); + CurrentHeader->HasX87 = true; - if (!Op->Src[0].IsNone()) { - // Memory arg - if constexpr (Integer) { - arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); - if (width == 16) { - arg = _Sbfe(OpSize::i64Bit, 16, 0, arg); - } - b = _Float_FromGPR_S(8, width == 64 ? 8 : 4, arg); - } else if constexpr (width == 32) { - arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - b = _Float_FToF(8, 4, arg); - } else if constexpr (width == 64) { - b = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - } - } else { - // Implicit arg - auto offset = _Constant(Op->OP & 7); - arg = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), mask); + if (Op->Src[0].IsNone()) { // Implicit argument case + auto offset = Op->OP & 7; + auto st0 = 0; if constexpr (ResInST0 == OpResult::RES_STI) { - StackLocation = arg; + _F80AddStack(offset, st0); + } else { + _F80AddStack(st0, offset); + } + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); } - b = _LoadContextIndexed(arg, 8, MMBaseOffset(), 16, FPRClass); + return; } - auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - auto result = _VFAdd(8, 8, a, b); - if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(top, false); - // Set the new top now - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87Top(top); + // We have one memory argument + Ref arg {}; + + if constexpr (Integer) { + arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); + if (width == 16) { + arg = _Sbfe(OpSize::i64Bit, 16, 0, arg); + } + arg = _Float_FromGPR_S(8, width == 64 ? 8 : 4, arg); + } else if constexpr (width == 32) { + arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); + arg = _Float_FToF(8, 4, arg); + } else if constexpr (width == 64) { + arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); } - // Write to ST[TOP] - _StoreContextIndexed(result, StackLocation, 8, MMBaseOffset(), 16, FPRClass); + // top of stack is at offset zero + _F80AddValue(0, arg); + + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); + } } template void OpDispatchBuilder::FADDF64<32, false, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); @@ -315,54 +276,49 @@ template void OpDispatchBuilder::FADDF64<80, false, OpDispatchBuilder::OpResult: template void OpDispatchBuilder::FADDF64<16, true, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); template void OpDispatchBuilder::FADDF64<32, true, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); +// FIXME: following is very similar to FADDF64 template void OpDispatchBuilder::FMULF64(OpcodeArgs) { - auto top = GetX87Top(); - Ref StackLocation = top; - Ref arg {}; - Ref b {}; + static_assert(width == 16 || width == 32 || width == 64 || width == 80, "Unsupported FMUL width"); - auto mask = _Constant(7); + CurrentHeader->HasX87 = true; - if (!Op->Src[0].IsNone()) { - // Memory arg - if constexpr (Integer) { - arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); - if (width == 16) { - arg = _Sbfe(OpSize::i64Bit, 16, 0, arg); - } - b = _Float_FromGPR_S(8, width == 64 ? 8 : 4, arg); - } else if constexpr (width == 32) { - arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - b = _Float_FToF(8, 4, arg); - } else if constexpr (width == 64) { - b = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - } - } else { - // Implicit arg - auto offset = _Constant(Op->OP & 7); - arg = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), mask); + if (Op->Src[0].IsNone()) { // Implicit argument case + auto offset = Op->OP & 7; + auto st0 = 0; if constexpr (ResInST0 == OpResult::RES_STI) { - StackLocation = arg; + _F80MulStack(offset, st0); + } else { + _F80MulStack(st0, offset); } - - b = _LoadContextIndexed(arg, 8, MMBaseOffset(), 16, FPRClass); + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); + } + return; } - auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - - auto result = _VFMul(8, 8, a, b); + // We have one memory argument + Ref arg {}; - if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(top, false); - // Set the new top now - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87Top(top); + if constexpr (Integer) { + arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); + if (width == 16) { + arg = _Sbfe(OpSize::i64Bit, 16, 0, arg); + } + arg = _Float_FromGPR_S(8, width == 64 ? 8 : 4, arg); + } else if constexpr (width == 32) { + arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); + arg = _Float_FToF(8, 4, arg); + } else if constexpr (width == 64) { + arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); } - // Write to ST[TOP] - _StoreContextIndexed(result, StackLocation, 8, MMBaseOffset(), 16, FPRClass); + // top of stack is at offset zero + _F80MulValue(0, arg); + + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); + } } template void OpDispatchBuilder::FMULF64<32, false, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); @@ -375,57 +331,61 @@ template void OpDispatchBuilder::FMULF64<32, true, OpDispatchBuilder::OpResult:: template void OpDispatchBuilder::FDIVF64(OpcodeArgs) { - auto top = GetX87Top(); - Ref StackLocation = top; - Ref arg {}; - Ref b {}; + static_assert(width == 16 || width == 32 || width == 64 || width == 80, "Unsupported FDIV width"); + CurrentHeader->HasX87 = true; + + if (Op->Src[0].IsNone()) { + const auto offset = Op->OP & 7; + const auto st0 = 0; + + if constexpr (reverse) { + if constexpr (ResInST0 == OpResult::RES_STI) { + _F80DivStack(offset, st0, offset); + } else { + _F80DivStack(st0, offset, st0); + } + } else { + if constexpr (ResInST0 == OpResult::RES_STI) { + _F80DivStack(offset, offset, st0); + } else { + _F80DivStack(st0, st0, offset); + } + } - auto mask = _Constant(7); + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); + } + return; + } - if (!Op->Src[0].IsNone()) { - // Memory arg + // We have one memory argument + Ref arg {}; + + if constexpr (width == 16 || width == 32 || width == 64) { if constexpr (Integer) { arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); if (width == 16) { arg = _Sbfe(OpSize::i64Bit, 16, 0, arg); } - b = _Float_FromGPR_S(8, width == 64 ? 8 : 4, arg); + arg = _Float_FromGPR_S(8, width == 64 ? 8 : 4, arg); } else if constexpr (width == 32) { arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - b = _Float_FToF(8, 4, arg); + arg = _Float_FToF(8, 4, arg); } else if constexpr (width == 64) { - b = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - } - } else { - // Implicit arg - auto offset = _Constant(Op->OP & 7); - arg = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), mask); - if constexpr (ResInST0 == OpResult::RES_STI) { - StackLocation = arg; + arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); } - - b = _LoadContextIndexed(arg, 8, MMBaseOffset(), 16, FPRClass); } - auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - - Ref result {}; + // top of stack is at offset zero if constexpr (reverse) { - result = _VFDiv(8, 8, b, a); + _F80DivRValue(arg, 0); } else { - result = _VFDiv(8, 8, a, b); + _F80DivValue(0, arg); } - if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(top, false); - // Set the new top now - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87Top(top); + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); } - - // Write to ST[TOP] - _StoreContextIndexed(result, StackLocation, 8, MMBaseOffset(), 16, FPRClass); } template void OpDispatchBuilder::FDIVF64<32, false, false, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); @@ -446,60 +406,64 @@ template void OpDispatchBuilder::FDIVF64<16, true, true, OpDispatchBuilder::OpRe template void OpDispatchBuilder::FDIVF64<32, true, false, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); template void OpDispatchBuilder::FDIVF64<32, true, true, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); + template void OpDispatchBuilder::FSUBF64(OpcodeArgs) { - auto top = GetX87Top(); - Ref StackLocation = top; - Ref arg {}; - Ref b {}; + static_assert(width == 16 || width == 32 || width == 64 || width == 80, "Unsupported FSUB width"); + CurrentHeader->HasX87 = true; + + if (Op->Src[0].IsNone()) { + const auto offset = Op->OP & 7; + const auto st0 = 0; + + if constexpr (reverse) { + if constexpr (ResInST0 == OpResult::RES_STI) { + _F80SubStack(offset, st0, offset); + } else { + _F80SubStack(st0, offset, st0); + } + } else { + if constexpr (ResInST0 == OpResult::RES_STI) { + _F80SubStack(offset, offset, st0); + } else { + _F80SubStack(st0, st0, offset); + } + } - auto mask = _Constant(7); + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); + } + return; + } - if (!Op->Src[0].IsNone()) { - // Memory arg + // We have one memory argument + Ref arg {}; + + if constexpr (width == 16 || width == 32 || width == 64) { if constexpr (Integer) { arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); if (width == 16) { arg = _Sbfe(OpSize::i64Bit, 16, 0, arg); } - b = _Float_FromGPR_S(8, width == 64 ? 8 : 4, arg); + arg = _Float_FromGPR_S(8, width == 64 ? 8 : 4, arg); } else if constexpr (width == 32) { arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - b = _Float_FToF(8, 4, arg); + arg = _Float_FToF(8, 4, arg); } else if constexpr (width == 64) { - b = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - } - } else { - // Implicit arg - auto offset = _Constant(Op->OP & 7); - arg = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), mask); - if constexpr (ResInST0 == OpResult::RES_STI) { - StackLocation = arg; + arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); } - - b = _LoadContextIndexed(arg, 8, MMBaseOffset(), 16, FPRClass); } - auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - - Ref result {}; + // top of stack is at offset zero if constexpr (reverse) { - result = _VFSub(8, 8, b, a); + _F80SubRValue(arg, 0); } else { - result = _VFSub(8, 8, a, b); + _F80SubValue(0, arg); } - if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(top, false); - // Set the new top now - - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87Top(top); + if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) { + _PopStackDestroy(); } - - // Write to ST[TOP] - _StoreContextIndexed(result, StackLocation, 8, MMBaseOffset(), 16, FPRClass); } template void OpDispatchBuilder::FSUBF64<32, false, false, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); @@ -520,126 +484,65 @@ template void OpDispatchBuilder::FSUBF64<16, true, true, OpDispatchBuilder::OpRe template void OpDispatchBuilder::FSUBF64<32, true, false, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); template void OpDispatchBuilder::FSUBF64<32, true, true, OpDispatchBuilder::OpResult::RES_ST0>(OpcodeArgs); -void OpDispatchBuilder::FCHSF64(OpcodeArgs) { - auto top = GetX87Top(); - auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - auto result = _VFNeg(8, 8, a); - // Write to ST[TOP] - _StoreContextIndexed(result, top, 8, MMBaseOffset(), 16, FPRClass); -} - -void OpDispatchBuilder::FABSF64(OpcodeArgs) { - auto top = GetX87Top(); - auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - auto result = _VFAbs(8, 8, a); - // Write to ST[TOP] - _StoreContextIndexed(result, top, 8, MMBaseOffset(), 16, FPRClass); -} void OpDispatchBuilder::FTSTF64(OpcodeArgs) { - auto top = GetX87Top(); - auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - - auto low = _Constant(0); - Ref data = _VCastFromGPR(8, 8, low); + CurrentHeader->HasX87 = true; // We are going to clobber NZCV, make sure it's in a GPR first. GetNZCV(); // Now we do our comparison. - _FCmp(8, a, data); + _F80StackTest(0, 0 /*No flags in reduced precision mode needed*/); PossiblySetNZCVBits = ~0; ConvertNZCVToX87(); } -// TODO: This should obey rounding mode -void OpDispatchBuilder::FRNDINTF64(OpcodeArgs) { - auto top = GetX87Top(); - auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - - auto result = _Vector_FToI(8, 8, a, FEXCore::IR::Round_Host); - - // Write to ST[TOP] - _StoreContextIndexed(result, top, 8, MMBaseOffset(), 16, FPRClass); -} - -void OpDispatchBuilder::FXTRACTF64(OpcodeArgs) { - auto orig_top = GetX87Top(); - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87ValidTag(top, true); - SetX87Top(top); - - auto a = _LoadContextIndexed(orig_top, 8, MMBaseOffset(), 16, FPRClass); - auto gpr = _VExtractToGPR(8, 8, a, 0); - Ref exp = _And(OpSize::i64Bit, gpr, _Constant(0x7ff0000000000000LL)); - exp = _Lshr(OpSize::i64Bit, exp, _Constant(52)); - exp = _Sub(OpSize::i64Bit, exp, _Constant(1023)); - exp = _Float_FromGPR_S(8, 8, exp); - Ref sig = _And(OpSize::i64Bit, gpr, _Constant(0x800fffffffffffffLL)); - sig = _Or(OpSize::i64Bit, sig, _Constant(0x3ff0000000000000LL)); - sig = _VCastFromGPR(8, 8, sig); - // Write to ST[TOP] - _StoreContextIndexed(exp, orig_top, 8, MMBaseOffset(), 16, FPRClass); - _StoreContextIndexed(sig, top, 8, MMBaseOffset(), 16, FPRClass); -} - - template void OpDispatchBuilder::FCOMIF64(OpcodeArgs) { - auto top = GetX87Top(); - auto mask = _Constant(7); - + CurrentHeader->HasX87 = true; Ref arg {}; Ref b {}; - if (!Op->Src[0].IsNone()) { + if (Op->Src[0].IsNone()) { + // Implicit arg + uint8_t offset = Op->OP & 7; + b = _ReadStackValue(offset); + } else { // Memory arg - if constexpr (Integer) { - arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); - if (width == 16) { - arg = _Sbfe(OpSize::i64Bit, 16, 0, arg); + if constexpr (width == 16 || width == 32 || width == 64) { + if constexpr (Integer) { + arg = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); + if (width == 16) { + arg = _Sbfe(OpSize::i64Bit, 16, 0, arg); + } + b = _Float_FromGPR_S(8, width == 64 ? 8 : 4, arg); + } else if constexpr (width == 32) { + arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); + b = _Float_FToF(8, 4, arg); + } else if constexpr (width == 64) { + b = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); } - b = _Float_FromGPR_S(8, width == 64 ? 8 : 4, arg); - } else if constexpr (width == 32) { - arg = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - b = _Float_FToF(8, 4, arg); - } else if constexpr (width == 64) { - b = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); } - } else { - // Implicit arg - auto offset = _Constant(Op->OP & 7); - arg = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, offset), mask); - b = _LoadContextIndexed(arg, 8, MMBaseOffset(), 16, FPRClass); } - auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - if constexpr (whichflags == FCOMIFlags::FLAGS_X87) { // We are going to clobber NZCV, make sure it's in a GPR first. GetNZCV(); - _FCmp(8, a, b); + _F80CmpValue(b, 0 /*Flags are unused in x87f64*/); PossiblySetNZCVBits = ~0; ConvertNZCVToX87(); } else { - Comiss(8, a, b, true /* InvalidateAF */); + HandleNZCVWrite(); + _F80CmpValue(b, 0 /*Flags are unused in x87f64*/); + ComissFlags(true /* InvalidateAF */); } if constexpr (poptwice) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(top, false); - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87ValidTag(top, false); - // Set the new top now - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87Top(top); + _PopStackDestroy(); + _PopStackDestroy(); } else if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) { - // if we are popping then we must first mark this location as empty - SetX87ValidTag(top, false); - // Set the new top now - top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - SetX87Top(top); + _PopStackDestroy(); } } @@ -655,145 +558,24 @@ template void OpDispatchBuilder::FCOMIF64<16, true, OpDispatchBuilder::FCOMIFlag template void OpDispatchBuilder::FCOMIF64<32, true, OpDispatchBuilder::FCOMIFlags::FLAGS_X87, false>(OpcodeArgs); - -void OpDispatchBuilder::FSQRTF64(OpcodeArgs) { - auto top = GetX87Top(); - auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - - auto result = _VFSqrt(8, 8, a); - - // Write to ST[TOP] - _StoreContextIndexed(result, top, 8, MMBaseOffset(), 16, FPRClass); -} - - -template -void OpDispatchBuilder::X87UnaryOpF64(OpcodeArgs) { - auto top = GetX87Top(); - auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - - DeriveOp(result, IROp, _F64SIN(a)); - - if constexpr (IROp == IR::OP_F64SIN || IROp == IR::OP_F64COS) { - // TODO: ACCURACY: should check source is in range –2^63 to +2^63 - SetRFLAG(_Constant(0)); - } - - // Write to ST[TOP] - _StoreContextIndexed(result, top, 8, MMBaseOffset(), 16, FPRClass); -} - -template void OpDispatchBuilder::X87UnaryOpF64(OpcodeArgs); -template void OpDispatchBuilder::X87UnaryOpF64(OpcodeArgs); -template void OpDispatchBuilder::X87UnaryOpF64(OpcodeArgs); - - -template -void OpDispatchBuilder::X87BinaryOpF64(OpcodeArgs) { - auto top = GetX87Top(); - - auto mask = _Constant(7); - Ref st1 = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, top, _Constant(1)), mask); - - auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - st1 = _LoadContextIndexed(st1, 8, MMBaseOffset(), 16, FPRClass); - - DeriveOp(result, IROp, _F64ATAN(a, st1)); - - if constexpr (IROp == IR::OP_F64FPREM || IROp == IR::OP_F64FPREM1) { - // TODO: Set C0 to Q2, C3 to Q1, C1 to Q0 - SetRFLAG(_Constant(0)); - } - - // Write to ST[TOP] - _StoreContextIndexed(result, top, 8, MMBaseOffset(), 16, FPRClass); -} - -template void OpDispatchBuilder::X87BinaryOpF64(OpcodeArgs); -template void OpDispatchBuilder::X87BinaryOpF64(OpcodeArgs); -template void OpDispatchBuilder::X87BinaryOpF64(OpcodeArgs); - -void OpDispatchBuilder::X87SinCosF64(OpcodeArgs) { - auto orig_top = GetX87Top(); - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87ValidTag(top, true); - SetX87Top(top); - - auto a = _LoadContextIndexed(orig_top, 8, MMBaseOffset(), 16, FPRClass); - - auto sin = _F64SIN(a); - auto cos = _F64COS(a); - - // TODO: ACCURACY: should check source is in range –2^63 to +2^63 - SetRFLAG(_Constant(0)); - - // Write to ST[TOP] - _StoreContextIndexed(sin, orig_top, 8, MMBaseOffset(), 16, FPRClass); - _StoreContextIndexed(cos, top, 8, MMBaseOffset(), 16, FPRClass); -} - void OpDispatchBuilder::X87FYL2XF64(OpcodeArgs) { - bool Plus1 = Op->OP == 0x01F9; // FYL2XP + CurrentHeader->HasX87 = true; - auto orig_top = GetX87Top(); - // if we are popping then we must first mark this location as empty - SetX87ValidTag(orig_top, false); - auto top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87Top(top); - - Ref st0 = _LoadContextIndexed(orig_top, 8, MMBaseOffset(), 16, FPRClass); - Ref st1 = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - - if (Plus1) { - auto one = _VCastFromGPR(8, 8, _Constant(0x3FF0000000000000)); - st0 = _VFAdd(8, 8, st0, one); + if (Op->OP == 0x01F9) { // fyl2xp1 + // create an add between top of stack and 1. + Ref One = _VCastFromGPR(8, 8, _Constant(0x3FF0000000000000)); + _F80AddValue(0, One); } - auto result = _F64FYL2X(st0, st1); - - // Write to ST[TOP] - _StoreContextIndexed(result, top, 8, MMBaseOffset(), 16, FPRClass); -} - -void OpDispatchBuilder::X87TANF64(OpcodeArgs) { - auto orig_top = GetX87Top(); - auto top = _And(OpSize::i32Bit, _Sub(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87ValidTag(top, true); - SetX87Top(top); - - auto a = _LoadContextIndexed(orig_top, 8, MMBaseOffset(), 16, FPRClass); - - auto result = _F64TAN(a); - - auto one = _VCastFromGPR(8, 8, _Constant(0x3FF0000000000000)); - - // TODO: ACCURACY: should check source is in range –2^63 to +2^63 - SetRFLAG(_Constant(0)); - - // Write to ST[TOP] - _StoreContextIndexed(result, orig_top, 8, MMBaseOffset(), 16, FPRClass); - _StoreContextIndexed(one, top, 8, MMBaseOffset(), 16, FPRClass); + _F80StackFYL2X(); } -void OpDispatchBuilder::X87ATANF64(OpcodeArgs) { - auto orig_top = GetX87Top(); - // if we are popping then we must first mark this location as empty - SetX87ValidTag(orig_top, false); - auto top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, orig_top, _Constant(1)), _Constant(7)); - SetX87Top(top); - - auto a = _LoadContextIndexed(orig_top, 8, MMBaseOffset(), 16, FPRClass); - Ref st1 = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - - auto result = _F64ATAN(st1, a); - - // Write to ST[TOP] - _StoreContextIndexed(result, top, 8, MMBaseOffset(), 16, FPRClass); -} // This function converts to F80 on save for compatibility void OpDispatchBuilder::X87FNSAVEF64(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _SyncStackToSlow(); // 14 bytes for 16bit // 2 Bytes : FCW // 2 Bytes : FSW @@ -821,13 +603,13 @@ void OpDispatchBuilder::X87FNSAVEF64(OpcodeArgs) { _StoreMem(GPRClass, Size, Mem, FCW, Size); } - { _StoreMem(GPRClass, Size, ReconstructFSW(), Mem, _Constant(Size * 1), Size, MEM_OFFSET_SXTX, 1); } + { _StoreMem(GPRClass, Size, ReconstructFSW_Helper(), Mem, _Constant(Size * 1), Size, MEM_OFFSET_SXTX, 1); } auto ZeroConst = _Constant(0); { // FTW - _StoreMem(GPRClass, Size, GetX87FTW(), Mem, _Constant(Size * 2), Size, MEM_OFFSET_SXTX, 1); + _StoreMem(GPRClass, Size, GetX87FTW_Helper(), Mem, _Constant(Size * 2), Size, MEM_OFFSET_SXTX, 1); } { @@ -876,6 +658,8 @@ void OpDispatchBuilder::X87FNSAVEF64(OpcodeArgs) { // This function converts from F80 on load for compatibility void OpDispatchBuilder::X87FRSTORF64(OpcodeArgs) { + CurrentHeader->HasX87 = true; + _StackForceSlow(); const auto Size = GetSrcSize(Op); Ref Mem = MakeSegmentAddress(Op, Op->Src[0]); @@ -892,7 +676,7 @@ void OpDispatchBuilder::X87FRSTORF64(OpcodeArgs) { _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); auto NewFSW = _LoadMem(GPRClass, Size, Mem, _Constant(Size * 1), Size, MEM_OFFSET_SXTX, 1); - auto Top = ReconstructX87StateFromFSW(NewFSW); + Ref Top = ReconstructX87StateFromFSW_Helper(NewFSW); { // FTW @@ -930,32 +714,4 @@ void OpDispatchBuilder::X87FRSTORF64(OpcodeArgs) { _StoreContextIndexed(Reg, Top, 8, MMBaseOffset(), 16, FPRClass); } - -// FXAM needs change -void OpDispatchBuilder::X87FXAMF64(OpcodeArgs) { - auto top = GetX87Top(); - auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass); - Ref Result = _VExtractToGPR(8, 8, a, 0); - - // Extract the sign bit - Result = _Bfe(OpSize::i64Bit, 1, 63, Result); - SetRFLAG(Result); - - // Claim this is a normal number - // We don't support anything else - auto TopValid = GetX87ValidTag(top); - auto ZeroConst = _Constant(0); - auto OneConst = _Constant(1); - - // In the case of top being invalid then C3:C2:C0 is 0b101 - auto C3 = _Select(FEXCore::IR::COND_EQ, TopValid, OneConst, ZeroConst, OneConst); - - auto C2 = TopValid; - auto C0 = C3; // Mirror C3 until something other than zero is supported - SetRFLAG(C0); - SetRFLAG(C2); - SetRFLAG(C3); -} - - } // namespace FEXCore::IR diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json index 03904018e6..ef966a10bf 100644 --- a/FEXCore/Source/Interface/IR/IR.json +++ b/FEXCore/Source/Interface/IR/IR.json @@ -168,7 +168,7 @@ "SwitchGen": false, "JITDispatchOverride": "NoOp" }, - "IRHeader SSA:$Blocks, u64:$OriginalRIP, u32:$BlockCount, u32:$NumHostInstructions": { + "IRHeader SSA:$Blocks, u64:$OriginalRIP, u32:$BlockCount, u32:$NumHostInstructions, i1:$HasX87{false}": { "SwitchGen": false, "JITDispatchOverride": "NoOp" }, @@ -2410,34 +2410,272 @@ } }, "F80": { + "GPR = SyncStackToSlow": { + "Desc": [ + "Synchronizes the virtual stack environment to the physical registers.", + "Returns the current stack top." + ], + "JITDispatch": false, + "HasSideEffects": true, + "DestSize": 8 + }, + "StackForceSlow": { + "Desc": [ + "Forces the slow path." + ], + "JITDispatch": false, + "HasSideEffects": true + }, + "InitStack": { + "Desc": [ + "Initializes the stack by marking all tags as invalid and setting top to zero." + ], + "JITDispatch": false, + "HasSideEffects": true + }, + "IncStackTop": { + "Desc": [ + "Increase stack top-pointer." + ], + "JITDispatch": false, + "HasSideEffects": true + }, + "DecStackTop": { + "Desc": [ + "Decrease stack top-pointer." + ], + "JITDispatch": false, + "HasSideEffects": true + }, + "InvalidateStack i8:$StackLocation": { + "Desc": [ + "Marks the value in TOP+$StackLocation as empty / invalid 0b11.", + "If the StackLocation is 0xff, we invalidate all locations." + ], + "JITDispatch": false, + "HasSideEffects": true + }, + "PushStack FPR:$X80Src, OpSize:$OpSize, i1:$Float, u8:$LoadSize": { + "Desc": [ + "Pushes the provided source on to the x87 stack.", + "Opsize is 128bit for F80 values, 64-bit for low precision.", + "LoadSize the original load size", + "Float: 80-bit, 64-bit, 32-bit", + "Int: 64-bit, 32-bit, 16-bit" + ], + "HasSideEffects": true, + "JITDispatch": false + }, + "StoreStackMemory GPR:$Addr, OpSize:$SourceSize, i1:$Float, u8:$StoreSize": { + "Desc": [ + "Takes the top value off the x87 stack and stores it to memory.", + "SourceSize is 128bit for F80 values, 64-bit for low precision.", + "StoreSize is the store size for conversion:", + "Float: 80-bit, 64-bit, or 32-bit", + "Int: 64-bit, 32-bit, 16-bit" + ], + "HasSideEffects": true, + "JITDispatch": false + }, + "StoreStackToStack i8:$StackLocation": { + "Desc": [ + "Takes the top value off the x87 stack and stores it to stack location TOP+StackLocation", + "Float: 80-bit, 64-bit, or 32-bit", + "Int: 64-bit, 32-bit, 16-bit" + ], + "HasSideEffects": true, + "JITDispatch": false + }, + "PopStackDestroy": { + "Desc": [ + "Pops the top value off the stack but doesn't save it anywhere." + ], + "HasSideEffects": true, + "JITDispatch": false + }, + "FPR = ReadStackValue u8:$StackLocation": { + "Desc": [ + "Reads a value off the stack at the offset" + ], + "DestSize": "16", + "JITDispatch": false + }, + "GPR = StackValidTag u8:$StackLocation": { + "Desc": [ + "Returns 1 if the value in location TOP+$StackLocation is valid, 0 otherwise." + ], + "DestSize": 4, + "JITDispatch": false + }, + "F80AddStack u8:$SrcStack1, u8:$SrcStack2": { + "Desc": [ + "Adds two stack locations together, storing the result in to the first stack location" + ], + "HasSideEffects": true, + "JITDispatch": false + }, + "F80AddValue u8:$SrcStack, FPR:$X80Src": { + "Desc": [ + "Adds a operand value to a stack location. The result stored in to the stack location provided." + ], + "HasSideEffects": true, + "JITDispatch": false + }, "FPR = F80Add FPR:$X80Src1, FPR:$X80Src2": { "DestSize": "16", "JITDispatch": false }, + "F80SubStack u8:$DstStack, u8:$SrcStack1, u8:$SrcStack2": { + "Desc": [ + "Subtracts the value in stack location TOP+$SrcStack2 from the value in stack location TOP+$SrcStack1.", + "The result is stored in stack location TOP+$DstStack." + ], + "HasSideEffects": true, + "JITDispatch": false + }, + "F80SubValue u8:$SrcStack, FPR:$X80Src": { + "Desc": [ + "Subtracts the value $X80Src from the value in stack location TOP+$SrcStack.", + "The result is stored in stack location TOP." + ], + "HasSideEffects": true, + "JITDispatch": false + }, + "F80SubRValue FPR:$X80Src, u8:$SrcStack": { + "Desc": [ + "Subtracts the value in stack location TOP+$SrcStack from the value $X80Src.", + "The result is stored in stack location TOP." + ], + "HasSideEffects": true, + "JITDispatch": false + }, "FPR = F80Sub FPR:$X80Src1, FPR:$X80Src2": { + "Desc": [ + "Subtracts the value in $X80Src1 from the value in $X80Src2.", + "The result is returned.", + "`FPR = X80Src2 - X80Src1`" + ], "DestSize": "16", "JITDispatch": false }, + "F80MulStack u8:$SrcStack1, u8:$SrcStack2": { + "Desc": [ + "Multiplies two stack locations together, storing the result in to the first stack location" + ], + "HasSideEffects": true, + "JITDispatch": false + }, + "F80MulValue u8:$SrcStack, FPR:$X80Src": { + "Desc": [ + "Multiplies a operand value to a stack location. The result stored in to the stack location provided." + ], + "HasSideEffects": true, + "JITDispatch": false + }, "FPR = F80Mul FPR:$X80Src1, FPR:$X80Src2": { "DestSize": "16", "JITDispatch": false }, + "F80DivStack u8:$DstStack, u8:$SrcStack1, u8:$SrcStack2": { + "Desc": [ + "Divides the value in stack location TOP+$SrcStack1 by the value in stack location TOP+$SrcStack2.", + "The result is stored in stack location TOP+$DstStack.", + "`FPR|Stack[TOP+DstStack] = Stack[TOP+SrcStack1] / Stack[TOP+SrcStack2]`" + ], + "HasSideEffects": true, + "JITDispatch": false + }, + "F80DivValue u8:$SrcStack, FPR:$X80Src": { + "Desc": [ + "Divides the value in stack location TOP+$SrcStack by the value $X80Src.", + "The result is stored in stack location TOP and returned.", + "`FPR|Stack[TOP] = Stack[TOP+SrcStack] / X80Src`" + ], + "HasSideEffects": true, + "JITDispatch": false + }, + "F80DivRValue FPR:$X80Src, u8:$SrcStack": { + "Desc": [ + "Divides the value X80Src by the value in stack location TOP+$SrcStack.", + "The result is stored in stack location TOP.", + "`FPR|Stack[TOP] = X80Src / Stack[TOP+SrcStack]`" + ], + "HasSideEffects": true, + "JITDispatch": false + }, "FPR = F80Div FPR:$X80Src1, FPR:$X80Src2": { + "Desc": [ + "Divides the value in $X80Src1 by the value in $X80Src2.", + "The result is returned.", + "`FPR = X80Src1 / X80Src2`" + ], "DestSize": "16", "JITDispatch": false }, + "F80StackXchange u8:$SrcStack": { + "Desc": [ + "Exchanges the value at the top of the stack with the value at TOP+$SrcStack." + ], + "JITDispatch": false, + "HasSideEffects": true + }, + "FPR = F80StackChangeSign": { + "Desc": [ + "Complements the sign bit of the value at the top of the stack.", + "Returns the new value at the top of the stack." + ], + "HasSideEffects": true, + "DestSize": "16", + "JITDispatch": false + }, + "FPR = F80StackAbs": { + "Desc": [ + "Clears the sign bit of the value at the top of the stack.", + "Returns the new value at the top of the stack." + ], + "HasSideEffects": true, + "DestSize": "16", + "JITDispatch": false + }, + "F80PTANStack": { + "Desc": [ + "Computes the approximate tangent of the source operand in register ST(0), stores the result in ST(0), and pushes a 1.0 onto the FPU register stack." + ], + "JITDispatch": false, + "HasSideEffects": true + }, + "FPR = F80ATANStack": { + "Desc": [ + "Computes arctan(st1/st0) and stores it in st0. Then pops the stack." + ], + "DestSize": "16", + "JITDispatch": false, + "HasSideEffects": true + }, "FPR = F80ATAN FPR:$X80Src1, FPR:$X80Src2": { "DestSize": "16", "JITDispatch": false }, + "F80FPREMStack": { + "JITDispatch": false, + "HasSideEffects": true + }, "FPR = F80FPREM FPR:$X80Src1, FPR:$X80Src2": { "DestSize": "16", "JITDispatch": false }, + "F80FPREM1Stack": { + "JITDispatch": false, + "HasSideEffects": true + }, "FPR = F80FPREM1 FPR:$X80Src1, FPR:$X80Src2": { "DestSize": "16", "JITDispatch": false }, + "F80SCALEStack": { + "JITDispatch": false, + "HasSideEffects": true + }, "FPR = F80SCALE FPR:$X80Src1, FPR:$X80Src2": { "DestSize": "16", "JITDispatch": false @@ -2458,10 +2696,21 @@ "DestSize": "16", "JITDispatch": false }, + "F80RoundStack": { + "Desc": [ + "Replaces the value at the top of the stack with its nearest integral value." + ], + "JITDispatch": false, + "HasSideEffects": true + }, "FPR = F80Round FPR:$X80Src": { "DestSize": "16", "JITDispatch": false }, + "F80F2XM1Stack": { + "JITDispatch": false, + "HasSideEffects": true + }, "FPR = F80F2XM1 FPR:$X80Src": { "DestSize": "16", "JITDispatch": false @@ -2470,18 +2719,34 @@ "DestSize": "16", "JITDispatch": false }, + "F80SINStack": { + "JITDispatch": false, + "HasSideEffects": true + }, "FPR = F80SIN FPR:$X80Src": { "DestSize": "16", "JITDispatch": false }, + "F80COSStack": { + "JITDispatch": false, + "HasSideEffects": true + }, "FPR = F80COS FPR:$X80Src": { "DestSize": "16", "JITDispatch": false }, + "F80SQRTStack": { + "JITDispatch": false, + "HasSideEffects": true + }, "FPR = F80SQRT FPR:$X80Src": { "DestSize": "16", "JITDispatch": false }, + "F80XTRACTStack": { + "JITDispatch": false, + "HasSideEffects": true + }, "FPR = F80XTRACT_EXP FPR:$X80Src": { "DestSize": "16", "JITDispatch": false @@ -2490,6 +2755,30 @@ "DestSize": "16", "JITDispatch": false }, + "GPR = F80StackTest u8:$SrcStack, u32:$Flags": { + "Desc": [ + "Does comparison between value in stack at TOP + SrcStack" + ], + "DestSize": "4", + "JITDispatch": false + }, + "GPR = F80CmpStack u8:$SrcStack, u32:$Flags": { + "Desc": [ + "Does a scalar unordered compare between the value at the top of the stack and the value in stack position TOP+$SrcStack and stores the asked for flags in to a GPR", + "Ordering flag result is true if either float input is NaN" + ], + "DestSize": "4", + "JITDispatch": false + }, + "GPR = F80CmpValue FPR:$X80Src, u32:$Flags": { + "Desc": [ + "Does a scalar unordered compare between the value at the top of the stack and $X80Src and stores the asked for flags in to a GPR", + "Ordering flag result is true if either float input is NaN" + ], + "DestSize": "4", + "HasSideEffects": true, + "JITDispatch": false + }, "GPR = F80Cmp FPR:$X80Src1, FPR:$X80Src2, u32:$Flags": { "Desc": ["Does a scalar unordered compare and stores the asked for flags in to a GPR", "Ordering flag result is true if either float input is NaN" @@ -2505,10 +2794,29 @@ "DestSize": "16", "JITDispatch": false }, - + "FPR = F80StackFYL2X": { + "Desc": [ + "Computes ST1 * log2(ST0)", + "Stores the result in ST1, and pops the top of the stack.", + "Returns the new value at the top of the stack, i.e. the result of the operation." + ], + "HasSideEffects": true, + "DestSize": "16", + "JITDispatch": false + }, "FPR = F80FYL2X FPR:$X80Src1, FPR:$X80Src2": { "DestSize": "16", "JITDispatch": false + }, + "F80VBSLStack u8:#RegisterSize, FPR:$VectorMask, u8:$SrcStack1, u8:$SrcStack2": { + "Desc": [ + "Does a vector bitwise select.", + "If the bit in the field is 1 then the corresponding bit is pulled from VectorTrue", + "If the bit in the field is 0 then the corresponding bit is pulled from VectorFalse", + "Writes the result to the top of the stack." + ], + "JITDispatch": false, + "HasSideEffects": true } }, "Backend": { diff --git a/FEXCore/Source/Interface/IR/PassManager.cpp b/FEXCore/Source/Interface/IR/PassManager.cpp index 476460a578..7cd7f5292f 100644 --- a/FEXCore/Source/Interface/IR/PassManager.cpp +++ b/FEXCore/Source/Interface/IR/PassManager.cpp @@ -70,6 +70,7 @@ void PassManager::AddDefaultPasses(FEXCore::Context::ContextImpl* ctx) { FEX_CONFIG_OPT(DisablePasses, O0); if (!DisablePasses()) { + InsertPass(CreateX87StackOptimizationPass()); InsertPass(CreateContextLoadStoreElimination(ctx->HostFeatures.SupportsSVE256)); InsertPass(CreateDeadStoreElimination()); InsertPass(CreateConstProp(ctx->HostFeatures.SupportsTSOImm9, &ctx->CPUID)); diff --git a/FEXCore/Source/Interface/IR/Passes.h b/FEXCore/Source/Interface/IR/Passes.h index 72474ad5ee..93dea6a5cf 100644 --- a/FEXCore/Source/Interface/IR/Passes.h +++ b/FEXCore/Source/Interface/IR/Passes.h @@ -21,6 +21,7 @@ fextl::unique_ptr CreateContextLoadStoreElimination(bool Supp fextl::unique_ptr CreateDeadFlagCalculationEliminination(); fextl::unique_ptr CreateDeadStoreElimination(); fextl::unique_ptr CreateRegisterAllocationPass(); +fextl::unique_ptr CreateX87StackOptimizationPass(); namespace Validation { fextl::unique_ptr CreateIRValidation(); diff --git a/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp new file mode 100644 index 0000000000..21fded0436 --- /dev/null +++ b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp @@ -0,0 +1,1892 @@ +#include "FEXCore/Utils/LogManager.h" +#include "Interface/IR/IR.h" +#include "Interface/IR/IREmitter.h" +#include "Interface/IR/PassManager.h" +#include +#include +#include + +#include +#include +#include +#include + +namespace FEXCore::IR { + +// FixedSizeStack is a model of the x87 Stack where each element in this +// fixed size stack lives at an offset from top. The top of the stack is at +// index 0. +template +class FixedSizeStack { +public: + enum class Slot { UNUSED, INVALID, VALID }; + FixedSizeStack() { + buffer.resize(MaxSize, {Slot::UNUSED, T()}); + } + + void push(const T& value) { + rotate(); + buffer.front() = {Slot::VALID, value}; + } + + // Rotate the elements with the direction controlled by Right + void rotate(bool Right = true) { + if (Right) { + // Right rotation + std::pair temp = buffer.back(); + buffer.pop_back(); + buffer.push_front(temp); + TopOffset++; + } else { + // Left rotation + std::pair temp = buffer.front(); + buffer.pop_front(); + buffer.push_back(temp); + TopOffset--; + } + } + + void pop() { + buffer.front() = {Slot::INVALID, T()}; + rotate(false); + } + + const std::pair& top(size_t Offset = 0) const { + return buffer[Offset]; + } + + void setTop(T Value, size_t Offset = 0) { + buffer[Offset] = {Slot::VALID, Value}; + } + + bool isValid(size_t Offset) const { + return buffer[Offset].first; + } + + inline void clear() { + for (auto& element : buffer) { + element = {Slot::UNUSED, T()}; // Set all elements as invalid + } + TopOffset = 0; + } + + void dump() const { + for (size_t i = 0; i < MaxSize; i++) { + const auto& [Valid, Element] = buffer[i]; + if (Valid == Slot::VALID) { + LogMan::Msg::DFmt("ST{}: 0x{:x}", i, (uintptr_t)(Element.StackDataNode)); + } + } + } + + constexpr size_t size() const { + return MaxSize; + } + + int8_t getTopOffset() const { + return TopOffset; + } + + void setTopOffset(int8_t Offset) { + TopOffset = Offset; + } + + void setValidTag(size_t Index, bool Valid) { + buffer[Index].first = Valid ? Slot::VALID : Slot::INVALID; + } + + // Returns a mask to set in AbridgedTagWord + uint8_t getValidMask() { + uint8_t Mask = 0; + for (size_t i = 0; i < buffer.size(); i++) { + const bool Valid = buffer[i].first == Slot::VALID; + if (Valid) { + Mask |= 1U << i; + } + } + return Mask; + } + + // Returns a mask to set in AbridgedTagWord + uint8_t getInvalidMask() { + uint8_t Mask = 0; + for (size_t i = 0; i < buffer.size(); i++) { + const bool Valid = buffer[i].first == Slot::INVALID; + if (Valid) { + Mask |= 1U << i; + } + } + return Mask; + } + +private: + fextl::deque> buffer; + // Real top as an offset from stored top value (or the one at the beginning of the block) + // For example, if we start and push a value to our simulated stack, because we don't + // update top straight away the TopOffset is 1. + // If SlowPath is true, then TopOffset is always zero. + int8_t TopOffset = 0; +}; + + +class X87StackOptimization final : public FEXCore::IR::Pass { +public: + X87StackOptimization() { + FEX_CONFIG_OPT(ReducedPrecision, X87REDUCEDPRECISION); + ReducedPrecisionMode = ReducedPrecision; + } + void Run(IREmitter* Emit) override; + +private: + bool ReducedPrecisionMode; + // FIXME(pmatos): copy from OpcodeDispatcher.h + [[nodiscard]] + uint32_t MMBaseOffset() { + return static_cast(offsetof(Core::CPUState, mm[0][0])); + } + std::tuple SplitF64SigExp(Ref Node); + + // Top Management Helpers + /// Set the valid tag for Value as valid (if Valid is true), or invalid (if Valid is false). + void SetX87ValidTag(Ref Value, bool Valid); + // Generates slow code to load/store a value from the top of the stack + Ref LoadStackValueAtTop_Slow(); + void StoreStackValueAtTop_Slow(Ref Value, bool SetValid = true); + // Generates slow code to load/store a value from an offset from the top of the stack + Ref LoadStackValueAtOffset_Slow(uint8_t Offset); + void StoreStackValueAtOffset_Slow(uint8_t Offset, Ref Value, bool SetValid = true); + // Update Top value in slow path for a pop + void UpdateTop4Pop_Slow(); + void UpdateTop4Push_Slow(); + // Synchronizes the current simulated stack with the actual values. + // Returns a new value for Top, that's synchronized between the simulated stack + // and the actual FPU stack. + Ref SynchronizeStackValues(); + // Moves us from the fast to the slow path if ShouldMigrate is true. + void MigrateToSlowPathIf(bool ShouldMigrate); + // Top Cache Management + Ref GetTopWithCache_Slow(); + Ref GetOffsetTopWithCache_Slow(uint8_t Offset); + void SetTopWithCache_Slow(Ref Value); + Ref GetX87ValidTag_Slow(uint8_t Offset); + // Resets fields to initial values + void Reset(bool AlsoSlowPath = true); + + struct StackMemberInfo { + IR::OpSize SourceDataSize; // Size of SourceDataNode + IR::OpSize StackDataSize; // Size of the data in the stack + IR::Ref SourceDataNode; // Reference to the source location of the data. + // In the case of a load, this is the source node of the load. + // If it's not a load, then it's nullptr. + IR::Ref StackDataNode; // Reference to the data in the Stack. + bool InterpretAsFloat {}; // True if this is a floating point value, false if integer + }; + + // StackData, TopCache need to be always properly set to ensure + // it reflects the current state of the FPU. This sync only makes sense while + // taking the fast path. Once in the slow path, these don't make sense anymore + // and we are syncing everything. + + // Index on vector is offset to top value at start of block + // If slow path is true, then StackData is always empty. + FixedSizeStack StackData; + using StackSlot = FixedSizeStack::Slot; + + void InvalidateCaches(); + void InvalidateTopOffsetCache(); + + // Cache for Constants + // ConstantPoll[i] has IREmit->_Constant(i); + constexpr static size_t ConstantPoolSize = 8; + std::array ConstantPool; + Ref GetConstant(ssize_t Offset); + + // Cached value for Top + // If slowpath is false, then TopCache is nullptr. + std::array TopOffsetCache; + // Are we on the slow path? + // Once we enter the slow path, we never come out. + // This just simplifies the code atm. If there's a need to return to the fast path in the future + // we can implement that but I would expect that there would be very few cases where that's necessary. + // On the slow path TopCache is always the last obtained version of top. + // TopOffset is ignored + bool SlowPath = false; + // Keeping IREmitter not to pass arguments around + IREmitter* IREmit = nullptr; +}; + +inline void X87StackOptimization::InvalidateCaches() { + LogMan::Msg::DFmt("Invalidating caches"); + + InvalidateTopOffsetCache(); + ConstantPool.fill(nullptr); +} + +inline void X87StackOptimization::InvalidateTopOffsetCache() { + TopOffsetCache.fill(nullptr); +} + +inline void X87StackOptimization::Reset(bool AlsoSlowPath) { + if (AlsoSlowPath) { + SlowPath = false; + } + StackData.clear(); + InvalidateCaches(); +} + +inline Ref X87StackOptimization::GetConstant(ssize_t Offset) { + if (Offset < 0 || Offset >= X87StackOptimization::ConstantPoolSize) { + // not dealt by pool + LogMan::Msg::DFmt("Generating uncacheable constant for {}", Offset); + return IREmit->_Constant(Offset); + } + if (ConstantPool[Offset] == nullptr) { + LogMan::Msg::DFmt("Generating and caching constant for {}", Offset); + + ConstantPool[Offset] = IREmit->_Constant(Offset); + } else { + LogMan::Msg::DFmt("Returning cached constant for {}", Offset); + } + return ConstantPool[Offset]; +} + +inline void X87StackOptimization::MigrateToSlowPathIf(bool ShouldMigrate) { + if (SlowPath) { + return; + } + if (!ShouldMigrate) { + return; + } + + LogMan::Msg::DFmt("Migrating to SlowPath"); + SynchronizeStackValues(); + Reset(false); // Reset everything but no need to change slowpath + SlowPath = true; +} + +inline Ref X87StackOptimization::GetTopWithCache_Slow() { + if (!TopOffsetCache[0]) { + TopOffsetCache[0] = IREmit->_LoadContext(1, GPRClass, offsetof(FEXCore::Core::CPUState, flags) + FEXCore::X86State::X87FLAG_TOP_LOC); + } + return TopOffsetCache[0]; +} + +inline Ref X87StackOptimization::GetOffsetTopWithCache_Slow(uint8_t Offset) { + if (TopOffsetCache[Offset]) { + return TopOffsetCache[Offset]; + } + + auto* OffsetTop = GetTopWithCache_Slow(); + if (Offset != 0) { + OffsetTop = IREmit->_And(OpSize::i32Bit, IREmit->_Add(OpSize::i32Bit, OffsetTop, GetConstant(Offset)), GetConstant(7)); + // GetTopWithCache_Slow already sets the cache so we don't need to set it here for offset == 0 + TopOffsetCache[Offset] = OffsetTop; + } + + return OffsetTop; +} + + +inline void X87StackOptimization::SetTopWithCache_Slow(Ref Value) { + IREmit->_StoreContext(1, GPRClass, Value, offsetof(FEXCore::Core::CPUState, flags) + FEXCore::X86State::X87FLAG_TOP_LOC); + InvalidateTopOffsetCache(); + TopOffsetCache[0] = Value; +} + +inline void X87StackOptimization::SetX87ValidTag(Ref Value, bool Valid) { + Ref AbridgedFTW = IREmit->_LoadContext(1, GPRClass, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + Ref RegMask = IREmit->_Lshl(OpSize::i32Bit, GetConstant(1), Value); + Ref NewAbridgedFTW = Valid ? IREmit->_Or(OpSize::i32Bit, AbridgedFTW, RegMask) : IREmit->_Andn(OpSize::i32Bit, AbridgedFTW, RegMask); + IREmit->_StoreContext(1, GPRClass, NewAbridgedFTW, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); +} + +inline Ref X87StackOptimization::GetX87ValidTag_Slow(uint8_t Offset) { + Ref AbridgedFTW = IREmit->_LoadContext(1, GPRClass, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + return IREmit->_And(OpSize::i32Bit, IREmit->_Lshr(OpSize::i32Bit, AbridgedFTW, GetOffsetTopWithCache_Slow(Offset)), GetConstant(1)); +} + +inline Ref X87StackOptimization::LoadStackValueAtTop_Slow() { + return LoadStackValueAtOffset_Slow(0); +} + +inline Ref X87StackOptimization::LoadStackValueAtOffset_Slow(uint8_t Offset) { + return IREmit->_LoadContextIndexed(GetOffsetTopWithCache_Slow(Offset), ReducedPrecisionMode ? 8 : 16, MMBaseOffset(), 16, FPRClass); +} + +inline void X87StackOptimization::StoreStackValueAtTop_Slow(Ref Value, bool SetValid) { + StoreStackValueAtOffset_Slow(0, Value, SetValid); +} + +inline void X87StackOptimization::StoreStackValueAtOffset_Slow(uint8_t Offset, Ref Value, bool SetValid) { + OrderedNode* TopOffset = GetOffsetTopWithCache_Slow(Offset); + // store + IREmit->_StoreContextIndexed(Value, TopOffset, ReducedPrecisionMode ? 8 : 16, MMBaseOffset(), 16, FPRClass); + // mark it valid + // In some cases we might already know it has been previously set as valid so we don't need to do it again + if (SetValid) { + SetX87ValidTag(TopOffset, true); + } +} + +inline void X87StackOptimization::UpdateTop4Pop_Slow() { + // Pop the top of the x87 stack + auto* TopOffset = GetTopWithCache_Slow(); + TopOffset = IREmit->_Add(OpSize::i32Bit, TopOffset, GetConstant(1)); + TopOffset = IREmit->_And(OpSize::i32Bit, TopOffset, GetConstant(7)); + SetTopWithCache_Slow(TopOffset); +} + +inline void X87StackOptimization::UpdateTop4Push_Slow() { + // Pop the top of the x87 stack + auto* TopOffset = GetTopWithCache_Slow(); + TopOffset = IREmit->_Sub(OpSize::i32Bit, TopOffset, GetConstant(1)); + TopOffset = IREmit->_And(OpSize::i32Bit, TopOffset, GetConstant(7)); + SetTopWithCache_Slow(TopOffset); +} + +// We synchronize stack values in a few occasions but one of the most important of those, +// is when we move from fast to a slow path and need to make sure that the context is properly +// written. +Ref X87StackOptimization::SynchronizeStackValues() { + if (SlowPath) { // Nothing to do here. + LogMan::Msg::DFmt("Sync called in slow path - nothing to do here"); + return GetTopWithCache_Slow(); + } + + // Store new top which is now the original top minus recorded top offset + // Careful with underflow wraparound. + const auto TopOffset = StackData.getTopOffset(); + LogMan::Msg::DFmt("Writing stack to context - topoffset: {}", TopOffset); + + if (TopOffset != 0) { + auto* OrigTop = GetTopWithCache_Slow(); + Ref NewTop = nullptr; + if (TopOffset > 0) { + NewTop = IREmit->_And(OpSize::i32Bit, IREmit->_Sub(OpSize::i32Bit, OrigTop, GetConstant(TopOffset)), GetConstant(0x7)); + } else { + NewTop = IREmit->_And(OpSize::i32Bit, IREmit->_Add(OpSize::i32Bit, OrigTop, GetConstant(-TopOffset)), GetConstant(0x7)); + } + SetTopWithCache_Slow(NewTop); + } + StackData.setTopOffset(0); + + // Before leaving we need to write the current values in the stack to + // context so that the values are correct. Copy SourceDataNode in the + // stack to the respective mmX register. + Ref TopValue = GetTopWithCache_Slow(); + StackData.dump(); + for (size_t i = 0; i < StackData.size(); ++i) { + const auto& [Valid, StackMember] = StackData.top(i); + + if (Valid == StackSlot::UNUSED) { + continue; + } + Ref TopIndex = GetOffsetTopWithCache_Slow(i); + if (Valid == StackSlot::VALID) { + LogMan::Msg::DFmt("Writing StackData[{}]", i); + IREmit->_StoreContextIndexed(StackMember.StackDataNode, TopIndex, ReducedPrecisionMode ? 8 : 16, MMBaseOffset(), 16, FPRClass); + } + } + { // Set valid tags + uint8_t Mask = StackData.getValidMask(); + Ref MaskC = GetConstant(Mask); + LogMan::Msg::DFmt("Writing valid tags 0x{:02x}", Mask); + if (Mask == 0xff) { + IREmit->_StoreContext(1, GPRClass, GetConstant(Mask), offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + } else if (Mask != 0) { + if (std::popcount(Mask) == 1) { + uint8_t BitIdx = __builtin_ctz(Mask); + SetX87ValidTag(GetOffsetTopWithCache_Slow(BitIdx), true); + } else { + // perform a rotate right on mask by top + // since we must operate on 32bits as a minimum: + // ror (mask, top) = ((M << 8) | M) >> TOP + auto* TopValue = GetTopWithCache_Slow(); + Ref RotAmount = IREmit->_Sub(OpSize::i32Bit, GetConstant(8), TopValue); + Ref RMask = IREmit->_Or(OpSize::i32Bit, MaskC, IREmit->_Lshl(OpSize::i32Bit, MaskC, GetConstant(8))); + RMask = IREmit->_Lshr(OpSize::i32Bit, RMask, RotAmount); + Ref AbridgedFTW = IREmit->_LoadContext(1, GPRClass, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + Ref NewAbridgedFTW = IREmit->_Or(OpSize::i32Bit, AbridgedFTW, RMask); + IREmit->_StoreContext(1, GPRClass, NewAbridgedFTW, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + } + } else { + LogMan::Msg::DFmt("No valid tags written"); + } + } + { // Set invalid tags + uint8_t Mask = StackData.getInvalidMask(); + Ref MaskC = GetConstant(Mask); + LogMan::Msg::DFmt("Writing invalid tags 0x{:02x}", Mask); + if (Mask == 0xff) { + IREmit->_StoreContext(1, GPRClass, GetConstant(0), offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + } else if (Mask != 0) { + if (std::popcount(Mask)) { + uint8_t BitIdx = __builtin_ctz(Mask); + SetX87ValidTag(GetOffsetTopWithCache_Slow(BitIdx), false); + } else { + // Same rotate right as above but this time on the invalid mask + auto* TopValue = GetTopWithCache_Slow(); + Ref RotAmount = IREmit->_Sub(OpSize::i32Bit, GetConstant(8), TopValue); + Ref RMask = IREmit->_Or(OpSize::i32Bit, MaskC, IREmit->_Lshl(OpSize::i32Bit, MaskC, GetConstant(8))); + RMask = IREmit->_Lshr(OpSize::i32Bit, RMask, RotAmount); + Ref AbridgedFTW = IREmit->_LoadContext(1, GPRClass, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + Ref NewAbridgedFTW = IREmit->_Andn(OpSize::i32Bit, AbridgedFTW, RMask); + IREmit->_StoreContext(1, GPRClass, NewAbridgedFTW, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + } + } else { + LogMan::Msg::DFmt("No invalid tags written"); + } + } + return TopValue; +} + +std::tuple X87StackOptimization::SplitF64SigExp(Ref Node) { + Ref Gpr = IREmit->_VExtractToGPR(8, 8, Node, 0); + + Ref Exp = IREmit->_And(OpSize::i64Bit, Gpr, GetConstant(0x7ff0000000000000LL)); + Exp = IREmit->_Lshr(OpSize::i64Bit, Exp, GetConstant(52)); + Exp = IREmit->_Sub(OpSize::i64Bit, Exp, GetConstant(1023)); + Exp = IREmit->_Float_FromGPR_S(8, 8, Exp); + Ref Sig = IREmit->_And(OpSize::i64Bit, Gpr, GetConstant(0x800fffffffffffffLL)); + Sig = IREmit->_Or(OpSize::i64Bit, Sig, GetConstant(0x3ff0000000000000LL)); + Sig = IREmit->_VCastFromGPR(8, 8, Sig); + + return std::tuple {Exp, Sig}; +} + +void X87StackOptimization::Run(IREmitter* Emit) { + FEXCORE_PROFILE_SCOPED("PassManager::x87StackOpt"); + + auto CurrentIR = Emit->ViewIR(); + auto* HeaderOp = CurrentIR.GetHeader(); + LOGMAN_THROW_AA_FMT(HeaderOp->Header.Op == OP_IRHEADER, "First op wasn't IRHeader"); + + if (!HeaderOp->HasX87) { + // If there is no x87 in this, just early exit. + return; + } + + // Initialize IREmit member + IREmit = Emit; + + auto* OriginalWriteCursor = IREmit->GetWriteCursor(); + + // Run optimization proper + for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) { + // Each time we deal with a new block we need to start over. + // The optimization should run per-block + LogMan::Msg::DFmt("Starting new block - resetting and back to fast path"); + Reset(); + + for (auto [CodeNode, IROp] : CurrentIR.GetCode(BlockNode)) { + IREmit->SetWriteCursor(CodeNode); + + switch (IROp->Op) { + + case IR::OP_INITSTACK: { + + StackData.clear(); + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_INVALIDATESTACK: { + + + LogMan::Msg::DFmt("OP_INVALIDATESTACK"); + const auto* Op = IROp->C(); + auto Offset = Op->StackLocation; + + if (Offset != 0xff) { // invalidate single offset + if (SlowPath) { + auto* TopValue = GetTopWithCache_Slow(); + if (Offset != 0) { + auto* Mask = GetConstant(7); + TopValue = IREmit->_And(OpSize::i32Bit, IREmit->_Add(OpSize::i32Bit, TopValue, GetConstant(Offset)), Mask); + } + SetX87ValidTag(TopValue, false); + } else { + StackData.setValidTag(Offset, false); + } + } else { // invalidate all + if (SlowPath) { + IREmit->_StoreContext(1, GPRClass, GetConstant(0), offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + } else { + for (size_t i = 0; i < StackData.size(); i++) { + StackData.setValidTag(i, false); + } + } + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_PUSHSTACK: { + + + const auto* Op = IROp->C(); + auto* SourceNode = CurrentIR.GetNode(Op->X80Src); + + if (SlowPath) { + LogMan::Msg::DFmt("OP_PUSHSTACK SlowPath"); + UpdateTop4Push_Slow(); + StoreStackValueAtTop_Slow(SourceNode); + } else { + LogMan::Msg::DFmt("OP_PUSHSTACK FastPath"); + auto* SourceNode = CurrentIR.GetNode(Op->X80Src); + auto* SourceNodeOp = CurrentIR.GetOp(SourceNode); + auto SourceNodeSize = SourceNodeOp->Size; + StackData.push(StackMemberInfo { + .SourceDataSize = IR::SizeToOpSize(SourceNodeSize), + .StackDataSize = IR::SizeToOpSize(Op->LoadSize), + .SourceDataNode = nullptr, + .StackDataNode = SourceNode, + .InterpretAsFloat = Op->Float, + }); + } + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_READSTACKVALUE: { + + + const auto* Op = IROp->C(); + auto Offset = Op->StackLocation; + const auto& [Valid, Value] = StackData.top(Offset); + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + Ref NewValue = nullptr; + if (SlowPath) { + // slow path + LogMan::Msg::DFmt("OP_READSTACKVALUE slow"); + NewValue = LoadStackValueAtOffset_Slow(Offset); + } else { // fast path + LogMan::Msg::DFmt("OP_READSTACKVALUE fast"); + NewValue = StackData.top(Offset).second.StackDataNode; + } + + IREmit->ReplaceUsesWithAfter(CodeNode, NewValue, CodeNode); + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_STACKVALIDTAG: { + + + // Returns 0 if value is valid and 1 otherwise. + const auto* Op = IROp->C(); + auto Offset = Op->StackLocation; + const auto& [Valid, Value] = StackData.top(Offset); + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + Ref Tag = nullptr; + + if (SlowPath) { + LogMan::Msg::DFmt("STACKVALIDTAG slow"); + Tag = GetX87ValidTag_Slow(Offset); + } else { + LogMan::Msg::DFmt("STACKVALIDTAG fast"); + Tag = StackData.top(Offset).first == StackSlot::VALID ? GetConstant(1) : GetConstant(0); + } + + IREmit->ReplaceUsesWithAfter(CodeNode, Tag, CodeNode); + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_STORESTACKMEMORY: { // stores top of stack in mem addr. + + + LogMan::Msg::DFmt("OP_STORESTACKMEMORY"); + const auto* Op = IROp->C(); + + const auto& [Valid, Value] = StackData.top(); + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + Ref StackNode = nullptr; + if (SlowPath) { // slow path + LogMan::Msg::DFmt("Slow path STORESTACKMEMORY"); + StackNode = LoadStackValueAtTop_Slow(); + } else { // fast path + LogMan::Msg::DFmt("Fast path STORESTACKMEMORY"); + StackNode = StackData.top().second.StackDataNode; + } + + auto* AddrNode = CurrentIR.GetNode(Op->Addr); + + if (ReducedPrecisionMode) { + switch (Op->StoreSize) { + case 4: { + StackNode = IREmit->_Float_FToF(4, 8, StackNode); + IREmit->_StoreMem(FPRClass, 8, AddrNode, StackNode); + break; + } + case 8: { + IREmit->_StoreMem(FPRClass, 8, AddrNode, StackNode); + break; + } + case 10: { + StackNode = IREmit->_F80CVTTo(StackNode, 8); + IREmit->_StoreMem(FPRClass, 8, AddrNode, StackNode); + auto Upper = IREmit->_VExtractToGPR(16, 8, StackNode, 1); + IREmit->_StoreMem(GPRClass, 2, Upper, AddrNode, GetConstant(8), 8, MEM_OFFSET_SXTX, 1); + break; + } + } + } else { + if (Op->StoreSize != 10) { // if it's not 80bits then convert + StackNode = IREmit->_F80CVT(Op->StoreSize, StackNode); + } + if (Op->StoreSize == 10) { // Part of code from StoreResult_WithOpSize() + // For X87 extended doubles, split before storing + IREmit->_StoreMem(FPRClass, 8, AddrNode, StackNode); + auto Upper = IREmit->_VExtractToGPR(16, 8, StackNode, 1); + auto DestAddr = IREmit->_Add(OpSize::i64Bit, AddrNode, GetConstant(8)); + IREmit->_StoreMem(GPRClass, 2, DestAddr, Upper, 8); + } else { + IREmit->_StoreMem(FPRClass, Op->StoreSize, AddrNode, StackNode); + } + } + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_STORESTACKTOSTACK: { // stores top of stack in another place in stack. + + + LogMan::Msg::DFmt("OP_STORESTACKTOSTACK"); + const auto* Op = IROp->C(); + + auto Offset = Op->StackLocation; + + if (Offset != 0) { + const auto& [Valid, Value] = StackData.top(); + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + // Need to store st0 to stack location - basically a copy. + if (SlowPath) { // slow path + LogMan::Msg::DFmt("Slow path STORESTACKTOSTACK"); + StoreStackValueAtOffset_Slow(Offset, LoadStackValueAtTop_Slow()); + } else { // fast path + LogMan::Msg::DFmt("Fast path STORESTACKTOSTACK"); + StackData.setTop(Value, Offset); + } + } else { + LogMan::Msg::DFmt("STORESTACKTOSTACK with 0 is NOP"); + } + + IREmit->Remove(CodeNode); + break; + } + case IR::OP_POPSTACKDESTROY: { + + + LogMan::Msg::DFmt("OP_POPSTACKDESTROY"); + + if (SlowPath) { // slow path + LogMan::Msg::DFmt("Slow path POPSTACKDESTROY"); + SetX87ValidTag(GetTopWithCache_Slow(), false); + UpdateTop4Pop_Slow(); + } else { + LogMan::Msg::DFmt("Fast path POPSTACKDESTROY"); + StackData.pop(); + } + + IREmit->Remove(CodeNode); + break; + } + case IR::OP_F80ADDSTACK: { + LogMan::Msg::DFmt("OP_F80ADDSTACK"); + const auto* Op = IROp->C(); + + // Adds two elements in the stack by offset. + auto StackOffset1 = Op->SrcStack1; + auto StackOffset2 = Op->SrcStack2; + + const auto& [Valid1, StackMember1] = StackData.top(StackOffset1); + const auto& [Valid2, StackMember2] = StackData.top(StackOffset2); + + MigrateToSlowPathIf(Valid1 != StackSlot::VALID || Valid2 != StackSlot::VALID); + + if (SlowPath) { // Slow Path + LogMan::Msg::DFmt("Slow path F80ADDSTACK"); + + // Load the current value from the x87 fpu stack + auto* StackNode1 = LoadStackValueAtOffset_Slow(StackOffset1); + auto* StackNode2 = LoadStackValueAtOffset_Slow(StackOffset2); + + Ref AddNode = {}; + if (ReducedPrecisionMode) { + AddNode = IREmit->_VFAdd(8, 8, StackNode1, StackNode2); + } else { + AddNode = IREmit->_F80Add(StackNode1, StackNode2); + } + StoreStackValueAtOffset_Slow(StackOffset1, AddNode, false); + } else { + // Fast path + LogMan::Msg::DFmt("Fast path F80ADDSTACK"); + Ref AddNode = {}; + if (ReducedPrecisionMode) { + AddNode = IREmit->_VFAdd(8, 8, StackMember1.StackDataNode, StackMember2.StackDataNode); + } else { + AddNode = IREmit->_F80Add(StackMember1.StackDataNode, StackMember2.StackDataNode); + } + // Store it in the stack + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember1.SourceDataSize, + .StackDataSize = StackMember1.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = AddNode, + .InterpretAsFloat = StackMember1.InterpretAsFloat}, + StackOffset1); + } + + IREmit->Remove(CodeNode); + break; + } + case IR::OP_F80ADDVALUE: { + + + LogMan::Msg::DFmt("F80ADDVALUE"); + const auto* Op = IROp->C(); + auto* ValueNode = CurrentIR.GetNode(Op->X80Src); + auto StackOffset = Op->SrcStack; + + const auto& [Valid, StackMember] = StackData.top(StackOffset); + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + if (SlowPath) { // slow path + LogMan::Msg::DFmt("Slow path F80ADDVALUE"); + + // Load the current value from the x87 fpu stack + auto* StackNode = LoadStackValueAtOffset_Slow(StackOffset); + Ref AddNode = {}; + if (ReducedPrecisionMode) { + AddNode = IREmit->_VFAdd(8, 8, ValueNode, StackNode); + } else { + AddNode = IREmit->_F80Add(ValueNode, StackNode); + } + // Store it in stack TOP + LogMan::Msg::DFmt("Storing node to TOP of stack"); + // We know top is valid if it's source so no need to set it as such. + // Only set it if source is not top. + StoreStackValueAtTop_Slow(AddNode, StackOffset != 0); + } else { + LogMan::Msg::DFmt("Fast path F80ADDVALUE"); + + Ref AddNode = {}; + if (ReducedPrecisionMode) { + AddNode = IREmit->_VFAdd(8, 8, ValueNode, StackMember.StackDataNode); + } else { + AddNode = IREmit->_F80Add(ValueNode, StackMember.StackDataNode); + } + // Store it in the stack + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = AddNode, + .InterpretAsFloat = StackMember.InterpretAsFloat}); + } + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80SUBSTACK: { + + + LogMan::Msg::DFmt("OP_F80SUBSTACK"); + const auto* Op = IROp->C(); + + // Adds two elements in the stack by offset. + auto StackDest = Op->DstStack; + auto StackOffset1 = Op->SrcStack1; + auto StackOffset2 = Op->SrcStack2; + + const auto& [Valid1, StackMember1] = StackData.top(StackOffset1); + const auto& [Valid2, StackMember2] = StackData.top(StackOffset2); + + MigrateToSlowPathIf(Valid1 != StackSlot::VALID || Valid2 != StackSlot::VALID); + + if (SlowPath) { // Slow Path + LogMan::Msg::DFmt("Slow path F80SUBSTACK"); + + // Load the current value from the x87 fpu stack + auto* StackNode1 = LoadStackValueAtOffset_Slow(StackOffset1); + auto* StackNode2 = LoadStackValueAtOffset_Slow(StackOffset2); + + Ref SubNode {}; + if (ReducedPrecisionMode) { + SubNode = IREmit->_VFSub(8, 8, StackNode1, StackNode2); + } else { + SubNode = IREmit->_F80Sub(StackNode1, StackNode2); + } + StoreStackValueAtOffset_Slow(StackDest, SubNode, StackDest != StackOffset1 && StackDest != StackOffset2); + } else { + // Fast path + LogMan::Msg::DFmt("Fast path F80SUBSTACK"); + Ref SubNode {}; + if (ReducedPrecisionMode) { + SubNode = IREmit->_VFSub(8, 8, StackMember1.StackDataNode, StackMember2.StackDataNode); + } else { + SubNode = IREmit->_F80Sub(StackMember1.StackDataNode, StackMember2.StackDataNode); + } + // Store it in the stack + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember1.SourceDataSize, + .StackDataSize = StackMember1.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = SubNode, + .InterpretAsFloat = StackMember1.InterpretAsFloat}, + StackDest); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80SUBRVALUE: + case IR::OP_F80SUBVALUE: { + + + LogMan::Msg::DFmt("F80SUBVALUE"); + const auto* Op = IROp->C(); + auto* ValueNode = CurrentIR.GetNode(Op->X80Src); + + auto StackOffset = Op->SrcStack; + const auto& [Valid, StackMember] = StackData.top(StackOffset); + + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + if (SlowPath) { // slow path + LogMan::Msg::DFmt("Slow path F80SUBVALUE"); + + // Load the current value from the x87 fpu stack + auto* StackNode = LoadStackValueAtOffset_Slow(StackOffset); + + Ref SubNode {}; + if (IROp->Op == IR::OP_F80SUBVALUE) { + if (ReducedPrecisionMode) { + SubNode = IREmit->_VFSub(8, 8, StackNode, ValueNode); + } else { + SubNode = IREmit->_F80Sub(StackNode, ValueNode); + } + } else { + if (ReducedPrecisionMode) { + SubNode = IREmit->_VFSub(8, 8, ValueNode, StackNode); + } else { + SubNode = IREmit->_F80Sub(ValueNode, StackNode); // IR::OP_F80SUBRVALUE + } + } + + // Store it in stack TOP + StoreStackValueAtTop_Slow(SubNode, StackOffset != 0); + } else { + LogMan::Msg::DFmt("Fast path F80SUBVALUE"); + Ref SubNode {}; + if (IROp->Op == IR::OP_F80SUBVALUE) { + if (ReducedPrecisionMode) { + SubNode = IREmit->_VFSub(8, 8, StackMember.StackDataNode, ValueNode); + + } else { + SubNode = IREmit->_F80Sub(StackMember.StackDataNode, ValueNode); + } + } else { + if (ReducedPrecisionMode) { + SubNode = IREmit->_VFSub(8, 8, ValueNode, StackMember.StackDataNode); + } else { + SubNode = IREmit->_F80Sub(ValueNode, StackMember.StackDataNode); // IR::OP_F80SUBRVALUE + } + } + // Store it in the stack + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = SubNode, + .InterpretAsFloat = StackMember.InterpretAsFloat}); + } + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80DIVSTACK: { + + + LogMan::Msg::DFmt("OP_F80DIVSTACK"); + const auto* Op = IROp->C(); + + // Adds two elements in the stack by offset. + auto StackDest = Op->DstStack; + auto StackOffset1 = Op->SrcStack1; + auto StackOffset2 = Op->SrcStack2; + + const auto& [Valid1, StackMember1] = StackData.top(StackOffset1); + const auto& [Valid2, StackMember2] = StackData.top(StackOffset2); + + MigrateToSlowPathIf(Valid1 != StackSlot::VALID || Valid2 != StackSlot::VALID); + + if (SlowPath) { // Slow Path + + LogMan::Msg::DFmt("Slow path F80DIVSTACK"); + + // Load the current value from the x87 fpu stack + auto* StackNode1 = LoadStackValueAtOffset_Slow(StackOffset1); + auto* StackNode2 = LoadStackValueAtOffset_Slow(StackOffset2); + + Ref DivNode {}; + if (ReducedPrecisionMode) { + DivNode = IREmit->_VFDiv(8, 8, StackNode1, StackNode2); + } else { + DivNode = IREmit->_F80Div(StackNode1, StackNode2); + } + StoreStackValueAtOffset_Slow(StackDest, DivNode, StackOffset1 != StackDest && StackOffset2 != StackDest); + } else { + // Fast path + LogMan::Msg::DFmt("Fast path F80DIVSTACK"); + Ref DivNode {}; + if (ReducedPrecisionMode) { + DivNode = IREmit->_VFDiv(8, 8, StackMember1.StackDataNode, StackMember2.StackDataNode); + } else { + DivNode = IREmit->_F80Div(StackMember1.StackDataNode, StackMember2.StackDataNode); + } + // Store it in the stack + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember1.SourceDataSize, + .StackDataSize = StackMember1.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = DivNode, + .InterpretAsFloat = StackMember1.InterpretAsFloat}, + StackDest); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80DIVRVALUE: + case IR::OP_F80DIVVALUE: { + + + LogMan::Msg::DFmt("F80DIVVALUE"); + const auto* Op = IROp->C(); + auto* ValueNode = CurrentIR.GetNode(Op->X80Src); + + auto StackOffset = Op->SrcStack; + const auto& [Valid, StackMember] = StackData.top(StackOffset); + + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + if (SlowPath) { // slow path + LogMan::Msg::DFmt("Slow path F80DIVVALUE"); + + // Load the current value from the x87 fpu stack + auto* StackNode = LoadStackValueAtOffset_Slow(StackOffset); + + Ref DivNode = nullptr; + if (IROp->Op == IR::OP_F80DIVVALUE) { + if (ReducedPrecisionMode) { + DivNode = IREmit->_VFDiv(8, 8, StackNode, ValueNode); + } else { + DivNode = IREmit->_F80Div(StackNode, ValueNode); + } + } else { + if (ReducedPrecisionMode) { + DivNode = IREmit->_VFDiv(8, 8, ValueNode, StackNode); + } else { + DivNode = IREmit->_F80Div(ValueNode, StackNode); // IR::OP_F80DIVRVALUE + } + } + + // Store it in stack TOP + StoreStackValueAtTop_Slow(DivNode, StackOffset != 0); + } else { + LogMan::Msg::DFmt("Fast path F80DIVVALUE"); + Ref DivNode {}; + if (IROp->Op == IR::OP_F80DIVVALUE) { + if (ReducedPrecisionMode) { + DivNode = IREmit->_VFDiv(8, 8, StackMember.StackDataNode, ValueNode); + } else { + DivNode = IREmit->_F80Div(StackMember.StackDataNode, ValueNode); + } + } else { + if (ReducedPrecisionMode) { + DivNode = IREmit->_VFDiv(8, 8, ValueNode, StackMember.StackDataNode); + } else { + DivNode = IREmit->_F80Div(ValueNode, StackMember.StackDataNode); // IR::OP_F80SUBRVALUE + } + } + // Store it in the stack + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = DivNode, + .InterpretAsFloat = StackMember.InterpretAsFloat}); + } + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80MULSTACK: { + + + LogMan::Msg::DFmt("OP_F80MULSTACK"); + const auto* Op = IROp->C(); + + // Multiplies two elements in the stack by offset. + auto StackOffset1 = Op->SrcStack1; + auto StackOffset2 = Op->SrcStack2; + + const auto& [Valid1, StackMember1] = StackData.top(StackOffset1); + const auto& [Valid2, StackMember2] = StackData.top(StackOffset2); + + MigrateToSlowPathIf(Valid1 != StackSlot::VALID || Valid2 != StackSlot::VALID); + + if (SlowPath) { // Slow Path + LogMan::Msg::DFmt("Slow path F80MULSTACK"); + + // Load the current value from the x87 fpu stack + auto* StackNode1 = LoadStackValueAtOffset_Slow(StackOffset1); + auto* StackNode2 = LoadStackValueAtOffset_Slow(StackOffset2); + + Ref MulNode = nullptr; + if (ReducedPrecisionMode) { + MulNode = IREmit->_VFMul(8, 8, StackNode1, StackNode2); + } else { + MulNode = IREmit->_F80Mul(StackNode1, StackNode2); + } + + StoreStackValueAtOffset_Slow(StackOffset1, MulNode, false); + } else { + // Fast Path + LogMan::Msg::DFmt("Fast path F80MULSTACK"); + Ref MulNode = nullptr; + if (ReducedPrecisionMode) { + MulNode = IREmit->_VFMul(8, 8, StackMember1.StackDataNode, StackMember2.StackDataNode); + } else { + MulNode = IREmit->_F80Mul(StackMember1.StackDataNode, StackMember2.StackDataNode); + } + + // Store it in the stack + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember1.SourceDataSize, + .StackDataSize = StackMember1.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = MulNode, + .InterpretAsFloat = StackMember1.InterpretAsFloat}, + StackOffset1); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80MULVALUE: { + + + LogMan::Msg::DFmt("F80MULVALUE"); + const auto* Op = IROp->C(); + auto* ValueNode = CurrentIR.GetNode(Op->X80Src); + + auto StackOffset = Op->SrcStack; + const auto& [Valid, StackMember] = StackData.top(StackOffset); + + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + if (SlowPath) { // slow path + LogMan::Msg::DFmt("Slow path F80MulVALUE"); + // Load the current value from the x87 fpu stack + auto* StackNode = LoadStackValueAtOffset_Slow(StackOffset); + Ref MulNode = nullptr; + if (ReducedPrecisionMode) { + MulNode = IREmit->_VFMul(8, 8, ValueNode, StackNode); + } else { + MulNode = IREmit->_F80Mul(ValueNode, StackNode); + } + + // Store it in stack TOP + StoreStackValueAtTop_Slow(MulNode, StackOffset != 0); + } else { + LogMan::Msg::DFmt("Fast path F80MULVALUE"); + Ref MulNode = nullptr; + if (ReducedPrecisionMode) { + MulNode = IREmit->_VFMul(8, 8, ValueNode, StackMember.StackDataNode); + } else { + MulNode = IREmit->_F80Mul(ValueNode, StackMember.StackDataNode); + } + + // Store it in the stack + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = MulNode, + .InterpretAsFloat = StackMember.InterpretAsFloat}); + } + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80STACKXCHANGE: { + + + LogMan::Msg::DFmt("F80Xchange"); + const auto* Op = IROp->C(); + auto Offset = Op->SrcStack; + + const auto& [ValidTop, StackTop] = StackData.top(); + const auto& [Valid, StackMember] = StackData.top(Offset); + + MigrateToSlowPathIf(ValidTop != StackSlot::VALID || Valid != StackSlot::VALID); + + if (SlowPath) { // slow path + auto* ValueTop = LoadStackValueAtTop_Slow(); + auto* ValueOffset = LoadStackValueAtOffset_Slow(Offset); + StoreStackValueAtTop_Slow(ValueOffset, false); + StoreStackValueAtOffset_Slow(Offset, ValueTop, false); + } else { // fast path + auto Tmp = StackTop; + StackData.setTop(StackMember); + StackData.setTop(Tmp, Offset); + } + IREmit->Remove(CodeNode); + break; + } + + case OP_F80STACKCHANGESIGN: { + + + LogMan::Msg::DFmt("F80ChangeSign"); + const auto& [Valid, StackMember] = StackData.top(); + + // We need a couple of intermediate instructions to change the sign + // of a value + Ref HelperNode {}; + if (!ReducedPrecisionMode) { + Ref Low = GetConstant(0); + Ref High = GetConstant(0b1'000'0000'0000'0000ULL); + HelperNode = IREmit->_VCastFromGPR(16, 8, Low); + HelperNode = IREmit->_VInsGPR(16, 8, 1, HelperNode, High); + } + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + if (SlowPath) { // slow path + Ref ResultNode {}; + Ref Value = LoadStackValueAtTop_Slow(); + // Negate value + if (ReducedPrecisionMode) { + ResultNode = IREmit->_VFNeg(8, 8, Value); + } else { + ResultNode = IREmit->_VXor(16, 1, Value, HelperNode); + } + StoreStackValueAtTop_Slow(ResultNode, false); + } else { // fast path + StackData.setTop(StackMemberInfo { + .SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = ReducedPrecisionMode ? IREmit->_VFNeg(8, 8, StackMember.StackDataNode) : + IREmit->_VXor(16, 1, StackMember.StackDataNode, HelperNode), + + }); + } + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80STACKABS: { + + + LogMan::Msg::DFmt("F80Abs"); + const auto& [Valid, StackMember] = StackData.top(); + + Ref HelperNode {}; + if (!ReducedPrecisionMode) { + // Intermediate insts + // FIXME: maybe we could just remove this OP and have a VAND Stack instead. + Ref Low = GetConstant(~0ULL); + Ref High = GetConstant(0b0'111'1111'1111'1111ULL); + HelperNode = IREmit->_VCastFromGPR(16, 8, Low); + HelperNode = IREmit->_VInsGPR(16, 8, 1, HelperNode, High); + } + + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + if (SlowPath) { + // slow path + Ref Value = LoadStackValueAtTop_Slow(); + Ref ResultNode {}; + if (ReducedPrecisionMode) { + ResultNode = IREmit->_VFAbs(8, 8, Value); + } else { + ResultNode = IREmit->_VAnd(16, 1, Value, HelperNode); + } + StoreStackValueAtTop_Slow(ResultNode, false); + } else { + // fast path + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = ReducedPrecisionMode ? IREmit->_VFAbs(8, 8, StackMember.StackDataNode) : + IREmit->_VAnd(16, 1, StackMember.StackDataNode, HelperNode), + .InterpretAsFloat = StackMember.InterpretAsFloat}); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80STACKFYL2X: { + + + LogMan::Msg::DFmt("OP_F80STACKFYL2X"); + const auto& [Valid1, StackMember1] = StackData.top(); + const auto& [Valid2, StackMember2] = StackData.top(1); + + MigrateToSlowPathIf(Valid1 != StackSlot::VALID || Valid2 != StackSlot::VALID); + + if (SlowPath) { + // slow path + auto* st0 = LoadStackValueAtTop_Slow(); + auto* st1 = LoadStackValueAtOffset_Slow(1); + + Ref Result {}; + if (ReducedPrecisionMode) { + Result = IREmit->_F64FYL2X(st0, st1); + } else { + Result = IREmit->_F80FYL2X(st0, st1); + } + StoreStackValueAtOffset_Slow(1, Result, false); // stores at st1 + UpdateTop4Pop_Slow(); // updates top + } else { + // fast path + auto Tmp = StackMember1; + StackData.pop(); // we need to write the result st1, so if popping and setTop has the same behaviour + StackData.setTop( + StackMemberInfo {.SourceDataSize = StackMember1.SourceDataSize, + .StackDataSize = StackMember1.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = ReducedPrecisionMode ? IREmit->_F64FYL2X(Tmp.StackDataNode, StackMember2.StackDataNode) : + IREmit->_F80FYL2X(Tmp.StackDataNode, StackMember2.StackDataNode), + .InterpretAsFloat = StackMember1.InterpretAsFloat}); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80CMPSTACK: { + + + LogMan::Msg::DFmt("OP_F80CMPSTACK"); + const auto* Op = IROp->C(); + auto offset = Op->SrcStack; + const auto& [Valid1, StackMember1] = StackData.top(); + const auto& [Valid2, StackMember2] = StackData.top(offset); + + MigrateToSlowPathIf(Valid1 != StackSlot::VALID || Valid2 != StackSlot::VALID); + + Ref CmpNode {}; + if (SlowPath) { + // slow path + LogMan::Msg::DFmt("OP_F80CMPSTACK Slow"); + Ref StackValue1 = LoadStackValueAtTop_Slow(); + Ref StackValue2 = LoadStackValueAtOffset_Slow(offset); + if (ReducedPrecisionMode) { + CmpNode = IREmit->_FCmp(8, StackValue1, StackValue2); + } else { + CmpNode = IREmit->_F80Cmp(StackValue1, StackValue2, Op->Flags); + } + } else { + // fast path + LogMan::Msg::DFmt("OP_F80CMPSTACK Fast"); + if (ReducedPrecisionMode) { + CmpNode = IREmit->_FCmp(8, StackMember1.StackDataNode, StackMember2.StackDataNode); + } else { + CmpNode = IREmit->_F80Cmp(StackMember1.StackDataNode, StackMember2.StackDataNode, Op->Flags); + } + } + IREmit->ReplaceUsesWithAfter(CodeNode, CmpNode, CodeNode); + IREmit->Remove(CodeNode); + break; + } + case IR::OP_F80STACKTEST: { + + + LogMan::Msg::DFmt("OP_F80STACKTEST"); + const auto* Op = IROp->C(); + auto offset = Op->SrcStack; + const auto& [Valid, StackMember] = StackData.top(offset); + + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + Ref CmpNode {}; + Ref ZeroConst = IREmit->_VCastFromGPR(ReducedPrecisionMode ? 8 : 16, 8, GetConstant(0)); + + if (SlowPath) { + // slow path + LogMan::Msg::DFmt("OP_F80STACKTEST Slow"); + auto* StackValue = LoadStackValueAtOffset_Slow(offset); + if (ReducedPrecisionMode) { + CmpNode = IREmit->_FCmp(8, StackValue, ZeroConst); + } else { + CmpNode = IREmit->_F80Cmp(StackValue, ZeroConst, Op->Flags); + } + } else { + // fast path + LogMan::Msg::DFmt("OP_F80STACKTEST Fast"); + if (ReducedPrecisionMode) { + CmpNode = IREmit->_FCmp(8, StackMember.StackDataNode, ZeroConst); + } else { + CmpNode = IREmit->_F80Cmp(StackMember.StackDataNode, ZeroConst, Op->Flags); + } + } + IREmit->ReplaceUsesWithAfter(CodeNode, CmpNode, CodeNode); + IREmit->Remove(CodeNode); + break; + } + + + case IR::OP_F80CMPVALUE: { + + + LogMan::Msg::DFmt("OP_F80CMPVALUE"); + const auto* Op = IROp->C(); + const auto& Value = CurrentIR.GetNode(Op->X80Src); + const auto& [Valid, StackMember] = StackData.top(); + + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + Ref CmpNode = nullptr; + if (SlowPath) { + // slow path + auto* StackValue = LoadStackValueAtTop_Slow(); + if (ReducedPrecisionMode) { + CmpNode = IREmit->_FCmp(8, StackValue, Value); + } else { + CmpNode = IREmit->_F80Cmp(StackValue, Value, Op->Flags); + } + } else { + // fast path + if (ReducedPrecisionMode) { + CmpNode = IREmit->_FCmp(8, StackMember.StackDataNode, Value); + } else { + CmpNode = IREmit->_F80Cmp(StackMember.StackDataNode, Value, Op->Flags); + } + } + + IREmit->Remove(CodeNode); + IREmit->ReplaceUsesWithAfter(CodeNode, CmpNode, CodeNode); + break; + } + + case IR::OP_F80ATANSTACK: { + + + LogMan::Msg::DFmt("OP_F80ATANSTACK"); + const auto& [Valid1, StackMember1] = StackData.top(); + const auto& [Valid2, StackMember2] = StackData.top(1); + + MigrateToSlowPathIf(Valid1 != StackSlot::VALID || Valid2 != StackSlot::VALID); + + if (SlowPath) { + // slow path + Ref st0 = LoadStackValueAtTop_Slow(); + Ref st1 = LoadStackValueAtOffset_Slow(1); + Ref Result {}; + if (ReducedPrecisionMode) { + Result = IREmit->_F64ATAN(st1, st0); + } else { + Result = IREmit->_F80ATAN(st1, st0); + } + StoreStackValueAtOffset_Slow(1, Result, false); + UpdateTop4Pop_Slow(); + } else { + // fast path + Ref st0 = StackMember1.StackDataNode; + Ref st1 = StackMember2.StackDataNode; + + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember1.SourceDataSize, + .StackDataSize = StackMember1.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = ReducedPrecisionMode ? IREmit->_F64ATAN(st1, st0) : IREmit->_F80ATAN(st1, st0), + .InterpretAsFloat = StackMember1.InterpretAsFloat}, + 1); + StackData.pop(); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80PTANSTACK: { + + + LogMan::Msg::DFmt("OP_F80PTANSTACK"); + const auto& [Valid, StackMember] = StackData.top(); + + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + Ref OneConst {}; + if (ReducedPrecisionMode) { + OneConst = IREmit->_VCastFromGPR(8, 8, GetConstant(0x3FF0000000000000)); + } else { + OneConst = IREmit->_LoadNamedVectorConstant(16, NamedVectorConstant::NAMED_VECTOR_X87_ONE); + } + + if (SlowPath) { + // slow path + auto* st0 = LoadStackValueAtTop_Slow(); + Ref Value = {}; + if (ReducedPrecisionMode) { + Value = IREmit->_F64TAN(st0); + } else { + Value = IREmit->_F80TAN(st0); + } + StoreStackValueAtTop_Slow(Value, false); + UpdateTop4Push_Slow(); + StoreStackValueAtTop_Slow(OneConst); + } else { + // fast path + auto* st0 = StackMember.StackDataNode; + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = ReducedPrecisionMode ? IREmit->_F64TAN(st0) : IREmit->_F80TAN(st0), + .InterpretAsFloat = true}); + StackData.push(StackMemberInfo {.SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = OneConst, + .InterpretAsFloat = false}); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80XTRACTSTACK: { + + + LogMan::Msg::DFmt("OP_F80XTRACTSTACK"); + const auto& [Valid, StackMember] = StackData.top(); + + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + if (SlowPath) { + // slow path + Ref st0 = LoadStackValueAtTop_Slow(); + Ref Exp {}; + Ref Sig {}; + if (ReducedPrecisionMode) { + std::tie(Exp, Sig) = SplitF64SigExp(st0); + } else { + Exp = IREmit->_F80XTRACT_EXP(st0); + Sig = IREmit->_F80XTRACT_SIG(st0); + } + // Write exp to top, update top for a push and set sig at new top. + StoreStackValueAtTop_Slow(Exp, false); + UpdateTop4Push_Slow(); + StoreStackValueAtTop_Slow(Sig); + } else { + // fast path + Ref st0 = StackMember.StackDataNode; + Ref Exp {}; + Ref Sig {}; + + if (ReducedPrecisionMode) { + std::tie(Exp, Sig) = SplitF64SigExp(st0); + } else { + Exp = IREmit->_F80XTRACT_EXP(st0); + Sig = IREmit->_F80XTRACT_SIG(st0); + } + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = Exp, + .InterpretAsFloat = StackMember.InterpretAsFloat}); + StackData.push(StackMemberInfo {.SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = Sig, + .InterpretAsFloat = StackMember.InterpretAsFloat}); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80FPREMSTACK: { + + + LogMan::Msg::DFmt("F80FPREMStack"); + const auto& [Valid1, StackMember1] = StackData.top(); + const auto& [Valid2, StackMember2] = StackData.top(1); + + MigrateToSlowPathIf(Valid1 != StackSlot::VALID || Valid2 != StackSlot::VALID); + + if (SlowPath) { + // slow path + auto* st0 = LoadStackValueAtTop_Slow(); + auto* st1 = LoadStackValueAtOffset_Slow(1); + + Ref Value {}; + if (ReducedPrecisionMode) { + Value = IREmit->_F64FPREM(st0, st1); + } else { + Value = IREmit->_F80FPREM(st0, st1); + } + StoreStackValueAtTop_Slow(Value, false); + } else { // fast path + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember1.SourceDataSize, + .StackDataSize = StackMember1.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = ReducedPrecisionMode ? + IREmit->_F64FPREM(StackMember1.StackDataNode, StackMember2.StackDataNode) : + IREmit->_F80FPREM(StackMember1.StackDataNode, StackMember2.StackDataNode), + .InterpretAsFloat = StackMember1.InterpretAsFloat}); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80FPREM1STACK: { + + + LogMan::Msg::DFmt("F80FPREM1Stack"); + const auto& [Valid1, StackMember1] = StackData.top(); + const auto& [Valid2, StackMember2] = StackData.top(1); + + MigrateToSlowPathIf(Valid1 != StackSlot::VALID || Valid2 != StackSlot::VALID); + + if (SlowPath) { + // slow path + auto* st0 = LoadStackValueAtTop_Slow(); + auto* st1 = LoadStackValueAtOffset_Slow(1); + + Ref Value {}; + if (ReducedPrecisionMode) { + Value = IREmit->_F64FPREM1(st0, st1); + } else { + Value = IREmit->_F80FPREM1(st0, st1); + } + StoreStackValueAtTop_Slow(Value, false); + } else { // fast path + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember1.SourceDataSize, + .StackDataSize = StackMember1.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = ReducedPrecisionMode ? + IREmit->_F64FPREM1(StackMember1.StackDataNode, StackMember2.StackDataNode) : + IREmit->_F80FPREM1(StackMember1.StackDataNode, StackMember2.StackDataNode), + .InterpretAsFloat = StackMember1.InterpretAsFloat}); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80SCALESTACK: { + + + LogMan::Msg::DFmt("F80FPSCALE"); + const auto& [Valid1, StackMember1] = StackData.top(); + const auto& [Valid2, StackMember2] = StackData.top(1); + + MigrateToSlowPathIf(Valid1 != StackSlot::VALID || Valid2 != StackSlot::VALID); + + if (SlowPath) { + // slow path + auto* st0 = LoadStackValueAtTop_Slow(); + auto* st1 = LoadStackValueAtOffset_Slow(1); + + Ref Value {}; + if (ReducedPrecisionMode) { + Value = IREmit->_F64SCALE(st0, st1); + } else { + Value = IREmit->_F80SCALE(st0, st1); + } + StoreStackValueAtTop_Slow(Value, false); + } else { // fast path + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember1.SourceDataSize, + .StackDataSize = StackMember1.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = ReducedPrecisionMode ? + IREmit->_F64SCALE(StackMember1.StackDataNode, StackMember2.StackDataNode) : + IREmit->_F80SCALE(StackMember1.StackDataNode, StackMember2.StackDataNode), + .InterpretAsFloat = StackMember1.InterpretAsFloat}); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80SQRTSTACK: { + + + LogMan::Msg::DFmt("F80SQRTSTACK"); + const auto& [Valid, StackMember] = StackData.top(); + + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + if (SlowPath) { + // slow path + auto* st0 = LoadStackValueAtTop_Slow(); + Ref Value {}; + if (ReducedPrecisionMode) { + Value = IREmit->_VFSqrt(8, 8, st0); + } else { + Value = IREmit->_F80SQRT(st0); + } + StoreStackValueAtTop_Slow(Value, false); + } else { + // fast path + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = ReducedPrecisionMode ? IREmit->_VFSqrt(8, 8, StackMember.StackDataNode) : + IREmit->_F80SQRT(StackMember.StackDataNode), + .InterpretAsFloat = StackMember.InterpretAsFloat}); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80SINSTACK: { + + + LogMan::Msg::DFmt("F80SINSTACK"); + const auto& [Valid, StackMember] = StackData.top(); + + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + if (SlowPath) { + // slow path + auto* st0 = LoadStackValueAtTop_Slow(); + Ref Value {}; + if (ReducedPrecisionMode) { + Value = IREmit->_F64SIN(st0); + } else { + Value = IREmit->_F80SIN(st0); + } + StoreStackValueAtTop_Slow(Value, false); + } else { + // fast path + StackData.setTop(StackMemberInfo { + .SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = ReducedPrecisionMode ? IREmit->_F64SIN(StackMember.StackDataNode) : IREmit->_F80SIN(StackMember.StackDataNode), + .InterpretAsFloat = StackMember.InterpretAsFloat}); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80COSSTACK: { + + + LogMan::Msg::DFmt("F80COSSTACK"); + const auto& [Valid, StackMember] = StackData.top(); + + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + if (SlowPath) { + // slow path + auto* st0 = LoadStackValueAtTop_Slow(); + Ref Value {}; + if (ReducedPrecisionMode) { + Value = IREmit->_F64COS(st0); + } else { + Value = IREmit->_F80COS(st0); + } + StoreStackValueAtTop_Slow(Value, false); + } else { + // fast path + StackData.setTop(StackMemberInfo { + .SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = ReducedPrecisionMode ? IREmit->_F64COS(StackMember.StackDataNode) : IREmit->_F80COS(StackMember.StackDataNode), + .InterpretAsFloat = StackMember.InterpretAsFloat}); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80F2XM1STACK: { + + + LogMan::Msg::DFmt("F80F2XM1STACK"); + const auto& [Valid, StackMember] = StackData.top(); + + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + if (SlowPath) { + // slow path + auto* st0 = LoadStackValueAtTop_Slow(); + Ref Value {}; + if (ReducedPrecisionMode) { + Value = IREmit->_F64F2XM1(st0); + } else { + Value = IREmit->_F80F2XM1(st0); + } + StoreStackValueAtTop_Slow(Value, false); + } else { + // fast path + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = ReducedPrecisionMode ? IREmit->_F64F2XM1(StackMember.StackDataNode) : + IREmit->_F80F2XM1(StackMember.StackDataNode), + .InterpretAsFloat = StackMember.InterpretAsFloat}); + } + + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_SYNCSTACKTOSLOW: { + + + LogMan::Msg::DFmt("SYNCSTACKTOSLOW"); + + // This synchronizes stack values but doesn't necessarily moves us off the FastPath! + Ref NewTop = SynchronizeStackValues(); + IREmit->ReplaceUsesWithAfter(CodeNode, NewTop, CodeNode); + IREmit->Remove(CodeNode); + + break; + } + + case IR::OP_STACKFORCESLOW: { + + + LogMan::Msg::DFmt("STACKFORCESLOW"); + + MigrateToSlowPathIf(true); + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_INCSTACKTOP: { + + + LogMan::Msg::DFmt("INCSTACKTOP"); + + if (SlowPath) { + UpdateTop4Pop_Slow(); + } else { + StackData.rotate(false); + } + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_DECSTACKTOP: { + + + LogMan::Msg::DFmt("DECSTACKTOP"); + + if (SlowPath) { + UpdateTop4Push_Slow(); + } else { + StackData.rotate(true); + } + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80ROUNDSTACK: { + + + LogMan::Msg::DFmt("F80ROUNDSTACK"); + + const auto& [Valid, StackMember] = StackData.top(); + MigrateToSlowPathIf(Valid != StackSlot::VALID); + + if (SlowPath) { + auto* st0 = LoadStackValueAtTop_Slow(); + Ref Value {}; + if (ReducedPrecisionMode) { + Value = IREmit->_Vector_FToI(8, 8, st0, FEXCore::IR::Round_Host); + } else { + Value = IREmit->_F80Round(st0); + } + StoreStackValueAtTop_Slow(Value, false); + } else { + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember.SourceDataSize, + .StackDataSize = StackMember.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = ReducedPrecisionMode ? + IREmit->_Vector_FToI(8, 8, StackMember.StackDataNode, FEXCore::IR::Round_Host) : + IREmit->_F80Round(StackMember.StackDataNode), + .InterpretAsFloat = false}); + } + IREmit->Remove(CodeNode); + break; + } + + case IR::OP_F80VBSLSTACK: { + + + LogMan::Msg::DFmt("F80VBSLStack"); + + const auto* Op = IROp->C(); + + // Multiplies two elements in the stack by offset. + auto* VecCond = CurrentIR.GetNode(Op->VectorMask); + auto StackOffset1 = Op->SrcStack1; + auto StackOffset2 = Op->SrcStack2; + + const auto& [Valid1, StackMember1] = StackData.top(StackOffset1); + const auto& [Valid2, StackMember2] = StackData.top(StackOffset2); + + MigrateToSlowPathIf(Valid1 != StackSlot::VALID || Valid2 != StackSlot::VALID); + + if (SlowPath) { // Slow Path + auto* Value1 = LoadStackValueAtOffset_Slow(StackOffset1); + auto* Value2 = LoadStackValueAtOffset_Slow(StackOffset2); + + StoreStackValueAtTop_Slow(IREmit->_VBSL(16, VecCond, Value1, Value2), StackOffset1 != 0 && StackOffset2 != 0); + } else { + StackData.setTop(StackMemberInfo {.SourceDataSize = StackMember1.SourceDataSize, + .StackDataSize = StackMember1.StackDataSize, + .SourceDataNode = nullptr, + .StackDataNode = IREmit->_VBSL(16, VecCond, StackMember1.StackDataNode, StackMember2.StackDataNode), + .InterpretAsFloat = false}); + } + + IREmit->Remove(CodeNode); + break; + } + + default: break; + } + } + LogMan::Msg::DFmt("Finished Block Processing"); + + // We need to write the registers before any branch in the block, + // so loop until a branch instruction is found. Add instructions _before_ + // the branch instruction. + [[maybe_unused]] bool ExitFound = false; // used for assertion + for (auto [CodeNode, IROp] : CurrentIR.GetCode(BlockNode)) { + if (IR::IsBlockExit(IROp->Op)) { + LogMan::Msg::DFmt("Found a block exit!"); + // Set write cursor to previous instruction + IREmit->SetWriteCursor(IREmit->UnwrapNode(CodeNode->Header.Previous)); + ExitFound = true; + break; + } + } + LOGMAN_THROW_A_FMT(ExitFound, "No block exit found is bad!"); + SynchronizeStackValues(); + IREmit->SetWriteCursor(OriginalWriteCursor); + LogMan::Msg::DFmt("===================================================\n\n"); + } + + return; +} + +fextl::unique_ptr CreateX87StackOptimizationPass() { + return fextl::make_unique(); +} +} // namespace FEXCore::IR diff --git a/Source/Common/Config.cpp b/Source/Common/Config.cpp index 093e116825..8fd5ea048a 100644 --- a/Source/Common/Config.cpp +++ b/Source/Common/Config.cpp @@ -168,6 +168,7 @@ MainLoader::MainLoader(FEXCore::Config::LayerType Type, const char* ConfigFile) , Config {ConfigFile} {} void MainLoader::Load() { + fextl::fmt::print(stderr, "[MainLoader] Loading config file: {}\n", Config.c_str()); JSON::LoadJSonConfig(Config, [this](const char* Name, const char* ConfigString) { MapNameToOption(Name, ConfigString); }); } @@ -181,6 +182,7 @@ AppLoader::AppLoader(const fextl::string& Filename, FEXCore::Config::LayerType T } void AppLoader::Load() { + fextl::fmt::print(stderr, "[AppLoader] Loading config file: {}\n", Config.c_str()); JSON::LoadJSonConfig(Config, [this](const char* Name, const char* ConfigString) { MapNameToOption(Name, ConfigString); }); } diff --git a/docs/SourceOutline.md b/docs/SourceOutline.md index 9ecae62ea8..568a3b6b88 100644 --- a/docs/SourceOutline.md +++ b/docs/SourceOutline.md @@ -5,7 +5,7 @@ See [FEXCore/Readme.md](../FEXCore/Readme.md) for more details ### Glossary -- Splatter: a code generator backend that concaternates configurable macros instead of doing isel +- Splatter: a code generator backend that concatenates configurable macros instead of doing isel - IR: Intermediate Representation, our high-level opcode representation, loosely modeling arm64 - SSA: Single Static Assignment, a form of representing IR in memory - Basic Block: A block of instructions with no control flow, terminated by control flow @@ -115,6 +115,7 @@ IR to IR Optimization - [RedundantFlagCalculationElimination.cpp](../FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp): This is not used right now, possibly broken - [RegisterAllocationPass.cpp](../FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp) - [RegisterAllocationPass.h](../FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.h) +- [x87StackOptimizationPass.cpp](../FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp): x87 stack optimization pass diff --git a/unittests/ASM/Known_Failures_host b/unittests/ASM/Known_Failures_host new file mode 100644 index 0000000000..322f758bca --- /dev/null +++ b/unittests/ASM/Known_Failures_host @@ -0,0 +1 @@ +Test_X87/FXAM_Simple.asm diff --git a/unittests/ASM/X87/FXAM_Push.asm b/unittests/ASM/X87/FXAM_Push.asm index a26e039bc8..d94511f3ca 100644 --- a/unittests/ASM/X87/FXAM_Push.asm +++ b/unittests/ASM/X87/FXAM_Push.asm @@ -11,7 +11,7 @@ mov rdx, 0xe0000000 ; This behaviour was seen around Wine 32-bit libraries ; Anything doing a call to a double application would spin ; the x87 stack on to the stack looking for fxam to return empty -; Empty in this case is that C0 and C3 is set whiel C2 is not +; Empty in this case is that C0 and C3 is set while C2 is not fninit ; Fill the x87 stack diff --git a/unittests/ASM/X87/FXAM_Push_2.asm b/unittests/ASM/X87/FXAM_Push_2.asm index c6ef4ff3fd..78edde24d3 100644 --- a/unittests/ASM/X87/FXAM_Push_2.asm +++ b/unittests/ASM/X87/FXAM_Push_2.asm @@ -11,7 +11,7 @@ mov rdx, 0xe0000000 ; This behaviour was seen around Wine 32-bit libraries ; Anything doing a call to a double application would spin ; the x87 stack on to the stack looking for fxam to return empty -; Empty in this case is that C0 and C3 is set whiel C2 is not +; Empty in this case is that C0 and C3 is set while C2 is not fninit ; Empty stack to make sure we don't push anything diff --git a/unittests/ASM/X87/FXAM_Push_Simple.asm b/unittests/ASM/X87/FXAM_Push_Simple.asm new file mode 100644 index 0000000000..6454abf06a --- /dev/null +++ b/unittests/ASM/X87/FXAM_Push_Simple.asm @@ -0,0 +1,40 @@ +%ifdef CONFIG +{ + "RegData": { + "RAX": "8" + } +} +%endif + +fninit +fld1 +fld1 +fld1 +fld1 +fld1 +fld1 +fld1 +fld1 + +mov ebx, 0 + +.ExamineStack: +; Examine st(0) +fxam +fwait +; Get the results in to AX +fnstsw ax +and ax, 0x4500 +; Check for empty +cmp ax, 0x4100 +je .Done + +; Now push the x87 stack value +; We know it isn't empty +fstp st0 +fwait +inc ebx +jmp .ExamineStack +.Done: +mov eax, ebx +hlt \ No newline at end of file diff --git a/unittests/ASM/X87/FXAM_Push_Simple_2.asm b/unittests/ASM/X87/FXAM_Push_Simple_2.asm new file mode 100644 index 0000000000..7c39e21234 --- /dev/null +++ b/unittests/ASM/X87/FXAM_Push_Simple_2.asm @@ -0,0 +1,51 @@ +%ifdef CONFIG +{ + "RegData": { + "RAX": "8" + } +} +%endif + +mov rdx, 0xe0000000 + +; This behaviour was seen around Wine 32-bit libraries +; Anything doing a call to a double application would spin +; the x87 stack on to the stack looking for fxam to return empty +; Empty in this case is that C0 and C3 is set while C2 is not + +fninit +; Fill the x87 stack +fldz +fldz +fldz +fldz +fldz +fldz +fldz +fldz + +mov eax, 0 +mov ecx, 0 + +.ExamineStack: +; Examine st(0) +fxam +fwait +; Get the results in to AX +fnstsw ax +and ax, 0x4500 +; Check for empty +cmp ax, 0x4100 +je .Done + +; Now push the x87 stack value +; We know it isn't empty +fstp qword [rdx + rcx * 8] +fwait +inc ecx +jmp .ExamineStack + +.Done: +; Save how many we stored +mov eax, ecx +hlt \ No newline at end of file diff --git a/unittests/ASM/X87/FXAM_Simple.asm b/unittests/ASM/X87/FXAM_Simple.asm new file mode 100644 index 0000000000..d14849e69a --- /dev/null +++ b/unittests/ASM/X87/FXAM_Simple.asm @@ -0,0 +1,49 @@ +;; Simpler versions of FXAM_Push* tests. +;; In hostrunner tests this will fail because we mentioned below there's no support +;; for the zero flag. In hostrunner RCX should contain 0x4000 instead of 0x400. +%ifdef CONFIG +{ + "RegData": { + "RAX": "0x6", + "RBX": "0x0400", + "RCX": "0x0400", + "RDX": "0x4100" + } +} +%endif + +mov rdx, 0xe0000000 + +fninit +;; Before adding anything to the stack, lets examine it. +;; The result should be empty. +fxam +fwait + +fnstsw ax +and ax, 0x4500 ; should be 0x4100 for zero +mov edx, eax + +fldz +fxam +fwait + +fnstsw ax +and ax, 0x4500 ; should be 0x4000 for zero, but there's no support for it at the moment, so it'll return 0x0400 as it does for a normal number. +mov ecx, eax + +fld1 +fxam +fwait + +fnstsw ax +mov ebx, eax +and ebx, 0x4500 ; should be 0x0400 for normal + +;; Top should be 6 +;; right shift status word by 11 and and with 0x7. +shr eax, 11 +and eax, 0x7 + + +hlt \ No newline at end of file diff --git a/unittests/ASM/X87/Memcopy.asm b/unittests/ASM/X87/Memcopy.asm new file mode 100644 index 0000000000..47d299a203 --- /dev/null +++ b/unittests/ASM/X87/Memcopy.asm @@ -0,0 +1,21 @@ +%ifdef CONFIG +{ + "RegData": { + "RAX": "0x3ff8000000000000", + "RBX": "0x3ff8000000000000" + }, + "MemoryRegions": { + "0x100000000": "4096" + } +} +%endif + +mov rdx, 0x100000000 +mov rax, 0x3ff8000000000000 ; 1.5 +mov [rdx], rax + +fld qword [rdx] +fstp qword [rdx + 8] + +mov rbx, [rdx + 8] +hlt diff --git a/unittests/ASM/x87_stack.asm b/unittests/ASM/x87_stack.asm new file mode 100644 index 0000000000..f032ca9c60 --- /dev/null +++ b/unittests/ASM/x87_stack.asm @@ -0,0 +1,26 @@ +%ifdef CONFIG +{ + "RegData": { + "RAX": "0x4142434445464748", + "RBX": "0" + } +} +%endif + +lea rax, [rel .data] +lea rbx, [rel .data_mov] + +fld qword [rax] +fstp qword [rbx] + +mov rax, [rbx] +mov rbx, [rbx + 8] +hlt + +.data: +dq 0x4142434445464748 +dq 0x5152535455565758 + +.data_mov: +dq 0 +dq 0 diff --git a/unittests/FEXLinuxTests/Known_Failures_Host b/unittests/FEXLinuxTests/Known_Failures_Host index e69de29bb2..81acd73a95 100644 --- a/unittests/FEXLinuxTests/Known_Failures_Host +++ b/unittests/FEXLinuxTests/Known_Failures_Host @@ -0,0 +1,2 @@ +## Unable to support zero flag +FXAM_Simple.asm diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json index b238ff47d0..3a58240acf 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json @@ -146,7 +146,7 @@ ] }, "Psychonauts matrix swizzle": { - "ExpectedInstructionCount": 2406, + "ExpectedInstructionCount": 1863, "Comment": [ "Hottest block in Windows Psychonauts", "Doing a 4x4 32-bit float matrix swizzle", @@ -268,7 +268,6 @@ "mov x21, #0xffffffffffffffbc", "str w5, [x20, w21, sxtw]", "ldr w4, [x20, w21, sxtw]", - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -297,19 +296,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w22, #0x1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x22, #0xffffffffffffffc0", + "sub w23, w20, #0x40 (64)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -336,16 +324,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x23, #0xffffffffffffffc0", - "str s2, [x9, w23, sxtw]", - "ldrb w24, [x28, #1298]", - "lsl w25, w22, w20", - "bic w24, w24, w25", - "strb w24, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, w21, sxtw]", + "str s2, [x23]", + "ldr w5, [x20, w21, sxtw]", "ldr s2, [x5, #16]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -374,17 +354,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w25, w22, w20", - "orr w24, w24, w25", - "strb w24, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x23, #0xffffffffffffffc4", + "sub w24, w20, #0x3c (60)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -411,16 +382,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x24, #0xffffffffffffffc4", - "str s2, [x9, w24, sxtw]", - "ldrb w25, [x28, #1298]", - "lsl w12, w22, w20", - "bic w25, w25, w12", - "strb w25, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, w21, sxtw]", + "str s2, [x24]", + "ldr w6, [x20, w21, sxtw]", "ldr s2, [x6, #32]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -449,17 +412,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w25, w25, w12", - "strb w25, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x24, #0xffffffffffffffc8", + "sub w25, w20, #0x38 (56)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -486,16 +440,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x25, #0xffffffffffffffc8", - "str s2, [x9, w25, sxtw]", - "ldrb w12, [x28, #1298]", - "lsl w13, w22, w20", - "bic w12, w12, w13", - "strb w12, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, w21, sxtw]", + "str s2, [x25]", + "ldr w4, [x20, w21, sxtw]", "ldr s2, [x4, #48]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -524,17 +470,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w13, w22, w20", - "orr w12, w12, w13", - "strb w12, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x25, #0xffffffffffffffcc", + "sub w12, w20, #0x34 (52)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -561,16 +498,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x12, #0xffffffffffffffcc", - "str s2, [x9, w12, sxtw]", - "ldrb w13, [x28, #1298]", - "lsl w14, w22, w20", - "bic w13, w13, w14", - "strb w13, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, w21, sxtw]", + "str s2, [x12]", + "ldr w5, [x20, w21, sxtw]", "ldr s2, [x5, #4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -599,17 +528,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w14, w22, w20", - "orr w13, w13, w14", - "strb w13, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x12, #0xffffffffffffffd0", + "sub w13, w20, #0x30 (48)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -636,16 +556,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x13, #0xffffffffffffffd0", - "str s2, [x9, w13, sxtw]", - "ldrb w14, [x28, #1298]", - "lsl w15, w22, w20", - "bic w14, w14, w15", - "strb w14, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, w21, sxtw]", + "str s2, [x13]", + "ldr w6, [x20, w21, sxtw]", "ldr s2, [x6, #20]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -674,17 +586,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w15, w22, w20", - "orr w14, w14, w15", - "strb w14, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x13, #0xffffffffffffffd4", + "sub w14, w20, #0x2c (44)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -711,16 +614,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x14, #0xffffffffffffffd4", - "str s2, [x9, w14, sxtw]", - "ldrb w15, [x28, #1298]", - "lsl w16, w22, w20", - "bic w15, w15, w16", - "strb w15, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, w21, sxtw]", + "str s2, [x14]", + "ldr w4, [x20, w21, sxtw]", "ldr s2, [x4, #36]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -749,17 +644,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w16, w22, w20", - "orr w15, w15, w16", - "strb w15, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x14, #0xffffffffffffffd8", + "sub w15, w20, #0x28 (40)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -786,16 +672,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x15, #0xffffffffffffffd8", - "str s2, [x9, w15, sxtw]", - "ldrb w16, [x28, #1298]", - "lsl w17, w22, w20", - "bic w16, w16, w17", - "strb w16, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, w21, sxtw]", + "str s2, [x15]", + "ldr w5, [x20, w21, sxtw]", "ldr s2, [x5, #52]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -824,17 +702,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w17, w22, w20", - "orr w16, w16, w17", - "strb w16, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x15, #0xffffffffffffffdc", + "sub w16, w20, #0x24 (36)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -861,16 +730,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x16, #0xffffffffffffffdc", - "str s2, [x9, w16, sxtw]", - "ldrb w17, [x28, #1298]", - "lsl w29, w22, w20", - "bic w17, w17, w29", - "strb w17, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, w21, sxtw]", + "str s2, [x16]", + "ldr w6, [x20, w21, sxtw]", "ldr s2, [x6, #8]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -899,17 +760,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w29, w22, w20", - "orr w17, w17, w29", - "strb w17, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x16, #0xffffffffffffffe0", + "sub w17, w20, #0x20 (32)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -936,16 +788,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x17, #0xffffffffffffffe0", - "str s2, [x9, w17, sxtw]", - "ldrb w29, [x28, #1298]", - "lsl w30, w22, w20", - "bic w29, w29, w30", - "strb w29, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, w21, sxtw]", + "str s2, [x17]", + "ldr w4, [x20, w21, sxtw]", "ldr s2, [x4, #24]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -974,17 +818,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w30, w22, w20", - "orr w29, w29, w30", - "strb w29, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x17, #0xffffffffffffffe4", + "sub w29, w20, #0x1c (28)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1011,16 +846,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x29, #0xffffffffffffffe4", - "str s2, [x9, w29, sxtw]", - "ldrb w30, [x28, #1298]", - "lsl w19, w22, w20", - "bic w30, w30, w19", - "strb w30, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, w21, sxtw]", + "str s2, [x29]", + "ldr w5, [x20, w21, sxtw]", "ldr s2, [x5, #40]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1049,17 +876,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w19, w22, w20", - "orr w30, w30, w19", - "strb w30, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x29, #0xffffffffffffffe8", + "sub w30, w20, #0x18 (24)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1086,16 +904,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x30, #0xffffffffffffffe8", - "str s2, [x9, w30, sxtw]", - "ldrb w19, [x28, #1298]", - "lsl w30, w22, w20", - "bic w30, w19, w30", - "strb w30, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, w21, sxtw]", + "str s2, [x30]", + "ldr w6, [x20, w21, sxtw]", "ldr s2, [x6, #56]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1124,17 +934,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w19, w22, w20", - "orr w30, w30, w19", - "strb w30, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x30, #0xffffffffffffffec", + "sub w19, w20, #0x14 (20)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1161,16 +962,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x30, #0xffffffffffffffec", - "str s2, [x9, w30, sxtw]", - "ldrb w19, [x28, #1298]", - "lsl w30, w22, w20", - "bic w30, w19, w30", - "strb w30, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, w21, sxtw]", + "str s2, [x19]", + "ldr w4, [x20, w21, sxtw]", "ldr s2, [x4, #12]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1199,17 +992,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w19, w22, w20", - "orr w30, w30, w19", - "strb w30, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x19, #0xfffffffffffffff0", + "sub w19, w20, #0x10 (16)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1236,16 +1020,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x30, #0xfffffffffffffff0", - "str s2, [x9, w30, sxtw]", - "ldrb w19, [x28, #1298]", - "lsl w30, w22, w20", - "bic w30, w19, w30", - "strb w30, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, w21, sxtw]", + "str s2, [x19]", + "ldr w5, [x20, w21, sxtw]", "ldr s2, [x5, #28]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1274,17 +1050,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w19, w22, w20", - "orr w30, w30, w19", - "strb w30, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x19, #0xfffffffffffffff4", + "sub w19, w20, #0xc (12)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1311,16 +1078,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x30, #0xfffffffffffffff4", - "str s2, [x9, w30, sxtw]", - "ldrb w19, [x28, #1298]", - "lsl w30, w22, w20", - "bic w30, w19, w30", - "strb w30, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, w21, sxtw]", + "str s2, [x19]", + "ldr w6, [x20, w21, sxtw]", "ldr s2, [x6, #44]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1349,17 +1108,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w19, w22, w20", - "orr w30, w30, w19", - "strb w30, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x19, #0xfffffffffffffff8", + "sub w19, w20, #0x8 (8)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1386,16 +1136,8 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x30, #0xfffffffffffffff8", - "str s2, [x9, w30, sxtw]", - "ldrb w19, [x28, #1298]", - "lsl w30, w22, w20", - "bic w30, w19, w30", - "strb w30, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, w21, sxtw]", + "str s2, [x19]", + "ldr w4, [x20, w21, sxtw]", "ldr s2, [x4, #60]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1424,17 +1166,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w21, w22, w20", - "orr w21, w30, w21", - "strb w21, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "mov x21, #0xfffffffffffffffc", + "sub w19, w20, #0x4 (4)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1461,17 +1194,9 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x21, #0xfffffffffffffffc", - "str s2, [x9, w21, sxtw]", - "ldrb w30, [x28, #1298]", - "lsl w19, w22, w20", - "bic w30, w30, w19", - "strb w30, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, #8]", - "ldr s2, [x9, w23, sxtw]", + "str s2, [x19]", + "ldr w5, [x20, #8]", + "ldr s2, [x20, w22, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1499,17 +1224,6 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w23, w22, w20", - "orr w23, w30, w23", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1537,15 +1251,8 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x5]", - "ldrb w23, [x28, #1298]", - "lsl w30, w22, w20", - "bic w23, w23, w30", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, #8]", - "ldr s2, [x9, w24, sxtw]", + "ldr w6, [x20, #8]", + "ldr s2, [x20, w23, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1573,17 +1280,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w6, #0x4 (4)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1610,16 +1307,9 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x6, #4]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, #8]", - "ldr s2, [x9, w25, sxtw]", + "str s2, [x22]", + "ldr w4, [x20, #8]", + "ldr s2, [x20, w24, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1647,17 +1337,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w4, #0x8 (8)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1684,16 +1364,9 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x4, #8]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, #8]", - "ldr s2, [x9, w12, sxtw]", + "str s2, [x22]", + "ldr w5, [x20, #8]", + "ldr s2, [x20, w25, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1721,17 +1394,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w5, #0xc (12)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1758,16 +1421,9 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x5, #12]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, #8]", - "ldr s2, [x9, w13, sxtw]", + "str s2, [x22]", + "ldr w6, [x20, #8]", + "ldr s2, [x20, w12, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1795,17 +1451,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w6, #0x10 (16)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1832,16 +1478,9 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x6, #16]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, #8]", - "ldr s2, [x9, w14, sxtw]", + "str s2, [x22]", + "ldr w4, [x20, #8]", + "ldr s2, [x20, w13, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1869,17 +1508,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w4, #0x14 (20)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1906,16 +1535,9 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x4, #20]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, #8]", - "ldr s2, [x9, w15, sxtw]", + "str s2, [x22]", + "ldr w5, [x20, #8]", + "ldr s2, [x20, w14, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1943,17 +1565,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w5, #0x18 (24)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1980,16 +1592,9 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x5, #24]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, #8]", - "ldr s2, [x9, w16, sxtw]", + "str s2, [x22]", + "ldr w6, [x20, #8]", + "ldr s2, [x20, w15, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2017,17 +1622,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w6, #0x1c (28)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2054,16 +1649,9 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x6, #28]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, #8]", - "ldr s2, [x9, w17, sxtw]", + "str s2, [x22]", + "ldr w4, [x20, #8]", + "ldr s2, [x20, w16, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2091,17 +1679,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w4, #0x20 (32)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2128,16 +1706,9 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x4, #32]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, #8]", - "ldr s2, [x9, w29, sxtw]", + "str s2, [x22]", + "ldr w5, [x20, #8]", + "ldr s2, [x20, w17, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2165,17 +1736,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w5, #0x24 (36)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2202,17 +1763,9 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x5, #36]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, #8]", - "mov x24, #0xffffffffffffffe8", - "ldr s2, [x9, w24, sxtw]", + "str s2, [x22]", + "ldr w6, [x20, #8]", + "ldr s2, [x20, w29, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2240,17 +1793,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w6, #0x28 (40)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2277,17 +1820,9 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x6, #40]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, #8]", - "mov x24, #0xffffffffffffffec", - "ldr s2, [x9, w24, sxtw]", + "str s2, [x22]", + "ldr w4, [x20, #8]", + "ldr s2, [x20, w30, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2315,17 +1850,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w4, #0x2c (44)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2352,17 +1877,10 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x4, #44]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, #8]", - "mov x24, #0xfffffffffffffff0", - "ldr s2, [x9, w24, sxtw]", + "str s2, [x22]", + "ldr w5, [x20, #8]", + "mov x22, #0xfffffffffffffff0", + "ldr s2, [x20, w22, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2390,17 +1908,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w5, #0x30 (48)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2427,17 +1935,10 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x5, #48]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, #8]", - "mov x24, #0xfffffffffffffff4", - "ldr s2, [x9, w24, sxtw]", + "str s2, [x22]", + "ldr w6, [x20, #8]", + "mov x22, #0xfffffffffffffff4", + "ldr s2, [x20, w22, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2465,17 +1966,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w6, #0x34 (52)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2502,17 +1993,10 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x6, #52]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, #8]", - "mov x24, #0xfffffffffffffff8", - "ldr s2, [x9, w24, sxtw]", + "str s2, [x22]", + "ldr w4, [x20, #8]", + "mov x22, #0xfffffffffffffff8", + "ldr s2, [x20, w22, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2540,17 +2024,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w22, w4, #0x38 (56)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2577,16 +2051,9 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x4, #56]", - "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, #8]", - "ldr s2, [x9, w21, sxtw]", + "str s2, [x22]", + "ldr w5, [x20, #8]", + "ldr s2, [x20, w21, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2614,17 +2081,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w21, w22, w20", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "add w21, w5, #0x3c (60)", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2651,19 +2108,19 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "str s2, [x5, #60]", - "ldrb w21, [x28, #1298]", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w20, w20, #0x1 (1)", + "str s2, [x21]", + "ldr w4, [x20, #8]", + "mov x8, x20", + "ldr w9, [x20]", + "add x8, x20, #0x4 (4)", + "ldrb w20, [x28, #1019]", + "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, #8]", - "mov x8, x9", - "ldr w20, [x9]", - "add x8, x9, #0x4 (4)", - "mov x9, x20" + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1298]" ] } } diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json index 378bd69afe..681473049c 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -1521,11 +1521,11 @@ "mov w21, #0x37f", "strh w21, [x28, #1296]", "strb w20, [x28, #1019]", + "strb w20, [x28, #1298]", "strb w20, [x28, #1016]", "strb w20, [x28, #1017]", "strb w20, [x28, #1018]", "strb w20, [x28, #1022]", - "strb w20, [x28, #1298]", "movi v2.2d, #0x0", "str q2, [x28, #1040]", "str q2, [x28, #1056]", diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json new file mode 100644 index 0000000000..f169f31ea6 --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json @@ -0,0 +1,6857 @@ +{ + "Features": { + "Bitness": 32, + "EnabledHostFeatures": [ + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256", + "AFP" + ] + }, + "Instructions": { + "Block1": { + "ExpectedInstructionCount": 1366, + "x86Insts": [ + "sub esp,0x2c", + "mov ecx,dword [esp + 0x34]", + "mov edx,dword [esp + 0x30]", + "mov eax,dword [esp + 0x38]", + "fld dword [ecx]", + "fld dword [edx]", + "fld st1", + "fsub st0,st1", + "fld dword [ecx + 0x4]", + "fld dword [edx + 0x4]", + "fld st1", + "fsub st0,st1", + "fstp dword [esp + 0x10]", + "fld dword [ecx + 0x8]", + "fld dword [edx + 0x8]", + "fld st1", + "fsub st0,st1", + "fstp dword [esp + 0x14]", + "fld dword [eax]", + "fsubr st7,st0", + "fxch st7", + "fstp dword [esp + 0x18]", + "fld dword [eax + 0x4]", + "fsubr st4,st0", + "fxch st4", + "fstp dword [esp + 0x1c]", + "fld dword [eax + 0x8]", + "fsubr st2,st0", + "fxch st6", + "fsubrp st7,st0", + "fxch st2", + "fsubrp st3,st0", + "fxch st4", + "fsubp", + "fxch st2", + "fmul st0", + "fldz", + "faddp", + "fld dword [esp + 0x10]", + "fld st0", + "fmulp", + "faddp", + "fld dword [esp + 0x14]", + "fld st0", + "fmulp", + "faddp", + "fld dword [esp + 0x18]", + "fld st0", + "fmulp", + "fldz", + "faddp", + "fld dword [esp + 0x1c]", + "fld st0", + "fmulp", + "faddp", + "fxch st4", + "fmul st0", + "faddp st4,st0", + "fxch st4", + "fmul st0", + "fldz", + "faddp", + "fxch", + "fmul st0", + "faddp", + "fxch", + "fmul st0", + "faddp", + "fxch st2", + "fucomi st0,st1", + "jbe 0x00022528" + ], + "ExpectedArm64ASM": [ + "mov x27, x8", + "subs w8, w8, #0x2c (44)", + "ldr w5, [x8, #52]", + "ldr w6, [x8, #48]", + "ldr w4, [x8, #56]", + "ldr s2, [x5]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x5, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x6, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w20, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x20]", + "mov w20, #0x8", + "ldr s7, [x5, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x6, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr s9, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x0", + "add w22, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w22, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x22]", + "ldr s5, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "movi v6.2d, #0x0", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s8, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "strb w21, [x28, #1017]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1560]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "rmif x22, #63, #nzCv", + "rmif x23, #62, #nZcv", + "mov w22, #0x1", + "eor w26, w21, #0x1", + "cset x21, hs", + "csel x21, x22, x21, eq", + "ldrb w23, [x28, #1019]", + "sub w23, w23, #0x3 (3)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q4, [x0, #1040]", + "add w24, w23, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "str q7, [x0, #1040]", + "add w24, w23, #0x2 (2)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "add w24, w23, #0x3 (3)", + "and w24, w24, #0x7", + "sub w20, w20, w23", + "mov w23, #0x707", + "lsr w20, w23, w20", + "ldrb w23, [x28, #1298]", + "orr w20, w23, w20", + "strb w20, [x28, #1298]", + "lsl w22, w22, w24", + "bic w20, w20, w22", + "strb w20, [x28, #1298]", + "cbnz x21, #+0x1c", + "ldr x0, pc+8", + "blr x0", + "mov x0, #0xffffffffffff4ff6", + "udf #0x7f", + "unallocated (Unallocated)", + "udf #0x0" + ] + }, + "Block2": { + "ExpectedInstructionCount": 559, + "x86Insts": [ + "sub esp,0x1c", + "mov edx,dword [esp + 0x20]", + "mov eax,dword [esp + 0x24]", + "fld dword [edx]", + "fabs", + "fld dword [eax]", + "fabs", + "fxch", + "fucomi st0,st1", + "fcmovbe st0,st1", + "fstp st1", + "fld dword [edx + 0x4]", + "fabs", + "fld dword [eax + 0x4]", + "fabs", + "fxch", + "fucomi st0,st1", + "fcmovbe st0,st1", + "fstp st1", + "fld dword [edx + 0x8]", + "fabs", + "fld dword [eax + 0x8]", + "fabs", + "fxch", + "fucomi st0,st1", + "fcmovbe st0,st1", + "fstp st1", + "fld st2", + "fmulp st3", + "fxch", + "fmul st0", + "faddp st2,st0", + "fmul st0", + "faddp", + "fld st0", + "fsqrt", + "fucomi st0,st0", + "jp 0x000230ab" + ], + "ExpectedArm64ASM": [ + "mvn w27, w8", + "subs w8, w8, #0x1c (28)", + "ldr w6, [x8, #32]", + "ldr w4, [x8, #36]", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x20, #0xffffffffffffffff", + "mov w21, #0x7fff", + "fmov d3, x20", + "mov v3.d[1], x21", + "and v2.16b, v2.16b, v3.16b", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "fmov d4, x20", + "mov v4.d[1], x21", + "and v3.16b, v3.16b, v4.16b", + "mov w22, #0x0", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1560]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov x23, x0", + "ubfx x24, x23, #1, #1", + "ubfx x25, x23, #0, #1", + "ubfx x23, x23, #2, #1", + "orr w24, w24, w23", + "orr w23, w25, w23", + "rmif x24, #63, #nzCv", + "rmif x23, #62, #nZcv", + "mov w23, #0x1", + "csetm x24, hs", + "csel x24, x20, x24, eq", + "dup v4.2d, x24", + "bit v2.16b, v3.16b, v4.16b", + "ldr s3, [x6, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "fmov d4, x20", + "mov v4.d[1], x21", + "and v3.16b, v3.16b, v4.16b", + "ldr s4, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "fmov d5, x20", + "mov v5.d[1], x21", + "and v4.16b, v4.16b, v5.16b", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1560]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov x24, x0", + "ubfx x25, x24, #1, #1", + "ubfx x12, x24, #0, #1", + "ubfx x24, x24, #2, #1", + "orr w25, w25, w24", + "orr w24, w12, w24", + "rmif x25, #63, #nzCv", + "rmif x24, #62, #nZcv", + "csetm x24, hs", + "csel x24, x20, x24, eq", + "dup v5.2d, x24", + "bit v3.16b, v4.16b, v5.16b", + "mov w24, #0x8", + "ldr s4, [x6, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "fmov d5, x20", + "mov v5.d[1], x21", + "and v4.16b, v4.16b, v5.16b", + "ldr s5, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "fmov d6, x20", + "mov v6.d[1], x21", + "and v5.16b, v5.16b, v6.16b", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1560]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov x21, x0", + "ubfx x25, x21, #1, #1", + "ubfx x12, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w25, w25, w21", + "orr w21, w12, w21", + "rmif x25, #63, #nzCv", + "rmif x21, #62, #nZcv", + "csetm x21, hs", + "csel x20, x20, x21, eq", + "dup v6.2d, x20", + "bit v4.16b, v5.16b, v6.16b", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "strb w22, [x28, #1017]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1608]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1560]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "rmif x21, #63, #nzCv", + "rmif x22, #62, #nZcv", + "eor w26, w20, #0x1", + "eor w20, w26, w26, lsr #4", + "eor w20, w20, w20, lsr #2", + "eon w20, w20, w20, lsr #1", + "and x20, x20, #0x1", + "ldrb w21, [x28, #1019]", + "sub w21, w21, #0x2 (2)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", + "str q3, [x0, #1040]", + "add w22, w21, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "add w22, w21, #0x6 (6)", + "and w22, w22, #0x7", + "sub w21, w24, w21", + "mov w24, #0x303", + "lsr w21, w24, w21", + "ldrb w24, [x28, #1298]", + "orr w21, w24, w21", + "strb w21, [x28, #1298]", + "lsl w22, w23, w22", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "cbnz x20, #+0x1c", + "ldr x0, pc+8", + "blr x0", + "mov x0, #0xffffffffffff4ff6", + "udf #0x7f", + "unallocated (Unallocated)", + "udf #0x0" + ] + }, + "Block3": { + "ExpectedInstructionCount": 865, + "x86Insts": [ + "fld dword [ecx]", + "fld dword [edx + 0x4]", + "fld dword [ecx + 0x4]", + "fld dword [edx]", + "fld dword [ecx + 0x8]", + "fstp dword [esp]", + "fld dword [edx + 0x8]", + "fld st4", + "fmul st4", + "fld st3", + "fmul st3", + "fsubp", + "fmul dword [eax + 0x8]", + "fxch st2", + "fmul dword [esp]", + "fxch st5", + "fmul st1", + "fsubp st5,st0", + "fld dword [eax + 0x4]", + "fmulp st5", + "fxch st4", + "faddp", + "fxch st3", + "fmulp", + "fxch", + "fmul dword [esp]", + "mov byte [esp],0x1", + "fsubp", + "fmul dword [eax]", + "faddp", + "fdivrp", + "fstp dword [esi]", + "jmp 0x000231f8" + ], + "ExpectedArm64ASM": [ + "ldr s2, [x5]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x6, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x5, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x5, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x8]", + "ldr s6, [x6, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mov w20, #0x0", + "ldr s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s5, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "strb w20, [x28, #1017]", + "ldr s5, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mov w20, #0x1", + "strb w20, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w21, [x28, #1019]", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "add w22, w21, #0x2 (2)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1298]", + "lsl w21, w20, w21", + "orr w21, w23, w21", + "strb w21, [x28, #1298]", + "lsl w22, w20, w22", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w21, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1688]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w23, w20, w21", + "bic w22, w22, w23", + "strb w22, [x28, #1298]", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x10]", + "ldrb w22, [x28, #1298]", + "lsl w20, w20, w21", + "bic w20, w22, w20", + "strb w20, [x28, #1298]", + "add w20, w21, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "mov w20, #0x354", + "movk w20, #0x1, lsl #16", + "mov w21, #0x31a8", + "movk w21, #0x2, lsl #16", + "add x20, x21, x20", + "ldr x0, [x28, #2304]", + "and x3, x20, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block4": { + "ExpectedInstructionCount": 207, + "x86Insts": [ + "push ebp", + "push edi", + "push esi", + "push ebx", + "sub esp,0x4c", + "mov eax,dword [esp + 0x68]", + "lea ebp,[esp + 0x38]", + "lea esi,[esp + 0x30]", + "fld qword [0x00052098]", + "mov dword [esp + 0xc],esi", + "mov edi,dword [esp + 0x64]", + "mov dword [esp + 0x8],ebp", + "mov ebx,dword [esp + 0x6c]", + "mov dword [esp + 0x28],eax", + "mov eax,dword [esp + 0x60]", + "fmul dword [eax + 0x4]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x2c]", + "fstp qword [esp]", + "call 0x0006d100", + "mov eax,dword [esp + 0x60]", + "mov dword [esp + 0xc],esi", + "mov dword [esp + 0x8],ebp", + "fld qword [esp + 0x38]", + "fstp dword [esp + 0x18]", + "fld qword [esp + 0x30]", + "fstp dword [esp + 0x1c]", + "fld qword [0x00052098]", + "fmul dword [eax]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x2c]", + "fstp qword [esp]", + "call 0x0006d100", + "mov eax,dword [esp + 0x60]", + "mov dword [esp + 0xc],esi", + "mov dword [esp + 0x8],ebp", + "fld qword [esp + 0x38]", + "fstp dword [esp + 0x20]", + "fld qword [esp + 0x30]", + "fstp dword [esp + 0x24]", + "fld qword [0x00052098]", + "fmul dword [eax + 0x8]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x2c]", + "fstp qword [esp]", + "call 0x0006d100", + "test edi,edi", + "mov eax,dword [esp + 0x28]", + "fld qword [esp + 0x38]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x2c]", + "fld qword [esp + 0x30]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x2c]", + "jz 0x00022f5d" + ], + "ExpectedArm64ASM": [ + "str w9, [x8, #-4]!", + "str w11, [x8, #-4]!", + "str w10, [x8, #-4]!", + "str w7, [x8, #-4]!", + "mov x27, x8", + "subs w26, w8, #0x4c (76)", + "cfinv", + "mov x8, x26", + "ldr w4, [x26, #104]", + "add w9, w26, #0x38 (56)", + "add w10, w26, #0x30 (48)", + "mov w20, #0x2098", + "movk w20, #0x5, lsl #16", + "ldr d2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str w10, [x26, #12]", + "ldr w11, [x26, #100]", + "str w9, [x26, #8]", + "ldr w7, [x26, #108]", + "str w4, [x26, #40]", + "ldr w4, [x26, #96]", + "ldr s3, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w26, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x26, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v2.8b, v0.8b", + "str d2, [x26]", + "mov w20, #0x434", + "movk w20, #0x1, lsl #16", + "mov w21, #0xd0bc", + "movk w21, #0x6, lsl #16", + "add w21, w20, w21", + "mov w8, w26", + "str w20, [x8, #-4]!", + "ldrb w20, [x28, #1019]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1298]", + "mov w23, #0x1", + "lsl w20, w23, w20", + "bic w20, w22, w20", + "strb w20, [x28, #1298]", + "ldr x0, [x28, #2304]", + "and x3, x21, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block5": { + "ExpectedInstructionCount": 971, + "x86Insts": [ + "fld dword [esp + 0x80]", + "fsub dword [esp + 0x7c]", + "mov eax,dword [esp + 0x88]", + "mov ecx,dword [esp + 0x8c]", + "movss xmm1,dword [esp + 0x7c]", + "mov dword [esp + 0x38],edx", + "fst dword [esp + 0x34]", + "fld dword [esp + 0x24]", + "fld st0", + "fmulp st2", + "fxch", + "fadd dword [esp + 0x7c]", + "fstp dword [esp + 0x2c]", + "fld dword [eax]", + "fsub dword [ebp]", + "movss xmm0,dword [esp + 0x2c]", + "fmul st1", + "fadd dword [ebp]", + "fstp dword [esp + 0x44]", + "fld dword [eax + 0x4]", + "fsub dword [ebp + 0x4]", + "fmul st1", + "fadd dword [ebp + 0x4]", + "fstp dword [esp + 0x48]", + "fld dword [eax + 0x8]", + "fsub dword [ebp + 0x8]", + "fmulp", + "fadd dword [ebp + 0x8]", + "mov dword [esp + 0x1c],ecx", + "movss dword [esp + 0x10],xmm0", + "lea ecx,[esp + 0x44]", + "movss dword [esp + 0xc],xmm1", + "mov dword [esp + 0x18],ecx", + "mov dword [esp + 0x14],ebp", + "fstp dword [esp + 0x4c]", + "fldz", + "fld dword [esp + 0x28]", + "fxch", + "fucomip st0,st1", + "fstp st0", + "seta byte [esp + 0x30]", + "movzx eax,byte [esp + 0x30]", + "movsx eax,word [esi + eax*0x2 + 0x4]", + "mov dword [esp + 0x8],eax", + "mov dword [esp + 0x4],ebx", + "mov dword [esp],edi", + "call 0x0002b5b0", + "mov edx,dword [esp + 0x38]", + "test al,al", + "jnz 0x0002b858" + ], + "ExpectedArm64ASM": [ + "ldr s2, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x8, #136]", + "ldr w5, [x8, #140]", + "ldr s17, [x8, #124]", + "str w6, [x8, #56]", + "add w20, w8, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x20]", + "ldr s3, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x0", + "ldr s4, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s4, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s16, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s4, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s4, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s4, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s4, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str w5, [x8, #28]", + "str s16, [x8, #16]", + "add w5, w8, #0x44 (68)", + "str s17, [x8, #12]", + "str w5, [x8, #24]", + "str w9, [x8, #20]", + "add w21, w8, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "movi v2.2d, #0x0", + "ldr s3, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "strb w20, [x28, #1017]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1560]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "rmif x21, #63, #nzCv", + "rmif x22, #62, #nZcv", + "mov w21, #0x1", + "eor w26, w20, #0x1", + "cset x20, lo", + "csel x20, x20, xzr, ne", + "strb w20, [x8, #48]", + "ldrb w4, [x8, #48]", + "add w20, w10, #0x4 (4)", + "add w20, w20, w4, lsl #1", + "ldrh w20, [x20]", + "sxth w4, w20", + "str w4, [x8, #8]", + "str w7, [x8, #4]", + "str w11, [x8]", + "mov w20, #0x60f", + "movk w20, #0x1, lsl #16", + "mov w22, #0xb4fe", + "movk w22, #0x2, lsl #16", + "add w22, w20, w22", + "str w20, [x8, #-4]!", + "ldrb w20, [x28, #1019]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", + "ldrb w23, [x28, #1298]", + "lsl w20, w21, w20", + "bic w20, w23, w20", + "strb w20, [x28, #1298]", + "ldr x0, [x28, #2304]", + "and x3, x22, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block6": { + "ExpectedInstructionCount": 934, + "x86Insts": [ + "push ebp", + "push edi", + "push esi", + "push ebx", + "sub esp,0x4", + "mov ecx,dword [esp + 0x20]", + "mov ebx,dword [esp + 0x24]", + "mov eax,dword [esp + 0x1c]", + "mov edx,dword [esp + 0x18]", + "fld dword [ecx]", + "fmul dword [ebx + 0x4]", + "mov ebp,dword [esp + 0x28]", + "mov edi,dword [esp + 0x2c]", + "mov esi,dword [esp + 0x30]", + "fld dword [ecx + 0x4]", + "fmul dword [ebx]", + "fsubp", + "fld dword [ebx]", + "fmul dword [ecx + 0x8]", + "fld dword [ecx]", + "fmul dword [ebx + 0x8]", + "fsubp", + "fld dword [ecx + 0x4]", + "fmul dword [ebx + 0x8]", + "fld dword [ebx + 0x4]", + "fmul dword [ecx + 0x8]", + "fsubp", + "fld dword [eax + 0x8]", + "fmul st3", + "fld dword [eax + 0x4]", + "fmul st3", + "faddp", + "fld dword [eax]", + "fmul st2", + "faddp", + "fldz", + "fxch", + "fucomi st0,st1", + "fstp st1", + "jp 0x0002312f" + ], + "ExpectedArm64ASM": [ + "str w9, [x8, #-4]!", + "str w11, [x8, #-4]!", + "str w10, [x8, #-4]!", + "str w7, [x8, #-4]!", + "mov x27, x8", + "subs w8, w8, #0x4 (4)", + "ldr w5, [x8, #32]", + "ldr w7, [x8, #36]", + "ldr w4, [x8, #28]", + "ldr w6, [x8, #24]", + "ldr s2, [x5]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x7, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w9, [x8, #40]", + "ldr w11, [x8, #44]", + "ldr w10, [x8, #48]", + "ldr s3, [x5, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x7]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x7]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mov w20, #0x8", + "ldr s4, [x5, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x5]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x7, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x5, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x7, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x7, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x5, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "movi v6.2d, #0x0", + "mov w21, #0x0", + "strb w21, [x28, #1017]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1560]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "rmif x22, #63, #nzCv", + "rmif x23, #62, #nZcv", + "mov w22, #0x1", + "eor w26, w21, #0x1", + "eor w21, w26, w26, lsr #4", + "eor w21, w21, w21, lsr #2", + "eon w21, w21, w21, lsr #1", + "and x21, x21, #0x1", + "ldrb w23, [x28, #1019]", + "sub w23, w23, #0x4 (4)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q5, [x0, #1040]", + "add w24, w23, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "str q4, [x0, #1040]", + "add w24, w23, #0x2 (2)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "str q3, [x0, #1040]", + "add w24, w23, #0x3 (3)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "add w24, w23, #0x7 (7)", + "and w24, w24, #0x7", + "sub w20, w20, w23", + "mov w23, #0xf0f", + "lsr w20, w23, w20", + "ldrb w23, [x28, #1298]", + "orr w20, w23, w20", + "strb w20, [x28, #1298]", + "lsl w22, w22, w24", + "bic w20, w20, w22", + "strb w20, [x28, #1298]", + "cbnz x21, #+0x1c", + "ldr x0, pc+8", + "blr x0", + "mov x0, #0xffffffffffff4ff6", + "udf #0x7f", + "unallocated (Unallocated)", + "udf #0x0" + ] + }, + "Block7": { + "ExpectedInstructionCount": 849, + "x86Insts": [ + "fld dword [ebx + 0x4]", + "fld dword [ebx]", + "fld dword [ebx + 0x8]", + "fld dword [edx]", + "fmul st3", + "fld dword [edx + 0x4]", + "fmul st3", + "fsubp", + "fmul dword [eax + 0x8]", + "fxch st2", + "fmul dword [edx + 0x8]", + "fld dword [edx]", + "fmul st2", + "fsubp", + "fmul dword [eax + 0x4]", + "faddp st2,st0", + "fmul dword [edx + 0x4]", + "fxch st2", + "fmul dword [edx + 0x8]", + "fsubp st2,st0", + "fxch", + "fmul dword [eax]", + "faddp", + "fdiv st0,st1", + "fstp dword [edi]" + ], + "ExpectedArm64ASM": [ + "ldr s2, [x7, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x7]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x7, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x6, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mov w20, #0x0", + "ldr s6, [x6, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s6, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s6, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s5, [x6, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x6, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "strb w20, [x28, #1017]", + "ldr s4, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w23, w20", + "strb w20, [x28, #1298]", + "lsl w22, w21, w22", + "bic w20, w20, w22", + "strb w20, [x28, #1298]", + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1688]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x11]", + "ldrb w22, [x28, #1298]", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" + ] + }, + "Block8": { + "ExpectedInstructionCount": 251, + "x86Insts": [ + "fstp st0", + "fstp st3", + "fstp st0", + "fstp st3", + "fxch", + "fxch st2", + "fstp dword [esp + 0x38]", + "fxch", + "fstp dword [esp + 0x2c]", + "fxch", + "fstp dword [esp + 0x28]", + "fstp qword [esp]", + "call 0x0006d0d8", + "fld dword [ebx]", + "fld dword [ebx + 0x4]", + "fld dword [ebx + 0x8]", + "fld dword [esp + 0x38]", + "fld dword [esp + 0x2c]", + "fld dword [esp + 0x28]", + "fxch st6", + "fxch st5", + "fxch", + "fxch st4", + "fxch st3", + "fxch", + "jmp 0x00022a68" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #1019]", + "mov w21, #0x1", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "mov w23, #0x0", + "ldrb w24, [x28, #1298]", + "lsl w22, w21, w22", + "bic w22, w24, w22", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w22, w21, w22", + "orr w22, w24, w22", + "strb w22, [x28, #1298]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w22, w21, w22", + "orr w22, w24, w22", + "strb w22, [x28, #1298]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w23, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w23, [x28, #1017]", + "add w22, w8, #0x38 (56)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w23, [x28, #1017]", + "add w22, w8, #0x2c (44)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w23, [x28, #1017]", + "add w22, w8, #0x28 (40)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v2.8b, v0.8b", + "str d2, [x8]", + "ldrb w22, [x28, #1298]", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "mov w20, #0x8b6", + "movk w20, #0x1, lsl #16", + "mov w21, #0xd0b4", + "movk w21, #0x6, lsl #16", + "add w21, w20, w21", + "str w20, [x8, #-4]!", + "ldr x0, [x28, #2304]", + "and x3, x21, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block9": { + "ExpectedInstructionCount": 251, + "x86Insts": [ + "fstp st0", + "fstp st3", + "fstp st0", + "fstp st3", + "fxch", + "fxch st2", + "fstp dword [esp + 0x38]", + "fxch", + "fstp dword [esp + 0x2c]", + "fxch", + "fstp dword [esp + 0x28]", + "fstp qword [esp]", + "call 0x0006d0d8", + "fld dword [ebx]", + "fld dword [ebx + 0x4]", + "fld dword [ebx + 0x8]", + "fld dword [esp + 0x38]", + "fld dword [esp + 0x2c]", + "fld dword [esp + 0x28]", + "fxch st6", + "fxch st5", + "fxch", + "fxch st4", + "fxch st3", + "fxch", + "jmp 0x00022bb8" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #1019]", + "mov w21, #0x1", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "mov w23, #0x0", + "ldrb w24, [x28, #1298]", + "lsl w22, w21, w22", + "bic w22, w24, w22", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w22, w21, w22", + "orr w22, w24, w22", + "strb w22, [x28, #1298]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w22, w21, w22", + "orr w22, w24, w22", + "strb w22, [x28, #1298]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w23, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w23, [x28, #1017]", + "add w22, w8, #0x38 (56)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w23, [x28, #1017]", + "add w22, w8, #0x2c (44)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w21, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w23, [x28, #1017]", + "add w22, w8, #0x28 (40)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v2.8b, v0.8b", + "str d2, [x8]", + "ldrb w22, [x28, #1298]", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "mov w20, #0x99b", + "movk w20, #0x1, lsl #16", + "mov w21, #0xd0b4", + "movk w21, #0x6, lsl #16", + "add w21, w20, w21", + "str w20, [x8, #-4]!", + "ldr x0, [x28, #2304]", + "and x3, x21, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block10": { + "ExpectedInstructionCount": 28, + "x86Insts": [ + "push esi", + "push ebx", + "sub esp,0xa4", + "mov ebx,dword [esp + 0xb0]", + "lea esi,[esp + 0x18]", + "mov eax,gs:[0x14]", + "mov dword [esp + 0x9c],eax", + "xor eax,eax", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x18]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x1c]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x20]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x24]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x28]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x2c]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x30]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x34]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x38]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x3c]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x40]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x44]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x48]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x4c]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x50]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x54]", + "call 0x00018ad0", + "mov dword [esp + 0x58],eax", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x7c]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x80]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x84]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x88]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x8c]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x90]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x94]", + "call 0x00019090", + "mov eax,dword [ebx + 0x5869c]", + "mov dword [esp],eax", + "fstp dword [esp + 0x98]", + "call 0x00019700", + "mov edx,0x1f", + "mov dword [esp + 0x8],edx", + "mov dword [esp + 0x4],eax", + "lea eax,[esp + 0x5c]", + "mov dword [esp],eax", + "call 0x0006d0dc", + "mov eax,dword [ebx + 0x130]", + "mov byte [esp + 0x7b],0x0", + "mov edx,dword [eax]", + "mov dword [esp],eax", + "mov dword [esp + 0x4],esi", + "call dword [edx + 0xc4]", + "mov eax,dword [esp + 0x9c]", + "xor eax,dword gs:[0x14]", + "jnz 0x00034f33" + ], + "ExpectedArm64ASM": [ + "str w10, [x8, #-4]!", + "str w7, [x8, #-4]!", + "sub w8, w8, #0xa4 (164)", + "ldr w7, [x8, #176]", + "add w10, w8, #0x18 (24)", + "ldr w20, [x28, #960]", + "ldr w4, [x20, #20]", + "str w4, [x8, #156]", + "mov w4, #0x0", + "mov w20, #0x869c", + "movk w20, #0x5, lsl #16", + "add w20, w7, w20", + "ldr w20, [x20]", + "mov x21, x4", + "mov x4, x20", + "str w20, [x8]", + "mov w20, #0xa8c", + "movk w20, #0x1, lsl #16", + "mov w22, #0x9060", + "movk w22, #0x1, lsl #16", + "add w22, w20, w22", + "str w20, [x8, #-4]!", + "mov x26, x21", + "tst w21, w21", + "ldr x0, [x28, #2304]", + "and x3, x22, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json new file mode 100644 index 0000000000..98d866fde8 --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json @@ -0,0 +1,82038 @@ +{ + "Features": { + "Bitness": 32, + "EnabledHostFeatures": [ + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256", + "AFP" + ] + }, + "Instructions": { + "Block1": { + "ExpectedInstructionCount": 26679, + "x86Insts": [ + "sub esp,0x118", + "fld dword [ecx + 0x1084]", + "fadd dword [ecx + 0x1008]", + "fstp dword [esp]", + "fld dword [ecx + 0x1080]", + "fadd dword [ecx + 0x100c]", + "fstp dword [esp + 0x4]", + "fld dword [ecx + 0x107c]", + "fadd dword [ecx + 0x1010]", + "fstp dword [esp + 0x8]", + "fld dword [ecx + 0x1078]", + "fadd dword [ecx + 0x1014]", + "fstp dword [esp + 0xc]", + "fld dword [ecx + 0x1074]", + "fadd dword [ecx + 0x1018]", + "fstp dword [esp + 0x10]", + "fld dword [ecx + 0x1070]", + "fadd dword [ecx + 0x101c]", + "fstp dword [esp + 0x14]", + "fld dword [ecx + 0x106c]", + "fadd dword [ecx + 0x1020]", + "fstp dword [esp + 0x18]", + "fld dword [ecx + 0x1068]", + "fadd dword [ecx + 0x1024]", + "fstp dword [esp + 0x1c]", + "fld dword [ecx + 0x1064]", + "fadd dword [ecx + 0x1028]", + "fstp dword [esp + 0x20]", + "fld dword [ecx + 0x1060]", + "fadd dword [ecx + 0x102c]", + "fstp dword [esp + 0x24]", + "fld dword [ecx + 0x105c]", + "fadd dword [ecx + 0x1030]", + "fstp dword [esp + 0x28]", + "fld dword [ecx + 0x1058]", + "fadd dword [ecx + 0x1034]", + "fstp dword [esp + 0x2c]", + "fld dword [ecx + 0x1054]", + "fadd dword [ecx + 0x1038]", + "fstp dword [esp + 0x30]", + "fld dword [ecx + 0x1050]", + "fadd dword [ecx + 0x103c]", + "fstp dword [esp + 0x34]", + "fld dword [ecx + 0x104c]", + "fadd dword [ecx + 0x1040]", + "fstp dword [esp + 0x38]", + "fld dword [ecx + 0x1048]", + "fadd dword [ecx + 0x1044]", + "fstp dword [esp + 0x3c]", + "fld dword [esp + 0x3c]", + "fld st0", + "fld dword [esp]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x38]", + "fld st0", + "fld dword [esp + 0x4]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x34]", + "fld st0", + "fld dword [esp + 0x8]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x4c]", + "fld dword [esp + 0x30]", + "fadd dword [esp + 0xc]", + "fstp dword [esp + 0x50]", + "fld dword [esp + 0x2c]", + "fadd dword [esp + 0x10]", + "fstp dword [esp + 0x54]", + "fld dword [esp + 0x28]", + "fadd dword [esp + 0x14]", + "fstp dword [esp + 0x58]", + "fld dword [esp + 0x24]", + "fadd dword [esp + 0x18]", + "fstp dword [esp + 0x5c]", + "fld dword [esp + 0x20]", + "fadd dword [esp + 0x1c]", + "fstp dword [esp + 0x60]", + "fxch st4", + "fsubrp st5,st0", + "fld dword [0x00b3c1d0]", + "fmulp st5", + "fxch st4", + "fstp dword [esp + 0x64]", + "fsubrp", + "fmul dword [0x00b3c1d4]", + "fstp dword [esp + 0x68]", + "fsubrp", + "fmul dword [0x00b3c1d8]", + "fstp dword [esp + 0x6c]", + "fld dword [esp + 0xc]", + "fsub dword [esp + 0x30]", + "fmul dword [0x00b3c1dc]", + "fstp dword [esp + 0x70]", + "fld dword [esp + 0x10]", + "fsub dword [esp + 0x2c]", + "fmul dword [0x00b3c1e0]", + "fstp dword [esp + 0x74]", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x28]", + "fmul dword [0x00b3c1e4]", + "fstp dword [esp + 0x78]", + "fld dword [esp + 0x18]", + "fsub dword [esp + 0x24]", + "fmul dword [0x00b3c1e8]", + "fstp dword [esp + 0x7c]", + "fld dword [esp + 0x1c]", + "fsub dword [esp + 0x20]", + "fmul dword [0x00b3c1ec]", + "fstp dword [esp + 0x80]", + "fld dword [esp + 0x60]", + "fld st0", + "fld dword [esp + 0x44]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp]", + "fld dword [esp + 0x5c]", + "fld st0", + "fld dword [esp + 0x48]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x58]", + "fld st0", + "fld dword [esp + 0x4c]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x54]", + "fadd dword [esp + 0x50]", + "fstp dword [esp + 0xc]", + "fxch st4", + "fsubrp st5,st0", + "fld dword [0x00b3c1f0]", + "fld st0", + "fmulp st6", + "fxch st5", + "fstp dword [esp + 0x10]", + "fxch", + "fsubrp st2,st0", + "fld dword [0x00b3c1f4]", + "fld st0", + "fmulp st3", + "fxch st2", + "fstp dword [esp + 0x14]", + "fsubp st2,st0", + "fld dword [0x00b3c1f8]", + "fld st0", + "fmulp st3", + "fxch st2", + "fstp dword [esp + 0x18]", + "fld dword [esp + 0x50]", + "fsub dword [esp + 0x54]", + "fld dword [0x00b3c1fc]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x1c]", + "fld dword [esp + 0x80]", + "fld st0", + "fld dword [esp + 0x64]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x20]", + "fld dword [esp + 0x7c]", + "fadd dword [esp + 0x68]", + "fstp dword [esp + 0x24]", + "fld dword [esp + 0x78]", + "fadd dword [esp + 0x6c]", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x74]", + "fadd dword [esp + 0x70]", + "fstp dword [esp + 0x2c]", + "fsubrp", + "fmul st4", + "fstp dword [esp + 0x30]", + "fld dword [esp + 0x68]", + "fsub dword [esp + 0x7c]", + "fmul st2", + "fstp dword [esp + 0x34]", + "fld dword [esp + 0x6c]", + "fsub dword [esp + 0x78]", + "fmul st3", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x70]", + "fsub dword [esp + 0x74]", + "fmulp", + "fstp dword [esp + 0x3c]", + "fld dword [esp + 0xc]", + "fld st0", + "fld dword [esp]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x8]", + "fld st0", + "fadd dword [esp + 0x4]", + "fstp dword [esp + 0x48]", + "fxch", + "fsubrp st2,st0", + "fld dword [0x00b3c200]", + "fld st0", + "fmulp st3", + "fxch st2", + "fstp dword [esp + 0x4c]", + "fsubr dword [esp + 0x4]", + "fld dword [0x00b3c204]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x50]", + "fld dword [esp + 0x1c]", + "fld st0", + "fadd dword [esp + 0x10]", + "fstp dword [esp + 0x54]", + "fld dword [esp + 0x18]", + "fadd dword [esp + 0x14]", + "fstp dword [esp + 0x58]", + "fsubr dword [esp + 0x10]", + "fmul st2", + "fstp dword [esp + 0x5c]", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x18]", + "fmul st1", + "fstp dword [esp + 0x60]", + "fld dword [esp + 0x2c]", + "fld st0", + "fadd dword [esp + 0x20]", + "fstp dword [esp + 0x64]", + "fld dword [esp + 0x28]", + "fadd dword [esp + 0x24]", + "fstp dword [esp + 0x68]", + "fsubr dword [esp + 0x20]", + "fmul st2", + "fstp dword [esp + 0x6c]", + "fld dword [esp + 0x24]", + "fsub dword [esp + 0x28]", + "fmul st1", + "fstp dword [esp + 0x70]", + "fld dword [esp + 0x3c]", + "fld st0", + "fadd dword [esp + 0x30]", + "fstp dword [esp + 0x74]", + "fld dword [esp + 0x38]", + "fadd dword [esp + 0x34]", + "fstp dword [esp + 0x78]", + "fsubr dword [esp + 0x30]", + "fmul st2", + "fstp dword [esp + 0x7c]", + "fld dword [esp + 0x34]", + "fsub dword [esp + 0x38]", + "fmul st1", + "fstp dword [esp + 0x80]", + "fld dword [esp + 0x48]", + "fld st0", + "fadd dword [esp + 0x44]", + "fstp dword [esp]", + "fsubr dword [esp + 0x44]", + "fld dword [0x00b3c208]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x50]", + "fadd dword [esp + 0x4c]", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x4c]", + "fsub dword [esp + 0x50]", + "fmul st1", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0x58]", + "fadd dword [esp + 0x54]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x54]", + "fsub dword [esp + 0x58]", + "fmul st1", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x60]", + "fadd dword [esp + 0x5c]", + "fstp dword [esp + 0x18]", + "fld dword [esp + 0x5c]", + "fsub dword [esp + 0x60]", + "fmul st1", + "fstp dword [esp + 0x1c]", + "fld dword [esp + 0x68]", + "fadd dword [esp + 0x64]", + "fstp dword [esp + 0x20]", + "fld dword [esp + 0x64]", + "fsub dword [esp + 0x68]", + "fmul st1", + "fstp dword [esp + 0x24]", + "fld dword [esp + 0x70]", + "fadd dword [esp + 0x6c]", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x6c]", + "fsub dword [esp + 0x70]", + "fmul st1", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x78]", + "fadd dword [esp + 0x74]", + "fstp dword [esp + 0x30]", + "fld dword [esp + 0x74]", + "fsub dword [esp + 0x78]", + "fmul st1", + "fstp dword [esp + 0x34]", + "fld dword [esp + 0x80]", + "fadd dword [esp + 0x7c]", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x7c]", + "fsub dword [esp + 0x80]", + "fmul st1", + "fstp dword [esp + 0x3c]", + "fld dword [esp + 0x1c]", + "fst dword [esp + 0xc0]", + "fadd dword [esp + 0x14]", + "fstp dword [esp + 0xa0]", + "fld dword [esp + 0xa0]", + "fchs", + "fstp dword [esp + 0x8c]", + "fld dword [esp + 0x8c]", + "fsub dword [esp + 0x18]", + "fstp dword [esp + 0xdc]", + "fld dword [esp + 0x18]", + "fchs", + "fsub dword [esp + 0x1c]", + "fsub dword [esp + 0x10]", + "fstp dword [esp + 0xfc]", + "fld dword [esp + 0x3c]", + "fst dword [esp + 0xc8]", + "fadd dword [esp + 0x2c]", + "fstp dword [esp + 0xb8]", + "fld dword [esp + 0xb8]", + "fadd dword [esp + 0x34]", + "fstp dword [esp + 0xa8]", + "fld dword [esp + 0x3c]", + "fadd dword [esp + 0x34]", + "fadd dword [esp + 0x24]", + "fstp dword [esp + 0x98]", + "fld dword [esp + 0x98]", + "fchs", + "fstp dword [esp + 0x84]", + "fld dword [esp + 0x84]", + "fsub dword [esp + 0x38]", + "fstp dword [esp + 0xd4]", + "fld dword [esp + 0x38]", + "fchs", + "fsub dword [esp + 0x3c]", + "fst qword [esp + 0x110]", + "fsub dword [esp + 0x28]", + "fsub dword [esp + 0x2c]", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x40]", + "fsub dword [esp + 0x34]", + "fstp dword [esp + 0xe4]", + "fld dword [esp + 0x30]", + "fsubr qword [esp + 0x110]", + "fsub dword [esp + 0x20]", + "fstp dword [esp + 0x104]", + "fld dword [esp + 0x40]", + "fsub dword [esp + 0x30]", + "fstp dword [esp + 0xf4]", + "fld dword [esp]", + "fchs", + "fstp dword [esp + 0x10c]", + "fld dword [esp + 0x4]", + "fstp dword [esp + 0x90]", + "fld dword [esp + 0xc]", + "fst dword [esp + 0xb0]", + "fchs", + "fsub dword [esp + 0x8]", + "fstp dword [esp + 0xec]", + "fld dword [ecx + 0x1008]", + "fsub dword [ecx + 0x1084]", + "fmul dword [0x00b3c190]", + "fstp dword [esp]", + "fld dword [ecx + 0x100c]", + "fsub dword [ecx + 0x1080]", + "fmul dword [0x00b3c194]", + "fstp dword [esp + 0x4]", + "fld dword [ecx + 0x1010]", + "fsub dword [ecx + 0x107c]", + "fmul dword [0x00b3c198]", + "fstp dword [esp + 0x8]", + "fld dword [ecx + 0x1014]", + "fsub dword [ecx + 0x1078]", + "fmul dword [0x00b3c19c]", + "fstp dword [esp + 0xc]", + "fld dword [ecx + 0x1018]", + "fsub dword [ecx + 0x1074]", + "fmul dword [0x00b3c1a0]", + "fstp dword [esp + 0x10]", + "fld dword [ecx + 0x101c]", + "fsub dword [ecx + 0x1070]", + "fmul dword [0x00b3c1a4]", + "fstp dword [esp + 0x14]", + "fld dword [ecx + 0x1020]", + "fsub dword [ecx + 0x106c]", + "fmul dword [0x00b3c1a8]", + "fstp dword [esp + 0x18]", + "fld dword [ecx + 0x1024]", + "fsub dword [ecx + 0x1068]", + "fmul dword [0x00b3c1ac]", + "fstp dword [esp + 0x1c]", + "fld dword [ecx + 0x1028]", + "fsub dword [ecx + 0x1064]", + "fmul dword [0x00b3c1b0]", + "fstp dword [esp + 0x20]", + "fld dword [ecx + 0x102c]", + "fsub dword [ecx + 0x1060]", + "fmul dword [0x00b3c1b4]", + "fstp dword [esp + 0x24]", + "fld dword [ecx + 0x1030]", + "fsub dword [ecx + 0x105c]", + "fmul dword [0x00b3c1b8]", + "fstp dword [esp + 0x28]", + "fld dword [ecx + 0x1034]", + "fsub dword [ecx + 0x1058]", + "fmul dword [0x00b3c1bc]", + "fstp dword [esp + 0x2c]", + "fld dword [ecx + 0x1038]", + "fsub dword [ecx + 0x1054]", + "fmul dword [0x00b3c1c0]", + "fstp dword [esp + 0x30]", + "fld dword [ecx + 0x103c]", + "fsub dword [ecx + 0x1050]", + "fmul dword [0x00b3c1c4]", + "fstp dword [esp + 0x34]", + "fld dword [ecx + 0x1040]", + "fsub dword [ecx + 0x104c]", + "fmul dword [0x00b3c1c8]", + "fstp dword [esp + 0x38]", + "fld dword [ecx + 0x1044]", + "fsub dword [ecx + 0x1048]", + "fmul dword [0x00b3c1cc]", + "fstp dword [esp + 0x3c]", + "fld dword [esp + 0x3c]", + "fadd dword [esp]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x38]", + "fadd dword [esp + 0x4]", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x34]", + "fadd dword [esp + 0x8]", + "fstp dword [esp + 0x4c]", + "fld dword [esp + 0x30]", + "fadd dword [esp + 0xc]", + "fstp dword [esp + 0x50]", + "fld dword [esp + 0x2c]", + "fadd dword [esp + 0x10]", + "fstp dword [esp + 0x54]", + "fld dword [esp + 0x28]", + "fadd dword [esp + 0x14]", + "fstp dword [esp + 0x58]", + "fld dword [esp + 0x24]", + "fadd dword [esp + 0x18]", + "fstp dword [esp + 0x5c]", + "fld dword [esp + 0x20]", + "fadd dword [esp + 0x1c]", + "fstp dword [esp + 0x60]", + "fld dword [esp]", + "fsub dword [esp + 0x3c]", + "fmul dword [0x00b3c1d0]", + "fstp dword [esp + 0x64]", + "fld dword [esp + 0x4]", + "fsub dword [esp + 0x38]", + "fmul dword [0x00b3c1d4]", + "fstp dword [esp + 0x68]", + "fld dword [esp + 0x8]", + "fsub dword [esp + 0x34]", + "fmul dword [0x00b3c1d8]", + "fstp dword [esp + 0x6c]", + "fld dword [esp + 0xc]", + "fsub dword [esp + 0x30]", + "fmul dword [0x00b3c1dc]", + "fstp dword [esp + 0x70]", + "fld dword [esp + 0x10]", + "fsub dword [esp + 0x2c]", + "fmul dword [0x00b3c1e0]", + "fstp dword [esp + 0x74]", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x28]", + "fmul dword [0x00b3c1e4]", + "fstp dword [esp + 0x78]", + "fld dword [esp + 0x18]", + "fsub dword [esp + 0x24]", + "fmul dword [0x00b3c1e8]", + "fstp dword [esp + 0x7c]", + "fld dword [esp + 0x1c]", + "fsub dword [esp + 0x20]", + "fmul dword [0x00b3c1ec]", + "fstp dword [esp + 0x80]", + "fld dword [esp + 0x60]", + "fadd dword [esp + 0x44]", + "fstp dword [esp]", + "fld dword [esp + 0x5c]", + "fadd dword [esp + 0x48]", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x58]", + "fadd dword [esp + 0x4c]", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x54]", + "fadd dword [esp + 0x50]", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0x44]", + "fsub dword [esp + 0x60]", + "fmul st6", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x48]", + "fsub dword [esp + 0x5c]", + "fmul st4", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x4c]", + "fsub dword [esp + 0x58]", + "fmul st5", + "fstp dword [esp + 0x18]", + "fld dword [esp + 0x50]", + "fsub dword [esp + 0x54]", + "fmul dword [0x00b3c1fc]", + "fstp dword [esp + 0x1c]", + "fld dword [esp + 0x80]", + "fadd dword [esp + 0x64]", + "fstp dword [esp + 0x20]", + "fld dword [esp + 0x7c]", + "fadd dword [esp + 0x68]", + "fstp dword [esp + 0x24]", + "fld dword [esp + 0x78]", + "fadd dword [esp + 0x6c]", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x74]", + "fadd dword [esp + 0x70]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x64]", + "fsub dword [esp + 0x80]", + "fmulp st6", + "fxch st5", + "fstp dword [esp + 0x30]", + "fld dword [esp + 0x68]", + "fsub dword [esp + 0x7c]", + "fmulp st3", + "fxch st2", + "fstp dword [esp + 0x34]", + "fld dword [esp + 0x6c]", + "fsub dword [esp + 0x78]", + "fmulp st3", + "fxch st2", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x70]", + "fsub dword [esp + 0x74]", + "fmul dword [0x00b3c1fc]", + "fstp dword [esp + 0x3c]", + "fld dword [esp + 0xc]", + "fld st0", + "fld dword [esp]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x8]", + "fld st0", + "fadd dword [esp + 0x4]", + "fstp dword [esp + 0x48]", + "fxch", + "fsubrp st2,st0", + "fld st3", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x4c]", + "fsubr dword [esp + 0x4]", + "fmul st1", + "fstp dword [esp + 0x50]", + "fld dword [esp + 0x1c]", + "fld st0", + "fld dword [esp + 0x10]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x54]", + "fld dword [esp + 0x18]", + "fld st0", + "fadd dword [esp + 0x14]", + "fstp dword [esp + 0x58]", + "fxch", + "fsubrp st2,st0", + "fld st3", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x5c]", + "fsubr dword [esp + 0x14]", + "fmul st1", + "fstp dword [esp + 0x60]", + "fld dword [esp + 0x2c]", + "fld st0", + "fld dword [esp + 0x20]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x64]", + "fld dword [esp + 0x28]", + "fld st0", + "fadd dword [esp + 0x24]", + "fstp dword [esp + 0x68]", + "fxch", + "fsubrp st2,st0", + "fld st3", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x6c]", + "fsubr dword [esp + 0x24]", + "fmul st1", + "fstp dword [esp + 0x70]", + "fld dword [esp + 0x3c]", + "fld st0", + "fld dword [esp + 0x30]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x74]", + "fld dword [esp + 0x38]", + "fld st0", + "fadd dword [esp + 0x34]", + "fstp dword [esp + 0x78]", + "fxch", + "fsubrp st2,st0", + "fxch", + "fmulp st3", + "fxch st2", + "fstp dword [esp + 0x7c]", + "fld dword [esp + 0x34]", + "fsubrp st2,st0", + "fmulp", + "fstp dword [esp + 0x80]", + "fld dword [esp + 0x48]", + "fld st0", + "fld dword [esp + 0x44]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp]", + "fsubrp", + "fmul st1", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x50]", + "fld st0", + "fld dword [esp + 0x4c]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x8]", + "fsubrp", + "fmul st1", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0x58]", + "fld st0", + "fld dword [esp + 0x54]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x10]", + "fsubrp", + "fmul st1", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x60]", + "fld st0", + "fld dword [esp + 0x5c]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x18]", + "fsubrp", + "fmul st1", + "fstp dword [esp + 0x1c]", + "fld dword [esp + 0x68]", + "fld st0", + "fld dword [esp + 0x64]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x20]", + "fsubrp", + "fmul st1", + "fstp dword [esp + 0x24]", + "fld dword [esp + 0x70]", + "fld st0", + "fld dword [esp + 0x6c]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x28]", + "fsubrp", + "fmul st1", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x78]", + "fld st0", + "fld dword [esp + 0x74]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x30]", + "fsubrp", + "fmul st1", + "fstp dword [esp + 0x34]", + "fld dword [esp + 0x80]", + "fld st0", + "fld dword [esp + 0x7c]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x38]", + "fsubrp", + "fmulp", + "fstp dword [esp + 0x3c]", + "fld dword [esp + 0x3c]", + "fld st0", + "fld dword [esp + 0x1c]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0xc4]", + "fld dword [esp + 0xc4]", + "fld st0", + "fld dword [esp + 0x2c]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0xbc]", + "fld dword [esp + 0xbc]", + "fadd dword [esp + 0x14]", + "fld dword [esp + 0x34]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0xa4]", + "fld st4", + "fadd st0,st2", + "fadd dword [esp + 0xc]", + "fstp dword [esp + 0xb4]", + "fld dword [esp + 0xb4]", + "fadd st0,st1", + "fstp dword [esp + 0xac]", + "fld st4", + "fadd st0,st1", + "fadd dword [esp + 0x24]", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x40]", + "fadd dword [esp + 0x4]", + "fstp dword [esp + 0x94]", + "fld dword [esp + 0x94]", + "fchs", + "fstp dword [esp + 0x110]", + "fld dword [esp + 0x110]", + "fld dword [esp + 0x38]", + "fld st0", + "fsubp st2,st0", + "fxch", + "fstp dword [esp + 0xd0]", + "fld dword [esp + 0x40]", + "fadd dword [esp + 0x14]", + "fadd st0,st5", + "fstp dword [esp + 0x9c]", + "fld dword [esp + 0x9c]", + "fchs", + "fstp dword [esp + 0x88]", + "fld dword [esp + 0x88]", + "fsub dword [esp + 0x18]", + "fsub st0,st1", + "fstp dword [esp + 0xd8]", + "fld dword [esp + 0x28]", + "fchs", + "fsubrp st3,st0", + "fld st0", + "fsubp st3,st0", + "fld st5", + "fsubp st3,st0", + "fxch st2", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x40]", + "fld st0", + "fsubrp st2,st0", + "fld dword [esp + 0x8]", + "fsubr st0,st2", + "fsub dword [esp + 0xc]", + "fstp dword [esp + 0xe8]", + "fld dword [esp + 0x14]", + "fsubp st2,st0", + "fld dword [esp + 0x18]", + "fsubp st2,st0", + "fld st4", + "fsubp st2,st0", + "fxch", + "fstp dword [esp + 0xe0]", + "fld dword [esp + 0x30]", + "fld st0", + "fsubp st2,st0", + "fld dword [esp + 0x8]", + "fsubr st0,st2", + "fsub dword [esp + 0xc]", + "fstp dword [esp + 0xf0]", + "fld dword [esp + 0x18]", + "fadd dword [esp + 0x10]", + "faddp st5,st0", + "mov eax,dword [ecx + 0x1004]", + "mov edx,dword [ecx + 0x1000]", + "fxch st4", + "lea eax,[edx + eax*0x4]", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x40]", + "fld st0", + "fsubp st2,st0", + "fxch", + "fstp dword [esp + 0xf8]", + "fld dword [esp + 0x20]", + "fchs", + "fsubrp st4,st0", + "fxch st3", + "fsubrp", + "fsub st0,st3", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x40]", + "fld st0", + "fsub dword [esp]", + "fstp dword [esp + 0x108]", + "fsubrp st2,st0", + "fxch", + "fstp dword [esp + 0x100]", + "fld dword [esp + 0x90]", + "fstp dword [eax]", + "fld dword [esp + 0x94]", + "fstp dword [eax + 0x40]", + "fld dword [esp + 0x98]", + "fstp dword [eax + 0x80]", + "fld dword [esp + 0x9c]", + "fstp dword [eax + 0xc0]", + "fld dword [esp + 0xa0]", + "fstp dword [eax + 0x100]", + "fld dword [esp + 0xa4]", + "fst dword [eax + 0x140]", + "fld dword [esp + 0xa8]", + "fst dword [eax + 0x180]", + "fld dword [esp + 0xac]", + "fst dword [eax + 0x1c0]", + "fld dword [esp + 0xb0]", + "fst dword [eax + 0x200]", + "fld dword [esp + 0xb4]", + "fstp dword [eax + 0x240]", + "fld dword [esp + 0xb8]", + "fst dword [eax + 0x280]", + "fld dword [esp + 0xbc]", + "fstp dword [eax + 0x2c0]", + "fld dword [esp + 0xc0]", + "fstp dword [eax + 0x300]", + "fxch st5", + "fst dword [eax + 0x340]", + "fld dword [esp + 0xc8]", + "fstp dword [eax + 0x380]", + "fxch st6", + "fst dword [eax + 0x3c0]", + "fldz", + "fstp dword [eax + 0x400]", + "fchs", + "fstp dword [eax + 0x440]", + "fld dword [esp + 0xc8]", + "fchs", + "fstp dword [eax + 0x480]", + "fxch st5", + "fchs", + "fstp dword [eax + 0x4c0]", + "fld dword [esp + 0xc0]", + "fchs", + "fstp dword [eax + 0x500]", + "fld dword [esp + 0xbc]", + "fchs", + "fstp dword [eax + 0x540]", + "fxch st3", + "fchs", + "fstp dword [eax + 0x580]", + "fld dword [esp + 0xb4]", + "fchs", + "fstp dword [eax + 0x5c0]", + "fxch st3", + "fchs", + "fstp dword [eax + 0x600]", + "fxch", + "fchs", + "fstp dword [eax + 0x640]", + "fxch", + "fchs", + "fstp dword [eax + 0x680]", + "fchs", + "fstp dword [eax + 0x6c0]", + "fld dword [esp + 0x8c]", + "fstp dword [eax + 0x700]", + "fld dword [esp + 0x88]", + "fstp dword [eax + 0x740]", + "fld dword [esp + 0x84]", + "fstp dword [eax + 0x780]", + "fld dword [esp + 0x110]", + "fstp dword [eax + 0x7c0]", + "cmp dword [ecx + 0x1000],ecx", + "lea eax,[ecx + 0x800]", + "jz 0x006b563e" + ], + "ExpectedArm64ASM": [ + "sub w8, w8, #0x118 (280)", + "ldr s2, [x5, #4228]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x8]", + "ldr s2, [x5, #4224]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4220]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4216]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4212]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4208]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4204]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4200]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4196]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4192]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4188]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4144]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4184]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4148]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4180]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4152]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4176]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4156]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4172]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4160]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x5, #4168]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #4164]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mov w20, #0x0", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0xc1d0", + "movk w21, #0xb3, lsl #16", + "ldr s3, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x64 (100)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w22, #0xc1d4", + "movk w22, #0xb3, lsl #16", + "ldr s3, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w23, w8, #0x68 (104)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w23, #0xc1d8", + "movk w23, #0xb3, lsl #16", + "ldr s3, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w24, w8, #0x6c (108)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldr s2, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w24, #0xc1dc", + "movk w24, #0xb3, lsl #16", + "ldr s3, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w25, w8, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x25]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w25, #0xc1e0", + "movk w25, #0xb3, lsl #16", + "ldr s3, [x25]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w12, w8, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w12, #0xc1e4", + "movk w12, #0xb3, lsl #16", + "ldr s3, [x12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w13, w8, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x13]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w13, #0xc1e8", + "movk w13, #0xb3, lsl #16", + "ldr s3, [x13]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w14, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x14]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w14, #0xc1ec", + "movk w14, #0xb3, lsl #16", + "ldr s3, [x14]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w15, w8, #0x80 (128)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x15]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x8]", + "ldr s4, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w15, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x15]", + "ldr s6, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w15, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x15]", + "ldr s8, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w15, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x15]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w15, #0xc1f0", + "movk w15, #0xb3, lsl #16", + "ldr s3, [x15]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w15, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x15]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w15, #0xc1f4", + "movk w15, #0xb3, lsl #16", + "ldr s4, [x15]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w15, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x15]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w15, #0xc1f8", + "movk w15, #0xb3, lsl #16", + "ldr s5, [x15]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w15, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x15]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s6, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w15, #0xc1fc", + "movk w15, #0xb3, lsl #16", + "ldr s6, [x15]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s7, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w16, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x16]", + "ldr s8, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w16, w8, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x16]", + "ldr s8, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w16, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x16]", + "ldr s8, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w16, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s7, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s7, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s7, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s6, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w16, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x16]", + "ldr s7, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w16, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w16, #0xc200", + "movk w16, #0xb3, lsl #16", + "ldr s6, [x16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w16, #0xc204", + "movk w16, #0xb3, lsl #16", + "ldr s7, [x16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w16, w8, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x16]", + "ldr s8, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w16, w8, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x16]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s8, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s8, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w16, w8, #0x64 (100)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x16]", + "ldr s8, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w16, w8, #0x68 (104)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x16]", + "ldr s8, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x6c (108)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s8, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s8, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w16, w8, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x16]", + "ldr s8, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w16, w8, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x16]", + "ldr s8, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s8, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x80 (128)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s8, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8]", + "ldr s8, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w16, #0xc208", + "movk w16, #0xb3, lsl #16", + "ldr s8, [x16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0xc0 (192)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x16]", + "ldr s9, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w16, w8, #0xa0 (160)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr s2, [x8, #160]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w16, #0x8000", + "fmov d9, x20", + "mov v9.d[1], x16", + "eor v2.16b, v2.16b, v9.16b", + "add w17, w8, #0x8c (140)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0xdc (220)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "fmov d9, x20", + "mov v9.d[1], x16", + "eor v2.16b, v2.16b, v9.16b", + "ldr s9, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0xfc (252)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0xc8 (200)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x17]", + "ldr s9, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0xb8 (184)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #184]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0xa8 (168)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x98 (152)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #152]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "fmov d9, x20", + "mov v9.d[1], x16", + "eor v2.16b, v2.16b, v9.16b", + "add w17, w8, #0x84 (132)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0xd4 (212)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "fmov d9, x20", + "mov v9.d[1], x16", + "eor v2.16b, v2.16b, v9.16b", + "ldr s9, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x110 (272)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v9.8b, v0.8b", + "str d9, [x17]", + "ldr s9, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0xe4 (228)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d9, [x8, #272]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x104 (260)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0xf4 (244)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "fmov d9, x20", + "mov v9.d[1], x16", + "eor v2.16b, v2.16b, v9.16b", + "add w17, w8, #0x10c (268)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x90 (144)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0xb0 (176)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x17]", + "fmov d9, x20", + "mov v9.d[1], x16", + "eor v2.16b, v2.16b, v9.16b", + "ldr s9, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0xec (236)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4228]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc190", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x8]", + "ldr s2, [x5, #4108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4224]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc194", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4220]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc198", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4216]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc19c", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4212]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc1a0", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4208]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc1a4", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4204]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc1a8", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4200]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc1ac", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4196]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc1b0", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4192]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc1b4", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4144]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4188]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc1b8", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4148]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4184]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc1bc", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4152]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4180]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc1c0", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4156]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4176]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc1c4", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4160]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4172]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc1c8", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x5, #4164]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x5, #4168]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w17, #0xc1cc", + "movk w17, #0xb3, lsl #16", + "ldr s9, [x17]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w17, w8, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr s2, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x64 (100)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x68 (104)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x6c (108)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x25]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x13]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x14]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x80 (128)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x8]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x15]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s9, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x15]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x64 (100)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x68 (104)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x6c (108)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x80 (128)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0xc4 (196)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #196]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0xbc (188)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #188]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0xa4 (164)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s8, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0xb4 (180)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #180]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0xac (172)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s8, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s8, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x94 (148)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #148]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "fmov d8, x20", + "mov v8.d[1], x16", + "eor v6.16b, v6.16b, v8.16b", + "add w21, w8, #0x110 (272)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #272]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s8, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0xd0 (208)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s9, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x9c (156)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #156]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "fmov d9, x20", + "mov v9.d[1], x16", + "eor v6.16b, v6.16b, v9.16b", + "add w21, w8, #0x88 (136)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s9, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0xd8 (216)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "fmov d9, x20", + "mov v9.d[1], x16", + "eor v6.16b, v6.16b, v9.16b", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s9, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0xe8 (232)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0xe0 (224)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s7, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s9, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0xf0 (240)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s9, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x5, #4100]", + "ldr w6, [x5, #4096]", + "add w4, w6, w4, lsl #2", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0xf8 (248)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "fmov d7, x20", + "mov v7.d[1], x16", + "eor v5.16b, v5.16b, v7.16b", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x108 (264)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x100 (256)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #144]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x4]", + "ldr s3, [x8, #148]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #152]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x80 (128)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #156]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0xc0 (192)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #160]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x100 (256)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #164]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x140 (320)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #168]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w4, #0x180 (384)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #172]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w4, #0x1c0 (448)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #176]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w4, #0x200 (512)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #180]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w4, #0x240 (576)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #184]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w4, #0x280 (640)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr s9, [x8, #188]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w4, #0x2c0 (704)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr s9, [x8, #192]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w4, #0x300 (768)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "add w21, w4, #0x340 (832)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr s9, [x8, #200]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w4, #0x380 (896)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "add w21, w4, #0x3c0 (960)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "movi v9.2d, #0x0", + "add w21, w4, #0x400 (1024)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "fmov d9, x20", + "mov v9.d[1], x16", + "eor v2.16b, v2.16b, v9.16b", + "add w21, w4, #0x440 (1088)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #200]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "fmov d9, x20", + "mov v9.d[1], x16", + "eor v2.16b, v2.16b, v9.16b", + "add w21, w4, #0x480 (1152)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "fmov d2, x20", + "mov v2.d[1], x16", + "eor v2.16b, v4.16b, v2.16b", + "add w21, w4, #0x4c0 (1216)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #192]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "fmov d4, x20", + "mov v4.d[1], x16", + "eor v2.16b, v2.16b, v4.16b", + "add w21, w4, #0x500 (1280)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #188]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "fmov d4, x20", + "mov v4.d[1], x16", + "eor v2.16b, v2.16b, v4.16b", + "add w21, w4, #0x540 (1344)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "fmov d2, x20", + "mov v2.d[1], x16", + "eor v2.16b, v8.16b, v2.16b", + "add w21, w4, #0x580 (1408)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #180]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "fmov d4, x20", + "mov v4.d[1], x16", + "eor v2.16b, v2.16b, v4.16b", + "add w21, w4, #0x5c0 (1472)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "fmov d2, x20", + "mov v2.d[1], x16", + "eor v2.16b, v7.16b, v2.16b", + "add w21, w4, #0x600 (1536)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "fmov d2, x20", + "mov v2.d[1], x16", + "eor v2.16b, v6.16b, v2.16b", + "add w21, w4, #0x640 (1600)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "strb w20, [x28, #1017]", + "fmov d2, x20", + "mov v2.d[1], x16", + "eor v2.16b, v5.16b, v2.16b", + "add w21, w4, #0x680 (1664)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "fmov d2, x20", + "mov v2.d[1], x16", + "eor v2.16b, v3.16b, v2.16b", + "add w21, w4, #0x6c0 (1728)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x700 (1792)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x740 (1856)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x780 (1920)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #272]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x7c0 (1984)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr w21, [x5, #4096]", + "add w4, w5, #0x800 (2048)", + "eor w27, w21, w5", + "subs w26, w21, w5", + "cfinv", + "strb w20, [x28, #1298]", + "b.eq #+0x1c", + "ldr x0, pc+8", + "blr x0", + "unallocated (Unallocated)", + "udf #0x7f", + "unallocated (Unallocated)", + "udf #0x0" + ] + }, + "Block2": { + "ExpectedInstructionCount": 16678, + "x86Insts": [ + "mov eax,dword [ebp + 0x8]", + "fld dword [eax + 0x40]", + "fld dword [eax + 0x44]", + "fadd st0,st1", + "fstp dword [eax + 0x44]", + "fld dword [eax + 0x3c]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x40]", + "fld dword [eax + 0x38]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x3c]", + "fld dword [eax + 0x34]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x38]", + "fld dword [eax + 0x30]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x34]", + "fld dword [eax + 0x2c]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x30]", + "fld dword [eax + 0x28]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x2c]", + "fld dword [eax + 0x24]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x28]", + "fld dword [eax + 0x20]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x24]", + "fld dword [eax + 0x1c]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x20]", + "fld dword [eax + 0x18]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x1c]", + "fld dword [eax + 0x14]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x18]", + "fld dword [eax + 0x10]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x14]", + "fld dword [eax + 0xc]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x10]", + "fld dword [eax + 0x8]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0xc]", + "fld dword [eax + 0x4]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x8]", + "fld dword [eax]", + "fst qword [esp + 0x20]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x8]", + "fst dword [eax + 0x4]", + "fld dword [eax + 0x3c]", + "fld dword [eax + 0x44]", + "fadd st0,st1", + "fstp dword [eax + 0x44]", + "fld dword [eax + 0x34]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x3c]", + "fld dword [eax + 0x2c]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x34]", + "fld dword [eax + 0x24]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x2c]", + "fld dword [eax + 0x1c]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x24]", + "fld dword [eax + 0x14]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x1c]", + "fld dword [eax + 0xc]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [eax + 0x14]", + "faddp", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x4]", + "fstp dword [eax + 0xc]", + "fadd st0,st0", + "fstp dword [esp + 0x14]", + "fld dword [eax + 0x30]", + "fst qword [esp + 0x18]", + "fld dword [esp + 0x14]", + "fst qword [esp + 0x28]", + "faddp", + "fstp dword [esp + 0x14]", + "fld dword [eax + 0x10]", + "fld dword [esp + 0x14]", + "fst qword [esp + 0x80]", + "fld dword [eax + 0x20]", + "fld dword [eax + 0x40]", + "fld st3", + "fld qword [0x00a77b70]", + "fmul st1", + "fxch", + "faddp st4,st0", + "fld st2", + "fld qword [0x00a77b68]", + "fmul st1", + "fxch st5", + "faddp", + "fld st2", + "fld qword [0x00a77b60]", + "fmul st1", + "fxch st2", + "faddp", + "fstp dword [esp + 0xc0]", + "fld qword [esp + 0x28]", + "fadd st0,st6", + "fsub st0,st4", + "fld qword [esp + 0x18]", + "fsub st1,st0", + "fsubp", + "fsub st0,st3", + "fstp dword [esp + 0xd0]", + "fld st5", + "fmul st1", + "fsubr qword [esp + 0x80]", + "fld st4", + "fmul st3", + "fsubp", + "fld st3", + "fmul st6", + "faddp", + "fstp dword [esp + 0xb8]", + "fld st5", + "fmul st5", + "fsubr qword [esp + 0x80]", + "fld st4", + "fmul st2", + "faddp", + "fld st3", + "fmul st3", + "fsubp", + "fstp dword [esp + 0xc8]", + "fld qword [esp + 0x20]", + "fsubrp st6,st0", + "fxch st5", + "faddp st3,st0", + "fxch st2", + "fsub qword [esp + 0x18]", + "faddp", + "fstp dword [esp + 0x80]", + "fld dword [eax + 0x18]", + "fmul qword [0x00a77b58]", + "fstp dword [esp + 0x14]", + "fld dword [eax + 0x8]", + "fst qword [esp + 0x18]", + "fld dword [esp + 0x14]", + "fst qword [esp + 0x20]", + "fld dword [eax + 0x28]", + "fst qword [esp + 0x90]", + "fld dword [eax + 0x38]", + "fst qword [esp + 0x28]", + "fld qword [0x00a77b50]", + "fmul st4", + "fxch st4", + "faddp st3,st0", + "fld qword [0x00a77b48]", + "fmul st2", + "fxch st3", + "faddp st2,st0", + "fld qword [0x00a77b40]", + "fmul st1", + "fxch st2", + "faddp", + "fstp dword [esp + 0xb4]", + "fld qword [esp + 0x18]", + "fld qword [esp + 0x90]", + "fsub st1,st0", + "fxch", + "fsub qword [esp + 0x28]", + "fmul qword [0x00a77b58]", + "fstp dword [esp + 0xc4]", + "fld qword [esp + 0x18]", + "fmul st3", + "fsub qword [esp + 0x20]", + "fxch", + "fmul st2", + "fsubp", + "fld qword [esp + 0x28]", + "fmul st4", + "faddp", + "fstp dword [esp + 0xa8]", + "fld qword [esp + 0x18]", + "fmul st1", + "fsub qword [esp + 0x20]", + "fld qword [esp + 0x90]", + "fmul st4", + "faddp", + "fld qword [esp + 0x28]", + "fmul st3", + "fsubp", + "fstp dword [esp + 0x90]", + "fld dword [esp + 0x8]", + "fst qword [esp + 0x8]", + "fadd st0,st0", + "fstp dword [esp + 0x14]", + "fld dword [eax + 0x34]", + "fst qword [esp + 0x98]", + "fld dword [esp + 0x14]", + "fst qword [esp + 0xa0]", + "faddp", + "fstp dword [esp + 0x14]", + "fld dword [eax + 0x14]", + "fst qword [esp + 0x20]", + "fld dword [esp + 0x14]", + "fstp qword [esp + 0x88]", + "fld dword [eax + 0x24]", + "fstp qword [esp + 0x18]", + "fld dword [eax + 0x44]", + "fstp qword [esp + 0x28]", + "fmul st4", + "fadd qword [esp + 0x88]", + "fld qword [esp + 0x18]", + "fmul st6", + "faddp", + "fld qword [esp + 0x28]", + "fmul st7", + "faddp", + "fstp dword [esp + 0xb0]", + "fld qword [esp + 0xa0]", + "fadd qword [esp + 0x20]", + "fsub qword [esp + 0x18]", + "fld qword [esp + 0x98]", + "fsub st1,st0", + "fsubp", + "fsub qword [esp + 0x28]", + "fstp dword [esp + 0x30]", + "fld qword [esp + 0x20]", + "fmul st6", + "fsubr qword [esp + 0x88]", + "fld qword [esp + 0x18]", + "fmul st5", + "fsubp", + "fld qword [esp + 0x28]", + "fmul st6", + "faddp", + "fstp dword [esp + 0xa0]", + "fld qword [esp + 0x20]", + "fld st0", + "fmulp st6", + "fld qword [esp + 0x88]", + "fsubrp st6,st0", + "fld qword [esp + 0x18]", + "fmulp st7", + "fxch st5", + "faddp st6,st0", + "fld qword [esp + 0x28]", + "fld st0", + "fmulp st5", + "fxch st6", + "fsubrp st4,st0", + "fxch st3", + "fstp dword [esp + 0x28]", + "fld qword [esp + 0x8]", + "fsubrp st4,st0", + "fxch st3", + "fadd qword [esp + 0x18]", + "fsub qword [esp + 0x98]", + "faddp st4,st0", + "fxch st3", + "fmul qword [0x00a77bd8]", + "fstp dword [esp + 0x18]", + "fld dword [eax + 0x1c]", + "fmul qword [0x00a77b58]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x14]", + "fld dword [eax + 0x2c]", + "fld dword [eax + 0x3c]", + "fld dword [esp + 0x4]", + "fmul st6", + "fadd st0,st3", + "fld st2", + "fmul st6", + "faddp", + "fld st1", + "fmul st5", + "faddp", + "fstp dword [esp + 0x14]", + "fld dword [eax + 0xc]", + "fst qword [esp + 0x20]", + "fsub st0,st2", + "fsub st0,st1", + "fmul qword [0x00a77b58]", + "fstp dword [esp + 0x98]", + "fld qword [esp + 0x20]", + "fmul st5", + "fsub st0,st3", + "fld st2", + "fmul st5", + "fsubp", + "fld st1", + "fmul st7", + "faddp", + "fstp dword [esp + 0x88]", + "fld qword [esp + 0x20]", + "fmulp st4", + "fxch st3", + "fsubrp st2,st0", + "fmulp st4", + "faddp st3,st0", + "fmulp", + "fsubp", + "fstp dword [esp + 0x20]", + "fld dword [esp + 0xb4]", + "fld dword [esp + 0xc0]", + "fld st0", + "fadd st0,st2", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x14]", + "fld dword [esp + 0xb0]", + "fld st0", + "fadd st0,st2", + "fmul qword [0x00a77b38]", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x4]", + "fld dword [esp + 0x8]", + "fld st0", + "fadd st0,st2", + "fstp dword [esp + 0x38]", + "fsubrp", + "fstp dword [esp + 0x7c]", + "fld dword [esp + 0xc4]", + "fld dword [esp + 0xd0]", + "fld st0", + "fadd st0,st2", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x98]", + "fst qword [esp + 0xd0]", + "fld dword [esp + 0x30]", + "fst qword [esp + 0x98]", + "faddp", + "fmul qword [0x00a77bd0]", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x4]", + "fld dword [esp + 0x8]", + "fst qword [esp + 0x30]", + "fadd st0,st1", + "fstp dword [esp + 0x3c]", + "fsubr qword [esp + 0x30]", + "fstp dword [esp + 0x78]", + "fld dword [esp + 0xa8]", + "fst qword [esp + 0xa8]", + "fld dword [esp + 0xb8]", + "fst qword [esp + 0xb8]", + "faddp", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x88]", + "fst qword [esp + 0x88]", + "fld dword [esp + 0xa0]", + "fst qword [esp + 0xa0]", + "faddp", + "fmul qword [0x00a77b30]", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x4]", + "fld dword [esp + 0x8]", + "fst qword [esp + 0x30]", + "fadd st0,st1", + "fstp dword [esp + 0x40]", + "fsubr qword [esp + 0x30]", + "fstp dword [esp + 0x74]", + "fld dword [esp + 0x90]", + "fst qword [esp + 0x90]", + "fld dword [esp + 0xc8]", + "fst qword [esp + 0xc8]", + "faddp", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x20]", + "fst qword [esp + 0x20]", + "fld dword [esp + 0x28]", + "fst qword [esp + 0x28]", + "faddp", + "fmul qword [0x00a77b28]", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x4]", + "fld dword [esp + 0x8]", + "fst qword [esp + 0x30]", + "fadd st0,st1", + "fstp dword [esp + 0x44]", + "fsubr qword [esp + 0x30]", + "fstp dword [esp + 0x70]", + "fld dword [esp + 0x18]", + "fld dword [esp + 0x80]", + "fst qword [esp + 0x80]", + "fadd st0,st1", + "fstp dword [esp + 0x48]", + "fsubr qword [esp + 0x80]", + "fstp dword [esp + 0x6c]", + "fld qword [esp + 0xc8]", + "fsub qword [esp + 0x90]", + "fstp dword [esp + 0x8]", + "fld qword [esp + 0x28]", + "fsub qword [esp + 0x20]", + "fmul qword [0x00a77b20]", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x4]", + "fld dword [esp + 0x8]", + "fst qword [esp + 0x30]", + "fadd st0,st1", + "fstp dword [esp + 0x4c]", + "fsubr qword [esp + 0x30]", + "fstp dword [esp + 0x68]", + "fld qword [esp + 0xb8]", + "fsub qword [esp + 0xa8]", + "fstp dword [esp + 0x8]", + "fld qword [esp + 0xa0]", + "fsub qword [esp + 0x88]", + "fmul qword [0x00a77b18]", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x4]", + "fld dword [esp + 0x8]", + "fst qword [esp + 0x30]", + "fadd st0,st1", + "fstp dword [esp + 0x50]", + "fsubr qword [esp + 0x30]", + "fstp dword [esp + 0x64]", + "fsubrp", + "fstp dword [esp + 0x8]", + "fld qword [esp + 0x98]", + "fsub qword [esp + 0xd0]", + "fmul qword [0x00a77be0]", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x4]", + "fld dword [esp + 0x8]", + "fld st0", + "fadd st0,st2", + "fstp dword [esp + 0x54]", + "fsubrp", + "fstp dword [esp + 0x60]", + "fxch st2", + "fsubrp st3,st0", + "fxch st2", + "fstp dword [esp + 0x8]", + "fsubrp", + "fmul qword [0x00a77b10]", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x4]", + "fld dword [esp + 0x8]", + "lea eax,[ecx + ecx*0x8]", + "fld st0", + "mov ecx,dword [ebp + 0xc]", + "fadd st0,st2", + "shl eax,0x4", + "add eax,0xb183d0", + "fstp dword [esp + 0x58]", + "fsubrp", + "fstp dword [esp + 0x5c]", + "fld dword [esp + 0x5c]", + "fld st0", + "fchs", + "fmul dword [eax]", + "fstp dword [ecx]", + "fld dword [eax + 0x4]", + "fld dword [esp + 0x60]", + "fld st0", + "fchs", + "fmulp st2", + "fxch", + "fstp dword [ecx + 0x4]", + "fld dword [eax + 0x8]", + "fld dword [esp + 0x64]", + "fld st0", + "fchs", + "fmulp st2", + "fxch", + "fstp dword [ecx + 0x8]", + "fld dword [eax + 0xc]", + "fld dword [esp + 0x68]", + "fld st0", + "fchs", + "fmulp st2", + "fxch", + "fstp dword [ecx + 0xc]", + "fld dword [eax + 0x10]", + "fld dword [esp + 0x6c]", + "fld st0", + "fchs", + "fmulp st2", + "fxch", + "fstp dword [ecx + 0x10]", + "fld dword [eax + 0x14]", + "fld dword [esp + 0x70]", + "fld st0", + "fchs", + "fmulp st2", + "fxch", + "fstp dword [ecx + 0x14]", + "fld dword [eax + 0x18]", + "fld dword [esp + 0x74]", + "fchs", + "fmulp", + "fstp dword [ecx + 0x18]", + "fld dword [eax + 0x1c]", + "fld dword [esp + 0x78]", + "fchs", + "fmulp", + "fstp dword [ecx + 0x1c]", + "fld dword [eax + 0x20]", + "fld dword [esp + 0x7c]", + "fchs", + "fmulp", + "fstp dword [ecx + 0x20]", + "fld dword [eax + 0x24]", + "fmul dword [esp + 0x7c]", + "fstp dword [ecx + 0x24]", + "fld dword [eax + 0x28]", + "fmul dword [esp + 0x78]", + "fstp dword [ecx + 0x28]", + "fld dword [eax + 0x2c]", + "fmul dword [esp + 0x74]", + "fstp dword [ecx + 0x2c]", + "fmul dword [eax + 0x30]", + "fstp dword [ecx + 0x30]", + "fmul dword [eax + 0x34]", + "fstp dword [ecx + 0x34]", + "fmul dword [eax + 0x38]", + "fstp dword [ecx + 0x38]", + "fmul dword [eax + 0x3c]", + "fstp dword [ecx + 0x3c]", + "fmul dword [eax + 0x40]", + "fstp dword [ecx + 0x40]", + "fmul dword [eax + 0x44]", + "fstp dword [ecx + 0x44]", + "fld dword [esp + 0x58]", + "fld dword [eax + 0x48]", + "fmul st1", + "fstp dword [ecx + 0x48]", + "fld dword [esp + 0x54]", + "fld dword [eax + 0x4c]", + "fmul st1", + "fstp dword [ecx + 0x4c]", + "fld dword [esp + 0x50]", + "fld dword [eax + 0x50]", + "fmul st1", + "fstp dword [ecx + 0x50]", + "fld dword [esp + 0x4c]", + "fld dword [eax + 0x54]", + "fmul st1", + "fstp dword [ecx + 0x54]", + "fld dword [esp + 0x48]", + "fld dword [eax + 0x58]", + "fmul st1", + "fstp dword [ecx + 0x58]", + "fld dword [esp + 0x44]", + "fld dword [eax + 0x5c]", + "fmul st1", + "fstp dword [ecx + 0x5c]", + "fld dword [esp + 0x40]", + "fst qword [esp + 0x18]", + "fmul dword [eax + 0x60]", + "fstp dword [ecx + 0x60]", + "fld dword [esp + 0x3c]", + "fst qword [esp + 0x80]", + "fmul dword [eax + 0x64]", + "fstp dword [ecx + 0x64]", + "fld dword [esp + 0x38]", + "fld dword [eax + 0x68]", + "fmul st1", + "fstp dword [ecx + 0x68]", + "fmul dword [eax + 0x6c]", + "fstp dword [ecx + 0x6c]", + "fld dword [eax + 0x70]", + "fmul qword [esp + 0x80]", + "fstp dword [ecx + 0x70]", + "fld dword [eax + 0x74]", + "fmul qword [esp + 0x18]", + "fstp dword [ecx + 0x74]", + "fmul dword [eax + 0x78]", + "fstp dword [ecx + 0x78]", + "fmul dword [eax + 0x7c]", + "fstp dword [ecx + 0x7c]", + "fmul dword [eax + 0x80]", + "fstp dword [ecx + 0x80]", + "fmul dword [eax + 0x84]", + "fstp dword [ecx + 0x84]", + "fmul dword [eax + 0x88]", + "fstp dword [ecx + 0x88]", + "fmul dword [eax + 0x8c]", + "fstp dword [ecx + 0x8c]", + "mov esp,ebp", + "pop ebp", + "ret 0xc" + ], + "ExpectedArm64ASM": [ + "ldr w4, [x9, #8]", + "ldr s2, [x4, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x4, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w20, w4, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x20]", + "ldr s3, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x0", + "add w21, w4, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v4.8b, v0.8b", + "str d4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x4, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w4, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w4, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w4, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w4, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v3.8b, v0.8b", + "str d3, [x21]", + "ldr s3, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v4.8b, v0.8b", + "str d4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x80 (128)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v4.8b, v0.8b", + "str d4, [x21]", + "ldr s4, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x4, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mov w21, #0x7b70", + "movk w21, #0xa7, lsl #16", + "ldr d6, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v6.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mov w21, #0x7b68", + "movk w21, #0xa7, lsl #16", + "ldr d7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v7.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mov w21, #0x7b60", + "movk w21, #0xa7, lsl #16", + "ldr d8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v8.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0xc0 (192)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr d3, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v3.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr d9, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0xd0 (208)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr d9, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0xb8 (184)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr d9, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0xc8 (200)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr d3, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v3.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d3, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v3.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x80 (128)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x7b58", + "movk w21, #0xa7, lsl #16", + "ldr d3, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v3.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v3.8b, v0.8b", + "str d3, [x22]", + "ldr s3, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w22, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v4.8b, v0.8b", + "str d4, [x22]", + "ldr s4, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w22, w8, #0x90 (144)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v5.8b, v0.8b", + "str d5, [x22]", + "ldr s5, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w22, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v9.8b, v0.8b", + "str d9, [x22]", + "mov w22, #0x7b50", + "movk w22, #0xa7, lsl #16", + "ldr d9, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w22, #0x7b48", + "movk w22, #0xa7, lsl #16", + "ldr d3, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v3.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w22, #0x7b40", + "movk w22, #0xa7, lsl #16", + "ldr d4, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v4.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0xb4 (180)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr d2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #144]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d10, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v10.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v10.16b, v10.16b, v10.16b", + "mov v10.d[0], x0", + "mov v10.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v10.d[0]", + "umov w4, v10.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d10, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v10.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v10.16b, v10.16b, v10.16b", + "mov v10.d[0], x0", + "mov v10.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v10.d[0]", + "umov w2, v10.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0xc4 (196)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr d2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d10, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v10.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v10.16b, v10.16b, v10.16b", + "mov v10.d[0], x0", + "mov v10.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v10.d[0]", + "umov w4, v10.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0xa8 (168)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr d2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #144]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x90 (144)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v5.8b, v0.8b", + "str d5, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x98 (152)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v5.8b, v0.8b", + "str d5, [x22]", + "ldr s5, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w22, w8, #0xa0 (160)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v10.8b, v0.8b", + "str d10, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v5.8b, v0.8b", + "str d5, [x22]", + "ldr s5, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w22, w8, #0x88 (136)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v5.8b, v0.8b", + "str d5, [x22]", + "ldr s5, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w22, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v5.8b, v0.8b", + "str d5, [x22]", + "ldr s5, [x4, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w22, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v5.8b, v0.8b", + "str d5, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0xb0 (176)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr d2, [x8, #160]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #152]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr d2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0xa0 (160)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr d2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr d7, [x8, #136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v7.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr d7, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v7.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr d7, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v7.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w22, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x22]", + "ldr d5, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x8, #152]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w22, #0x7bd8", + "movk w22, #0xa7, lsl #16", + "ldr d5, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr d5, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v5.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s5, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w22, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x22]", + "ldr s7, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w22, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v8.8b, v0.8b", + "str d8, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr d8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v8.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x98 (152)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr d7, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v7.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x88 (136)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr d7, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v7.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #180]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #192]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #176]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mov w21, #0x7b38", + "movk w21, #0xa7, lsl #16", + "ldr d7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v7.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #196]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #208]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #152]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0xd0 (208)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v9.8b, v0.8b", + "str d9, [x21]", + "ldr s9, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x98 (152)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v10.8b, v0.8b", + "str d10, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mov w21, #0x7bd0", + "movk w21, #0xa7, lsl #16", + "ldr d9, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v10.8b, v0.8b", + "str d10, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr d9, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #168]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0xa8 (168)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v9.8b, v0.8b", + "str d9, [x21]", + "ldr s9, [x8, #184]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0xb8 (184)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v10.8b, v0.8b", + "str d10, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x88 (136)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v9.8b, v0.8b", + "str d9, [x21]", + "ldr s9, [x8, #160]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0xa0 (160)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v10.8b, v0.8b", + "str d10, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mov w21, #0x7b30", + "movk w21, #0xa7, lsl #16", + "ldr d9, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v10.8b, v0.8b", + "str d10, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr d9, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #144]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x90 (144)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v9.8b, v0.8b", + "str d9, [x21]", + "ldr s9, [x8, #200]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0xc8 (200)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v10.8b, v0.8b", + "str d10, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v9.8b, v0.8b", + "str d9, [x21]", + "ldr s9, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v10.8b, v0.8b", + "str d10, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mov w21, #0x7b28", + "movk w21, #0xa7, lsl #16", + "ldr d9, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v10.8b, v0.8b", + "str d10, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr d9, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x80 (128)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v10.8b, v0.8b", + "str d10, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr d9, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x6c (108)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr d8, [x8, #200]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v8.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr d9, [x8, #144]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr d8, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v8.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr d9, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mov w21, #0x7b20", + "movk w21, #0xa7, lsl #16", + "ldr d9, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v10.8b, v0.8b", + "str d10, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr d9, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x68 (104)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr d8, [x8, #184]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v8.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr d9, [x8, #168]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr d8, [x8, #160]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v8.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr d9, [x8, #136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mov w21, #0x7b18", + "movk w21, #0xa7, lsl #16", + "ldr d9, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v10.8b, v0.8b", + "str d10, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr d9, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x64 (100)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr d6, [x8, #152]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v6.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr d7, [x8, #208]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v7.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mov w21, #0x7be0", + "movk w21, #0xa7, lsl #16", + "ldr d7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v7.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x7b10", + "movk w21, #0xa7, lsl #16", + "ldr d3, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v3.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w4, w5, w5, lsl #3", + "ldr w5, [x9, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "lsl w4, w4, #4", + "mov w21, #0x83d0", + "movk w21, #0xb1, lsl #16", + "mvn w27, w4", + "adds w26, w4, w21", + "mov x4, x26", + "add w21, w8, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x8000", + "fmov d3, x20", + "mov v3.d[1], x21", + "eor v3.16b, v2.16b, v3.16b", + "ldr s4, [x26]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x5]", + "ldr s3, [x26, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "fmov d5, x20", + "mov v5.d[1], x21", + "eor v5.16b, v4.16b, v5.16b", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w22, w5, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x22]", + "ldr s3, [x26, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s5, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "fmov d6, x20", + "mov v6.d[1], x21", + "eor v6.16b, v5.16b, v6.16b", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w22, w5, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x22]", + "ldr s3, [x26, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s6, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "fmov d7, x20", + "mov v7.d[1], x21", + "eor v7.16b, v6.16b, v7.16b", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w22, w5, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x22]", + "ldr s3, [x26, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s7, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "fmov d8, x20", + "mov v8.d[1], x21", + "eor v8.16b, v7.16b, v8.16b", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w22, w5, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x22]", + "ldr s3, [x26, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s8, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "fmov d9, x20", + "mov v9.d[1], x21", + "eor v9.16b, v8.16b, v9.16b", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "strb w20, [x28, #1017]", + "add w22, w5, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x22]", + "ldr s3, [x26, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s9, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "fmov d10, x20", + "mov v10.d[1], x21", + "eor v9.16b, v9.16b, v10.16b", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w22, w5, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x22]", + "ldr s3, [x26, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s9, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "fmov d10, x20", + "mov v10.d[1], x21", + "eor v9.16b, v9.16b, v10.16b", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w22, w5, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x22]", + "ldr s3, [x26, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s9, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "fmov d10, x20", + "mov v10.d[1], x21", + "eor v9.16b, v9.16b, v10.16b", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w5, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x26, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s9, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w5, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x26, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s9, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w5, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x26, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s9, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w5, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x26, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w5, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x26, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w5, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x26, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w5, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x26, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w5, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x26, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w5, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x26, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w5, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x26, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w5, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x26, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w5, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x26, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w5, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x26, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w5, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x26, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w5, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x26, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w5, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v9.8b, v0.8b", + "str d9, [x21]", + "ldr s9, [x26, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w5, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x80 (128)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1448]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "mov v9.8b, v0.8b", + "str d9, [x21]", + "ldr s9, [x26, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w5, #0x64 (100)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x26, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w5, #0x68 (104)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr s9, [x26, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w5, #0x6c (108)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x26, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr d9, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w5, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x26, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr d9, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v9.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w5, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x26, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w5, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x26, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w5, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x26, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w5, #0x80 (128)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x26, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w5, #0x84 (132)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x26, #136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w5, #0x88 (136)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x26, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w5, #0x8c (140)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "mov x8, x9", + "ldr w21, [x9]", + "add x8, x9, #0x4 (4)", + "mov x9, x21", + "ldr w21, [x8]", + "add w22, w8, #0x4 (4)", + "add w8, w22, #0xc (12)", + "strb w20, [x28, #1298]", + "ldr x0, [x28, #2304]", + "and x3, x21, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block3": { + "ExpectedInstructionCount": 16758, + "x86Insts": [ + "fld dword [esi + 0x64]", + "mov eax,dword [esi + 0x88]", + "fstp dword [esp + 0x5c]", + "mov ecx,dword [esi + 0x8c]", + "fld dword [esi + 0x70]", + "mov edx,dword [esi + 0x90]", + "fstp dword [esp + 0x60]", + "mov dword [esp + 0x2e4],0x3f", + "fld dword [esi + 0x7c]", + "mov dword [esp + 0x94],eax", + "fstp dword [esp + 0x64]", + "mov dword [esp + 0x98],ecx", + "fld dword [esi + 0x68]", + "mov dword [esp + 0x9c],edx", + "fstp dword [esp + 0x14]", + "mov dword [esp + 0xe8],eax", + "fld dword [esi + 0x74]", + "mov dword [esp + 0xec],ecx", + "fstp dword [esp + 0x18]", + "mov dword [esp + 0xf0],edx", + "fld dword [esi + 0x80]", + "fstp dword [esp + 0x1c]", + "fld dword [esi + 0xf4]", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x28]", + "fld dword [esp + 0x14]", + "fmul st1", + "fstp dword [esp + 0x8c]", + "fld dword [esp + 0x18]", + "fmul st1", + "fstp dword [esp + 0x7c]", + "fmul dword [esp + 0x1c]", + "fstp dword [esp + 0x84]", + "fld dword [esi + 0x6c]", + "fstp dword [esp + 0x14]", + "fld dword [esi + 0x78]", + "fstp dword [esp + 0x18]", + "fld dword [esi + 0x84]", + "fstp dword [esp + 0x1c]", + "fld dword [esi + 0xf0]", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x28]", + "fld dword [esp + 0x14]", + "fmul st1", + "fstp dword [esp + 0x54]", + "fld dword [esp + 0x18]", + "fmul st1", + "fstp dword [esp + 0x50]", + "fmul dword [esp + 0x1c]", + "fstp dword [esp + 0x58]", + "fld dword [esi + 0x100]", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x28]", + "fld dword [esp + 0x54]", + "fmul st1", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x28]", + "fst dword [esp + 0x10]", + "fld dword [esp + 0x50]", + "fmul st2", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x28]", + "fst dword [esp + 0x2c]", + "fld dword [esp + 0x58]", + "fmul st3", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x28]", + "fst dword [esp + 0x14]", + "fld dword [esp + 0x8c]", + "fmul st4", + "fstp dword [esp + 0x4c]", + "fld dword [esp + 0x4c]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x7c]", + "fmul st4", + "fstp dword [esp + 0x8c]", + "fld dword [esp + 0x8c]", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x84]", + "fmul st4", + "fstp dword [esp + 0x58]", + "fld dword [esp + 0x58]", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x5c]", + "fmul st4", + "fstp dword [esp + 0x50]", + "fld dword [esp + 0x50]", + "fstp dword [esp + 0x84]", + "fld dword [esp + 0x60]", + "fmul st4", + "fstp dword [esp + 0x54]", + "fld dword [esp + 0x54]", + "fstp dword [esp + 0x7c]", + "fld dword [esp + 0x64]", + "fmulp st4", + "fxch st3", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x28]", + "fstp dword [esp + 0x5c]", + "fld dword [esp + 0x94]", + "fld dword [esp + 0x84]", + "fadd st0,st1", + "fstp dword [esp + 0x84]", + "fld dword [esp + 0x98]", + "fld dword [esp + 0x7c]", + "fadd st0,st1", + "fstp dword [esp + 0x7c]", + "fld dword [esp + 0x9c]", + "fld dword [esp + 0x5c]", + "fadd st0,st1", + "fstp dword [esp + 0x5c]", + "fld dword [esp + 0x84]", + "fadd dword [esp + 0x44]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x7c]", + "fadd dword [esp + 0x48]", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x5c]", + "fadd dword [esp + 0x40]", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x44]", + "fadd dword [esp + 0x10]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x48]", + "fadd dword [esp + 0x2c]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x40]", + "fadd dword [esp + 0x14]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x10]", + "fstp dword [esp + 0x5c]", + "mov eax,dword [esp + 0x5c]", + "fld dword [esp + 0x2c]", + "mov dword [esp + 0xf4],eax", + "fstp dword [esp + 0x60]", + "mov ecx,dword [esp + 0x60]", + "fld dword [esp + 0x14]", + "mov dword [esp + 0xf8],ecx", + "fstp dword [esp + 0x64]", + "mov edx,dword [esp + 0x64]", + "fxch st4", + "mov dword [esp + 0xfc],edx", + "fst dword [esp + 0x5c]", + "fxch st3", + "fst dword [esp + 0x84]", + "fxch st5", + "fst dword [esp + 0x7c]", + "fld dword [esp + 0x4c]", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x8c]", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x58]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x50]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x54]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x28]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fadd st0,st3", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fadd st0,st2", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fadd st0,st5", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fadd dword [esp + 0x40]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fadd dword [esp + 0x48]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fadd dword [esp + 0x44]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x5c]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fsub dword [esp + 0x84]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fsub dword [esp + 0x7c]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fstp dword [esp + 0x14]", + "mov eax,dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "mov dword [esp + 0x100],eax", + "fstp dword [esp + 0x18]", + "mov ecx,dword [esp + 0x18]", + "fld dword [esp + 0x10]", + "mov dword [esp + 0x104],ecx", + "fstp dword [esp + 0x1c]", + "mov edx,dword [esp + 0x1c]", + "fxch st3", + "mov dword [esp + 0x108],edx", + "fst dword [esp + 0x5c]", + "fxch st5", + "fst dword [esp + 0x84]", + "fxch st3", + "fst dword [esp + 0x7c]", + "fld dword [esp + 0x4c]", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x8c]", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x58]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x50]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x54]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x28]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fadd st0,st3", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fadd st0,st2", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fadd st0,st5", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x40]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fsub dword [esp + 0x48]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fsub dword [esp + 0x44]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fadd dword [esp + 0x5c]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fadd dword [esp + 0x84]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fadd dword [esp + 0x7c]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fstp dword [esp + 0x14]", + "mov eax,dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "mov dword [esp + 0x10c],eax", + "fstp dword [esp + 0x18]", + "mov ecx,dword [esp + 0x18]", + "fld dword [esp + 0x10]", + "mov dword [esp + 0x110],ecx", + "fstp dword [esp + 0x1c]", + "mov edx,dword [esp + 0x1c]", + "fxch st5", + "mov dword [esp + 0x114],edx", + "fstp dword [esp + 0x5c]", + "fxch st2", + "fstp dword [esp + 0x84]", + "fxch st3", + "fstp dword [esp + 0x7c]", + "fld dword [esp + 0x4c]", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x8c]", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x58]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x50]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x54]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x28]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "faddp st3,st0", + "fxch st2", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x2c]", + "fadd dword [esp + 0x10]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x40]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fsub dword [esp + 0x48]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fsub dword [esp + 0x44]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x5c]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fsub dword [esp + 0x84]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fsub dword [esp + 0x7c]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fstp dword [esp + 0x14]", + "mov eax,dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "mov dword [esp + 0x118],eax", + "mov eax,dword [ebx + 0x88]", + "fstp dword [esp + 0x18]", + "fld dword [esp + 0x10]", + "mov ecx,dword [esp + 0x18]", + "fstp dword [esp + 0x1c]", + "mov edx,dword [esp + 0x1c]", + "fld dword [ebx + 0x64]", + "mov dword [esp + 0x11c],ecx", + "mov ecx,dword [ebx + 0x8c]", + "fstp dword [esp + 0x70]", + "fld dword [ebx + 0x70]", + "mov dword [esp + 0x120],edx", + "mov edx,dword [ebx + 0x90]", + "fstp dword [esp + 0x74]", + "fld dword [ebx + 0x7c]", + "mov dword [esp + 0x94],eax", + "mov dword [esp + 0x98],ecx", + "mov dword [esp + 0x9c],edx", + "fstp dword [esp + 0x78]", + "mov dword [esp + 0xac],eax", + "fld dword [ebx + 0x68]", + "mov dword [esp + 0xb0],ecx", + "fstp dword [esp + 0x2c]", + "mov dword [esp + 0xb4],edx", + "fld dword [ebx + 0x74]", + "fstp dword [esp + 0x30]", + "fld dword [ebx + 0x80]", + "fstp dword [esp + 0x34]", + "fld dword [ebx + 0xf4]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fmul st1", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x30]", + "fmul st1", + "fstp dword [esp + 0x48]", + "fmul dword [esp + 0x34]", + "fstp dword [esp + 0x44]", + "fld dword [ebx + 0x6c]", + "fstp dword [esp + 0x5c]", + "fld dword [ebx + 0x78]", + "fstp dword [esp + 0x60]", + "fld dword [ebx + 0x84]", + "fstp dword [esp + 0x64]", + "fld dword [ebx + 0xf0]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x14]", + "fld dword [esp + 0x5c]", + "fmul st1", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x60]", + "fmul st1", + "fstp dword [esp + 0x2c]", + "fmul dword [esp + 0x64]", + "fstp dword [esp + 0x10]", + "fld dword [ebx + 0x100]", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x28]", + "fld dword [esp + 0x14]", + "fmul st1", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x14]", + "fst dword [esp + 0x5c]", + "fld dword [esp + 0x2c]", + "fmul st2", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x14]", + "fst dword [esp + 0x84]", + "fld dword [esp + 0x10]", + "fmul st3", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x14]", + "fst dword [esp + 0x7c]", + "fld dword [esp + 0x40]", + "fmul st4", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x28]", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x48]", + "fmul st4", + "fstp dword [esp + 0x54]", + "fld dword [esp + 0x54]", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x44]", + "fmul st4", + "fstp dword [esp + 0x50]", + "fld dword [esp + 0x50]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x70]", + "fmul st4", + "fstp dword [esp + 0x58]", + "fld dword [esp + 0x58]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x74]", + "fmul st4", + "fstp dword [esp + 0x8c]", + "fld dword [esp + 0x8c]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x78]", + "fmulp st4", + "fxch st3", + "fstp dword [esp + 0x4c]", + "fld dword [esp + 0x4c]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x94]", + "fld dword [esp + 0x14]", + "fadd st0,st1", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x98]", + "fld dword [esp + 0x2c]", + "fadd st0,st1", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x9c]", + "fld dword [esp + 0x10]", + "fadd st0,st1", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fadd dword [esp + 0x40]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fadd dword [esp + 0x48]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fadd dword [esp + 0x44]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fadd dword [esp + 0x5c]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fadd dword [esp + 0x84]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fadd dword [esp + 0x7c]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fstp dword [esp + 0x70]", + "mov eax,dword [esp + 0x70]", + "fld dword [esp + 0x2c]", + "mov dword [esp + 0xb8],eax", + "fstp dword [esp + 0x74]", + "mov ecx,dword [esp + 0x74]", + "fld dword [esp + 0x10]", + "mov dword [esp + 0xbc],ecx", + "fstp dword [esp + 0x78]", + "mov edx,dword [esp + 0x78]", + "fxch st4", + "mov dword [esp + 0xc0],edx", + "fst dword [esp + 0x5c]", + "fxch st3", + "fst dword [esp + 0x84]", + "fxch st5", + "fst dword [esp + 0x7c]", + "fld dword [esp + 0x28]", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x54]", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x50]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x58]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x8c]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x4c]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fadd st0,st3", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fadd st0,st2", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fadd st0,st5", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fadd dword [esp + 0x40]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fadd dword [esp + 0x48]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fadd dword [esp + 0x44]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x5c]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fsub dword [esp + 0x84]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fsub dword [esp + 0x7c]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fstp dword [esp + 0x70]", + "mov eax,dword [esp + 0x70]", + "fld dword [esp + 0x2c]", + "mov dword [esp + 0xc4],eax", + "fstp dword [esp + 0x74]", + "mov ecx,dword [esp + 0x74]", + "fld dword [esp + 0x10]", + "mov dword [esp + 0xc8],ecx", + "fstp dword [esp + 0x78]", + "mov edx,dword [esp + 0x78]", + "fxch st3", + "mov dword [esp + 0xcc],edx", + "fst dword [esp + 0x5c]", + "fxch st5", + "fst dword [esp + 0x84]", + "fxch st3", + "fst dword [esp + 0x7c]", + "fld dword [esp + 0x28]", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x54]", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x50]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x58]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x8c]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x4c]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fadd st0,st3", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fadd st0,st2", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fadd st0,st5", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x40]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fsub dword [esp + 0x48]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fsub dword [esp + 0x44]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fadd dword [esp + 0x5c]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x2c]", + "fadd dword [esp + 0x84]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x10]", + "fadd dword [esp + 0x7c]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x14]", + "fstp dword [esp + 0x70]", + "mov eax,dword [esp + 0x70]", + "fld dword [esp + 0x2c]", + "mov dword [esp + 0xd0],eax", + "fstp dword [esp + 0x74]", + "mov ecx,dword [esp + 0x74]", + "fld dword [esp + 0x10]", + "mov dword [esp + 0xd4],ecx", + "fstp dword [esp + 0x78]", + "mov edx,dword [esp + 0x78]", + "mov dword [esp + 0xd8],edx", + "fxch st5", + "push 0x0", + "fstp dword [esp + 0x60]", + "fxch st2", + "fstp dword [esp + 0x88]", + "fxch st3", + "fstp dword [esp + 0x80]", + "fld dword [esp + 0x2c]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x58]", + "fstp dword [esp + 0x4c]", + "fld dword [esp + 0x54]", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x5c]", + "fstp dword [esp + 0x18]", + "fld dword [esp + 0x90]", + "fstp dword [esp + 0x30]", + "fld dword [esp + 0x50]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x18]", + "faddp st3,st0", + "fxch st2", + "fstp dword [esp + 0x18]", + "fld dword [esp + 0x30]", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x30]", + "fadd dword [esp + 0x14]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x18]", + "fsub dword [esp + 0x44]", + "fstp dword [esp + 0x18]", + "fld dword [esp + 0x30]", + "fsub dword [esp + 0x4c]", + "fstp dword [esp + 0x30]", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x48]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x18]", + "fsub dword [esp + 0x60]", + "fstp dword [esp + 0x18]", + "fld dword [esp + 0x30]", + "fsub dword [esp + 0x88]", + "fstp dword [esp + 0x30]", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x80]", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0x18]", + "fstp dword [esp + 0x74]", + "mov eax,dword [esp + 0x74]", + "fld dword [esp + 0x30]", + "mov dword [esp + 0xe0],eax", + "fstp dword [esp + 0x78]", + "mov ecx,dword [esp + 0x78]", + "fld dword [esp + 0x14]", + "mov dword [esp + 0xe4],ecx", + "fstp dword [esp + 0x7c]", + "mov edx,dword [esp + 0x7c]", + "lea ecx,[esp + 0x190]", + "mov dword [esp + 0xe8],edx", + "call 0x0070df30", + "mov dword [esp + 0x198],esi", + "add esi,0xec", + "push esi", + "lea ecx,[esp + 0x190]", + "mov dword [esp + 0x314],0x0", + "call 0x0070e040", + "mov ecx,0x19", + "lea esi,[esp + 0x1b8]", + "lea edi,[esp + 0x21c]", + "rep movsd", + "mov dword [esp + 0x198],ebx", + "add ebx,0xec", + "push ebx", + "lea ecx,[esp + 0x190]", + "call 0x0070e040", + "mov ecx,0x19", + "lea esi,[esp + 0x1b8]", + "lea edi,[esp + 0x284]", + "rep movsd", + "lea esi,[esp + 0x124]", + "mov edi,0x5" + ], + "ExpectedArm64ASM": [ + "ldr s2, [x10, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x10, #136]", + "add w20, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr w5, [x10, #140]", + "ldr s2, [x10, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x10, #144]", + "add w20, w8, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "mov w20, #0x3f", + "str w20, [x8, #740]", + "ldr s2, [x10, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str w4, [x8, #148]", + "add w20, w8, #0x64 (100)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "str w5, [x8, #152]", + "ldr s2, [x10, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str w6, [x8, #156]", + "add w20, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "str w4, [x8, #232]", + "ldr s2, [x10, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str w5, [x8, #236]", + "add w20, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "str w6, [x8, #240]", + "ldr s2, [x10, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x10, #244]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w20, w8, #0x8c (140)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x20]", + "ldr s3, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w20, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x20]", + "ldr s3, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x84 (132)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x10, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x10, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x10, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x10, #240]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w20, w8, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x20]", + "ldr s3, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w20, w8, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x20]", + "ldr s3, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x10, #256]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w20, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x20]", + "ldr s3, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w20, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x20]", + "ldr s4, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w20, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x20]", + "ldr s4, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w20, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x20]", + "ldr s5, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w20, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x20]", + "ldr s5, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w20, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x20]", + "ldr s6, [x8, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w20, w8, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x20]", + "ldr s6, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w20, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x20]", + "ldr s6, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w20, w8, #0x8c (140)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x20]", + "ldr s6, [x8, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w20, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x20]", + "ldr s6, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w20, w8, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x20]", + "ldr s6, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w20, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x20]", + "ldr s6, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w20, w8, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x20]", + "ldr s6, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w20, w8, #0x84 (132)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x20]", + "ldr s6, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w20, w8, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x20]", + "ldr s6, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w20, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x20]", + "ldr s6, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x0", + "add w21, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #148]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s6, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x84 (132)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #152]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #156]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w4, [x8, #92]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "str w4, [x8, #244]", + "add w21, w8, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w5, [x8, #96]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "str w5, [x8, #248]", + "add w21, w8, #0x64 (100)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w6, [x8, #100]", + "str w6, [x8, #252]", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "add w21, w8, #0x84 (132)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "add w21, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w4, [x8, #20]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "str w4, [x8, #256]", + "add w21, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w5, [x8, #24]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "str w5, [x8, #260]", + "add w21, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w6, [x8, #28]", + "str w6, [x8, #264]", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "add w21, w8, #0x84 (132)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "add w21, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w4, [x8, #20]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "str w4, [x8, #268]", + "add w21, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w5, [x8, #24]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "str w5, [x8, #272]", + "add w21, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w6, [x8, #28]", + "str w6, [x8, #276]", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "add w21, w8, #0x84 (132)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "add w21, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr w4, [x8, #20]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str w4, [x8, #280]", + "ldr w4, [x7, #136]", + "add w21, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w5, [x8, #24]", + "add w21, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr w6, [x8, #28]", + "ldr s2, [x7, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str w5, [x8, #284]", + "ldr w5, [x7, #140]", + "add w21, w8, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x7, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str w6, [x8, #288]", + "ldr w6, [x7, #144]", + "add w21, w8, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x7, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str w4, [x8, #148]", + "str w5, [x8, #152]", + "str w6, [x8, #156]", + "add w21, w8, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "str w4, [x8, #172]", + "ldr s2, [x7, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str w5, [x8, #176]", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "str w6, [x8, #180]", + "ldr s2, [x7, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x7, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x7, #244]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x7, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x7, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x7, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x64 (100)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x7, #240]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x7, #256]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x84 (132)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x8c (140)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #148]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s6, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #152]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #156]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w4, [x8, #112]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "str w4, [x8, #184]", + "add w21, w8, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w5, [x8, #116]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "str w5, [x8, #188]", + "add w21, w8, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w6, [x8, #120]", + "str w6, [x8, #192]", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "add w21, w8, #0x84 (132)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "add w21, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w4, [x8, #112]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "str w4, [x8, #196]", + "add w21, w8, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w5, [x8, #116]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "str w5, [x8, #200]", + "add w21, w8, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w6, [x8, #120]", + "str w6, [x8, #204]", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "add w21, w8, #0x84 (132)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "add w21, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w4, [x8, #112]", + "ldr s8, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "str w4, [x8, #208]", + "add w21, w8, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w5, [x8, #116]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "str w5, [x8, #212]", + "add w21, w8, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr w6, [x8, #120]", + "str w6, [x8, #216]", + "str w20, [x8, #-4]!", + "add w21, w8, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "add w21, w8, #0x88 (136)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "add w21, w8, #0x80 (128)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #144]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "strb w20, [x28, #1017]", + "add w20, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr w4, [x8, #116]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str w4, [x8, #224]", + "add w20, w8, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr w5, [x8, #120]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str w5, [x8, #228]", + "add w20, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr w6, [x8, #124]", + "add w5, w8, #0x190 (400)", + "str w6, [x8, #232]", + "mov w20, #0x229f", + "movk w20, #0x1, lsl #16", + "mov w21, #0xd4f1", + "movk w21, #0x70, lsl #16", + "add w21, w20, w21", + "str w20, [x8, #-4]!", + "ldrb w20, [x28, #1019]", + "mov w22, #0x1", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w23, [x28, #1298]", + "lsl w20, w22, w20", + "bic w20, w23, w20", + "strb w20, [x28, #1298]", + "ldr x0, [x28, #2304]", + "and x3, x21, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block4": { + "ExpectedInstructionCount": 63, + "x86Insts": [ + "fldz", + "push 0x0", + "push -0x1", + "push 0x1000172", + "push 0x37", + "push ecx", + "fstp dword [esp]", + "push 0x0", + "push 0xa33c14", + "push 0x52424157", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x1000172", + "push 0x38", + "push ecx", + "fstp dword [esp]", + "push 0x0", + "push 0xa33c04", + "push 0x41574157", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x2b", + "push ecx", + "fstp dword [esp]", + "push 0x0", + "push 0xa33bfc", + "push 0x444c4853", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x3d", + "push ecx", + "fstp dword [esp]", + "push 0x0", + "push 0xa33bf0", + "push 0x48534946", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x44", + "push ecx", + "fstp dword [esp]", + "push 0x0", + "push 0xa33bdc", + "push 0x4853494c", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x3e", + "push ecx", + "fstp dword [esp]", + "push 0x0", + "push 0xa33bcc", + "push 0x48535246", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x52485446", + "push 0x4c505344", + "push 0x2", + "push 0x40", + "push 0x1000073", + "push 0xb", + "push ecx", + "fstp dword [esp]", + "push 0x0", + "push 0xa33bc4", + "push 0x4e445242", + "call 0x00417220", + "fldz", + "add esp,0x28", + "push 0x4c505344", + "push 0x1", + "push 0x40", + "push 0x1000076", + "push 0xb", + "push ecx", + "fstp dword [esp]", + "push 0x0", + "push 0xa33bbc", + "push 0x52485446", + "call 0x00417220", + "fldz", + "add esp,0x24", + "push 0x0", + "push -0x1", + "push 0xe0", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x0", + "push 0xa32700", + "push 0x4b434f4c", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0xc0", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x0", + "push 0xa33bb4", + "push 0x4e45504f", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x48534946", + "push 0x49465352", + "push 0x4c505344", + "push 0x3", + "push 0x3d", + "push 0x21000475", + "push 0x8", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33ba8", + "push 0x47444946", + "call 0x00417220", + "fldz", + "add esp,0x2c", + "push 0x4853494c", + "push 0x48535352", + "push 0x4c505344", + "push 0x3", + "push 0x44", + "push 0x21000075", + "push 0x8", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33b98", + "push 0x47444853", + "call 0x00417220", + "fldz", + "add esp,0x2c", + "push 0x48535246", + "push 0x52465352", + "push 0x4c505344", + "push 0x3", + "push 0x3e", + "push 0x1000075", + "push 0x8", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33b88", + "push 0x47445246", + "call 0x00417220", + "fldz", + "add esp,0x2c", + "push 0x54414241", + "push 0x54414f46", + "push 0x54414552", + "push 0x4c505344", + "push 0x4", + "push 0x40", + "push 0x100075", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33b74", + "push 0x54414744", + "call 0x00417220", + "fldz", + "add esp,0x30", + "push 0x45484241", + "push 0x45484f46", + "push 0x45484552", + "push 0x4c505344", + "push 0x4", + "push 0x40", + "push 0x21000075", + "push 0x8", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33b64", + "push 0x45484744", + "call 0x00417220", + "fldz", + "add esp,0x30", + "push 0x50534241", + "push 0x50534f46", + "push 0x50534552", + "push 0x4c505344", + "push 0x4", + "push 0x40", + "push 0x1000075", + "push 0x9", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33b50", + "push 0x50534744", + "call 0x00417220", + "fldz", + "add esp,0x30", + "push 0x41464241", + "push 0x41464f46", + "push 0x41464552", + "push 0x4c505344", + "push 0x4", + "push 0x40", + "push 0x1000075", + "push 0xa", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33b40", + "push 0x41464744", + "call 0x00417220", + "fldz", + "add esp,0x30", + "push 0x54414241", + "push 0x54414f46", + "push 0x54414552", + "push 0x4c505344", + "push 0x4", + "push 0x40", + "push 0x100077", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33b30", + "push 0x54415244", + "call 0x00417220", + "fldz", + "add esp,0x30", + "push 0x4b534241", + "push 0x4b534f46", + "push 0x4c505344", + "push 0x3", + "push 0x40", + "push 0x80077", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33b24", + "push 0x4b535244", + "call 0x00417220", + "fldz", + "add esp,0x2c", + "push 0x45484241", + "push 0x45484f46", + "push 0x45484552", + "push 0x4c505344", + "push 0x4", + "push 0x40", + "push 0x1000077", + "push 0x8", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33b14", + "push 0x45485244", + "call 0x00417220", + "fldz", + "add esp,0x30", + "push 0x50534241", + "push 0x50534f46", + "push 0x50534552", + "push 0x4c505344", + "push 0x4", + "push 0x40", + "push 0x1000077", + "push 0x9", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33b00", + "push 0x50535244", + "call 0x00417220", + "fldz", + "add esp,0x30", + "push 0x41464241", + "push 0x41464f46", + "push 0x41464552", + "push 0x4c505344", + "push 0x4", + "push 0x40", + "push 0x1000077", + "push 0xa", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33af0", + "push 0x41465244", + "call 0x00417220", + "fldz", + "add esp,0x30", + "push 0x4c505344", + "push 0x49465352", + "push 0x48534946", + "push 0x3", + "push 0x40", + "push 0x100007f", + "push 0x3d", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33adc", + "push 0x49464b57", + "call 0x00417220", + "fldz", + "add esp,0x2c", + "push 0x4c505344", + "push 0x52465352", + "push 0x48535246", + "push 0x3", + "push 0x40", + "push 0x100007f", + "push 0x3e", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33ac8", + "push 0x52464b57", + "call 0x00417220", + "fldz", + "add esp,0x2c", + "push 0x4c505344", + "push 0x48535352", + "push 0x4853494c", + "push 0x3", + "push 0x40", + "push 0x100007f", + "push 0x44", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33ab4", + "push 0x48534b57", + "call 0x00417220", + "fldz", + "add esp,0x2c", + "push 0x4c505344", + "push 0x414d5352", + "push 0x2", + "push 0x40", + "push 0x100007f", + "push 0x40", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33aa0", + "push 0x414d4b57", + "call 0x00417220", + "fldz", + "add esp,0x28", + "push 0x4c505344", + "push 0x49445352", + "push 0x2", + "push 0x40", + "push 0x100007f", + "push 0x3f", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33a8c", + "push 0x49444b57", + "call 0x00417220", + "fldz", + "add esp,0x28", + "push 0x4c505344", + "push 0x4f505352", + "push 0x2", + "push 0x40", + "push 0x100007f", + "push 0x43", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33a78", + "push 0x4f504b57", + "call 0x00417220", + "add esp,0x28", + "push 0x4c505344", + "push 0x574e5352", + "push 0x2", + "push 0x40", + "push 0x100007f", + "push 0x41", + "push ecx", + "fldz", + "fstp dword [esp]", + "push 0x2", + "push 0xa33a5c", + "push 0x574e4b57", + "call 0x00417220", + "fldz", + "add esp,0x28", + "push 0x48535246", + "push 0x4853494c", + "push 0x48534946", + "push 0x444c4853", + "push 0x4c505344", + "push 0x5", + "push 0x40", + "push 0x75", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33a48", + "push 0x52414944", + "call 0x00417220", + "fldz", + "add esp,0x34", + "push 0x48535246", + "push 0x4853494c", + "push 0x48534946", + "push 0x444c4853", + "push 0x4c505344", + "push 0x5", + "push 0x40", + "push 0x75", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33a30", + "push 0x45574944", + "call 0x00417220", + "fldz", + "add esp,0x34", + "push 0x0", + "push 0x3f", + "push 0x10000092", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33a24", + "push 0x504d4156", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x14", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33a18", + "push 0x47445553", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x1000112", + "push 0x39", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa33a08", + "push 0x414d5453", + "call 0x00417220", + "add esp,0x20", + "push 0x4f505543", + "push 0x1", + "push 0x43", + "push 0x800000", + "fldz", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa339fc", + "push 0x4e534f50", + "call 0x00417220", + "fldz", + "add esp,0x24", + "push 0x49445543", + "push 0x1", + "push 0x3f", + "push 0x800000", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa339ec", + "push 0x45534944", + "call 0x00417220", + "fldz", + "add esp,0x24", + "push 0x45484241", + "push 0x45484f46", + "push 0x45484552", + "push 0x4c505344", + "push 0x4", + "push 0x40", + "push 0x21000075", + "push 0x8", + "push ecx", + "fstp dword [esp]", + "push 0x2", + "push 0xa339cc", + "push 0x594d5544", + "call 0x00417220", + "fldz", + "add esp,0x30", + "push 0x0", + "push -0x1", + "push 0x1000172", + "push 0x2f", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa339bc", + "push 0x49564e49", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x2e", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa339b0", + "push 0x4c4d4843", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x4c505344", + "push 0x41505543", + "push 0x2", + "push 0x42", + "push 0x1000173", + "push 0x30", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa339a4", + "push 0x41524150", + "call 0x00417220", + "add esp,0x28", + "push 0x4c505344", + "push 0x1", + "push 0x40", + "push 0x1000173", + "push 0x31", + "fldz", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa3399c", + "push 0x434e4c53", + "call 0x00417220", + "fldz", + "add esp,0x24", + "push 0x4c505344", + "push 0x1", + "push 0x40", + "push 0x1000062", + "push 0x6", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa33994", + "push 0x4d524843", + "call 0x00417220", + "fldz", + "add esp,0x24", + "push 0x594c4152", + "push 0x4c505344", + "push 0x2", + "push 0x40", + "push 0x41000066", + "push 0x22", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa33988", + "push 0x4f4d4544", + "call 0x00417220", + "fldz", + "add esp,0x28", + "push 0x4f4d4544", + "push 0x4c505344", + "push 0x2", + "push 0x40", + "push 0x1000062", + "push 0x22", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa33980", + "push 0x594c4152", + "call 0x00417220", + "fldz", + "add esp,0x28", + "push 0x4d4c4143", + "push 0x4c505344", + "push 0x2", + "push 0x40", + "push 0x41000062", + "push 0x21", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa33978", + "push 0x5a4e5246", + "call 0x00417220", + "fldz", + "add esp,0x28", + "push 0x5a4e5246", + "push 0x4c505344", + "push 0x2", + "push 0x40", + "push 0x41000066", + "push 0x21", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa33970", + "push 0x4d4c4143", + "call 0x00417220", + "add esp,0x28", + "push 0x0", + "push -0x1", + "push 0x1000112", + "push 0x29", + "fldz", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa33964", + "push 0x4559454e", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x80000072", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa3395c", + "push 0x5448474c", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x81000072", + "push 0x46", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa33950", + "push 0x4b524144", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push 0x40", + "push 0xf0", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x4", + "push 0xa33948", + "push 0x4c505344", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x4c505344", + "push 0x1", + "push 0x40", + "push 0x163", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x4", + "push 0xa3393c", + "push 0x50525453", + "call 0x00417220", + "fldz", + "add esp,0x24", + "push 0x0", + "push -0x1", + "push 0x81000242", + "push 0x3c", + "push ecx", + "fstp dword [esp]", + "push 0x4", + "push 0xa33930", + "push 0x454c4554", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x81000012", + "push 0x3a", + "push ecx", + "fstp dword [esp]", + "push 0x4", + "push 0xa33924", + "push 0x54435444", + "call 0x00417220", + "add esp,0x20", + "fldz", + "push 0x0", + "push 0x40", + "push 0x1000072", + "push 0x34", + "push ecx", + "fstp dword [esp]", + "push 0x4", + "push 0xa33910", + "push 0x53424153", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x35", + "push ecx", + "fstp dword [esp]", + "push 0x4", + "push 0xa33908", + "push 0x434c4652", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100001a", + "push 0x3b", + "push ecx", + "fstp dword [esp]", + "push 0x4", + "push 0xa338f8", + "push 0x47444552", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100070", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa338e4", + "push 0x54414552", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x1000070", + "push 0x8", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa338d4", + "push 0x45484552", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x1000070", + "push 0x9", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa338bc", + "push 0x50534552", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x1000070", + "push 0xa", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa338ac", + "push 0x41464552", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100072", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa33898", + "push 0x54414f46", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x80072", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa33888", + "push 0x4b534f46", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x1000072", + "push 0x8", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa33878", + "push 0x45484f46", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x1000072", + "push 0x9", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa33860", + "push 0x50534f46", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x1000072", + "push 0xa", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa33850", + "push 0x41464f46", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x4b535244", + "push 0x4b534241", + "push 0x4c505344", + "push 0x3", + "push 0x40", + "push 0x80027", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa33840", + "push 0x4b534241", + "call 0x00417220", + "add esp,0x2c", + "push 0x54414744", + "push 0x54415244", + "push 0x54414241", + "fldz", + "push 0x4c505344", + "push 0x4", + "push 0x40", + "push 0x100027", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa3382c", + "push 0x54414241", + "call 0x00417220", + "fldz", + "add esp,0x30", + "push 0x594d5544", + "push 0x45484744", + "push 0x45485244", + "push 0x45484241", + "push 0x4c505344", + "push 0x4", + "push 0x40", + "push 0x1000025", + "push 0x8", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa3381c", + "push 0x45484241", + "call 0x00417220", + "fldz", + "add esp,0x34", + "push 0x41464744", + "push 0x41465244", + "push 0x41464241", + "push 0x4c505344", + "push 0x4", + "push 0x40", + "push 0x1000025", + "push 0xa", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa3380c", + "push 0x41464241", + "call 0x00417220", + "fldz", + "add esp,0x30", + "push 0x50534744", + "push 0x50535244", + "push 0x50534241", + "push 0x4c505344", + "push 0x4", + "push 0x40", + "push 0x1000025", + "push 0x9", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa337f8", + "push 0x50534241", + "call 0x00417220", + "fldz", + "add esp,0x30", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x3d", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa337ec", + "push 0x49465352", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x3e", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa337dc", + "push 0x52465352", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x44", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa337cc", + "push 0x48535352", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x40", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa337bc", + "push 0x414d5352", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x3f", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa337ac", + "push 0x49445352", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x43", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa3379c", + "push 0x4f505352", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x42", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa33788", + "push 0x41505352", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100007a", + "push 0x41", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa33770", + "push 0x574e5352", + "call 0x00417220", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x100017a", + "push 0x47", + "fldz", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa3375c", + "push 0x44575352", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x1f0", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa3374c", + "push 0x49445543", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x1f0", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa33740", + "push 0x4f505543", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x1f0", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa33730", + "push 0x41505543", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x1000012", + "push 0x28", + "push ecx", + "fstp dword [esp]", + "push 0x5", + "push 0xa33714", + "push 0x4d4d4f46", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33704", + "push 0x4f48475a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa336f8", + "push 0x43494c5a", + "call 0x00417220", + "add esp,0x20", + "push 0x0", + "fldz", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa336e8", + "push 0x454b535a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa336d0", + "push 0x414b535a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa336b4", + "push 0x434b535a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa3369c", + "push 0x484b535a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa3368c", + "push 0x4152575a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33678", + "push 0x4c52575a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33668", + "push 0x4d4f5a5a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33650", + "push 0x5a44485a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33638", + "push 0x4149465a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33620", + "push 0x4152465a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33608", + "push 0x4154535a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa335f8", + "push 0x4541445a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa335e8", + "push 0x4552445a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa335d4", + "push 0x4c52445a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa335c4", + "push 0x4143535a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa335b0", + "push 0x414c435a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33598", + "push 0x4450535a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33588", + "push 0x5649585a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33578", + "push 0x3130305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33568", + "push 0x3230305a", + "call 0x00417220", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "fldz", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33558", + "push 0x3330305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33548", + "push 0x3430305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33538", + "push 0x3530305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33528", + "push 0x3630305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33518", + "push 0x3730305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33508", + "push 0x3830305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa334f8", + "push 0x3930305a", + "call 0x00417220", + "add esp,0x20", + "push 0x0", + "fldz", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa334e8", + "push 0x3031305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa334d8", + "push 0x3131305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa334c8", + "push 0x3231305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa334b8", + "push 0x3331305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa334a8", + "push 0x3431305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33498", + "push 0x3531305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33488", + "push 0x3631305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33478", + "push 0x3731305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33468", + "push 0x3831305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33458", + "push 0x3931305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x40112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33448", + "push 0x3032305a", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x4c505344", + "push 0x1", + "push -0x1", + "push 0x40000062", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa33434", + "push 0x55484f43", + "call 0x00417220", + "fldz", + "add esp,0x24", + "push 0x4c505344", + "push 0x1", + "push -0x1", + "push 0x40000062", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x3", + "push 0xa33420", + "push 0x52434f43", + "call 0x00417220", + "add esp,0x24", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fldz", + "fstp dword [esp]", + "push 0x1", + "push 0xa33414", + "push 0x58415742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33408", + "push 0x4f425742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa333f8", + "push 0x41445742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa333ec", + "push 0x414d5742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa333e0", + "push 0x57535742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa333d4", + "push 0x4f424142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa333c4", + "push 0x55434142", + "call 0x00417220", + "add esp,0x20", + "push 0x0", + "push -0x1", + "fldz", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa333b4", + "push 0x41474142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa333a4", + "push 0x52474142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33394", + "push 0x45484142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33384", + "push 0x48534142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa3336c", + "push 0x31304142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33354", + "push 0x32304142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa3333c", + "push 0x33304142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33324", + "push 0x34304142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa3330c", + "push 0x35304142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa332f4", + "push 0x36304142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa332dc", + "push 0x37304142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa332c4", + "push 0x38304142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa332ac", + "push 0x39304142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33294", + "push 0x30314142", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa3327c", + "push 0x31305742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33264", + "push 0x32305742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa3324c", + "push 0x33305742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33234", + "push 0x34305742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa3321c", + "push 0x35305742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33204", + "push 0x36305742", + "call 0x00417220", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fldz", + "fstp dword [esp]", + "push 0x1", + "push 0xa331ec", + "push 0x37305742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa331d4", + "push 0x38305742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa331bc", + "push 0x39305742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa331a4", + "push 0x30315742", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x594c4152", + "push 0x4c505344", + "push 0x2", + "push 0x40", + "push 0x40000063", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33198", + "push 0x4e525554", + "call 0x00417220", + "fldz", + "add esp,0x28", + "push 0x4c505344", + "push 0x1", + "push -0x1", + "push 0x170", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x6", + "push 0xa33188", + "push 0x46464553", + "call 0x00417220", + "fldz", + "add esp,0x24", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa3316c", + "push 0x4854594d", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x20112", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33154", + "push 0x4c48594d", + "call 0x00417220", + "fldz", + "add esp,0x20", + "push 0x0", + "push -0x1", + "push 0x10000360", + "push 0x0", + "push ecx", + "fstp dword [esp]", + "push 0x1", + "push 0xa33148", + "push 0x4e414552", + "call 0x00417220", + "add esp,0x20", + "ret" + ], + "ExpectedArm64ASM": [ + "movi v2.2d, #0x0", + "mov w20, #0x0", + "str w20, [x8, #-4]!", + "mov w21, #0xffffffff", + "str w21, [x8, #-4]!", + "mov w21, #0x172", + "movk w21, #0x100, lsl #16", + "str w21, [x8, #-4]!", + "mov w21, #0x37", + "str w21, [x8, #-4]!", + "str w5, [x8, #-4]!", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x8]", + "str w20, [x8, #-4]!", + "mov w20, #0x3c14", + "movk w20, #0xa3, lsl #16", + "str w20, [x8, #-4]!", + "mov w20, #0x4157", + "movk w20, #0x5242, lsl #16", + "str w20, [x8, #-4]!", + "mov w20, #0x23d2", + "movk w20, #0x1, lsl #16", + "mov w21, #0x71fe", + "movk w21, #0x41, lsl #16", + "add w21, w20, w21", + "str w20, [x8, #-4]!", + "ldrb w20, [x28, #1019]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1298]", + "mov w23, #0x1", + "lsl w20, w23, w20", + "bic w20, w22, w20", + "strb w20, [x28, #1298]", + "ldr x0, [x28, #2304]", + "and x3, x21, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block5": { + "ExpectedInstructionCount": 442, + "x86Insts": [ + "mov ebx,dword [eax + 0x68]", + "fld dword [esi + 0x2c]", + "mov eax,dword [ebp + 0x68]", + "sub esp,0x14", + "fstp dword [esp + 0x10]", + "movzx ecx,al", + "fld1", + "mov dword [esp + 0x38],ecx", + "fstp dword [esp + 0xc]", + "movzx edx,bl", + "fldz", + "fstp dword [esp + 0x8]", + "fild dword [esp + 0x38]", + "mov dword [esp + 0x40],eax", + "fld qword [0x00a3ddd8]", + "fdiv st1,st0", + "fxch", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x38]", + "fstp dword [esp + 0x4]", + "mov dword [esp + 0x38],edx", + "fild dword [esp + 0x38]", + "fdivrp", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x38]", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [esp + 0x24]", + "fld dword [esi + 0x2c]", + "movzx eax,byte [esp + 0x41]", + "fstp dword [esp + 0x10]", + "mov dword [esp + 0x38],eax", + "fld1", + "movzx ecx,bh", + "fstp dword [esp + 0xc]", + "fldz", + "fstp dword [esp + 0x8]", + "fild dword [esp + 0x38]", + "fld qword [0x00a3ddd8]", + "fdiv st1,st0", + "fxch", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x38]", + "fstp dword [esp + 0x4]", + "mov dword [esp + 0x38],ecx", + "fild dword [esp + 0x38]", + "fdivrp", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x38]", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [esp + 0x28]", + "mov eax,dword [esp + 0x40]", + "fld dword [esi + 0x2c]", + "fstp dword [esp + 0x10]", + "shr eax,0x10", + "fld1", + "movzx edx,al", + "fstp dword [esp + 0xc]", + "mov dword [esp + 0x40],edx", + "fldz", + "shr ebx,0x10", + "movzx eax,bl", + "fstp dword [esp + 0x8]", + "fild dword [esp + 0x40]", + "fld qword [0x00a3ddd8]", + "fdiv st1,st0", + "fxch", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x40]", + "fstp dword [esp + 0x4]", + "mov dword [esp + 0x40],eax", + "fild dword [esp + 0x40]", + "fdivrp", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x40]", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [esp + 0x2c]", + "fld1", + "fst dword [esp + 0x30]", + "mov ecx,dword [esp + 0x24]", + "mov edx,dword [esp + 0x28]", + "mov eax,dword [esp + 0x2c]", + "mov dword [0x00b45e14],ecx", + "mov ecx,dword [esp + 0x30]", + "mov [0x00b45e1c],eax", + "mov dword [0x00b45e20],ecx", + "mov dword [0x00b45e18],edx", + "fld dword [esi + 0x2c]", + "mov eax,dword [ebp + 0x6c]", + "fstp dword [esp + 0x10]", + "mov dword [esp + 0x40],eax", + "fstp dword [esp + 0xc]", + "movzx eax,al", + "fldz", + "mov dword [esp + 0x38],eax", + "fstp dword [esp + 0x8]", + "mov edx,dword [esi + 0x20]", + "fild dword [esp + 0x38]", + "mov ebx,dword [edx + 0x6c]", + "fld qword [0x00a3ddd8]", + "movzx ecx,bl", + "fdiv st1,st0", + "fxch", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x38]", + "fstp dword [esp + 0x4]", + "mov dword [esp + 0x38],ecx", + "fild dword [esp + 0x38]", + "fdivrp", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x38]", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [esp + 0x24]", + "fld dword [esi + 0x2c]", + "movzx edx,byte [esp + 0x41]", + "fstp dword [esp + 0x10]", + "mov dword [esp + 0x38],edx", + "fld1", + "movzx eax,bh", + "fstp dword [esp + 0xc]", + "fldz", + "fstp dword [esp + 0x8]", + "fild dword [esp + 0x38]", + "fld qword [0x00a3ddd8]", + "fdiv st1,st0", + "fxch", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x38]", + "fstp dword [esp + 0x4]", + "mov dword [esp + 0x38],eax", + "fild dword [esp + 0x38]", + "fdivrp", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x38]", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [esp + 0x28]", + "mov eax,dword [esp + 0x40]", + "fld dword [esi + 0x2c]", + "fstp dword [esp + 0x10]", + "shr eax,0x10", + "fld1", + "movzx ecx,al", + "fstp dword [esp + 0xc]", + "mov dword [esp + 0x40],ecx", + "fldz", + "shr ebx,0x10", + "movzx edx,bl", + "fstp dword [esp + 0x8]", + "fild dword [esp + 0x40]", + "fld qword [0x00a3ddd8]", + "fdiv st1,st0", + "fxch", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x40]", + "fstp dword [esp + 0x4]", + "mov dword [esp + 0x40],edx", + "fild dword [esp + 0x40]", + "fdivrp", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x40]", + "fstp dword [esp]", + "call 0x00410eb0", + "mov eax,dword [esp + 0x24]", + "fstp dword [esp + 0x2c]", + "fld1", + "mov ecx,dword [esp + 0x28]", + "mov edx,dword [esp + 0x2c]", + "fst dword [esp + 0x30]", + "mov [0x00b45e24],eax", + "mov eax,dword [esp + 0x30]", + "mov dword [0x00b45e2c],edx", + "mov [0x00b45e30],eax", + "mov dword [0x00b45e28],ecx", + "fld dword [esi + 0x2c]", + "mov eax,dword [ebp + 0x70]", + "fstp dword [esp + 0x10]", + "movzx edx,al", + "fstp dword [esp + 0xc]", + "mov dword [esp + 0x38],edx", + "fldz", + "mov ecx,dword [esi + 0x20]", + "fstp dword [esp + 0x8]", + "mov ebx,dword [ecx + 0x70]", + "fild dword [esp + 0x38]", + "mov dword [esp + 0x40],eax", + "fld qword [0x00a3ddd8]", + "movzx eax,bl", + "fdiv st1,st0", + "fxch", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x38]", + "fstp dword [esp + 0x4]", + "mov dword [esp + 0x38],eax", + "fild dword [esp + 0x38]", + "fdivrp", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x38]", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [esp + 0x24]", + "fld dword [esi + 0x2c]", + "movzx ecx,byte [esp + 0x41]", + "fstp dword [esp + 0x10]", + "mov dword [esp + 0x38],ecx", + "fld1", + "movzx edx,bh", + "fstp dword [esp + 0xc]", + "fldz", + "fstp dword [esp + 0x8]", + "fild dword [esp + 0x38]", + "fld qword [0x00a3ddd8]", + "fdiv st1,st0", + "fxch", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x38]", + "fstp dword [esp + 0x4]", + "mov dword [esp + 0x38],edx", + "fild dword [esp + 0x38]", + "fdivrp", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x38]", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [esp + 0x28]", + "mov eax,dword [esp + 0x40]", + "fld dword [esi + 0x2c]", + "fstp dword [esp + 0x10]", + "shr eax,0x10", + "fld1", + "movzx eax,al", + "fstp dword [esp + 0xc]", + "mov dword [esp + 0x40],eax", + "fldz", + "fstp dword [esp + 0x8]", + "fild dword [esp + 0x40]", + "fld qword [0x00a3ddd8]", + "fdiv st1,st0", + "fxch", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x40]", + "shr ebx,0x10", + "movzx ecx,bl", + "fstp dword [esp + 0x4]", + "mov dword [esp + 0x40],ecx", + "fild dword [esp + 0x40]", + "fdivrp", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x40]", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [esp + 0x2c]", + "fld1", + "mov edx,dword [esp + 0x24]", + "mov eax,dword [esp + 0x28]", + "fst dword [esp + 0x30]", + "mov ecx,dword [esp + 0x2c]", + "mov dword [0x00b45e34],edx", + "mov edx,dword [esp + 0x30]", + "mov [0x00b45e38],eax", + "mov dword [0x00b45e3c],ecx", + "mov dword [0x00b45e40],edx", + "fld dword [esi + 0x2c]", + "mov eax,dword [esi + 0x24]", + "fstp dword [esp + 0x10]", + "mov ecx,dword [esi + 0x20]", + "fstp dword [esp + 0xc]", + "fldz", + "fstp dword [esp + 0x8]", + "fld dword [eax + 0x4c]", + "fstp dword [esp + 0x4]", + "fld dword [ecx + 0x4c]", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [0x00b45e44]", + "fld dword [esi + 0x2c]", + "mov edx,dword [esi + 0x24]", + "mov eax,dword [esi + 0x20]", + "fstp dword [esp + 0x10]", + "fld1", + "fstp dword [esp + 0xc]", + "fldz", + "fstp dword [esp + 0x8]", + "fld dword [edx + 0x50]", + "fstp dword [esp + 0x4]", + "fld dword [eax + 0x50]", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [0x00b45e48]", + "fld dword [esi + 0x2c]", + "mov ecx,dword [esi + 0x24]", + "add esp,0x8", + "fstp dword [esp + 0x8]", + "fld1", + "fstp dword [esp + 0x4]", + "fldz", + "fstp dword [esp]", + "call 0x004ed660", + "push ecx", + "mov ecx,dword [esi + 0x20]", + "fstp dword [esp]", + "call 0x004ed660", + "push ecx", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [0x00b45e4c]", + "mov ecx,dword [esi + 0x24]", + "fld dword [esi + 0x2c]", + "add esp,0x8", + "fstp dword [esp + 0x8]", + "fld1", + "fstp dword [esp + 0x4]", + "fldz", + "fstp dword [esp]", + "call 0x004ed680", + "push ecx", + "mov ecx,dword [esi + 0x20]", + "fstp dword [esp]", + "call 0x004ed680", + "push ecx", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [0x00b45e50]", + "fld dword [esi + 0x2c]", + "mov ecx,dword [esi + 0x24]", + "mov edx,dword [esi + 0x20]", + "fstp dword [esp + 0x10]", + "fld1", + "fstp dword [esp + 0xc]", + "fldz", + "fstp dword [esp + 0x8]", + "fld dword [ecx + 0x58]", + "fstp dword [esp + 0x4]", + "fld dword [edx + 0x58]", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [0x00b45e54]", + "fld dword [esi + 0x2c]", + "mov eax,dword [esi + 0x24]", + "mov ecx,dword [esi + 0x20]", + "fstp dword [esp + 0x10]", + "fld1", + "fstp dword [esp + 0xc]", + "fldz", + "fstp dword [esp + 0x8]", + "fld dword [eax + 0x5c]", + "fstp dword [esp + 0x4]", + "fld dword [ecx + 0x5c]", + "fstp dword [esp]", + "call 0x00410eb0", + "fstp dword [0x00b45e58]", + "fld dword [esi + 0x2c]", + "mov edx,dword [esi + 0x24]", + "mov eax,dword [esi + 0x20]", + "fstp dword [esp + 0x10]", + "fld1", + "fstp dword [esp + 0xc]", + "fldz", + "fstp dword [esp + 0x8]", + "fld dword [edx + 0x54]", + "fstp dword [esp + 0x4]", + "fld dword [eax + 0x54]", + "fstp dword [esp]", + "call 0x00410eb0", + "add esp,0x14", + "jmp 0x00499d78" + ], + "ExpectedArm64ASM": [ + "ldr w7, [x4, #104]", + "ldr s2, [x10, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #104]", + "mvn w27, w8", + "subs w26, w8, #0x14 (20)", + "cfinv", + "mov x8, x26", + "add w20, w26, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "uxtb w5, w4", + "ldr q2, [x28, #2576]", + "str w5, [x26, #56]", + "add w20, w26, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "uxtb w6, w7", + "movi v2.2d, #0x0", + "add w20, w26, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr w20, [x26, #56]", + "mov w21, #0x0", + "sxtw x20, w20", + "mrs x22, nzcv", + "cmp x20, #0x0 (0)", + "mov w23, #0x8000", + "csel x24, x23, xzr, lt", + "cneg x20, x20, mi", + "mov w25, #0x3f", + "mov x0, #0x3f", + "clz x12, x20", + "sub x12, x0, x12", + "sub x12, x25, x12", + "lsl x13, x20, x12", + "mov w14, #0x403e", + "sub x12, x14, x12", + "cmp x20, #0x0 (0)", + "csel x20, x21, x12, eq", + "orr x20, x24, x20", + "fmov d2, x13", + "fmov d3, x20", + "mov v2.d[1], v3.d[0]", + "str w4, [x26, #64]", + "mov w20, #0xddd8", + "movk w20, #0xa3, lsl #16", + "ldr d3, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v3.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1688]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "strb w21, [x28, #1017]", + "add w20, w26, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x26, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w26, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "str w6, [x26, #56]", + "ldr w20, [x26, #56]", + "sxtw x20, w20", + "cmp x20, #0x0 (0)", + "csel x23, x23, xzr, lt", + "cneg x20, x20, mi", + "mov x0, #0x3f", + "clz x24, x20", + "sub x24, x0, x24", + "sub x24, x25, x24", + "lsl x25, x20, x24", + "sub x24, x14, x24", + "cmp x20, #0x0 (0)", + "csel x20, x21, x24, eq", + "orr x20, x23, x20", + "fmov d2, x25", + "fmov d4, x20", + "mov v2.d[1], v4.d[0]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1688]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w26, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x26, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x26]", + "mov w20, #0x3e35", + "movk w20, #0x1, lsl #16", + "mov w21, #0xe52", + "movk w21, #0x41, lsl #16", + "add w21, w20, w21", + "mov w8, w26", + "str w20, [x8, #-4]!", + "msr nzcv, x22", + "ldrb w20, [x28, #1019]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1298]", + "mov w23, #0x1", + "lsl w20, w23, w20", + "bic w20, w22, w20", + "strb w20, [x28, #1298]", + "ldr x0, [x28, #2304]", + "and x3, x21, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block6": { + "ExpectedInstructionCount": 58, + "x86Insts": [ + "mov eax,dword [esp + 0x110]", + "fldz", + "mov ecx,dword [eax]", + "mov edx,dword [esp + 0x5c]", + "mov ebx,dword [edx + 0x18]", + "mov esi,dword [esp + 0x58]", + "mov dword [ebx + 0xc],ecx", + "mov edx,dword [eax + 0x4]", + "mov dword [ebx + 0x10],edx", + "mov eax,dword [eax + 0x8]", + "mov dword [ebx + 0x14],eax", + "mov ecx,dword [esi + 0x50]", + "push ecx", + "fstp dword [esp]", + "call 0x00784370", + "mov ecx,dword [esi + 0x50]", + "fstp dword [esp + 0x54]", + "fldz", + "push ecx", + "fstp dword [esp]", + "call 0x00784370", + "fstp dword [esp + 0x64]", + "mov eax,dword [esp + 0x11c]", + "lea ebp,[ebx + 0x1c]", + "mov esi,eax", + "mov ecx,0x9", + "mov edi,ebp", + "rep movsd", + "fld dword [eax + 0x4]", + "mov ecx,dword [esp + 0x120]", + "sub esp,0xc", + "fmul dword [ecx + 0x4]", + "fld dword [ecx]", + "fmul dword [eax]", + "faddp", + "fld dword [eax + 0x8]", + "fmul dword [ecx + 0x8]", + "faddp", + "fstp dword [esp + 0x28]", + "fld dword [eax + 0xc]", + "fmul dword [ecx]", + "fld dword [eax + 0x10]", + "fmul dword [ecx + 0x4]", + "faddp", + "fld dword [eax + 0x14]", + "fmul dword [ecx + 0x8]", + "faddp", + "fstp dword [esp + 0x44]", + "fld dword [eax + 0x18]", + "fmul dword [ecx]", + "fld dword [eax + 0x1c]", + "fmul dword [ecx + 0x4]", + "faddp", + "fld dword [eax + 0x20]", + "mov eax,esp", + "fmul dword [ecx + 0x8]", + "faddp", + "fstp dword [esp + 0x34]", + "fld dword [esp + 0x28]", + "fstp dword [esp + 0x48]", + "mov ecx,dword [esp + 0x48]", + "fld dword [esp + 0x44]", + "mov dword [eax],ecx", + "fstp dword [esp + 0x4c]", + "mov edx,dword [esp + 0x4c]", + "fld dword [esp + 0x34]", + "mov dword [eax + 0x4],edx", + "fstp dword [esp + 0x50]", + "mov ecx,dword [esp + 0x50]", + "fld dword [esp + 0x3c]", + "mov dword [eax + 0x8],ecx", + "push ecx", + "mov ecx,ebp", + "fstp dword [esp]", + "call 0x0078f050", + "fld dword [esp + 0x54]", + "sub esp,0x8", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x6c]", + "fadd dword [esp + 0x3c]", + "fstp dword [esp + 0x24]", + "fld dword [esp + 0x24]", + "mov ecx,ebp", + "fstp dword [esp]", + "call 0x0078ef60", + "fld dword [ebp + 0xc]", + "mov esi,dword [esp + 0x58]", + "fld dword [0x00b2b71c]", + "fld st0", + "fmulp st2", + "fld dword [ebp]", + "fld dword [0x00b2b718]", + "fld st0", + "fmulp st2", + "fxch st3", + "faddp", + "fld dword [ebp + 0x18]", + "fld dword [0x00b2b720]", + "fld st0", + "fmulp st2", + "fxch st2", + "faddp", + "fstp dword [esp + 0x1c]", + "fld dword [ebp + 0x10]", + "fmul st2", + "fld dword [ebp + 0x4]", + "fmul st4", + "faddp", + "fld dword [ebp + 0x1c]", + "fmul st2", + "faddp", + "fstp dword [esp + 0x38]", + "fld dword [ebp + 0x14]", + "fmulp st2", + "fld dword [ebp + 0x8]", + "fmulp st3", + "fxch", + "faddp st2,st0", + "fmul dword [ebp + 0x20]", + "faddp", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x1c]", + "fstp dword [esp + 0x3c]", + "mov edx,dword [esp + 0x3c]", + "fld dword [esp + 0x38]", + "mov dword [ebx],edx", + "fstp dword [esp + 0x40]", + "mov eax,dword [esp + 0x40]", + "fld dword [esp + 0x28]", + "mov dword [ebx + 0x4],eax", + "fstp dword [esp + 0x44]", + "mov ecx,dword [esp + 0x44]", + "fldz", + "mov dword [ebx + 0x8],ecx", + "mov ecx,dword [esi + 0x68]", + "push ecx", + "fstp dword [esp]", + "call 0x00784210", + "fmul dword [esp + 0x6c]", + "fstp dword [ebx + 0x18]", + "mov ecx,dword [esi + 0x5c]", + "fldz", + "push ecx", + "fstp dword [esp]", + "call 0x00784210", + "fmul dword [esp + 0x80]", + "push 0xb2b724", + "mov ecx,ebx", + "fstp dword [esp + 0x54]", + "call 0x0078fcc0", + "fmul qword [0x00a8ba48]", + "fstp dword [esp + 0x34]", + "fld dword [esp + 0x34]", + "fsubr qword [0x00a65a18]", + "fstp dword [esp + 0x1c]", + "fld dword [esp + 0x1c]", + "fabs", + "fstp dword [esp + 0x1c]", + "fld dword [esp + 0x1c]", + "fmul qword [0x00a8c698]", + "fld1", + "fsubrp", + "fstp dword [esp + 0x38]", + "fld dword [0x00b2b72c]", + "fld st0", + "fmul dword [ebx + 0x4]", + "fld dword [ebx + 0x8]", + "fld dword [0x00b2b728]", + "fld st0", + "fmulp st2", + "fxch st2", + "fsubrp", + "fstp dword [esp + 0x24]", + "fld dword [ebx + 0x8]", + "fld dword [0x00b2b724]", + "fld st0", + "fmulp st2", + "fld dword [ebx]", + "fmulp st4", + "fxch", + "fsubrp st3,st0", + "fxch st2", + "fstp dword [esp + 0x30]", + "fmul dword [ebx]", + "fld dword [ebx + 0x4]", + "fmulp st2", + "fsubrp", + "fstp dword [esp + 0x4c]", + "fld dword [esp + 0x30]", + "fld dword [esp + 0x24]", + "fld dword [esp + 0x4c]", + "fld st1", + "fmulp st2", + "fld st2", + "fmulp st3", + "fxch", + "faddp st2,st0", + "fmul st0", + "faddp", + "fstp dword [esp + 0x1c]", + "fld dword [esp + 0x1c]", + "call 0x00982c30", + "fstp dword [esp + 0x1c]", + "fld dword [esp + 0x1c]", + "mov ecx,dword [esi + 0x70]", + "fld1", + "push ecx", + "fdivrp", + "fstp dword [esp + 0x20]", + "fld dword [esp + 0x28]", + "fld dword [esp + 0x20]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x34]", + "fmul st1", + "fstp dword [esp + 0x44]", + "fmul dword [esp + 0x50]", + "fstp dword [esp + 0x48]", + "fldz", + "fstp dword [esp]", + "call 0x00784210", + "fsub qword [0x00a2faa0]", + "mov edx,dword [esp + 0x3c]", + "mov ecx,dword [esp + 0x40]", + "sub esp,0xc", + "fadd st0,st0", + "mov eax,esp", + "mov dword [eax],edx", + "fmul qword [0x00a3d360]", + "fstp dword [esp + 0x28]", + "fld1", + "fst dword [esp + 0xb8]", + "fldz", + "fst dword [esp + 0xbc]", + "fst dword [esp + 0xc0]", + "fst dword [esp + 0xc4]", + "fst dword [esp + 0xcc]", + "fst dword [esp + 0xd0]", + "fstp dword [esp + 0xd4]", + "fst dword [esp + 0xc8]", + "fstp dword [esp + 0xd8]", + "fld dword [esp + 0x28]", + "mov edx,dword [esp + 0x50]", + "fmul dword [esp + 0x90]", + "mov dword [eax + 0x4],ecx", + "push ecx", + "mov dword [eax + 0x8],edx", + "fmul dword [esp + 0x44]", + "lea ecx,[esp + 0xbc]", + "fmul dword [esp + 0x48]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x2c]", + "fstp dword [esp]", + "call 0x0078f160", + "lea eax,[esp + 0xac]", + "push eax", + "lea ecx,[esp + 0xd4]", + "push ecx", + "mov ecx,ebp", + "call 0x0078edd0", + "cmp dword [esp + 0x124],0x0", + "mov esi,eax", + "mov ecx,0x9", + "mov edi,ebp", + "rep movsd", + "fld dword [ebp + 0xc]", + "fld dword [0x00b2b71c]", + "fld st0", + "fmulp st2", + "fld dword [ebp]", + "fld dword [0x00b2b718]", + "fld st0", + "fmulp st2", + "fxch st3", + "faddp", + "fld dword [ebp + 0x18]", + "fld dword [0x00b2b720]", + "fld st0", + "fmulp st2", + "fxch st2", + "faddp", + "fstp dword [esp + 0x1c]", + "fld dword [ebp + 0x10]", + "fmul st2", + "fld dword [ebp + 0x4]", + "fmul st4", + "faddp", + "fld dword [ebp + 0x1c]", + "fmul st2", + "faddp", + "fstp dword [esp + 0x38]", + "fld dword [ebp + 0x14]", + "fmulp st2", + "fld dword [ebp + 0x8]", + "fmulp st3", + "fxch", + "faddp st2,st0", + "fmul dword [ebp + 0x20]", + "faddp", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0x1c]", + "fstp dword [esp + 0x3c]", + "mov edx,dword [esp + 0x3c]", + "fld dword [esp + 0x38]", + "mov dword [ebx],edx", + "fstp dword [esp + 0x40]", + "mov eax,dword [esp + 0x40]", + "fld dword [esp + 0x28]", + "mov dword [ebx + 0x4],eax", + "mov eax,dword [esp + 0x10c]", + "fstp dword [esp + 0x44]", + "mov ecx,dword [esp + 0x44]", + "mov dword [ebx + 0x8],ecx", + "jz 0x00792dd2" + ], + "ExpectedArm64ASM": [ + "ldr w4, [x8, #272]", + "movi v2.2d, #0x0", + "ldr w5, [x4]", + "ldr w6, [x8, #92]", + "ldr w7, [x6, #24]", + "ldr w10, [x8, #88]", + "str w5, [x7, #12]", + "ldr w6, [x4, #4]", + "str w6, [x7, #16]", + "ldr w4, [x4, #8]", + "str w4, [x7, #20]", + "ldr w5, [x10, #80]", + "str w5, [x8, #-4]!", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x8]", + "mov w20, #0x43d3", + "movk w20, #0x1, lsl #16", + "mov w21, #0x433f", + "movk w21, #0x78, lsl #16", + "add w21, w20, w21", + "str w20, [x8, #-4]!", + "ldrb w20, [x28, #1019]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1298]", + "mov w23, #0x1", + "lsl w20, w23, w20", + "bic w20, w22, w20", + "strb w20, [x28, #1298]", + "ldr x0, [x28, #2304]", + "and x3, x21, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block7": { + "ExpectedInstructionCount": 7453, + "x86Insts": [ + "fld dword [ecx + 0xc]", + "fld dword [ecx + 0x18]", + "fadd st0,st1", + "fstp dword [ecx + 0x18]", + "fld dword [ecx]", + "fadd st1,st0", + "fxch", + "fstp dword [ecx + 0xc]", + "fld dword [ecx + -0xc]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [ecx]", + "fld dword [ecx + -0x18]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [ecx + -0xc]", + "fld dword [ecx + -0x24]", + "fld st0", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x8]", + "fst dword [ecx + -0x18]", + "fld dword [ecx]", + "fld dword [ecx + 0x18]", + "fadd st0,st1", + "fstp dword [ecx + 0x18]", + "fadd st0,st1", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x8]", + "fst dword [ecx]", + "fld dword [ecx + -0xc]", + "fmul st6", + "fstp dword [esp + 0x4]", + "fld dword [ecx + 0xc]", + "fld st0", + "fmul st6", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x8]", + "fadd st0,st4", + "fstp dword [esp + 0x8]", + "fsubp st3,st0", + "fxch st2", + "fstp dword [esp + 0x3c]", + "fld dword [esp + 0x8]", + "fld dword [esp + 0x4]", + "fld st0", + "fadd st0,st2", + "fstp dword [esp + 0x38]", + "fsubp", + "fstp dword [esp + 0x40]", + "fxch", + "fmul st4", + "fstp dword [esp + 0x4]", + "fld dword [ecx + 0x18]", + "fld st0", + "fmul st4", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x8]", + "fadd st0,st2", + "fstp dword [esp + 0x8]", + "fsubp", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x8]", + "fld dword [esp + 0x4]", + "fld st0", + "fadd st0,st2", + "fstp dword [esp + 0x4c]", + "fsubp", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x8]", + "fmul qword [0x00a77be0]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x48]", + "fmul qword [0x00a77bd8]", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x4c]", + "fmul qword [0x00a77bd0]", + "fstp dword [esp + 0x4c]", + "fld dword [esp + 0x38]", + "fst dword [esp + 0x8]", + "fld dword [esp + 0x4c]", + "fadd st1,st0", + "fxch", + "fstp dword [esp + 0x38]", + "fsubr dword [esp + 0x8]", + "fstp dword [esp + 0x4c]", + "fld dword [esp + 0x3c]", + "fst dword [esp + 0x8]", + "fld dword [esp + 0x48]", + "fadd st1,st0", + "fxch", + "fstp dword [esp + 0x3c]", + "fsubr dword [esp + 0x8]", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x40]", + "fst dword [esp + 0x8]", + "fld dword [esp + 0x44]", + "fadd st1,st0", + "fxch", + "fstp dword [esp + 0x40]", + "fsubr dword [esp + 0x8]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x38]", + "fmul qword [0x00a77bc8]", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x3c]", + "fmul qword [0x00a77bc0]", + "fstp dword [esp + 0x3c]", + "fld dword [esp + 0x40]", + "fmul qword [0x00a77bb8]", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x44]", + "fmul qword [0x00a77bb0]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x48]", + "fmul qword [0x00a77ba8]", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x4c]", + "fmul qword [0x00a77ba0]", + "fstp dword [esp + 0x4c]", + "fld dword [esp + 0x38]", + "fchs", + "fld st0", + "fmul st2", + "fstp dword [esp + 0x58]", + "fld qword [0x00a77b98]", + "fmul st1", + "fxch", + "fstp dword [esp + 0x5c]", + "fld dword [esp + 0x3c]", + "fchs", + "fld st0", + "fld qword [0x00a77b90]", + "fmul st1", + "fxch", + "fstp dword [esp + 0x54]", + "fxch", + "fmul qword [0x00a77b88]", + "fstp dword [esp + 0x60]", + "fld dword [esp + 0x40]", + "fchs", + "fld qword [0x00a77b80]", + "fmul st1", + "fstp dword [esp + 0x50]", + "fmul qword [0x00a77b78]", + "fstp dword [esp + 0x64]", + "fld dword [esp + 0x44]", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x48]", + "fld qword [0x00a77b88]", + "fmul st1", + "fstp dword [esp + 0x3c]", + "fld dword [esp + 0x4c]", + "fld st0", + "fmulp st4", + "fxch st3", + "fstp dword [esp + 0x40]", + "fxch st2", + "fchs", + "fmul st3", + "add eax,0x18", + "add ecx,0x4", + "sub edx,0x1", + "fstp dword [esp + 0x44]", + "fxch", + "fchs", + "fmulp", + "fstp dword [esp + 0x48]", + "fld dword [esp + 0x38]", + "fld st0", + "fchs", + "fmul qword [0x00a77b80]", + "fstp dword [esp + 0x4c]", + "fmul qword [0x00a77b78]", + "fstp dword [esp + 0x38]", + "fld dword [eax + -0x1c]", + "fadd dword [esp + 0x38]", + "fstp dword [eax + -0x1c]", + "fld dword [eax + -0x18]", + "fadd dword [esp + 0x3c]", + "fstp dword [eax + -0x18]", + "fld dword [esp + 0x40]", + "fadd dword [eax + -0x14]", + "fstp dword [eax + -0x14]", + "fld dword [eax + -0x10]", + "fadd dword [esp + 0x44]", + "fstp dword [eax + -0x10]", + "fld dword [eax + -0xc]", + "fadd dword [esp + 0x48]", + "fstp dword [eax + -0xc]", + "fld dword [eax + -0x8]", + "fadd dword [esp + 0x4c]", + "fstp dword [eax + -0x8]", + "fld dword [esp + 0x50]", + "fadd dword [eax + -0x4]", + "fstp dword [eax + -0x4]", + "fld dword [eax]", + "fadd dword [esp + 0x54]", + "fstp dword [eax]", + "fld dword [eax + 0x4]", + "fadd dword [esp + 0x58]", + "fstp dword [eax + 0x4]", + "fld dword [eax + 0x8]", + "fadd dword [esp + 0x5c]", + "fstp dword [eax + 0x8]", + "fld dword [esp + 0x60]", + "fadd dword [eax + 0xc]", + "fstp dword [eax + 0xc]", + "fld dword [eax + 0x10]", + "fadd dword [esp + 0x64]", + "fstp dword [eax + 0x10]", + "jnz 0x006b1f09" + ], + "ExpectedArm64ASM": [ + "ldr s2, [x5, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w20, w5, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x20]", + "ldr s3, [x5]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x0", + "add w21, w5, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "mov x21, #0xfffffffffffffff4", + "ldr s2, [x5, w21, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x5]", + "mov x22, #0xffffffffffffffe8", + "ldr s3, [x5, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w5, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "mov x23, #0xffffffffffffffdc", + "ldr s2, [x5, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "strb w20, [x28, #1017]", + "mov w23, #0x8", + "add w24, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x24]", + "ldr s3, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "sub w24, w5, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x24]", + "ldr s4, [x5]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x5, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w24, w5, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w24, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x24]", + "ldr s4, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x5]", + "ldr s5, [x5, w21, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldrb w24, [x28, #1019]", + "sub w24, w24, #0x4 (4)", + "and w24, w24, #0x7", + "strb w24, [x28, #1019]", + "add x0, x28, x24, lsl #4", + "str q5, [x0, #1040]", + "mov w25, #0x1", + "add w12, w24, #0x1 (1)", + "and w12, w12, #0x7", + "add x0, x28, x12, lsl #4", + "str q4, [x0, #1040]", + "add w12, w24, #0x2 (2)", + "and w12, w12, #0x7", + "add x0, x28, x12, lsl #4", + "str q3, [x0, #1040]", + "add w12, w24, #0x3 (3)", + "and w12, w12, #0x7", + "add x0, x28, x12, lsl #4", + "str q2, [x0, #1040]", + "sub w23, w23, w24", + "mov w24, #0xf0f", + "lsr w23, w24, w23", + "ldrb w24, [x28, #1298]", + "orr w23, w24, w23", + "strb w23, [x28, #1298]", + "ldrb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w23, #0x6 (6)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x4 (4)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x5, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w23, #0x6 (6)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x8 (8)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w23, #0x4 (4)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x8 (8)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add w24, w23, #0x3 (3)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w23, #0x2 (2)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "strb w20, [x28, #1017]", + "add w24, w8, #0x3c (60)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "ldr s2, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w23, #0x2 (2)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x38 (56)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add w24, w23, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add w24, w8, #0x40 (64)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w23, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "strb w20, [x28, #1017]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w23, #0x4 (4)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x4 (4)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x5, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w23, #0x4 (4)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x8 (8)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w23, #0x2 (2)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x8 (8)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add w24, w23, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add w24, w8, #0x48 (72)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "ldr s2, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w23, #0x2 (2)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x4c (76)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add w24, w23, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add w24, w8, #0x8 (8)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "mov w24, #0x7be0", + "movk w24, #0xa7, lsl #16", + "ldr d2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x44 (68)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "mov w24, #0x7bd8", + "movk w24, #0xa7, lsl #16", + "ldr d2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x48 (72)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "mov w24, #0x7bd0", + "movk w24, #0xa7, lsl #16", + "ldr d2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x4c (76)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add w24, w8, #0x8 (8)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add w24, w23, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "strb w20, [x28, #1017]", + "add w24, w8, #0x38 (56)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x4c (76)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add w24, w8, #0x8 (8)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add w24, w23, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "strb w20, [x28, #1017]", + "add w24, w8, #0x3c (60)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x48 (72)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add w24, w8, #0x8 (8)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "add w24, w23, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "strb w20, [x28, #1017]", + "add w24, w8, #0x40 (64)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x44 (68)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "mov w24, #0x7bc8", + "movk w24, #0xa7, lsl #16", + "ldr d2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x38 (56)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "mov w24, #0x7bc0", + "movk w24, #0xa7, lsl #16", + "ldr d2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x3c (60)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "mov w24, #0x7bb8", + "movk w24, #0xa7, lsl #16", + "ldr d2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x40 (64)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "mov w24, #0x7bb0", + "movk w24, #0xa7, lsl #16", + "ldr d2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x44 (68)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "mov w24, #0x7ba8", + "movk w24, #0xa7, lsl #16", + "ldr d2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x48 (72)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "mov w24, #0x7ba0", + "movk w24, #0xa7, lsl #16", + "ldr d2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x4c (76)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w25, w23", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "mov w24, #0x8000", + "fmov d2, x20", + "mov v2.d[1], x24", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w25, w23", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w12, w23, #0x2 (2)", + "and w12, w12, #0x7", + "add x0, x28, x12, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w12, w8, #0x58 (88)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w13, w25, w23", + "bic w12, w12, w13", + "strb w12, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "mov w12, #0x7b98", + "movk w12, #0xa7, lsl #16", + "ldr d2, [x12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w25, w23", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w12, w23, #0x1 (1)", + "and w12, w12, #0x7", + "add x0, x28, x12, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x12, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x12, lsl #4", + "str q2, [x0, #1040]", + "strb w20, [x28, #1017]", + "add w12, w8, #0x5c (92)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w13, w25, w23", + "bic w12, w12, w13", + "strb w12, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w25, w23", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "fmov d2, x20", + "mov v2.d[1], x24", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w25, w23", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "mov w12, #0x7b90", + "movk w12, #0xa7, lsl #16", + "ldr d2, [x12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w25, w23", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w12, w23, #0x1 (1)", + "and w12, w12, #0x7", + "add x0, x28, x12, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x12, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x12, lsl #4", + "str q2, [x0, #1040]", + "strb w20, [x28, #1017]", + "add w12, w8, #0x54 (84)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w13, w25, w23", + "bic w12, w12, w13", + "strb w12, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w12, w23, #0x1 (1)", + "and w12, w12, #0x7", + "add x0, x28, x12, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x12, lsl #4", + "str q2, [x0, #1040]", + "strb w20, [x28, #1017]", + "mov w12, #0x7b88", + "movk w12, #0xa7, lsl #16", + "ldr d2, [x12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w13, w8, #0x60 (96)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x13]", + "ldrb w13, [x28, #1298]", + "lsl w14, w25, w23", + "bic w13, w13, w14", + "strb w13, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w13, [x28, #1298]", + "lsl w14, w25, w23", + "orr w13, w13, w14", + "strb w13, [x28, #1298]", + "fmov d2, x20", + "mov v2.d[1], x24", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "mov w13, #0x7b80", + "movk w13, #0xa7, lsl #16", + "ldr d2, [x13]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w14, [x28, #1298]", + "lsl w15, w25, w23", + "orr w14, w14, w15", + "strb w14, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w14, w23, #0x1 (1)", + "and w14, w14, #0x7", + "add x0, x28, x14, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w14, w8, #0x50 (80)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x14]", + "ldrb w14, [x28, #1298]", + "lsl w15, w25, w23", + "bic w14, w14, w15", + "strb w14, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "mov w14, #0x7b78", + "movk w14, #0xa7, lsl #16", + "ldr d2, [x14]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w15, w8, #0x64 (100)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x15]", + "ldrb w15, [x28, #1298]", + "lsl w16, w25, w23", + "bic w15, w15, w16", + "strb w15, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w15, [x28, #1298]", + "lsl w16, w25, w23", + "orr w15, w15, w16", + "strb w15, [x28, #1298]", + "add w15, w8, #0x38 (56)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x15]", + "ldrb w15, [x28, #1298]", + "lsl w16, w25, w23", + "bic w15, w15, w16", + "strb w15, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w15, [x28, #1298]", + "lsl w16, w25, w23", + "orr w15, w15, w16", + "strb w15, [x28, #1298]", + "ldr d2, [x12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w15, w25, w23", + "orr w12, w12, w15", + "strb w12, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w12, w23, #0x1 (1)", + "and w12, w12, #0x7", + "add x0, x28, x12, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w12, w8, #0x3c (60)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w15, w25, w23", + "bic w12, w12, w15", + "strb w12, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w15, w25, w23", + "orr w12, w12, w15", + "strb w12, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w15, w25, w23", + "orr w12, w12, w15", + "strb w12, [x28, #1298]", + "add w12, w23, #0x4 (4)", + "and w12, w12, #0x7", + "add x0, x28, x12, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x12, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w15, w25, w23", + "bic w12, w12, w15", + "strb w12, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w12, w23, #0x3 (3)", + "and w12, w12, #0x7", + "add x0, x28, x12, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x12, lsl #4", + "str q2, [x0, #1040]", + "strb w20, [x28, #1017]", + "add w12, w8, #0x40 (64)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w15, w25, w23", + "bic w12, w12, w15", + "strb w12, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w12, w23, #0x2 (2)", + "and w12, w12, #0x7", + "add x0, x28, x12, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x12, lsl #4", + "str q2, [x0, #1040]", + "strb w20, [x28, #1017]", + "fmov d2, x20", + "mov v2.d[1], x24", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w12, w23, #0x3 (3)", + "and w12, w12, #0x7", + "add x0, x28, x12, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w4, w4, #0x18 (24)", + "add w5, w5, #0x4 (4)", + "mov x27, x6", + "subs w26, w6, #0x1 (1)", + "cfinv", + "mov x6, x26", + "add w12, w8, #0x44 (68)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w15, w25, w23", + "bic w12, w12, w15", + "strb w12, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add w12, w23, #0x1 (1)", + "and w12, w12, #0x7", + "add x0, x28, x12, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x12, lsl #4", + "str q2, [x0, #1040]", + "strb w20, [x28, #1017]", + "fmov d2, x20", + "mov v2.d[1], x24", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x12, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x12, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w15, w25, w23", + "bic w12, w12, w15", + "strb w12, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add w12, w8, #0x48 (72)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w15, w25, w23", + "bic w12, w12, w15", + "strb w12, [x28, #1298]", + "add w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w15, w25, w23", + "orr w12, w12, w15", + "strb w12, [x28, #1298]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w23, w23, #0x1 (1)", + "and w23, w23, #0x7", + "strb w23, [x28, #1019]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w15, w25, w23", + "orr w12, w12, w15", + "strb w12, [x28, #1298]", + "fmov d2, x20", + "mov v2.d[1], x24", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldr d2, [x13]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "add w20, w8, #0x4c (76)", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldrb w20, [x28, #1298]", + "lsl w24, w25, w23", + "bic w20, w20, w24", + "strb w20, [x28, #1298]", + "add w20, w23, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr d2, [x14]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x38 (56)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w25, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "mov x23, #0xffffffffffffffe4", + "ldr s2, [x4, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w25, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w23, w4, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w25, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x4, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w23, w25, w20", + "orr w22, w22, w23", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w22, w4, #0x18 (24)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w23, w25, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w23, w25, w20", + "orr w22, w22, w23", + "strb w22, [x28, #1298]", + "mov x22, #0xffffffffffffffec", + "ldr s2, [x4, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w22, w4, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w23, w25, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "mov x22, #0xfffffffffffffff0", + "ldr s2, [x4, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w23, w25, w20", + "orr w22, w22, w23", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w22, w4, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w23, w25, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x4, w21, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w21, w4, #0xc (12)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "mov x21, #0xfffffffffffffff8", + "ldr s2, [x4, w21, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w21, w4, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "mov x21, #0xfffffffffffffffc", + "ldr s2, [x4, w21, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w21, w4, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w4, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w4, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w4, #0xc (12)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w4, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w25, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "b.ne #+0x1c", + "ldr x0, pc+8", + "blr x0", + "unallocated (Unallocated)", + "udf #0x7f", + "unallocated (Unallocated)", + "udf #0x0" + ] + }, + "Block8": { + "ExpectedInstructionCount": 6645, + "x86Insts": [ + "movzx eax,word [esi + edx*0x8]", + "fld dword [esi + edx*0x8 + 0x4]", + "fstp dword [esp + 0x24]", + "mov esi,dword [esp + 0x1c8]", + "fld dword [esp + 0x9c]", + "movzx eax,ax", + "mov ecx,eax", + "imul ecx,dword [esp + 0x1e4]", + "lea eax,[eax + eax*0x2]", + "add eax,eax", + "add eax,eax", + "lea edi,[eax + esi*0x1 + 0x8]", + "mov dword [esp + 0x10],edi", + "fmul dword [eax + esi*0x1 + 0x4]", + "fld dword [esp + 0x98]", + "fmul dword [eax + esi*0x1]", + "faddp", + "fld dword [esp + 0xa0]", + "fmul dword [edi]", + "faddp", + "fadd dword [esp + 0x88]", + "fstp dword [esp + 0xd0]", + "fld dword [esp + 0xa8]", + "fmul dword [eax + esi*0x1 + 0x4]", + "fld dword [esp + 0xa4]", + "fmul dword [eax + esi*0x1]", + "faddp", + "fld dword [esp + 0xac]", + "fmul dword [edi]", + "faddp", + "fadd dword [esp + 0x8c]", + "fstp dword [esp + 0xd4]", + "fld dword [esp + 0xb4]", + "fmul dword [eax + esi*0x1 + 0x4]", + "fld dword [esp + 0xb0]", + "fmul dword [eax + esi*0x1]", + "mov esi,edi", + "faddp", + "fld dword [esp + 0xb8]", + "fmul dword [esi]", + "mov esi,dword [esp + 0x38]", + "lea edi,[esi + eax*0x1 + 0x8]", + "mov dword [esp + 0x10],edi", + "faddp", + "fadd dword [esp + 0x90]", + "fstp dword [esp + 0xd8]", + "fld dword [esp + 0x64]", + "fld st0", + "fmul dword [eax + ebx*0x1]", + "fld dword [esp + 0x68]", + "fld st0", + "fmul dword [eax + ebx*0x1 + 0x4]", + "faddp st2,st0", + "fld dword [esp + 0x6c]", + "fld st0", + "fmul dword [eax + ebx*0x1 + 0x8]", + "faddp st3,st0", + "fxch st2", + "fstp dword [esp + 0xe8]", + "fld dword [esp + 0x70]", + "fld st0", + "fmul dword [eax + ebx*0x1]", + "fld dword [esp + 0x74]", + "fld st0", + "fmul dword [eax + ebx*0x1 + 0x4]", + "faddp st2,st0", + "fld dword [esp + 0x78]", + "fmul dword [eax + ebx*0x1 + 0x8]", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0xec]", + "fld dword [esp + 0x7c]", + "fmul dword [eax + ebx*0x1]", + "fld dword [esp + 0x80]", + "fmul dword [eax + ebx*0x1 + 0x4]", + "faddp", + "fld dword [esp + 0x84]", + "fmul dword [eax + ebx*0x1 + 0x8]", + "faddp", + "fstp dword [esp + 0xf0]", + "fld st2", + "fmul dword [esi + eax*0x1 + 0x4]", + "fld st5", + "fmul dword [esi + eax*0x1]", + "faddp", + "fld st4", + "fmul dword [edi]", + "faddp", + "fstp dword [esp + 0x58]", + "fld st0", + "fmul dword [esi + eax*0x1 + 0x4]", + "fld st2", + "fmul dword [esi + eax*0x1]", + "faddp", + "fld dword [esp + 0x78]", + "fmul dword [edi]", + "faddp", + "fstp dword [esp + 0x5c]", + "fld dword [esp + 0x80]", + "fmul dword [esi + eax*0x1 + 0x4]", + "fld dword [esp + 0x7c]", + "fmul dword [esi + eax*0x1]", + "mov esi,edi", + "faddp", + "fld dword [esp + 0x84]", + "fmul dword [esi]", + "mov esi,dword [esp + 0x20]", + "lea edi,[esi + eax*0x1 + 0x4]", + "mov dword [esp + 0x10],edi", + "faddp", + "lea edi,[esi + eax*0x1 + 0x8]", + "mov dword [esp + 0xbc],edi", + "mov edi,dword [esp + 0x10]", + "fstp dword [esp + 0x60]", + "fld dword [esi + eax*0x1]", + "fmulp st5", + "fld dword [edi]", + "mov edi,dword [esp + 0xbc]", + "fmulp st3", + "fxch st4", + "faddp st2,st0", + "fld dword [edi]", + "mov edi,dword [esp + 0x10]", + "fmulp st3", + "fxch", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x4c]", + "fmul dword [esi + eax*0x1]", + "fld dword [edi]", + "mov edi,dword [esp + 0xbc]", + "fmulp st2", + "faddp", + "fld dword [esp + 0x78]", + "fmul dword [edi]", + "faddp", + "fstp dword [esp + 0x50]", + "fld dword [esp + 0x7c]", + "fmul dword [esi + eax*0x1]", + "mov eax,dword [esp + 0x10]", + "fld dword [esp + 0x80]", + "fmul dword [eax]", + "mov eax,dword [esp + 0x1d4]", + "faddp", + "fld dword [esp + 0x84]", + "fmul dword [edi]", + "faddp", + "fstp dword [esp + 0x54]", + "fld dword [esp + 0xd0]", + "fld dword [esp + 0x24]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0xc0]", + "fld dword [esp + 0xd4]", + "fmul st1", + "fstp dword [esp + 0xc4]", + "fld dword [esp + 0xd8]", + "fmul st1", + "fstp dword [esp + 0xc8]", + "fld dword [esp + 0xc0]", + "fadd dword [ecx + eax*0x1]", + "fstp dword [ecx + eax*0x1]", + "add edx,0x1", + "cmp edx,dword [esp + 0x1c]", + "fld dword [esp + 0xc4]", + "fadd dword [ecx + eax*0x1 + 0x4]", + "fstp dword [ecx + eax*0x1 + 0x4]", + "lea eax,[ecx + eax*0x1 + 0x8]", + "fld dword [eax]", + "fadd dword [esp + 0xc8]", + "fstp dword [eax]", + "mov eax,dword [esp + 0x1dc]", + "fld dword [esp + 0xe8]", + "fmul st1", + "fstp dword [esp + 0xdc]", + "fld dword [esp + 0xec]", + "fmul st1", + "fstp dword [esp + 0xe0]", + "fld dword [esp + 0xf0]", + "fmul st1", + "fstp dword [esp + 0xe4]", + "fld dword [esp + 0xdc]", + "fadd dword [ecx + ebp*0x1]", + "fstp dword [ecx + ebp*0x1]", + "fld dword [esp + 0xe0]", + "fadd dword [ecx + ebp*0x1 + 0x4]", + "fstp dword [ecx + ebp*0x1 + 0x4]", + "fld dword [esp + 0xe4]", + "fadd dword [ecx + ebp*0x1 + 0x8]", + "fstp dword [ecx + ebp*0x1 + 0x8]", + "fld dword [esp + 0x58]", + "fmul st1", + "fstp dword [esp + 0x3c]", + "fld dword [esp + 0x5c]", + "fmul st1", + "fstp dword [esp + 0x40]", + "fld dword [esp + 0x60]", + "fmul st1", + "fstp dword [esp + 0x44]", + "fld dword [ecx + eax*0x1]", + "fadd dword [esp + 0x3c]", + "fstp dword [ecx + eax*0x1]", + "fld dword [esp + 0x40]", + "fadd dword [ecx + eax*0x1 + 0x4]", + "fstp dword [ecx + eax*0x1 + 0x4]", + "lea eax,[ecx + eax*0x1 + 0x8]", + "fld dword [esp + 0x44]", + "fadd dword [eax]", + "fstp dword [eax]", + "mov eax,dword [esp + 0x1e0]", + "fld dword [esp + 0x4c]", + "fmul st1", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x50]", + "fmul st1", + "fstp dword [esp + 0x30]", + "fmul dword [esp + 0x54]", + "fstp dword [esp + 0x34]", + "fld dword [ecx + eax*0x1]", + "fadd dword [esp + 0x2c]", + "fstp dword [ecx + eax*0x1]", + "fld dword [esp + 0x30]", + "fadd dword [ecx + eax*0x1 + 0x4]", + "fstp dword [ecx + eax*0x1 + 0x4]", + "lea ecx,[ecx + eax*0x1 + 0x8]", + "fld dword [esp + 0x34]", + "fadd dword [ecx]", + "fstp dword [ecx]", + "jc 0x0072b180" + ], + "ExpectedArm64ASM": [ + "add w20, w10, w6, lsl #3", + "ldrh w4, [x20]", + "add w20, w10, #0x4 (4)", + "add w20, w20, w6, lsl #3", + "ldr s2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr w10, [x8, #456]", + "ldr s2, [x8, #156]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x5, x4", + "ldr w20, [x8, #484]", + "mul w5, w4, w20", + "add w4, w4, w4, lsl #1", + "add w4, w4, w4", + "add w4, w4, w4", + "add w20, w4, #0x8 (8)", + "add w11, w20, w10", + "str w11, [x8, #16]", + "add w20, w4, #0x4 (4)", + "add w20, w20, w10", + "ldr s3, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #152]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w20, w4, w10", + "ldr s4, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #160]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0xd0 (208)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #168]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w4, #0x4 (4)", + "add w20, w20, w10", + "ldr s3, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #164]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w20, w4, w10", + "ldr s4, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #172]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0xd4 (212)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #180]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w4, #0x4 (4)", + "add w20, w20, w10", + "ldr s3, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #176]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w20, w4, w10", + "ldr s4, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mov x10, x11", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #184]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w10, [x8, #56]", + "add w20, w10, #0x8 (8)", + "add w11, w20, w4", + "str w11, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #144]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0xd8 (216)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w4, w7", + "ldr s3, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w20, w4, #0x4 (4)", + "add w20, w20, w7", + "ldr s5, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s5, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w20, w4, #0x8 (8)", + "add w20, w20, w7", + "ldr s6, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mov w20, #0x0", + "add w21, w8, #0xe8 (232)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, w7", + "ldr s6, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w4, #0x4 (4)", + "add w21, w21, w7", + "ldr s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s8, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w4, #0x8 (8)", + "add w21, w21, w7", + "ldr s9, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0xec (236)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w4, w7", + "ldr s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s8, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w4, #0x4 (4)", + "add w21, w21, w7", + "ldr s9, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s8, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w4, #0x8 (8)", + "add w21, w21, w7", + "ldr s9, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0xf0 (240)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "add w21, w10, #0x4 (4)", + "add w21, w21, w4", + "ldr s6, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w10, w4", + "ldr s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s8, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "add w21, w10, #0x4 (4)", + "add w21, w21, w4", + "ldr s6, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w10, w4", + "ldr s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s8, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w10, #0x4 (4)", + "add w21, w21, w4", + "ldr s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s8, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w10, w4", + "ldr s9, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mov x10, x11", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s8, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr w10, [x8, #32]", + "add w21, w10, #0x4 (4)", + "add w11, w21, w4", + "str w11, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w10, #0x8 (8)", + "add w11, w21, w4", + "str w11, [x8, #188]", + "ldr w11, [x8, #16]", + "add w21, w8, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "add w21, w10, w4", + "ldr s6, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s6, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w11, [x8, #188]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s4, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w11, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w10, w4", + "ldr s2, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w11, [x8, #188]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w10, w4", + "ldr s3, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x8, #16]", + "ldr s3, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x8, #468]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #208]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "strb w20, [x28, #1017]", + "add w20, w8, #0xc0 (192)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #212]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0xc4 (196)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #216]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0xc8 (200)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #192]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w5, w4", + "ldr s4, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w5, w4", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "mov w20, #0x1", + "add w6, w6, #0x1 (1)", + "ldr w21, [x8, #28]", + "ldr s2, [x8, #196]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, #0x4 (4)", + "add w22, w22, w4", + "ldr s4, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, #0x4 (4)", + "add w22, w22, w4", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "add w22, w5, #0x8 (8)", + "add w4, w22, w4", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s4, [x8, #200]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x8, #476]", + "ldr s2, [x8, #232]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0xdc (220)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #236]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0xe0 (224)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #240]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0xe4 (228)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #220]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, w9", + "ldr s4, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, w9", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #224]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, #0x4 (4)", + "add w22, w22, w9", + "ldr s4, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, #0x4 (4)", + "add w22, w22, w9", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #228]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, #0x8 (8)", + "add w22, w22, w9", + "ldr s4, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, #0x8 (8)", + "add w22, w22, w9", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "add w22, w5, w4", + "ldr s2, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s4, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, w4", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, #0x4 (4)", + "add w22, w22, w4", + "ldr s4, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, #0x4 (4)", + "add w22, w22, w4", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "add w22, w5, #0x8 (8)", + "add w4, w22, w4", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s4, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x8, #480]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w8, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "add w22, w5, w4", + "ldr s2, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, w4", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, #0x4 (4)", + "add w22, w22, w4", + "ldr s3, [x22]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w22, w5, #0x4 (4)", + "add w22, w22, w4", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "add w22, w5, #0x8 (8)", + "add w5, w22, w4", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x5]", + "eor w27, w6, w21", + "subs w26, w6, w21", + "cfinv", + "ldrb w21, [x28, #1019]", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldrb w22, [x28, #1298]", + "lsl w20, w20, w21", + "bic w20, w22, w20", + "strb w20, [x28, #1298]", + "b.hs #+0x1c", + "ldr x0, pc+8", + "blr x0", + "unallocated (Unallocated)", + "udf #0x7f", + "unallocated (Unallocated)", + "udf #0x0" + ] + }, + "Block9": { + "ExpectedInstructionCount": 251, + "x86Insts": [ + "fld dword [edi]", + "fmul st0", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0xc]", + "fadd qword [0x00a2f928]", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0xc]", + "call 0x00982c30", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0xc]", + "lea ecx,[esp + 0x10]", + "fld1", + "push ecx", + "fdivrp", + "lea edx,[esp + 0x50]", + "push edx", + "lea ecx,[esp + 0x7c]", + "fstp dword [esp + 0x10]", + "fld dword [edi]", + "fchs", + "fld dword [esp + 0x10]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x3c]", + "fmul st1", + "fstp dword [esp + 0x6c]", + "fld dword [esp + 0x40]", + "fmul st1", + "fstp dword [esp + 0x70]", + "fmul dword [esp + 0x44]", + "fstp dword [esp + 0x74]", + "fld dword [esp + 0x30]", + "fld dword [esp + 0x10]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x60]", + "fld dword [esp + 0x34]", + "fmul st1", + "fstp dword [esp + 0x64]", + "fmul dword [esp + 0x38]", + "fstp dword [esp + 0x68]", + "fld dword [esp + 0x60]", + "fadd dword [esp + 0x6c]", + "fstp dword [esp + 0x54]", + "fld dword [esp + 0x64]", + "fadd dword [esp + 0x70]", + "fstp dword [esp + 0x58]", + "fld dword [esp + 0x68]", + "fadd dword [esp + 0x74]", + "fstp dword [esp + 0x5c]", + "call 0x00716e00", + "mov ecx,dword [eax]", + "mov dword [esi + 0x20],ecx", + "mov edx,dword [eax + 0x4]", + "mov dword [esi + 0x24],edx", + "mov ecx,dword [eax + 0x8]", + "mov dword [esi + 0x28],ecx", + "mov edx,dword [eax + 0xc]", + "mov dword [esi + 0x2c],edx", + "fld dword [edi + 0x4]", + "fmul st0", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0xc]", + "fadd qword [0x00a2f928]", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0xc]", + "call 0x00982c30", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0xc]", + "fld1", + "fdivrp", + "fstp dword [esp + 0x8]", + "fld dword [edi + 0x4]", + "fld dword [esp + 0x8]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x8]", + "fchs", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0x34]", + "fld dword [esp + 0xc]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x58]", + "fld dword [esp + 0x38]", + "fmul st1", + "fstp dword [esp + 0x5c]", + "fmul dword [esp + 0x3c]", + "fstp dword [esp + 0x60]", + "fld dword [esp + 0x28]", + "fld dword [esp + 0x8]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x64]", + "fld dword [esp + 0x2c]", + "fmul st1", + "fstp dword [esp + 0x68]", + "fmul dword [esp + 0x30]", + "fstp dword [esp + 0x6c]", + "fld dword [esp + 0x64]", + "fadd dword [esp + 0x58]", + "fstp dword [esp + 0x74]", + "mov eax,dword [esp + 0x74]", + "fld dword [esp + 0x68]", + "mov dword [esp + 0x4c],eax", + "fadd dword [esp + 0x5c]", + "lea eax,[esp + 0x10]", + "push eax", + "fstp dword [esp + 0x7c]", + "mov ecx,dword [esp + 0x7c]", + "fld dword [esp + 0x70]", + "mov dword [esp + 0x54],ecx", + "fadd dword [esp + 0x64]", + "lea ecx,[esp + 0x50]", + "push ecx", + "lea ecx,[esp + 0x7c]", + "fstp dword [esp + 0x84]", + "mov edx,dword [esp + 0x84]", + "mov dword [esp + 0x5c],edx", + "call 0x00716e00", + "mov edx,dword [eax]", + "mov dword [esi + 0x30],edx", + "mov ecx,dword [eax + 0x4]", + "mov dword [esi + 0x34],ecx", + "mov edx,dword [eax + 0x8]", + "mov dword [esi + 0x38],edx", + "mov eax,dword [eax + 0xc]", + "mov dword [esi + 0x3c],eax", + "fld dword [edi + 0x8]", + "fmul st0", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0xc]", + "fadd qword [0x00a2f928]", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0xc]", + "call 0x00982c30", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0xc]", + "fld1", + "fdivrp", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x8]", + "fld st0", + "fmul dword [edi + 0x8]", + "fstp dword [esp + 0x8]", + "fchs", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0x40]", + "fld dword [esp + 0xc]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x64]", + "fld dword [esp + 0x44]", + "fmul st1", + "fstp dword [esp + 0x68]", + "fmul dword [esp + 0x48]", + "fstp dword [esp + 0x6c]", + "fld dword [esp + 0x28]", + "fld dword [esp + 0x8]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x74]", + "fld dword [esp + 0x2c]", + "fmul st1", + "fstp dword [esp + 0x78]", + "fmul dword [esp + 0x30]", + "fstp dword [esp + 0x7c]", + "fld dword [esp + 0x74]", + "fadd dword [esp + 0x64]", + "fstp dword [esp + 0x58]", + "mov ecx,dword [esp + 0x58]", + "fld dword [esp + 0x78]", + "mov dword [esp + 0x4c],ecx", + "fadd dword [esp + 0x68]", + "lea ecx,[esp + 0x10]", + "push ecx", + "lea ecx,[esp + 0x78]", + "fstp dword [esp + 0x60]", + "mov edx,dword [esp + 0x60]", + "fld dword [esp + 0x80]", + "mov dword [esp + 0x54],edx", + "fadd dword [esp + 0x70]", + "lea edx,[esp + 0x50]", + "push edx", + "fstp dword [esp + 0x68]", + "mov eax,dword [esp + 0x68]", + "mov dword [esp + 0x5c],eax", + "call 0x00716e00", + "mov ecx,dword [eax]", + "mov dword [esi + 0x40],ecx", + "mov edx,dword [eax + 0x4]", + "mov dword [esi + 0x44],edx", + "mov ecx,dword [eax + 0x8]", + "mov dword [esi + 0x48],ecx", + "mov edx,dword [eax + 0xc]", + "mov dword [esi + 0x4c],edx", + "fld dword [edi + 0xc]", + "fmul st0", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0xc]", + "fadd qword [0x00a2f928]", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0xc]", + "call 0x00982c30", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0xc]", + "fld1", + "fdivrp", + "fstp dword [esp + 0x8]", + "fld dword [edi + 0xc]", + "fchs", + "fld dword [esp + 0x8]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x40]", + "fmul st1", + "fstp dword [esp + 0x64]", + "fld dword [esp + 0x44]", + "fmul st1", + "fstp dword [esp + 0x68]", + "fmul dword [esp + 0x48]", + "fstp dword [esp + 0x6c]", + "fld dword [esp + 0x28]", + "fld dword [esp + 0x8]", + "fld st0", + "fmulp st2", + "fxch", + "fstp dword [esp + 0x74]", + "fld dword [esp + 0x2c]", + "fmul st1", + "fstp dword [esp + 0x78]", + "fmul dword [esp + 0x30]", + "fstp dword [esp + 0x7c]", + "fld dword [esp + 0x74]", + "fadd dword [esp + 0x64]", + "fstp dword [esp + 0x58]", + "mov eax,dword [esp + 0x58]", + "fld dword [esp + 0x78]", + "mov dword [esp + 0x4c],eax", + "fadd dword [esp + 0x68]", + "lea eax,[esp + 0x10]", + "fstp dword [esp + 0x5c]", + "mov ecx,dword [esp + 0x5c]", + "fld dword [esp + 0x7c]", + "mov dword [esp + 0x50],ecx", + "fadd dword [esp + 0x6c]", + "lea ecx,[esp + 0x4c]", + "fstp dword [esp + 0x60]", + "mov edx,dword [esp + 0x60]", + "mov dword [esp + 0x54],edx" + ], + "ExpectedArm64ASM": [ + "ldr s2, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0xf928", + "movk w20, #0xa2, lsl #16", + "ldr d3, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "mov v0.8b, v3.8b", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1432]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x5003", + "movk w20, #0x1, lsl #16", + "mov w21, #0x2c11", + "movk w21, #0x98, lsl #16", + "add w21, w20, w21", + "str w20, [x8, #-4]!", + "ldrb w20, [x28, #1019]", + "mov w22, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w20, w22, w20", + "orr w20, w23, w20", + "strb w20, [x28, #1298]", + "ldr x0, [x28, #2304]", + "and x3, x21, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block10": { + "ExpectedInstructionCount": 1085, + "x86Insts": [ + "fld dword [0x00b42a74]", + "push ecx", + "fstp dword [0x00b42a20]", + "lea ecx,[esp + 0x48]", + "fld dword [0x00b42a78]", + "fstp dword [0x00b42a24]", + "fld dword [0x00b42a7c]", + "fstp dword [0x00b42a28]", + "fld dword [0x00b42a68]", + "fstp dword [0x00b42a2c]", + "fld dword [0x00b42a6c]", + "fstp dword [0x00b42a30]", + "fld dword [0x00b42a70]", + "fstp dword [0x00b42a34]", + "fld dword [0x00b42a5c]", + "fstp dword [0x00b42a38]", + "fld dword [0x00b42a60]", + "fstp dword [0x00b42a3c]", + "fld dword [0x00b42a64]", + "fstp dword [0x00b42a40]", + "fld dword [0x00b42a50]", + "fstp dword [0x00b42a44]", + "fld dword [0x00b42a54]", + "fstp dword [0x00b42a48]", + "fld dword [0x00b42a58]", + "fstp dword [0x00b42a4c]", + "fst dword [esp + 0x48]", + "fst dword [esp + 0x58]", + "fstp dword [esp + 0x68]", + "fst dword [esp + 0x4c]", + "fst dword [esp + 0x50]", + "fst dword [esp + 0x54]", + "fst dword [esp + 0x5c]", + "fst dword [esp + 0x60]", + "fstp dword [esp + 0x64]", + "fld dword [esp + 0x4]", + "fstp dword [esp]", + "call 0x00793aa0", + "fld dword [esp + 0x50]", + "fld dword [0x00b42a78]", + "fst qword [esp + 0x28]", + "fld dword [0x00b42a74]", + "fst qword [esp + 0x30]", + "fld dword [esp + 0x44]", + "fld dword [esp + 0x5c]", + "fld dword [0x00b42a7c]", + "fst qword [esp + 0x10]", + "fld st2", + "fmul st4", + "fld st6", + "fmul st6", + "faddp", + "fld st2", + "fmulp st2", + "faddp", + "fstp dword [esp + 0x38]", + "fld dword [esp + 0x54]", + "fld dword [esp + 0x48]", + "fld dword [esp + 0x60]", + "fstp qword [esp]", + "fld st0", + "fmulp st5", + "fld st1", + "fmulp st6", + "fxch st4", + "faddp st5,st0", + "fld qword [esp]", + "fmul qword [esp + 0x10]", + "faddp st5,st0", + "fxch st4", + "fstp dword [esp + 0x3c]", + "fld dword [esp + 0x58]", + "fst qword [esp + 0x20]", + "fld dword [esp + 0x4c]", + "fst qword [esp + 0x18]", + "fld dword [esp + 0x64]", + "fstp qword [esp + 0x8]", + "fmul qword [esp + 0x30]", + "fxch", + "fmul qword [esp + 0x28]", + "faddp", + "fld qword [esp + 0x8]", + "mov eax,dword [esp + 0x38]", + "fmul qword [esp + 0x10]", + "mov ecx,dword [esp + 0x3c]", + "mov [0x00b2ba7c],eax", + "mov dword [0x00b2ba80],ecx", + "faddp", + "fstp dword [esp + 0x40]", + "mov edx,dword [esp + 0x40]", + "fld dword [0x00b42a6c]", + "mov dword [0x00b2ba84],edx", + "fst qword [esp + 0x30]", + "fld dword [0x00b42a68]", + "fst qword [esp + 0x28]", + "fld dword [0x00b42a70]", + "fstp qword [esp + 0x10]", + "fmul st3", + "fld st6", + "fmulp st2", + "faddp", + "fld st1", + "fmul qword [esp + 0x10]", + "faddp", + "fstp dword [esp + 0x38]", + "mov eax,dword [esp + 0x38]", + "fld st2", + "mov [0x00b2ba88],eax", + "fmul qword [esp + 0x28]", + "fld st4", + "fmul qword [esp + 0x30]", + "faddp", + "fld qword [esp]", + "fmul qword [esp + 0x10]", + "faddp", + "fstp dword [esp + 0x3c]", + "mov ecx,dword [esp + 0x3c]", + "fld qword [esp + 0x18]", + "mov dword [0x00b2ba8c],ecx", + "fmul qword [esp + 0x28]", + "fld qword [esp + 0x20]", + "fmul qword [esp + 0x30]", + "faddp", + "fld qword [esp + 0x8]", + "fmul qword [esp + 0x10]", + "faddp", + "fstp dword [esp + 0x40]", + "mov edx,dword [esp + 0x40]", + "fld dword [0x00b42a60]", + "mov dword [0x00b2ba90],edx", + "fst qword [esp + 0x28]", + "fld dword [0x00b42a5c]", + "fst qword [esp + 0x30]", + "fld dword [0x00b42a64]", + "fstp qword [esp + 0x10]", + "fmul st3", + "fld st6", + "fmulp st2", + "faddp", + "fld st1", + "fmul qword [esp + 0x10]", + "faddp", + "fstp dword [esp + 0x38]", + "mov eax,dword [esp + 0x38]", + "fld st2", + "fmul qword [esp + 0x30]", + "fld st4", + "fmul qword [esp + 0x28]", + "faddp", + "fld qword [esp]", + "fmul qword [esp + 0x10]", + "faddp", + "fstp dword [esp + 0x3c]", + "fld qword [esp + 0x18]", + "fmul qword [esp + 0x30]", + "fld qword [esp + 0x20]", + "fmul qword [esp + 0x28]", + "faddp", + "fld qword [esp + 0x8]", + "fmul qword [esp + 0x10]", + "faddp", + "fstp dword [esp + 0x40]", + "fld dword [0x00b42a54]", + "mov ecx,dword [esp + 0x3c]", + "fld dword [0x00b42a50]", + "mov edx,dword [esp + 0x40]", + "fld dword [0x00b42a58]", + "mov [0x00b2ba94],eax", + "fxch st4", + "mov dword [0x00b2ba98],ecx", + "fmul st1", + "mov dword [0x00b2ba9c],edx", + "fxch st7", + "fmul st2", + "faddp st7,st0", + "fxch st2", + "fmul st3", + "faddp st6,st0", + "fxch st5", + "fstp dword [esp + 0x38]", + "mov eax,dword [esp + 0x38]", + "mov [0x00b2baa0],eax", + "fmul st2", + "fxch st3", + "fmul st4", + "faddp st2,st0", + "fld qword [esp]", + "fmul st1", + "faddp st2,st0", + "fxch", + "fstp dword [esp + 0x3c]", + "mov ecx,dword [esp + 0x3c]", + "fld qword [esp + 0x18]", + "mov dword [0x00b2baa4],ecx", + "fmulp st2", + "fld qword [esp + 0x20]", + "fmulp st3", + "fxch", + "faddp st2,st0", + "fmul qword [esp + 0x8]", + "faddp", + "fstp dword [esp + 0x40]", + "mov edx,dword [esp + 0x40]", + "mov dword [0x00b2baa8],edx", + "mov esp,ebp", + "pop ebp", + "ret" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x2a74", + "movk w20, #0xb4, lsl #16", + "ldr s2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str w5, [x8, #-4]!", + "mov w20, #0x2a20", + "movk w20, #0xb4, lsl #16", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "add w5, w8, #0x48 (72)", + "mov w20, #0x2a78", + "movk w20, #0xb4, lsl #16", + "ldr s2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x2a24", + "movk w20, #0xb4, lsl #16", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "mov w20, #0x2a7c", + "movk w20, #0xb4, lsl #16", + "ldr s2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x2a28", + "movk w20, #0xb4, lsl #16", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "mov w20, #0x2a68", + "movk w20, #0xb4, lsl #16", + "ldr s2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x2a2c", + "movk w20, #0xb4, lsl #16", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "mov w20, #0x2a6c", + "movk w20, #0xb4, lsl #16", + "ldr s2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x2a30", + "movk w20, #0xb4, lsl #16", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "mov w20, #0x2a70", + "movk w20, #0xb4, lsl #16", + "ldr s2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x2a34", + "movk w20, #0xb4, lsl #16", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "mov w20, #0x2a5c", + "movk w20, #0xb4, lsl #16", + "ldr s2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x2a38", + "movk w20, #0xb4, lsl #16", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "mov w20, #0x2a60", + "movk w20, #0xb4, lsl #16", + "ldr s2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x2a3c", + "movk w20, #0xb4, lsl #16", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "mov w20, #0x2a64", + "movk w20, #0xb4, lsl #16", + "ldr s2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x2a40", + "movk w20, #0xb4, lsl #16", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "mov w20, #0x2a50", + "movk w20, #0xb4, lsl #16", + "ldr s2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x2a44", + "movk w20, #0xb4, lsl #16", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "mov w20, #0x2a54", + "movk w20, #0xb4, lsl #16", + "ldr s2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x2a48", + "movk w20, #0xb4, lsl #16", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "mov w20, #0x2a58", + "movk w20, #0xb4, lsl #16", + "ldr s2, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w20, #0x2a4c", + "movk w20, #0xb4, lsl #16", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "add w20, w8, #0x48 (72)", + "ldrb w21, [x28, #1019]", + "add w22, w21, #0x7 (7)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1298]", + "mov w24, #0x1", + "lsl w22, w24, w22", + "bic w22, w23, w22", + "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "add w20, w8, #0x58 (88)", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "add w20, w8, #0x68 (104)", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldrb w20, [x28, #1298]", + "lsl w22, w24, w21", + "bic w20, w20, w22", + "strb w20, [x28, #1298]", + "add w20, w21, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w8, #0x4c (76)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w8, #0x50 (80)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w8, #0x54 (84)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w8, #0x5c (92)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w8, #0x60 (96)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w8, #0x64 (100)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w24, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w24, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x8]", + "ldrb w21, [x28, #1298]", + "lsl w22, w24, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "mov w20, #0x54ca", + "movk w20, #0x1, lsl #16", + "mov w21, #0x39db", + "movk w21, #0x79, lsl #16", + "add w21, w20, w21", + "str w20, [x8, #-4]!", + "ldr x0, [x28, #2304]", + "and x3, x21, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json new file mode 100644 index 0000000000..c1209613b7 --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json @@ -0,0 +1,98715 @@ +{ + "Features": { + "Bitness": 32, + "EnabledHostFeatures": [ + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256", + "AFP" + ] + }, + "Instructions": { + "Block1": { + "ExpectedInstructionCount": 16349, + "x86Insts": [ + "sub esp,0x88", + "fld dword [ecx + 0x4]", + "mov edx,dword [ecx + 0x18]", + "fld dword [ecx + 0x10]", + "mov dword [esp + 0x14],edx", + "fld dword [ecx + 0x14]", + "mov edx,dword [ecx + 0x1c]", + "fld dword [ecx + 0x20]", + "mov dword [esp + 0x10],edx", + "fld dword [ecx + 0x24]", + "fld dword [eax]", + "fsub dword [eax + 0x44]", + "fld dword [eax + 0x40]", + "fadd dword [eax + 0x4]", + "fld dword [eax + 0x20]", + "fsub dword [eax + 0x64]", + "fstp dword [esp + 0x8]", + "fld dword [eax + 0x24]", + "fadd dword [eax + 0x60]", + "fstp dword [esp]", + "fld dword [esp + 0x8]", + "fsub dword [esp]", + "fmul st7", + "fstp dword [esp + 0x4]", + "fld dword [esp]", + "fadd dword [esp + 0x8]", + "fmul st7", + "fstp dword [esp]", + "fld dword [esp + 0x4]", + "fadd st0,st2", + "fstp dword [esp + 0x80]", + "fld dword [esp]", + "fadd st0,st1", + "fstp dword [esp + 0x78]", + "fxch", + "fsub dword [esp + 0x4]", + "fstp dword [esp + 0x60]", + "fsub dword [esp]", + "fstp dword [esp + 0x40]", + "fld dword [eax + 0x44]", + "fadd dword [eax]", + "fld dword [eax + 0x4]", + "fsub dword [eax + 0x40]", + "fld dword [eax + 0x64]", + "fadd dword [eax + 0x20]", + "fstp dword [esp + 0x8]", + "fld dword [eax + 0x24]", + "fsub dword [eax + 0x60]", + "fstp dword [esp]", + "fld dword [esp + 0x8]", + "fsub dword [esp]", + "fmul st7", + "fstp dword [esp + 0x4]", + "fld dword [esp]", + "fadd dword [esp + 0x8]", + "fmul st7", + "fstp dword [esp]", + "fld st1", + "fsub dword [esp]", + "fstp dword [esp + 0x24]", + "fld dword [esp + 0x4]", + "fadd st0,st1", + "fstp dword [esp + 0x34]", + "fld dword [esp]", + "fadd st0,st2", + "fstp dword [esp + 0x5c]", + "fsub dword [esp + 0x4]", + "fstp dword [esp + 0x64]", + "fstp st0", + "fld dword [eax + 0x8]", + "fsub dword [eax + 0x4c]", + "fld dword [eax + 0xc]", + "fadd dword [eax + 0x48]", + "fstp dword [esp]", + "fld st0", + "fmul st5", + "fld dword [esp]", + "fmul st5", + "fsubp", + "fstp dword [esp + 0xc]", + "fmul st3", + "fld dword [esp]", + "fmul st5", + "faddp", + "fstp dword [esp + 0x8]", + "fld dword [eax + 0x28]", + "fsub dword [eax + 0x6c]", + "fld dword [eax + 0x2c]", + "fadd dword [eax + 0x68]", + "fstp dword [esp]", + "fld dword [esp + 0x10]", + "fmul st1", + "fld dword [esp]", + "fmul dword [esp + 0x14]", + "fsubp", + "fstp dword [esp + 0x4]", + "fld dword [esp]", + "fmul dword [esp + 0x10]", + "fxch", + "fmul dword [esp + 0x14]", + "faddp", + "fstp dword [esp]", + "fld dword [esp + 0x4]", + "fadd dword [esp + 0xc]", + "fstp dword [esp + 0x58]", + "fld dword [esp]", + "fadd dword [esp + 0x8]", + "fstp dword [esp + 0x30]", + "fld dword [esp + 0xc]", + "fsub dword [esp + 0x4]", + "fstp dword [esp + 0x68]", + "fld dword [esp + 0x8]", + "fsub dword [esp]", + "fstp dword [esp + 0x50]", + "fld dword [eax + 0x4c]", + "fadd dword [eax + 0x8]", + "fld dword [eax + 0xc]", + "fsub dword [eax + 0x48]", + "fstp dword [esp]", + "fld dword [esp + 0x14]", + "fmul st1", + "fld dword [esp]", + "fmul dword [esp + 0x10]", + "fsubp", + "fstp dword [esp + 0xc]", + "fmul dword [esp + 0x10]", + "fld dword [esp]", + "fmul dword [esp + 0x14]", + "faddp", + "fstp dword [esp + 0x8]", + "fld dword [eax + 0x6c]", + "fadd dword [eax + 0x28]", + "fld dword [eax + 0x2c]", + "fsub dword [eax + 0x68]", + "fst dword [esp]", + "fmul st4", + "fld st1", + "fmul st6", + "faddp", + "fstp dword [esp + 0x4]", + "fld dword [esp]", + "fmul st5", + "fxch", + "fmul st4", + "fsubp", + "fstp dword [esp]", + "fld dword [esp + 0xc]", + "fsub dword [esp + 0x4]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x8]", + "fsub dword [esp]", + "fstp dword [esp + 0x4c]", + "fld dword [esp + 0x4]", + "fadd dword [esp + 0xc]", + "fstp dword [esp + 0x74]", + "fld dword [esp]", + "fadd dword [esp + 0x8]", + "fstp dword [esp + 0x84]", + "fld dword [eax + 0x10]", + "fsub dword [eax + 0x54]", + "fld dword [eax + 0x14]", + "fadd dword [eax + 0x50]", + "fstp dword [esp]", + "fld st0", + "fmul st3", + "fld dword [esp]", + "fmul st3", + "fsubp", + "fstp dword [esp + 0xc]", + "fmul st1", + "fld dword [esp]", + "fmul st3", + "faddp", + "fstp dword [esp + 0x8]", + "fld dword [eax + 0x30]", + "fsub dword [eax + 0x74]", + "fld dword [eax + 0x34]", + "fadd dword [eax + 0x70]", + "fstp dword [esp]", + "fld st0", + "fmul st2", + "fld dword [esp]", + "fmul st4", + "fsubp", + "fstp dword [esp + 0x4]", + "fld dword [esp]", + "fmul st2", + "fxch", + "fmul st3", + "faddp", + "fstp dword [esp]", + "fld dword [esp + 0x4]", + "fadd dword [esp + 0xc]", + "fstp dword [esp + 0x20]", + "fld dword [esp]", + "fadd dword [esp + 0x8]", + "fstp dword [esp + 0x28]", + "fld dword [esp + 0xc]", + "fsub dword [esp + 0x4]", + "fstp dword [esp + 0x18]", + "fld dword [esp + 0x8]", + "fsub dword [esp]", + "fstp dword [esp + 0x38]", + "fld dword [eax + 0x54]", + "fadd dword [eax + 0x10]", + "fld dword [eax + 0x14]", + "fsub dword [eax + 0x50]", + "fstp dword [esp]", + "fld st0", + "fmul st2", + "fld dword [esp]", + "fmul st4", + "fsubp", + "fstp dword [esp + 0xc]", + "fld dword [esp]", + "fmul st2", + "fxch", + "fmul st3", + "faddp", + "fstp dword [esp + 0x8]", + "fld dword [eax + 0x74]", + "fadd dword [eax + 0x30]", + "fld dword [eax + 0x34]", + "fsub dword [eax + 0x70]", + "fstp dword [esp]", + "fld st0", + "fmul st3", + "fld dword [esp]", + "fmul st3", + "fsubp", + "fstp dword [esp + 0x4]", + "fmul st1", + "fld dword [esp]", + "fmul st3", + "faddp", + "fstp dword [esp]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0xc]", + "fsub dword [esp + 0x4]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x8]", + "fsub dword [esp]", + "fstp dword [esp + 0x3c]", + "fld dword [esp + 0x4]", + "fadd dword [esp + 0xc]", + "fstp dword [esp + 0x6c]", + "fld dword [esp]", + "fadd dword [esp + 0x8]", + "fstp dword [esp + 0x54]", + "fld dword [eax + 0x18]", + "fsub dword [eax + 0x5c]", + "fld dword [eax + 0x1c]", + "fadd dword [eax + 0x58]", + "fld st1", + "fmul dword [esp + 0x14]", + "fld st1", + "fmul dword [esp + 0x10]", + "fsubp", + "fstp dword [esp + 0xc]", + "fxch", + "fmul dword [esp + 0x10]", + "fxch", + "fmul dword [esp + 0x14]", + "faddp", + "fld dword [eax + 0x38]", + "fsub dword [eax + 0x7c]", + "fld dword [eax + 0x78]", + "fadd dword [eax + 0x3c]", + "fld st1", + "fmul st4", + "fld st1", + "fmul st6", + "fsubp", + "fstp dword [esp + 0x4]", + "fmul st3", + "fxch", + "fmul st4", + "faddp", + "fstp dword [esp]", + "fld dword [esp + 0x4]", + "fadd dword [esp + 0xc]", + "fstp dword [esp + 0x8]", + "fld dword [esp]", + "fadd st0,st1", + "fstp dword [esp + 0x70]", + "fld dword [esp + 0xc]", + "fsub dword [esp + 0x4]", + "fstp dword [esp + 0x1c]", + "fsub dword [esp]", + "fstp dword [esp + 0x48]", + "fld dword [eax + 0x5c]", + "fadd dword [eax + 0x18]", + "fld dword [eax + 0x1c]", + "fsub dword [eax + 0x58]", + "fld st1", + "fmul st3", + "fld st1", + "fmul st5", + "faddp", + "fstp dword [esp + 0xc]", + "fmul st2", + "fxch", + "fmul st3", + "fsubp", + "fstp st2", + "fstp st0", + "fld dword [eax + 0x7c]", + "fadd dword [eax + 0x38]", + "fld dword [eax + 0x3c]", + "fsub dword [eax + 0x78]", + "fld st1", + "fmul dword [esp + 0x10]", + "fld st1", + "fmul dword [esp + 0x14]", + "fsubp", + "fstp dword [esp + 0x4]", + "fmul dword [esp + 0x10]", + "fxch", + "fmul dword [esp + 0x14]", + "faddp", + "fld dword [esp + 0x4]", + "fadd dword [esp + 0xc]", + "fstp dword [esp + 0x14]", + "fld st0", + "fadd st0,st2", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0xc]", + "fsub dword [esp + 0x4]", + "fstp dword [esp + 0x7c]", + "fsubp", + "fld dword [esp + 0x20]", + "fadd dword [esp + 0x80]", + "fld dword [esp + 0x28]", + "fadd dword [esp + 0x78]", + "fld dword [esp + 0x8]", + "fadd dword [esp + 0x58]", + "fld dword [esp + 0x70]", + "fadd dword [esp + 0x30]", + "fstp dword [esp]", + "fld st0", + "fadd st0,st3", + "fstp dword [eax]", + "fld dword [esp]", + "fadd st0,st2", + "fstp dword [eax + 0x4]", + "fxch st2", + "fsub st0,st2", + "fstp dword [eax + 0x8]", + "fstp st1", + "fsub dword [esp]", + "fstp dword [eax + 0xc]", + "fld dword [esp + 0x80]", + "fsub dword [esp + 0x20]", + "fld dword [esp + 0x78]", + "fsub dword [esp + 0x28]", + "fld dword [esp + 0x58]", + "fsub dword [esp + 0x8]", + "fld dword [esp + 0x30]", + "fsub dword [esp + 0x70]", + "fld st3", + "fsub st0,st1", + "fstp dword [eax + 0x10]", + "fld st1", + "fadd st0,st3", + "fstp dword [eax + 0x14]", + "fadd st0,st3", + "fstp dword [eax + 0x18]", + "fxch", + "fsub st0,st1", + "fstp dword [eax + 0x1c]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x60]", + "fsub dword [esp + 0x38]", + "fld dword [esp + 0x18]", + "fadd dword [esp + 0x40]", + "fld dword [esp + 0x68]", + "fsub dword [esp + 0x48]", + "fld dword [esp + 0x1c]", + "fadd dword [esp + 0x50]", + "fld st1", + "fsub st0,st1", + "fmul st6", + "fstp dword [esp + 0x4]", + "faddp", + "fmul st4", + "fld dword [esp + 0x4]", + "fadd st0,st3", + "fstp dword [eax + 0x20]", + "fld st0", + "fadd st0,st2", + "fstp dword [eax + 0x24]", + "fxch st2", + "fsub dword [esp + 0x4]", + "fstp dword [eax + 0x28]", + "fsub st0,st1", + "fstp dword [eax + 0x2c]", + "fstp st0", + "fld dword [esp + 0x38]", + "fadd dword [esp + 0x60]", + "fld dword [esp + 0x40]", + "fsub dword [esp + 0x18]", + "fld dword [esp + 0x48]", + "fadd dword [esp + 0x68]", + "fld dword [esp + 0x50]", + "fsub dword [esp + 0x1c]", + "fld st1", + "fsub st0,st1", + "fmul st6", + "fstp dword [esp + 0x4]", + "faddp", + "fmul st4", + "fld st2", + "fsub st0,st1", + "fstp dword [eax + 0x30]", + "fld dword [esp + 0x4]", + "fadd st0,st2", + "fstp dword [eax + 0x34]", + "fadd st0,st2", + "fstp dword [eax + 0x38]", + "fsub dword [esp + 0x4]", + "fstp dword [eax + 0x3c]", + "fstp st0", + "fld dword [esp + 0x2c]", + "fadd dword [esp + 0x24]", + "fld dword [esp + 0x3c]", + "fadd dword [esp + 0x34]", + "fld dword [esp + 0x44]", + "fsub dword [esp + 0x14]", + "fld dword [esp + 0x4c]", + "fsub dword [esp + 0x10]", + "fstp dword [esp]", + "fld st0", + "fadd st0,st3", + "fstp dword [eax + 0x40]", + "fld dword [esp]", + "fadd st0,st2", + "fstp dword [eax + 0x44]", + "fxch st2", + "fsub st0,st2", + "fstp dword [eax + 0x48]", + "fstp st1", + "fsub dword [esp]", + "fstp dword [eax + 0x4c]", + "fld dword [esp + 0x24]", + "fsub dword [esp + 0x2c]", + "fld dword [esp + 0x34]", + "fsub dword [esp + 0x3c]", + "fld dword [esp + 0x14]", + "fadd dword [esp + 0x44]", + "fld dword [esp + 0x10]", + "fadd dword [esp + 0x4c]", + "fld st3", + "fsub st0,st1", + "fstp dword [eax + 0x50]", + "fld st1", + "fadd st0,st3", + "fstp dword [eax + 0x54]", + "fadd st0,st3", + "fstp dword [eax + 0x58]", + "fxch", + "fsub st0,st1", + "fstp dword [eax + 0x5c]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x5c]", + "fsub dword [esp + 0x54]", + "fld dword [esp + 0x6c]", + "fadd dword [esp + 0x64]", + "fld st2", + "fadd dword [esp + 0x74]", + "fld dword [esp + 0x84]", + "fsub dword [esp + 0x7c]", + "fld st1", + "fsub st0,st1", + "fmul st6", + "fstp dword [esp + 0x4]", + "faddp", + "fmul st4", + "fld dword [esp + 0x4]", + "fadd st0,st3", + "fstp dword [eax + 0x60]", + "fld st0", + "fadd st0,st2", + "fstp dword [eax + 0x64]", + "fxch st2", + "fsub dword [esp + 0x4]", + "fstp dword [eax + 0x68]", + "fsub st0,st1", + "fstp dword [eax + 0x6c]", + "fstp st0", + "fld dword [esp + 0x54]", + "fadd dword [esp + 0x5c]", + "fstp dword [esp + 0xc]", + "fld dword [esp + 0x64]", + "fsub dword [esp + 0x6c]", + "fstp dword [esp + 0x8]", + "fsubr dword [esp + 0x74]", + "fld dword [esp + 0x7c]", + "fadd dword [esp + 0x84]", + "fld st1", + "fsub st0,st1", + "fmul st3", + "fstp dword [esp + 0x4]", + "fadd st0,st1", + "fmulp st2", + "fstp st0", + "fld dword [esp + 0xc]", + "fsub st0,st1", + "fstp dword [eax + 0x70]", + "fld dword [esp + 0x4]", + "fadd dword [esp + 0x8]", + "fstp dword [eax + 0x74]", + "fadd dword [esp + 0xc]", + "fstp dword [eax + 0x78]", + "fld dword [esp + 0x8]", + "fsub dword [esp + 0x4]", + "fstp dword [eax + 0x7c]", + "add esp,0x88", + "ret" + ], + "ExpectedArm64ASM": [ + "sub w8, w8, #0x88 (136)", + "ldr s2, [x5, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x5, #24]", + "ldr s3, [x5, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "str w6, [x8, #20]", + "ldr s4, [x5, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w6, [x5, #28]", + "ldr s5, [x5, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "str w6, [x8, #16]", + "ldr s6, [x5, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "ldr s10, [x4, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s10", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v10.16b, v10.16b, v10.16b", + "mov v10.d[0], x0", + "mov v10.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v10.d[0]", + "umov w4, v10.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w20, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x20]", + "ldr s9, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "ldr s10, [x4, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s10", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v10.16b, v10.16b, v10.16b", + "mov v10.d[0], x0", + "mov v10.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v10.d[0]", + "umov w2, v10.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x8]", + "ldr s9, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "ldr s10, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s10", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v10.16b, v10.16b, v10.16b", + "mov v10.d[0], x0", + "mov v10.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v10.d[0]", + "umov w4, v10.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w20, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x20]", + "ldr s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "ldr s10, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s10", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v10.16b, v10.16b, v10.16b", + "mov v10.d[0], x0", + "mov v10.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v10.d[0]", + "umov w2, v10.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x8]", + "ldr s9, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w20, w8, #0x80 (128)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x20]", + "ldr s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w20, w8, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x20]", + "mov w20, #0x0", + "ldr s9, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "ldr s10, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s10", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v10.16b, v10.16b, v10.16b", + "mov v10.d[0], x0", + "mov v10.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v10.d[0]", + "umov w2, v10.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr s9, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "ldr s10, [x4, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s10", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v10.16b, v10.16b, v10.16b", + "mov v10.d[0], x0", + "mov v10.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v10.d[0]", + "umov w4, v10.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x8]", + "ldr s9, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "ldr s10, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s10", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v10.16b, v10.16b, v10.16b", + "mov v10.d[0], x0", + "mov v10.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v10.d[0]", + "umov w4, v10.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "ldr s10, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s10", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v10.16b, v10.16b, v10.16b", + "mov v10.d[0], x0", + "mov v10.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v10.d[0]", + "umov w2, v10.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x8]", + "ldr s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr s9, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "add w21, w8, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x21]", + "ldr s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x64 (100)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "ldr s10, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s10", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v10.16b, v10.16b, v10.16b", + "mov v10.d[0], x0", + "mov v10.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v10.d[0]", + "umov w2, v10.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x8]", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x68 (104)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8]", + "ldr s8, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "ldr s10, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s10", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v10.16b, v10.16b, v10.16b", + "mov v10.d[0], x0", + "mov v10.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v10.d[0]", + "umov w2, v10.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s9, s0", + "str s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x8]", + "ldr s7, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x84 (132)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x8]", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x8]", + "ldr s5, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x6c (108)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x4, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s7, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x4, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x4, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x8]", + "ldr s6, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x4, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x4, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x4, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x4]", + "ldr s7, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w4, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w4, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w4, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w4, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w4, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w4, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w4, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w4, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w4, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w4, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w4, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w4, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w4, #0x64 (100)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "strb w20, [x28, #1017]", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x68 (104)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x6c (108)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "mov x27, x8", + "adds w26, w8, #0x88 (136)", + "mov x8, x26", + "ldr w21, [x26]", + "add w8, w26, #0x4 (4)", + "strb w20, [x28, #1298]", + "ldr x0, [x28, #2304]", + "and x3, x21, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block2": { + "ExpectedInstructionCount": 14014, + "x86Insts": [ + "sub esp,0x90", + "fld dword [ecx + 0x4]", + "fld st0", + "fmul dword [ecx + 0x8]", + "fld st0", + "fadd dword [ecx + 0x8]", + "fld dword [eax + 0x40]", + "fadd dword [eax]", + "fld dword [eax + 0x44]", + "fadd dword [eax + 0x4]", + "fld dword [eax]", + "fsub dword [eax + 0x40]", + "fstp dword [esp + 0x8]", + "fld dword [eax + 0x4]", + "fsub dword [eax + 0x44]", + "fstp dword [esp + 0x4]", + "fld dword [eax + 0x20]", + "fadd dword [eax + 0x60]", + "fld dword [eax + 0x64]", + "fadd dword [eax + 0x24]", + "fstp dword [esp + 0x10]", + "fld dword [eax + 0x20]", + "fsub dword [eax + 0x60]", + "fstp dword [esp]", + "fld dword [eax + 0x24]", + "fsub dword [eax + 0x64]", + "fstp dword [esp + 0xc]", + "fld st0", + "fadd st0,st3", + "fstp dword [esp + 0x54]", + "fld dword [esp + 0x10]", + "fadd st0,st2", + "fstp dword [esp + 0x64]", + "fxch st2", + "fsub st0,st2", + "fstp dword [esp + 0x3c]", + "fstp st1", + "fsub dword [esp + 0x10]", + "fstp dword [esp + 0x44]", + "fld dword [esp + 0x8]", + "fsub dword [esp + 0xc]", + "fstp dword [esp + 0x60]", + "fld dword [esp]", + "fadd dword [esp + 0x4]", + "fstp dword [esp + 0x78]", + "fld dword [esp + 0xc]", + "fadd dword [esp + 0x8]", + "fstp dword [esp + 0x50]", + "fld dword [esp + 0x4]", + "fsub dword [esp]", + "fstp dword [esp + 0x28]", + "fld dword [eax + 0x8]", + "fadd dword [eax + 0x48]", + "fld dword [eax + 0x4c]", + "fadd dword [eax + 0xc]", + "fld dword [eax + 0x8]", + "fsub dword [eax + 0x48]", + "fstp dword [esp + 0x8]", + "fld dword [eax + 0xc]", + "fsub dword [eax + 0x4c]", + "fstp dword [esp + 0x4]", + "fld dword [eax + 0x28]", + "fadd dword [eax + 0x68]", + "fld dword [eax + 0x6c]", + "fadd dword [eax + 0x2c]", + "fstp dword [esp + 0x10]", + "fld dword [eax + 0x28]", + "fsub dword [eax + 0x68]", + "fstp dword [esp]", + "fld dword [eax + 0x2c]", + "fsub dword [eax + 0x6c]", + "fstp dword [esp + 0xc]", + "fld st0", + "fadd st0,st3", + "fstp dword [esp + 0x74]", + "fld dword [esp + 0x10]", + "fadd st0,st2", + "fstp dword [esp + 0x84]", + "fxch st2", + "fsub st0,st2", + "fstp dword [esp + 0x20]", + "fstp st1", + "fsub dword [esp + 0x10]", + "fstp dword [esp + 0x24]", + "fld dword [esp + 0x8]", + "fsub dword [esp + 0xc]", + "fld dword [esp]", + "fadd dword [esp + 0x4]", + "fld st1", + "fmul st3", + "fld st1", + "fmul st5", + "fsubp", + "fstp dword [esp + 0x68]", + "fmul st2", + "fxch", + "fmul st3", + "faddp", + "fstp dword [esp + 0x88]", + "fld dword [esp + 0xc]", + "fadd dword [esp + 0x8]", + "fld dword [esp + 0x4]", + "fsub dword [esp]", + "fld st1", + "fmul st4", + "fld st1", + "fmul st4", + "fsubp", + "fstp dword [esp + 0x80]", + "fxch", + "fmul st2", + "fxch", + "fmul st3", + "faddp", + "fstp dword [esp + 0x30]", + "fld dword [eax + 0x10]", + "fadd dword [eax + 0x50]", + "fld dword [eax + 0x54]", + "fadd dword [eax + 0x14]", + "fld dword [eax + 0x10]", + "fsub dword [eax + 0x50]", + "fstp dword [esp + 0x8]", + "fld dword [eax + 0x14]", + "fsub dword [eax + 0x54]", + "fstp dword [esp + 0x4]", + "fld dword [eax + 0x30]", + "fadd dword [eax + 0x70]", + "fld dword [eax + 0x74]", + "fadd dword [eax + 0x34]", + "fstp dword [esp + 0x10]", + "fld dword [eax + 0x30]", + "fsub dword [eax + 0x70]", + "fstp dword [esp]", + "fld dword [eax + 0x34]", + "fsub dword [eax + 0x74]", + "fstp dword [esp + 0xc]", + "fld st0", + "fadd st0,st3", + "fstp dword [esp + 0x5c]", + "fld dword [esp + 0x10]", + "fadd st0,st2", + "fstp dword [esp + 0x6c]", + "fxch st2", + "fsub st0,st2", + "fstp dword [esp + 0x4c]", + "fstp st1", + "fsub dword [esp + 0x10]", + "fstp dword [esp + 0x34]", + "fld dword [esp + 0x8]", + "fsub dword [esp + 0xc]", + "fld dword [esp]", + "fadd dword [esp + 0x4]", + "fld st1", + "fsub st0,st1", + "fmul st5", + "fstp dword [esp + 0x38]", + "fadd st0,st1", + "fmul st4", + "fstp dword [esp + 0x40]", + "fstp st0", + "fld dword [esp + 0xc]", + "fadd dword [esp + 0x8]", + "fld dword [esp + 0x4]", + "fsub dword [esp]", + "fld st0", + "fadd st0,st2", + "fmul st5", + "fstp dword [esp + 0x48]", + "fsub st0,st1", + "fmul st4", + "fstp dword [esp + 0x58]", + "fstp st0", + "fld dword [eax + 0x58]", + "fadd dword [eax + 0x18]", + "fld dword [eax + 0x1c]", + "fadd dword [eax + 0x5c]", + "fld dword [eax + 0x18]", + "fsub dword [eax + 0x58]", + "fstp dword [esp + 0x8]", + "fld dword [eax + 0x1c]", + "fsub dword [eax + 0x5c]", + "fstp dword [esp + 0x4]", + "fld dword [eax + 0x78]", + "fadd dword [eax + 0x38]", + "fld dword [eax + 0x3c]", + "fadd dword [eax + 0x7c]", + "fstp dword [esp + 0x10]", + "fld dword [eax + 0x38]", + "fsub dword [eax + 0x78]", + "fstp dword [esp]", + "fld dword [eax + 0x3c]", + "fsub dword [eax + 0x7c]", + "fstp dword [esp + 0xc]", + "fld st0", + "fadd st0,st3", + "fstp dword [esp + 0x7c]", + "fld dword [esp + 0x10]", + "fadd st0,st2", + "fstp dword [esp + 0x8c]", + "fxch st2", + "fsub st0,st2", + "fstp dword [esp + 0x2c]", + "fstp st1", + "fsub dword [esp + 0x10]", + "fstp dword [esp + 0x70]", + "fld dword [esp + 0x8]", + "fsub dword [esp + 0xc]", + "fld dword [esp]", + "fadd dword [esp + 0x4]", + "fld st1", + "fmul st4", + "fld st1", + "fmul st4", + "fsubp", + "fstp dword [esp + 0x1c]", + "fxch", + "fmul st2", + "fxch", + "fmul st3", + "faddp", + "fstp dword [esp + 0x14]", + "fld dword [esp + 0xc]", + "fadd dword [esp + 0x8]", + "fld dword [esp + 0x4]", + "fsub dword [esp]", + "fld st1", + "fmul st3", + "fld st1", + "fmul st5", + "fsubp", + "fstp dword [esp]", + "fmul st2", + "fxch", + "fmul st3", + "faddp", + "fstp st2", + "fstp st0", + "fld dword [esp + 0x50]", + "fsub dword [esp + 0x48]", + "fld dword [esp + 0x28]", + "fsub dword [esp + 0x58]", + "fstp dword [esp + 0x18]", + "fld dword [esp + 0x48]", + "fadd dword [esp + 0x50]", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x58]", + "fadd dword [esp + 0x28]", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x80]", + "fsub dword [esp]", + "fld dword [esp + 0x30]", + "fsub st0,st3", + "fstp dword [esp + 0x10]", + "fld dword [esp]", + "fadd dword [esp + 0x80]", + "fstp dword [esp]", + "fxch st2", + "fadd dword [esp + 0x30]", + "fstp dword [esp + 0xc]", + "fxch", + "fld st0", + "fadd st0,st2", + "fstp dword [eax + 0x60]", + "fld dword [esp + 0x10]", + "fadd dword [esp + 0x18]", + "fstp dword [eax + 0x64]", + "fxch", + "fsub st0,st1", + "fstp dword [eax + 0x68]", + "fstp st0", + "fld dword [esp + 0x18]", + "fsub dword [esp + 0x10]", + "fstp dword [eax + 0x6c]", + "fld dword [esp + 0x8]", + "fsub dword [esp + 0xc]", + "fstp dword [eax + 0x70]", + "fld dword [esp]", + "fadd dword [esp + 0x4]", + "fstp dword [eax + 0x74]", + "fld dword [esp + 0xc]", + "fadd dword [esp + 0x8]", + "fstp dword [eax + 0x78]", + "fld dword [esp + 0x4]", + "fsub dword [esp]", + "fstp dword [eax + 0x7c]", + "fld dword [esp + 0x38]", + "fadd dword [esp + 0x60]", + "fld dword [esp + 0x40]", + "fadd dword [esp + 0x78]", + "fld dword [esp + 0x60]", + "fsub dword [esp + 0x38]", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x78]", + "fsub dword [esp + 0x40]", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x1c]", + "fadd dword [esp + 0x68]", + "fld dword [esp + 0x14]", + "fadd dword [esp + 0x88]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x68]", + "fsub dword [esp + 0x1c]", + "fstp dword [esp]", + "fld dword [esp + 0x88]", + "fsub dword [esp + 0x14]", + "fstp dword [esp + 0xc]", + "fld st0", + "fadd st0,st3", + "fstp dword [eax + 0x40]", + "fld dword [esp + 0x10]", + "fadd st0,st2", + "fstp dword [eax + 0x44]", + "fxch st2", + "fsub st0,st2", + "fstp dword [eax + 0x48]", + "fstp st1", + "fsub dword [esp + 0x10]", + "fstp dword [eax + 0x4c]", + "fld dword [esp + 0x8]", + "fsub dword [esp + 0xc]", + "fstp dword [eax + 0x50]", + "fld dword [esp]", + "fadd dword [esp + 0x4]", + "fstp dword [eax + 0x54]", + "fld dword [esp + 0xc]", + "fadd dword [esp + 0x8]", + "fstp dword [eax + 0x58]", + "fld dword [esp + 0x4]", + "fsub dword [esp]", + "fstp dword [eax + 0x5c]", + "fld dword [esp + 0x20]", + "fsub dword [esp + 0x70]", + "fld dword [esp + 0x2c]", + "fadd dword [esp + 0x24]", + "fld st1", + "fsub st0,st1", + "fmul st3", + "fstp dword [esp + 0x14]", + "faddp", + "fmul st1", + "fld dword [esp + 0x70]", + "fadd dword [esp + 0x20]", + "fld dword [esp + 0x24]", + "fsub dword [esp + 0x2c]", + "fld st1", + "fsub st0,st1", + "fmul st4", + "fstp dword [esp]", + "fadd st0,st1", + "fmul st3", + "fstp dword [esp + 0xc]", + "fstp st0", + "fld dword [esp + 0x3c]", + "fsub dword [esp + 0x34]", + "fld dword [esp + 0x4c]", + "fadd dword [esp + 0x44]", + "fstp dword [esp + 0x18]", + "fld dword [esp + 0x34]", + "fadd dword [esp + 0x3c]", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x44]", + "fsub dword [esp + 0x4c]", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x14]", + "fadd st0,st1", + "fstp dword [eax + 0x20]", + "fld st1", + "fadd dword [esp + 0x18]", + "fstp dword [eax + 0x24]", + "fsub dword [esp + 0x14]", + "fstp dword [eax + 0x28]", + "fld dword [esp + 0x18]", + "fsub st0,st1", + "fstp dword [eax + 0x2c]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x8]", + "fsub dword [esp + 0xc]", + "fstp dword [eax + 0x30]", + "fld dword [esp]", + "fadd dword [esp + 0x4]", + "fstp dword [eax + 0x34]", + "fld dword [esp + 0xc]", + "fadd dword [esp + 0x8]", + "fstp dword [eax + 0x38]", + "fld dword [esp + 0x4]", + "fsub dword [esp]", + "fstp dword [eax + 0x3c]", + "fld dword [esp + 0x5c]", + "fadd dword [esp + 0x54]", + "fld dword [esp + 0x6c]", + "fadd dword [esp + 0x64]", + "fld dword [esp + 0x54]", + "fsub dword [esp + 0x5c]", + "fstp dword [esp + 0x8]", + "fld dword [esp + 0x64]", + "fsub dword [esp + 0x6c]", + "fstp dword [esp + 0x4]", + "fld dword [esp + 0x7c]", + "fadd dword [esp + 0x74]", + "fld dword [esp + 0x8c]", + "fadd dword [esp + 0x84]", + "fstp dword [esp + 0x10]", + "fld dword [esp + 0x74]", + "fsub dword [esp + 0x7c]", + "fstp dword [esp]", + "fld dword [esp + 0x84]", + "fsub dword [esp + 0x8c]", + "fstp dword [esp + 0xc]", + "fld st0", + "fadd st0,st3", + "fstp dword [eax]", + "fld dword [esp + 0x10]", + "fadd st0,st2", + "fstp dword [eax + 0x4]", + "fxch st2", + "fsub st0,st2", + "fstp dword [eax + 0x8]", + "fstp st1", + "fsub dword [esp + 0x10]", + "fstp dword [eax + 0xc]", + "fld dword [esp + 0x8]", + "fsub dword [esp + 0xc]", + "fstp dword [eax + 0x10]", + "fld dword [esp]", + "fadd dword [esp + 0x4]", + "fstp dword [eax + 0x14]", + "fld dword [esp + 0xc]", + "fadd dword [esp + 0x8]", + "fstp dword [eax + 0x18]", + "fld dword [esp + 0x4]", + "fsub dword [esp]", + "fstp dword [eax + 0x1c]", + "add esp,0x90", + "ret" + ], + "ExpectedArm64ASM": [ + "sub w8, w8, #0x90 (144)", + "ldr s2, [x5, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x5, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x5, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x4, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w20, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x20]", + "ldr s7, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w20, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x20]", + "ldr s7, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8]", + "ldr s8, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0x64 (100)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "mov w20, #0x0", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8]", + "ldr s8, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x84 (132)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x68 (104)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x88 (136)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x80 (128)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8]", + "ldr s8, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x6c (108)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x4, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x4, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "ldr s7, [x4, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v9.d[0]", + "umov w2, v9.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x8]", + "ldr s8, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr s9, [x4, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "ldr s8, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w21, w8, #0x8c (140)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "add w21, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s7, s0", + "str s7, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #128]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x8]", + "ldr s6, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x60 (96)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s6, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x64 (100)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x68 (104)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x6c (108)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x70 (112)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x74 (116)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x78 (120)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x7c (124)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x8]", + "ldr s6, [x8, #136]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr s7, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w4, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "ldr s6, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "add w21, w4, #0x44 (68)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x48 (72)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x4c (76)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x50 (80)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x54 (84)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x58 (88)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add w21, w4, #0x5c (92)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s3, s0", + "str s3, [x21]", + "ldr s3, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #112]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s6, s0", + "str s6, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s4, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s4, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w4, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w21, w4, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #100]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s4, s0", + "str s4, [x21]", + "ldr s4, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr s5, [x8, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "ldr s5, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #124]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x8]", + "ldr s5, [x8, #132]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr s6, [x8, #140]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x4]", + "ldr s5, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "add w21, w4, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s5, s0", + "str s5, [x21]", + "strb w20, [x28, #1017]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w4, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w4, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w4, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w4, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w4, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "ldr s2, [x8, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add w20, w4, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x20]", + "mvn w27, w8", + "adds w26, w8, #0x90 (144)", + "mov x8, x26", + "ldr w20, [x26]", + "add w8, w26, #0x4 (4)", + "ldrb w21, [x28, #1019]", + "mov w22, #0x1", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldrb w23, [x28, #1298]", + "lsl w21, w22, w21", + "bic w21, w23, w21", + "strb w21, [x28, #1298]", + "ldr x0, [x28, #2304]", + "and x3, x20, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block3": { + "ExpectedInstructionCount": 118, + "x86Insts": [ + "mov eax,dword [ebp + 0xffffff44]", + "mov ecx,dword [eax + 0x4]", + "mov edx,dword [ebp + 0xffffff7c]", + "mov eax,edx", + "add eax,eax", + "add eax,edx", + "shl eax,0x5", + "lea eax,[ecx + eax*0x1]", + "mov dword [ebp + -0x7c],eax", + "mov eax,dword [ebp + 0xffffff44]", + "mov ecx,dword [eax + 0x4]", + "mov edx,dword [ebp + 0xffffff7c]", + "mov eax,edx", + "add eax,eax", + "add eax,edx", + "add eax,0x1", + "shl eax,0x5", + "lea eax,[ecx + eax*0x1]", + "mov dword [ebp + -0x78],eax", + "mov eax,dword [ebp + 0xffffff44]", + "mov ecx,dword [eax + 0x4]", + "mov edx,dword [ebp + 0xffffff7c]", + "mov eax,edx", + "add eax,eax", + "add eax,edx", + "shl eax,0x5", + "add eax,0x40", + "lea eax,[ecx + eax*0x1]", + "mov dword [ebp + -0x74],eax", + "mov eax,dword [ebp + 0xffffff44]", + "mov ecx,dword [eax + 0x4]", + "mov edx,dword [ebp + 0xffffff7c]", + "mov eax,edx", + "add eax,eax", + "add eax,edx", + "shl eax,0x5", + "lea eax,[ecx + eax*0x1]", + "add eax,0xc", + "mov dword [ebp + -0x70],eax", + "mov eax,dword [ebp + 0xffffff44]", + "mov ecx,dword [eax + 0x4]", + "mov edx,dword [ebp + 0xffffff7c]", + "mov eax,edx", + "add eax,eax", + "add eax,edx", + "add eax,0x1", + "shl eax,0x5", + "lea eax,[ecx + eax*0x1]", + "add eax,0xc", + "mov dword [ebp + -0x6c],eax", + "mov eax,dword [ebp + 0xffffff44]", + "mov ecx,dword [eax + 0x4]", + "mov edx,dword [ebp + 0xffffff7c]", + "mov eax,edx", + "add eax,eax", + "add eax,edx", + "shl eax,0x5", + "add eax,0x40", + "lea eax,[ecx + eax*0x1]", + "add eax,0xc", + "mov dword [ebp + -0x68],eax", + "mov eax,dword [ebp + 0xffffff44]", + "mov ecx,dword [eax + 0x4]", + "mov edx,dword [ebp + 0xffffff7c]", + "mov eax,edx", + "add eax,eax", + "add eax,edx", + "shl eax,0x5", + "lea eax,[ecx + eax*0x1]", + "add eax,0x18", + "mov dword [ebp + -0x64],eax", + "mov eax,dword [ebp + 0xffffff44]", + "mov ecx,dword [eax + 0x4]", + "mov edx,dword [ebp + 0xffffff7c]", + "mov eax,edx", + "add eax,eax", + "add eax,edx", + "add eax,0x1", + "shl eax,0x5", + "lea eax,[ecx + eax*0x1]", + "add eax,0x18", + "mov dword [ebp + -0x60],eax", + "mov eax,dword [ebp + 0xffffff44]", + "mov ecx,dword [eax + 0x4]", + "mov edx,dword [ebp + 0xffffff7c]", + "mov eax,edx", + "add eax,eax", + "add eax,edx", + "shl eax,0x5", + "add eax,0x40", + "lea eax,[ecx + eax*0x1]", + "add eax,0x18", + "mov dword [ebp + -0x5c],eax", + "lea eax,[ebp + 0xffffff04]", + "mov dword [esp],eax", + "call 0x0819ba1a", + "lea eax,[ebp + 0xfffffef8]", + "mov dword [esp],eax", + "call 0x0819ba1a", + "lea eax,[ebp + 0xfffffeec]", + "mov dword [esp],eax", + "call 0x0819ba1a", + "lea eax,[ebp + 0xfffffee0]", + "mov dword [esp],eax", + "call 0x0819ba1a", + "mov eax,dword [ebp + -0x7c]", + "mov eax,dword [eax]", + "mov dword [ebp + 0xfffffe68],eax", + "mov eax,dword [ebp + -0x7c]", + "mov eax,dword [eax + 0x4]", + "mov dword [ebp + 0xfffffe6c],eax", + "mov eax,dword [ebp + -0x7c]", + "mov eax,dword [eax + 0x8]", + "mov dword [ebp + 0xfffffe70],eax", + "mov eax,dword [ebp + -0x78]", + "mov eax,dword [eax]", + "mov dword [ebp + 0xfffffe20],eax", + "mov eax,dword [ebp + -0x78]", + "mov eax,dword [eax + 0x4]", + "mov dword [ebp + 0xfffffe24],eax", + "mov eax,dword [ebp + -0x78]", + "mov eax,dword [eax + 0x8]", + "mov dword [ebp + 0xfffffe28],eax", + "mov eax,dword [ebp + -0x74]", + "mov eax,dword [eax]", + "mov dword [ebp + 0xfffffe8c],eax", + "mov eax,dword [ebp + -0x74]", + "mov eax,dword [eax + 0x4]", + "mov dword [ebp + 0xfffffe90],eax", + "mov eax,dword [ebp + -0x74]", + "mov eax,dword [eax + 0x8]", + "mov dword [ebp + 0xfffffe94],eax", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + 0xffffff04]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax + 0x4]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax + 0x4]", + "fsubp", + "fstp dword [ebp + 0xffffff08]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax + 0x8]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax + 0x8]", + "fsubp", + "fstp dword [ebp + 0xffffff0c]", + "mov eax,dword [ebp + 0xffffff04]", + "mov dword [ebp + 0xfffffeec],eax", + "mov eax,dword [ebp + 0xffffff08]", + "mov dword [ebp + 0xfffffef0],eax", + "mov eax,dword [ebp + 0xffffff0c]", + "mov dword [ebp + 0xfffffef4],eax", + "fld dword [ebp + 0xfffffeec]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax]", + "fmulp", + "fld dword [ebp + 0xfffffef0]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax + 0x4]", + "fmulp", + "faddp", + "fld dword [ebp + 0xfffffef4]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax + 0x8]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x80]", + "fld dword [ebp + 0xfffffeec]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffeec]", + "fld dword [ebp + 0xfffffef0]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax + 0x4]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffef0]", + "fld dword [ebp + 0xfffffef4]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax + 0x8]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffef4]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax]", + "fld dword [ebp + 0xfffffeec]", + "fld dword [0x085cefdc]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe44]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax + 0x4]", + "fld dword [ebp + 0xfffffef0]", + "fld dword [0x085cefdc]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe48]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax + 0x8]", + "fld dword [ebp + 0xfffffef4]", + "fld dword [0x085cefdc]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe4c]", + "mov eax,dword [ebp + 0xffffff04]", + "mov dword [ebp + 0xfffffee0],eax", + "mov eax,dword [ebp + 0xffffff08]", + "mov dword [ebp + 0xfffffee4],eax", + "mov eax,dword [ebp + 0xffffff0c]", + "mov dword [ebp + 0xfffffee8],eax", + "fld dword [ebp + 0xfffffee0]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax]", + "fmulp", + "fld dword [ebp + 0xfffffee4]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax + 0x4]", + "fmulp", + "faddp", + "fld dword [ebp + 0xfffffee8]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax + 0x8]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x80]", + "fld dword [ebp + 0xfffffee0]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffee0]", + "fld dword [ebp + 0xfffffee4]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax + 0x4]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffee4]", + "fld dword [ebp + 0xfffffee8]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax + 0x8]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffee8]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax]", + "fld dword [ebp + 0xfffffee0]", + "fld dword [0x085cefe0]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe2c]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax + 0x4]", + "fld dword [ebp + 0xfffffee4]", + "fld dword [0x085cefe0]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe30]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax + 0x8]", + "fld dword [ebp + 0xfffffee8]", + "fld dword [0x085cefe0]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe34]", + "mov eax,dword [ebp + -0x74]", + "fld dword [eax]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + 0xffffff04]", + "mov eax,dword [ebp + -0x74]", + "fld dword [eax + 0x4]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax + 0x4]", + "fsubp", + "fstp dword [ebp + 0xffffff08]", + "mov eax,dword [ebp + -0x74]", + "fld dword [eax + 0x8]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax + 0x8]", + "fsubp", + "fstp dword [ebp + 0xffffff0c]", + "mov eax,dword [ebp + 0xffffff04]", + "mov dword [ebp + 0xfffffeec],eax", + "mov eax,dword [ebp + 0xffffff08]", + "mov dword [ebp + 0xfffffef0],eax", + "mov eax,dword [ebp + 0xffffff0c]", + "mov dword [ebp + 0xfffffef4],eax", + "fld dword [ebp + 0xfffffeec]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax]", + "fmulp", + "fld dword [ebp + 0xfffffef0]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax + 0x4]", + "fmulp", + "faddp", + "fld dword [ebp + 0xfffffef4]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax + 0x8]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x80]", + "fld dword [ebp + 0xfffffeec]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffeec]", + "fld dword [ebp + 0xfffffef0]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax + 0x4]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffef0]", + "fld dword [ebp + 0xfffffef4]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax + 0x8]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffef4]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax]", + "fld dword [ebp + 0xfffffeec]", + "fld dword [0x085cefdc]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe38]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax + 0x4]", + "fld dword [ebp + 0xfffffef0]", + "fld dword [0x085cefdc]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe3c]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax + 0x8]", + "fld dword [ebp + 0xfffffef4]", + "fld dword [0x085cefdc]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe40]", + "mov eax,dword [ebp + 0xffffff04]", + "mov dword [ebp + 0xfffffee0],eax", + "mov eax,dword [ebp + 0xffffff08]", + "mov dword [ebp + 0xfffffee4],eax", + "mov eax,dword [ebp + 0xffffff0c]", + "mov dword [ebp + 0xfffffee8],eax", + "fld dword [ebp + 0xfffffee0]", + "mov eax,dword [ebp + -0x68]", + "fld dword [eax]", + "fmulp", + "fld dword [ebp + 0xfffffee4]", + "mov eax,dword [ebp + -0x68]", + "fld dword [eax + 0x4]", + "fmulp", + "faddp", + "fld dword [ebp + 0xfffffee8]", + "mov eax,dword [ebp + -0x68]", + "fld dword [eax + 0x8]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x80]", + "fld dword [ebp + 0xfffffee0]", + "mov eax,dword [ebp + -0x68]", + "fld dword [eax]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffee0]", + "fld dword [ebp + 0xfffffee4]", + "mov eax,dword [ebp + -0x68]", + "fld dword [eax + 0x4]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffee4]", + "fld dword [ebp + 0xfffffee8]", + "mov eax,dword [ebp + -0x68]", + "fld dword [eax + 0x8]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffee8]", + "mov eax,dword [ebp + -0x74]", + "fld dword [eax]", + "fld dword [ebp + 0xfffffee0]", + "fld dword [0x085cefe0]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe5c]", + "mov eax,dword [ebp + -0x74]", + "fld dword [eax + 0x4]", + "fld dword [ebp + 0xfffffee4]", + "fld dword [0x085cefe0]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe60]", + "mov eax,dword [ebp + -0x74]", + "fld dword [eax + 0x8]", + "fld dword [ebp + 0xfffffee8]", + "fld dword [0x085cefe0]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe64]", + "mov eax,dword [ebp + -0x74]", + "fld dword [eax]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + 0xffffff04]", + "mov eax,dword [ebp + -0x74]", + "fld dword [eax + 0x4]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax + 0x4]", + "fsubp", + "fstp dword [ebp + 0xffffff08]", + "mov eax,dword [ebp + -0x74]", + "fld dword [eax + 0x8]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax + 0x8]", + "fsubp", + "fstp dword [ebp + 0xffffff0c]", + "mov eax,dword [ebp + 0xffffff04]", + "mov dword [ebp + 0xfffffeec],eax", + "mov eax,dword [ebp + 0xffffff08]", + "mov dword [ebp + 0xfffffef0],eax", + "mov eax,dword [ebp + 0xffffff0c]", + "mov dword [ebp + 0xfffffef4],eax", + "fld dword [ebp + 0xfffffeec]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax]", + "fmulp", + "fld dword [ebp + 0xfffffef0]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax + 0x4]", + "fmulp", + "faddp", + "fld dword [ebp + 0xfffffef4]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax + 0x8]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x80]", + "fld dword [ebp + 0xfffffeec]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffeec]", + "fld dword [ebp + 0xfffffef0]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax + 0x4]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffef0]", + "fld dword [ebp + 0xfffffef4]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax + 0x8]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffef4]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax]", + "fld dword [ebp + 0xfffffeec]", + "fld dword [0x085cefdc]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe74]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax + 0x4]", + "fld dword [ebp + 0xfffffef0]", + "fld dword [0x085cefdc]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe78]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax + 0x8]", + "fld dword [ebp + 0xfffffef4]", + "fld dword [0x085cefdc]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe7c]", + "mov eax,dword [ebp + 0xffffff04]", + "mov dword [ebp + 0xfffffee0],eax", + "mov eax,dword [ebp + 0xffffff08]", + "mov dword [ebp + 0xfffffee4],eax", + "mov eax,dword [ebp + 0xffffff0c]", + "mov dword [ebp + 0xfffffee8],eax", + "fld dword [ebp + 0xfffffee0]", + "mov eax,dword [ebp + -0x68]", + "fld dword [eax]", + "fmulp", + "fld dword [ebp + 0xfffffee4]", + "mov eax,dword [ebp + -0x68]", + "fld dword [eax + 0x4]", + "fmulp", + "faddp", + "fld dword [ebp + 0xfffffee8]", + "mov eax,dword [ebp + -0x68]", + "fld dword [eax + 0x8]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x80]", + "fld dword [ebp + 0xfffffee0]", + "mov eax,dword [ebp + -0x68]", + "fld dword [eax]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffee0]", + "fld dword [ebp + 0xfffffee4]", + "mov eax,dword [ebp + -0x68]", + "fld dword [eax + 0x4]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffee4]", + "fld dword [ebp + 0xfffffee8]", + "mov eax,dword [ebp + -0x68]", + "fld dword [eax + 0x8]", + "fmul dword [ebp + -0x80]", + "fsubp", + "fstp dword [ebp + 0xfffffee8]", + "mov eax,dword [ebp + -0x74]", + "fld dword [eax]", + "fld dword [ebp + 0xfffffee0]", + "fld dword [0x085cefe0]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe80]", + "mov eax,dword [ebp + -0x74]", + "fld dword [eax + 0x4]", + "fld dword [ebp + 0xfffffee4]", + "fld dword [0x085cefe0]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe84]", + "mov eax,dword [ebp + -0x74]", + "fld dword [eax + 0x8]", + "fld dword [ebp + 0xfffffee8]", + "fld dword [0x085cefe0]", + "fmulp", + "faddp", + "fstp dword [ebp + 0xfffffe88]", + "fld dword [ebp + 0xfffffe2c]", + "fld dword [ebp + 0xfffffe44]", + "faddp", + "fld dword [ebp + 0xfffffe38]", + "faddp", + "fld dword [ebp + 0xfffffe5c]", + "faddp", + "fld dword [ebp + 0xfffffe74]", + "faddp", + "fld dword [ebp + 0xfffffe80]", + "faddp", + "fld dword [0x085cefe4]", + "fdivp", + "fstp dword [ebp + 0xfffffe50]", + "fld dword [ebp + 0xfffffe30]", + "fld dword [ebp + 0xfffffe48]", + "faddp", + "fld dword [ebp + 0xfffffe3c]", + "faddp", + "fld dword [ebp + 0xfffffe60]", + "faddp", + "fld dword [ebp + 0xfffffe78]", + "faddp", + "fld dword [ebp + 0xfffffe84]", + "faddp", + "fld dword [0x085cefe4]", + "fdivp", + "fstp dword [ebp + 0xfffffe54]", + "fld dword [ebp + 0xfffffe34]", + "fld dword [ebp + 0xfffffe4c]", + "faddp", + "fld dword [ebp + 0xfffffe40]", + "faddp", + "fld dword [ebp + 0xfffffe64]", + "faddp", + "fld dword [ebp + 0xfffffe7c]", + "faddp", + "fld dword [ebp + 0xfffffe88]", + "faddp", + "fld dword [0x085cefe4]", + "fdivp", + "fstp dword [ebp + 0xfffffe58]", + "fld dword [ebp + 0xfffffe50]", + "fld dword [ebp + 0xfffffe20]", + "fld dword [ebp + 0xfffffe68]", + "faddp", + "fld dword [ebp + 0xfffffe8c]", + "faddp", + "fld dword [0x085cefe8]", + "fdivp", + "faddp", + "fstp dword [ebp + 0xfffffe50]", + "fld dword [ebp + 0xfffffe54]", + "fld dword [ebp + 0xfffffe24]", + "fld dword [ebp + 0xfffffe6c]", + "faddp", + "fld dword [ebp + 0xfffffe90]", + "faddp", + "fld dword [0x085cefe8]", + "fdivp", + "faddp", + "fstp dword [ebp + 0xfffffe54]", + "fld dword [ebp + 0xfffffe58]", + "fld dword [ebp + 0xfffffe28]", + "fld dword [ebp + 0xfffffe70]", + "faddp", + "fld dword [ebp + 0xfffffe94]", + "faddp", + "fld dword [0x085cefe8]", + "fdivp", + "faddp", + "fstp dword [ebp + 0xfffffe58]", + "mov eax,dword [ebp + -0x70]", + "mov eax,dword [eax]", + "mov dword [ebp + 0xfffffebc],eax", + "mov eax,dword [ebp + -0x70]", + "mov eax,dword [eax + 0x4]", + "mov dword [ebp + 0xfffffec0],eax", + "mov eax,dword [ebp + -0x70]", + "mov eax,dword [eax + 0x8]", + "mov dword [ebp + 0xfffffec4],eax", + "mov eax,dword [ebp + -0x6c]", + "mov eax,dword [eax]", + "mov dword [ebp + 0xfffffe98],eax", + "mov eax,dword [ebp + -0x6c]", + "mov eax,dword [eax + 0x4]", + "mov dword [ebp + 0xfffffe9c],eax", + "mov eax,dword [ebp + -0x6c]", + "mov eax,dword [eax + 0x8]", + "mov dword [ebp + 0xfffffea0],eax", + "mov eax,dword [ebp + -0x68]", + "mov eax,dword [eax]", + "mov dword [ebp + 0xfffffed4],eax", + "mov eax,dword [ebp + -0x68]", + "mov eax,dword [eax + 0x4]", + "mov dword [ebp + 0xfffffed8],eax", + "mov eax,dword [ebp + -0x68]", + "mov eax,dword [eax + 0x8]", + "mov dword [ebp + 0xfffffedc],eax", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax]", + "faddp", + "fstp dword [ebp + 0xfffffef8]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax + 0x4]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax + 0x4]", + "faddp", + "fstp dword [ebp + 0xfffffefc]", + "mov eax,dword [ebp + -0x70]", + "fld dword [eax + 0x8]", + "mov eax,dword [ebp + -0x6c]", + "fld dword [eax + 0x8]", + "faddp", + "fstp dword [ebp + 0xffffff00]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + 0xffffff04]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax + 0x4]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax + 0x4]", + "fsubp", + "fstp dword [ebp + 0xffffff08]", + "mov eax,dword [ebp + -0x78]", + "fld dword [eax + 0x8]", + "mov eax,dword [ebp + -0x7c]", + "fld dword [eax + 0x8]", + "fsubp", + "fstp dword [ebp + 0xffffff0c]", + "fld dword [ebp + 0xffffff04]", + "fld dword [ebp + 0xffffff04]", + "fmulp", + "fld dword [ebp + 0xffffff08]", + "fld dword [ebp + 0xffffff08]", + "fmulp", + "faddp", + "fld dword [ebp + 0xffffff0c]", + "fld dword [ebp + 0xffffff0c]", + "fmulp", + "faddp", + "fstp qword [esp]", + "call 0x0811028c", + "fstp dword [ebp + -0x80]", + "fld dword [ebp + -0x80]", + "fldz", + "fxch", + "fucomip st0,st1", + "fstp st0", + "seta al", + "test al,al", + "jz 0x08470ef5" + ], + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffff44", + "ldr w4, [x9, w20, sxtw]", + "ldr w5, [x4, #4]", + "mov x21, #0xffffffffffffff7c", + "ldr w6, [x9, w21, sxtw]", + "mov x4, x6", + "add w4, w6, w6", + "add w4, w4, w6", + "lsl w4, w4, #5", + "add w4, w5, w4", + "mov x22, #0xffffffffffffff84", + "str w4, [x9, w22, sxtw]", + "ldr w4, [x9, w20, sxtw]", + "ldr w5, [x4, #4]", + "ldr w6, [x9, w21, sxtw]", + "mov x4, x6", + "add w4, w6, w6", + "add w4, w4, w6", + "add w4, w4, #0x1 (1)", + "lsl w4, w4, #5", + "add w4, w5, w4", + "mov x22, #0xffffffffffffff88", + "str w4, [x9, w22, sxtw]", + "ldr w4, [x9, w20, sxtw]", + "ldr w5, [x4, #4]", + "ldr w6, [x9, w21, sxtw]", + "mov x4, x6", + "add w4, w6, w6", + "add w4, w4, w6", + "lsl w4, w4, #5", + "add w4, w4, #0x40 (64)", + "add w4, w5, w4", + "mov x22, #0xffffffffffffff8c", + "str w4, [x9, w22, sxtw]", + "ldr w4, [x9, w20, sxtw]", + "ldr w5, [x4, #4]", + "ldr w6, [x9, w21, sxtw]", + "mov x4, x6", + "add w4, w6, w6", + "add w4, w4, w6", + "lsl w4, w4, #5", + "add w4, w5, w4", + "add w4, w4, #0xc (12)", + "mov x22, #0xffffffffffffff90", + "str w4, [x9, w22, sxtw]", + "ldr w4, [x9, w20, sxtw]", + "ldr w5, [x4, #4]", + "ldr w6, [x9, w21, sxtw]", + "mov x4, x6", + "add w4, w6, w6", + "add w4, w4, w6", + "add w4, w4, #0x1 (1)", + "lsl w4, w4, #5", + "add w4, w5, w4", + "add w4, w4, #0xc (12)", + "mov x22, #0xffffffffffffff94", + "str w4, [x9, w22, sxtw]", + "ldr w4, [x9, w20, sxtw]", + "ldr w5, [x4, #4]", + "ldr w6, [x9, w21, sxtw]", + "mov x4, x6", + "add w4, w6, w6", + "add w4, w4, w6", + "lsl w4, w4, #5", + "add w4, w4, #0x40 (64)", + "add w4, w5, w4", + "add w4, w4, #0xc (12)", + "mov x22, #0xffffffffffffff98", + "str w4, [x9, w22, sxtw]", + "ldr w4, [x9, w20, sxtw]", + "ldr w5, [x4, #4]", + "ldr w6, [x9, w21, sxtw]", + "mov x4, x6", + "add w4, w6, w6", + "add w4, w4, w6", + "lsl w4, w4, #5", + "add w4, w5, w4", + "add w4, w4, #0x18 (24)", + "mov x22, #0xffffffffffffff9c", + "str w4, [x9, w22, sxtw]", + "ldr w4, [x9, w20, sxtw]", + "ldr w5, [x4, #4]", + "ldr w6, [x9, w21, sxtw]", + "mov x4, x6", + "add w4, w6, w6", + "add w4, w4, w6", + "add w4, w4, #0x1 (1)", + "lsl w4, w4, #5", + "add w4, w5, w4", + "add w4, w4, #0x18 (24)", + "mov x22, #0xffffffffffffffa0", + "str w4, [x9, w22, sxtw]", + "ldr w4, [x9, w20, sxtw]", + "ldr w5, [x4, #4]", + "ldr w6, [x9, w21, sxtw]", + "mov x4, x6", + "add w4, w6, w6", + "add w4, w4, w6", + "lsl w4, w4, #5", + "add w4, w4, #0x40 (64)", + "add w4, w5, w4", + "mvn w27, w4", + "adds w26, w4, #0x18 (24)", + "mov x4, x26", + "mov x20, #0xffffffffffffffa4", + "str w26, [x9, w20, sxtw]", + "sub w4, w9, #0xfc (252)", + "str w4, [x8]", + "mov w20, #0xf09", + "movk w20, #0x1, lsl #16", + "mov w21, #0xb8da", + "movk w21, #0x819, lsl #16", + "add w21, w20, w21", + "str w20, [x8, #-4]!", + "ldr x0, [x28, #2304]", + "and x3, x21, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block4": { + "ExpectedInstructionCount": 12300, + "x86Insts": [ + "mov ebp,dword [esp + 0x64]", + "fadd dword [ebp + 0x8]", + "add ebp,0x10", + "mov dword [esp + 0x64],ebp", + "fmul dword [esp + 0x74]", + "fstp dword [esp + 0x6c]", + "fld dword [esp + 0x34]", + "fadd dword [ebp + -0x4]", + "fmul dword [esp + 0x74]", + "fstp dword [esp + 0x68]", + "fld dword [esp + 0x38]", + "fadd dword [ebp]", + "fmul dword [esp + 0x78]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x3c]", + "fsub dword [ebp + 0x4]", + "fmul dword [esp + 0x78]", + "fstp dword [esp + 0x28]", + "fld dword [ebp + -0x8]", + "mov ebp,dword [ebp + -0x4]", + "mov dword [esp + 0x34],ebp", + "mov ebp,dword [esp + 0x64]", + "mov ebp,dword [ebp]", + "mov dword [esp + 0x38],ebp", + "mov ebp,dword [esp + 0x64]", + "fld dword [ebp + 0x4]", + "fchs", + "fstp dword [esp + 0x3c]", + "fld dword [edi + -0x8]", + "fadd dword [edx + -0x8]", + "fld dword [edi + -0x4]", + "fchs", + "fsub dword [edx + -0x4]", + "fld dword [edi + -0x8]", + "fsub dword [edx + -0x8]", + "fstp dword [esp + 0x14]", + "fld dword [edx + -0x4]", + "fsub dword [edi + -0x4]", + "fstp dword [esp + 0x1c]", + "fld dword [edi]", + "fadd dword [edx]", + "fstp dword [esp + 0x44]", + "fld dword [edi + 0x4]", + "fchs", + "fsub dword [edx + 0x4]", + "fstp dword [esp + 0x50]", + "fld dword [edi]", + "fsub dword [edx]", + "fstp dword [esp + 0x54]", + "fld dword [edx + 0x4]", + "fsub dword [edi + 0x4]", + "fstp dword [esp + 0x5c]", + "fld dword [ecx + -0x8]", + "fadd dword [esi + -0x8]", + "fld dword [ecx + -0x4]", + "fadd dword [esi + -0x4]", + "fstp dword [esp + 0x10]", + "fld dword [esi + -0x8]", + "fsub dword [ecx + -0x8]", + "fstp dword [esp + 0x20]", + "fld dword [esi + -0x4]", + "fsub dword [ecx + -0x4]", + "fstp dword [esp + 0x18]", + "fld dword [ecx]", + "fadd dword [esi]", + "fstp dword [esp + 0x48]", + "fld dword [ecx + 0x4]", + "fadd dword [esi + 0x4]", + "fstp dword [esp + 0x4c]", + "fld dword [esi]", + "fsub dword [ecx]", + "fstp dword [esp + 0x60]", + "fld dword [esi + 0x4]", + "fsub dword [ecx + 0x4]", + "fstp dword [esp + 0x58]", + "fld st0", + "fadd st0,st3", + "fstp dword [edi + -0x8]", + "fld st1", + "fsub dword [esp + 0x10]", + "fstp dword [edi + -0x4]", + "fld dword [esp + 0x48]", + "fadd dword [esp + 0x44]", + "fstp dword [edi]", + "fld dword [esp + 0x50]", + "fsub dword [esp + 0x4c]", + "fstp dword [edi + 0x4]", + "fxch st2", + "fsub st0,st2", + "fstp dword [esi + -0x8]", + "fstp st1", + "fld dword [esp + 0x10]", + "fadd st0,st1", + "fstp dword [esi + -0x4]", + "fstp st0", + "fld dword [esp + 0x44]", + "fsub dword [esp + 0x48]", + "fstp dword [esi]", + "fld dword [esp + 0x4c]", + "fadd dword [esp + 0x50]", + "fstp dword [esi + 0x4]", + "fld dword [esp + 0x18]", + "fadd dword [esp + 0x14]", + "fld dword [esp + 0x20]", + "fadd dword [esp + 0x1c]", + "fld dword [esp + 0x6c]", + "fmul st2", + "fld dword [esp + 0x68]", + "fmul st2", + "fsubp", + "fstp dword [edx + -0x8]", + "fld dword [esp + 0x6c]", + "fmul st1", + "fld dword [esp + 0x68]", + "fmul st3", + "faddp", + "fstp dword [edx + -0x4]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x58]", + "fadd dword [esp + 0x54]", + "fld dword [esp + 0x60]", + "fadd dword [esp + 0x5c]", + "fld st2", + "fmul st2", + "fld dword [esp + 0x34]", + "fmul st2", + "fsubp", + "fstp dword [edx]", + "fld st2", + "fmul st1", + "fld dword [esp + 0x34]", + "fmul st3", + "faddp", + "fstp dword [edx + 0x4]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x18]", + "fld dword [esp + 0x1c]", + "fsub dword [esp + 0x20]", + "fld dword [esp + 0x28]", + "fmul st1", + "mov ebp,dword [esp + 0x24]", + "fld dword [esp + 0x2c]", + "fmul st3", + "faddp", + "fstp dword [ecx + -0x8]", + "fld dword [esp + 0x2c]", + "fmul st1", + "fld dword [esp + 0x28]", + "fmul st3", + "fsubp", + "fstp dword [ecx + -0x4]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x54]", + "fsub dword [esp + 0x58]", + "fld dword [esp + 0x5c]", + "fsub dword [esp + 0x60]", + "fld dword [esp + 0x3c]", + "fmul st1", + "fld dword [esp + 0x38]", + "fmul st3", + "faddp", + "fstp dword [ecx]", + "fld dword [esp + 0x38]", + "fmul st1", + "fld dword [esp + 0x3c]", + "fmul st3", + "fsubp", + "fstp dword [ecx + 0x4]", + "fstp st0", + "fstp st0", + "fld dword [ebp + 0x8]", + "mov ebp,dword [esp + 0x30]", + "fadd dword [ebp + 0x8]", + "mov ebp,dword [esp + 0x24]", + "fld dword [ebp + 0xc]", + "mov ebp,dword [esp + 0x30]", + "fchs", + "fsub dword [ebp + 0xc]", + "mov ebp,dword [esp + 0x24]", + "fld dword [ebp + 0x8]", + "mov ebp,dword [esp + 0x30]", + "fsub dword [ebp + 0x8]", + "fstp dword [esp + 0x14]", + "fld dword [ebp + 0xc]", + "mov ebp,dword [esp + 0x24]", + "fsub dword [ebp + 0xc]", + "mov ebp,dword [esp + 0x30]", + "fstp dword [esp + 0x1c]", + "fld dword [ebp]", + "mov ebp,dword [esp + 0x24]", + "fadd dword [ebp]", + "fstp dword [esp + 0x44]", + "fld dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x30]", + "fchs", + "fsub dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x24]", + "fstp dword [esp + 0x50]", + "fld dword [ebp]", + "mov ebp,dword [esp + 0x30]", + "fsub dword [ebp]", + "fstp dword [esp + 0x54]", + "fld dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x24]", + "fsub dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x70]", + "fstp dword [esp + 0x5c]", + "fld dword [ebp + 0x8]", + "fadd dword [ebx + 0x8]", + "fld dword [ebp + 0xc]", + "fadd dword [ebx + 0xc]", + "fstp dword [esp + 0x10]", + "fld dword [ebp + 0x8]", + "fsub dword [ebx + 0x8]", + "fstp dword [esp + 0x20]", + "fld dword [ebp + 0xc]", + "fsub dword [ebx + 0xc]", + "fstp dword [esp + 0x18]", + "fld dword [ebp]", + "fadd dword [ebx]", + "fstp dword [esp + 0x48]", + "fld dword [ebx + 0x4]", + "fadd dword [ebp + 0x4]", + "fstp dword [esp + 0x4c]", + "fld dword [ebp]", + "fsub dword [ebx]", + "fstp dword [esp + 0x60]", + "fld dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x24]", + "fsub dword [ebx + 0x4]", + "fstp dword [esp + 0x58]", + "fld st0", + "fadd st0,st3", + "fstp dword [ebp + 0x8]", + "fld st1", + "fsub dword [esp + 0x10]", + "fstp dword [ebp + 0xc]", + "fld dword [esp + 0x48]", + "fadd dword [esp + 0x44]", + "fstp dword [ebp]", + "fld dword [esp + 0x50]", + "fsub dword [esp + 0x4c]", + "fstp dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x70]", + "fxch st2", + "fsub st0,st2", + "fstp dword [ebp + 0x8]", + "fstp st1", + "fld dword [esp + 0x10]", + "fadd st0,st1", + "fstp dword [ebp + 0xc]", + "fstp st0", + "fld dword [esp + 0x44]", + "fsub dword [esp + 0x48]", + "fstp dword [ebp]", + "fld dword [esp + 0x4c]", + "fadd dword [esp + 0x50]", + "fstp dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x30]", + "fld dword [esp + 0x18]", + "fadd dword [esp + 0x14]", + "fld dword [esp + 0x20]", + "fadd dword [esp + 0x1c]", + "fld dword [esp + 0x68]", + "fmul st2", + "fld dword [esp + 0x6c]", + "fmul st2", + "fsubp", + "fstp dword [ebp + 0x8]", + "fld dword [esp + 0x68]", + "fmul st1", + "fld dword [esp + 0x6c]", + "fmul st3", + "faddp", + "fstp dword [ebp + 0xc]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x58]", + "fadd dword [esp + 0x54]", + "fld dword [esp + 0x60]", + "fadd dword [esp + 0x5c]", + "fld dword [esp + 0x34]", + "fmul st2", + "fld st3", + "fmul st2", + "fsubp", + "fstp dword [ebp]", + "sub ebp,0x10", + "fld dword [esp + 0x34]", + "mov dword [esp + 0x30],ebp", + "fmul st1", + "add ecx,0x10", + "fld st3", + "add edx,0x10", + "fmul st3", + "add esi,0x10", + "add edi,0x10", + "faddp", + "sub ebx,0x10", + "fstp dword [ebp + 0x14]", + "mov ebp,dword [esp + 0x70]", + "sub ebp,0x10", + "fstp st0", + "mov dword [esp + 0x70],ebp", + "fstp st0", + "mov ebp,dword [esp + 0x24]", + "fld dword [esp + 0x14]", + "sub ebp,0x10", + "fsub dword [esp + 0x18]", + "mov dword [esp + 0x24],ebp", + "fld dword [esp + 0x1c]", + "mov ebp,dword [esp + 0x7c]", + "fsub dword [esp + 0x20]", + "dec ebp", + "fld dword [esp + 0x2c]", + "mov dword [esp + 0x7c],ebp", + "fmul st1", + "fld dword [esp + 0x28]", + "fmul st3", + "faddp", + "fstp dword [ebx + 0x18]", + "fld dword [esp + 0x28]", + "fmul st1", + "fld dword [esp + 0x2c]", + "fmul st3", + "fsubp", + "fstp dword [ebx + 0x1c]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x54]", + "fsub dword [esp + 0x58]", + "fld dword [esp + 0x5c]", + "fsub dword [esp + 0x60]", + "fld dword [esp + 0x38]", + "fmul st1", + "fld dword [esp + 0x3c]", + "fmul st3", + "faddp", + "fstp dword [ebx + 0x10]", + "fld dword [esp + 0x3c]", + "fmul st1", + "fld dword [esp + 0x38]", + "fmul st3", + "fsubp", + "fstp dword [ebx + 0x14]", + "fstp st0", + "fstp st0", + "jnz 0x08537ca0" + ], + "ExpectedArm64ASM": [ + "ldr w9, [x8, #100]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w9, w9, #0x10 (16)", + "str w9, [x8, #100]", + "ldr s2, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x6c (108)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "mov w23, #0x1", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "mov x22, #0xfffffffffffffffc", + "ldr s2, [x9, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x68 (104)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w23, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w23, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x2c (44)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w23, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w23, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x28 (40)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w23, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "mov x24, #0xfffffffffffffff8", + "ldr s2, [x9, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "ldr w9, [x9, w22, sxtw]", + "str w9, [x8, #52]", + "ldr w9, [x8, #100]", + "ldr w9, [x9]", + "str w9, [x8, #56]", + "ldr w9, [x8, #100]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "mov w25, #0x8000", + "fmov d2, x21", + "mov v2.d[1], x25", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w12, w8, #0x3c (60)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "bic w12, w12, w13", + "strb w12, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x11, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "ldr s2, [x6, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x11, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "fmov d2, x21", + "mov v2.d[1], x25", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x6, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x11, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "ldr s2, [x6, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w12, w8, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "bic w12, w12, w13", + "strb w12, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x6, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "ldr s2, [x11, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w12, w8, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "bic w12, w12, w13", + "strb w12, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w12, w8, #0x44 (68)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "bic w12, w12, w13", + "strb w12, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x11, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "fmov d2, x21", + "mov v2.d[1], x25", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x6, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w12, w8, #0x50 (80)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "bic w12, w12, w13", + "strb w12, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w12, w8, #0x54 (84)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "bic w12, w12, w13", + "strb w12, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x6, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "ldr s2, [x11, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w12, w8, #0x5c (92)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "bic w12, w12, w13", + "strb w12, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x5, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "ldr s2, [x10, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x5, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "ldr s2, [x10, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w12, w8, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "bic w12, w12, w13", + "strb w12, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x10, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w12, [x28, #1298]", + "lsl w13, w23, w20", + "orr w12, w12, w13", + "strb w12, [x28, #1298]", + "ldr s2, [x5, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x20 (32)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w12, w23, w20", + "bic w24, w24, w12", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x10, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w12, w23, w20", + "orr w24, w24, w12", + "strb w24, [x28, #1298]", + "ldr s2, [x5, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x18 (24)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x5]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x10]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x48 (72)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x5, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x10, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x4c (76)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x10]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x5]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x60 (96)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x10, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x5, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x58 (88)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w22, w11, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w22, w11, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x11]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w11, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w22, w10, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w22, w23, w22", + "orr w22, w24, w22", + "strb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w22, w10, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x10]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w10, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w22, w6, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w22, w6, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x6]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w22, w6, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #36]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w22, w5, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w22, w5, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x5]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w22, w5, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #48]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #36]", + "ldr s2, [x9, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #48]", + "fmov d2, x21", + "mov v2.d[1], x25", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x9, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #36]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #48]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #36]", + "ldr s2, [x9, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #48]", + "add w22, w8, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #36]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x44 (68)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #48]", + "fmov d2, x21", + "mov v2.d[1], x25", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #36]", + "add w22, w8, #0x50 (80)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #48]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x54 (84)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #36]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #112]", + "add w22, w8, #0x5c (92)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x7, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x9, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x7, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x7, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x20 (32)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x7, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x18 (24)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x7]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x48 (72)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x7, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x4c (76)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x7]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x60 (96)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #36]", + "ldr s2, [x7, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x58 (88)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w9, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w9, #0xc (12)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x9]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w9, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w9, [x8, #112]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w9, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w21, w23, w21", + "orr w21, w22, w21", + "strb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w9, #0xc (12)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x9]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w9, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w9, [x8, #48]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w9, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w9, #0xc (12)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x9]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w9, w9, #0x10 (16)", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "str w9, [x8, #48]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w5, w5, #0x10 (16)", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add w6, w6, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w10, w10, #0x10 (16)", + "add w11, w11, #0x10 (16)", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w7, w7, #0x10 (16)", + "add w21, w9, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w9, [x8, #112]", + "sub w9, w9, #0x10 (16)", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "str w9, [x8, #112]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w9, [x8, #36]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "subs w9, w9, #0x10 (16)", + "cfinv", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "str w9, [x8, #36]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr w9, [x8, #124]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "cset w21, hs", + "mov x27, x9", + "subs w26, w9, #0x1 (1)", + "rmif x21, #63, #nzCv", + "mov x9, x26", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "str w9, [x8, #124]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w7, #0x18 (24)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w7, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w7, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w7, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "b.ne #+0x1c", + "ldr x0, pc+8", + "blr x0", + "unallocated (Unallocated)", + "udf #0x7f", + "unallocated (Unallocated)", + "udf #0x0" + ] + }, + "Block5": { + "ExpectedInstructionCount": 12237, + "x86Insts": [ + "mov ebp,dword [esp + 0x64]", + "fadd dword [ebp + 0x8]", + "add ebp,0x10", + "mov dword [esp + 0x64],ebp", + "fmul dword [esp + 0x74]", + "fstp dword [esp + 0x6c]", + "fld dword [esp + 0x34]", + "fadd dword [ebp + -0x4]", + "fmul dword [esp + 0x74]", + "fstp dword [esp + 0x68]", + "fld dword [esp + 0x38]", + "fadd dword [ebp]", + "fmul dword [esp + 0x78]", + "fstp dword [esp + 0x30]", + "fld dword [esp + 0x3c]", + "fsub dword [ebp + 0x4]", + "fmul dword [esp + 0x78]", + "fstp dword [esp + 0x2c]", + "fld dword [ebp + -0x8]", + "mov ebp,dword [ebp + -0x4]", + "mov dword [esp + 0x34],ebp", + "mov ebp,dword [esp + 0x64]", + "mov ebp,dword [ebp]", + "mov dword [esp + 0x38],ebp", + "mov ebp,dword [esp + 0x64]", + "fld dword [ebp + 0x4]", + "fchs", + "fstp dword [esp + 0x3c]", + "fld dword [edx + -0x8]", + "fadd dword [edi + -0x8]", + "fld dword [edi + -0x4]", + "fadd dword [edx + -0x4]", + "fld dword [edi + -0x8]", + "fsub dword [edx + -0x8]", + "fstp dword [esp + 0x18]", + "fld dword [edi + -0x4]", + "fsub dword [edx + -0x4]", + "fstp dword [esp + 0x1c]", + "fld dword [edi]", + "fadd dword [edx]", + "fstp dword [esp + 0x44]", + "fld dword [edi + 0x4]", + "fadd dword [edx + 0x4]", + "fstp dword [esp + 0x4c]", + "fld dword [edi]", + "fsub dword [edx]", + "fstp dword [esp + 0x58]", + "fld dword [edi + 0x4]", + "fsub dword [edx + 0x4]", + "fstp dword [esp + 0x5c]", + "fld dword [ecx + -0x8]", + "fadd dword [esi + -0x8]", + "fld dword [ecx + -0x4]", + "fadd dword [esi + -0x4]", + "fstp dword [esp + 0x10]", + "fld dword [esi + -0x8]", + "fsub dword [ecx + -0x8]", + "fstp dword [esp + 0x20]", + "fld dword [esi + -0x4]", + "fsub dword [ecx + -0x4]", + "fstp dword [esp + 0x14]", + "fld dword [ecx]", + "fadd dword [esi]", + "fstp dword [esp + 0x48]", + "fld dword [ecx + 0x4]", + "fadd dword [esi + 0x4]", + "fstp dword [esp + 0x50]", + "fld dword [esi]", + "fsub dword [ecx]", + "fstp dword [esp + 0x60]", + "fld dword [esi + 0x4]", + "fsub dword [ecx + 0x4]", + "fstp dword [esp + 0x54]", + "fld st0", + "fadd st0,st3", + "fstp dword [edi + -0x8]", + "fld dword [esp + 0x10]", + "fadd st0,st2", + "fstp dword [edi + -0x4]", + "fld dword [esp + 0x48]", + "fadd dword [esp + 0x44]", + "fstp dword [edi]", + "fld dword [esp + 0x50]", + "fadd dword [esp + 0x4c]", + "fstp dword [edi + 0x4]", + "fxch st2", + "fsub st0,st2", + "fstp dword [esi + -0x8]", + "fstp st1", + "fsub dword [esp + 0x10]", + "fstp dword [esi + -0x4]", + "fld dword [esp + 0x44]", + "fsub dword [esp + 0x48]", + "fstp dword [esi]", + "fld dword [esp + 0x4c]", + "fsub dword [esp + 0x50]", + "fstp dword [esi + 0x4]", + "fld dword [esp + 0x18]", + "fsub dword [esp + 0x14]", + "fld dword [esp + 0x20]", + "fadd dword [esp + 0x1c]", + "fld dword [esp + 0x6c]", + "fmul st2", + "fld dword [esp + 0x68]", + "fmul st2", + "fsubp", + "fstp dword [edx + -0x8]", + "fld dword [esp + 0x6c]", + "fmul st1", + "fld dword [esp + 0x68]", + "fmul st3", + "faddp", + "fstp dword [edx + -0x4]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x58]", + "fsub dword [esp + 0x54]", + "fld dword [esp + 0x60]", + "fadd dword [esp + 0x5c]", + "fld st2", + "fmul st2", + "fld dword [esp + 0x34]", + "fmul st2", + "fsubp", + "fstp dword [edx]", + "fld st2", + "fmul st1", + "fld dword [esp + 0x34]", + "fmul st3", + "faddp", + "fstp dword [edx + 0x4]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x14]", + "fadd dword [esp + 0x18]", + "fld dword [esp + 0x1c]", + "fsub dword [esp + 0x20]", + "fld dword [esp + 0x2c]", + "fmul st1", + "fld dword [esp + 0x30]", + "fmul st3", + "faddp", + "mov ebp,dword [esp + 0x24]", + "fstp dword [ecx + -0x8]", + "fld dword [esp + 0x30]", + "fmul st1", + "fld dword [esp + 0x2c]", + "fmul st3", + "fsubp", + "fstp dword [ecx + -0x4]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x54]", + "fadd dword [esp + 0x58]", + "fld dword [esp + 0x5c]", + "fsub dword [esp + 0x60]", + "fld dword [esp + 0x3c]", + "fmul st1", + "fld dword [esp + 0x38]", + "fmul st3", + "faddp", + "fstp dword [ecx]", + "fld dword [esp + 0x38]", + "fmul st1", + "fld dword [esp + 0x3c]", + "fmul st3", + "fsubp", + "fstp dword [ecx + 0x4]", + "fstp st0", + "fstp st0", + "fld dword [ebp + 0x8]", + "mov ebp,dword [esp + 0x28]", + "fadd dword [ebp + 0x8]", + "mov ebp,dword [esp + 0x24]", + "fld dword [ebp + 0xc]", + "mov ebp,dword [esp + 0x28]", + "fadd dword [ebp + 0xc]", + "mov ebp,dword [esp + 0x24]", + "fld dword [ebp + 0x8]", + "mov ebp,dword [esp + 0x28]", + "fsub dword [ebp + 0x8]", + "mov ebp,dword [esp + 0x24]", + "fstp dword [esp + 0x18]", + "fld dword [ebp + 0xc]", + "mov ebp,dword [esp + 0x28]", + "fsub dword [ebp + 0xc]", + "mov ebp,dword [esp + 0x24]", + "fstp dword [esp + 0x1c]", + "fld dword [ebp]", + "mov ebp,dword [esp + 0x28]", + "fadd dword [ebp]", + "mov ebp,dword [esp + 0x24]", + "fstp dword [esp + 0x44]", + "fld dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x28]", + "fadd dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x24]", + "fstp dword [esp + 0x4c]", + "fld dword [ebp]", + "mov ebp,dword [esp + 0x28]", + "fsub dword [ebp]", + "mov ebp,dword [esp + 0x24]", + "fstp dword [esp + 0x58]", + "fld dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x28]", + "fsub dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x70]", + "fstp dword [esp + 0x5c]", + "fld dword [ebp + 0x8]", + "fadd dword [ebx + 0x8]", + "fld dword [ebp + 0xc]", + "fadd dword [ebx + 0xc]", + "fstp dword [esp + 0x10]", + "fld dword [ebp + 0x8]", + "fsub dword [ebx + 0x8]", + "fstp dword [esp + 0x20]", + "fld dword [ebp + 0xc]", + "fsub dword [ebx + 0xc]", + "fstp dword [esp + 0x14]", + "fld dword [ebx]", + "fadd dword [ebp]", + "fstp dword [esp + 0x48]", + "fld dword [ebp + 0x4]", + "fadd dword [ebx + 0x4]", + "fstp dword [esp + 0x50]", + "fld dword [ebp]", + "fsub dword [ebx]", + "fstp dword [esp + 0x60]", + "fld dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x24]", + "fsub dword [ebx + 0x4]", + "fstp dword [esp + 0x54]", + "fld st0", + "fadd st0,st3", + "fstp dword [ebp + 0x8]", + "fld dword [esp + 0x10]", + "fadd st0,st2", + "fstp dword [ebp + 0xc]", + "fld dword [esp + 0x48]", + "fadd dword [esp + 0x44]", + "fstp dword [ebp]", + "fld dword [esp + 0x50]", + "fadd dword [esp + 0x4c]", + "fstp dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x70]", + "fxch st2", + "fsub st0,st2", + "fstp dword [ebp + 0x8]", + "fstp st1", + "fsub dword [esp + 0x10]", + "fstp dword [ebp + 0xc]", + "fld dword [esp + 0x44]", + "fsub dword [esp + 0x48]", + "fstp dword [ebp]", + "fld dword [esp + 0x4c]", + "fsub dword [esp + 0x50]", + "fstp dword [ebp + 0x4]", + "mov ebp,dword [esp + 0x28]", + "fld dword [esp + 0x18]", + "fsub dword [esp + 0x14]", + "fld dword [esp + 0x20]", + "fadd dword [esp + 0x1c]", + "fld dword [esp + 0x68]", + "fmul st2", + "fld dword [esp + 0x6c]", + "fmul st2", + "fsubp", + "fstp dword [ebp + 0x8]", + "fld dword [esp + 0x68]", + "fmul st1", + "fld dword [esp + 0x6c]", + "fmul st3", + "faddp", + "fstp dword [ebp + 0xc]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x58]", + "fsub dword [esp + 0x54]", + "fld dword [esp + 0x60]", + "fadd dword [esp + 0x5c]", + "fld dword [esp + 0x34]", + "fmul st2", + "fld st3", + "fmul st2", + "fsubp", + "fstp dword [ebp]", + "fld dword [esp + 0x34]", + "fmul st1", + "fld st3", + "fmul st3", + "sub ebp,0x10", + "mov dword [esp + 0x28],ebp", + "add ecx,0x10", + "faddp", + "add edx,0x10", + "add esi,0x10", + "fstp dword [ebp + 0x14]", + "mov ebp,dword [esp + 0x70]", + "sub ebp,0x10", + "fstp st0", + "mov dword [esp + 0x70],ebp", + "fstp st0", + "mov ebp,dword [esp + 0x24]", + "fld dword [esp + 0x14]", + "sub ebp,0x10", + "fadd dword [esp + 0x18]", + "mov dword [esp + 0x24],ebp", + "fld dword [esp + 0x1c]", + "mov ebp,dword [esp + 0x7c]", + "fsub dword [esp + 0x20]", + "add edi,0x10", + "fld dword [esp + 0x30]", + "sub ebx,0x10", + "dec ebp", + "fmul st1", + "mov dword [esp + 0x7c],ebp", + "fld dword [esp + 0x2c]", + "fmul st3", + "faddp", + "fstp dword [ebx + 0x18]", + "fld dword [esp + 0x2c]", + "fmul st1", + "fld dword [esp + 0x30]", + "fmul st3", + "fsubp", + "fstp dword [ebx + 0x1c]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x54]", + "fadd dword [esp + 0x58]", + "fld dword [esp + 0x5c]", + "fsub dword [esp + 0x60]", + "fld dword [esp + 0x38]", + "fmul st1", + "fld dword [esp + 0x3c]", + "fmul st3", + "faddp", + "fstp dword [ebx + 0x10]", + "fld dword [esp + 0x3c]", + "fmul st1", + "fld dword [esp + 0x38]", + "fmul st3", + "fsubp", + "fstp dword [ebx + 0x14]", + "fstp st0", + "fstp st0", + "jnz 0x08537433" + ], + "ExpectedArm64ASM": [ + "ldr w9, [x8, #100]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w9, w9, #0x10 (16)", + "str w9, [x8, #100]", + "ldr s2, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x6c (108)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "mov w23, #0x1", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "mov x22, #0xfffffffffffffffc", + "ldr s2, [x9, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x68 (104)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w23, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w23, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x30 (48)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w23, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w23, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x2c (44)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w23, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "mov x24, #0xfffffffffffffff8", + "ldr s2, [x9, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "ldr w9, [x9, w22, sxtw]", + "str w9, [x8, #52]", + "ldr w9, [x8, #100]", + "ldr w9, [x9]", + "str w9, [x8, #56]", + "ldr w9, [x8, #100]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "mov w25, #0x8000", + "fmov d2, x21", + "mov v2.d[1], x25", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w25, w8, #0x3c (60)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x25]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "bic w25, w25, w12", + "strb w25, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x6, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "ldr s2, [x11, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x11, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "ldr s2, [x6, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x11, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "ldr s2, [x6, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w25, w8, #0x18 (24)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x25]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "bic w25, w25, w12", + "strb w25, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x11, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "ldr s2, [x6, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w25, w8, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x25]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "bic w25, w25, w12", + "strb w25, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w25, w8, #0x44 (68)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x25]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "bic w25, w25, w12", + "strb w25, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x11, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "ldr s2, [x6, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w25, w8, #0x4c (76)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x25]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "bic w25, w25, w12", + "strb w25, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x11]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w25, w8, #0x58 (88)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x25]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "bic w25, w25, w12", + "strb w25, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x11, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "ldr s2, [x6, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w25, w8, #0x5c (92)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x25]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "bic w25, w25, w12", + "strb w25, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x5, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "ldr s2, [x10, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x5, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "ldr s2, [x10, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w25, w8, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x25]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "bic w25, w25, w12", + "strb w25, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x10, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w12, w23, w20", + "orr w25, w25, w12", + "strb w25, [x28, #1298]", + "ldr s2, [x5, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x20 (32)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w23, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x10, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w23, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x5, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x5]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x10]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x48 (72)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x5, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x10, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x50 (80)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x10]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x5]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x60 (96)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x10, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x5, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x54 (84)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w22, w11, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w22, w11, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x11]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w11, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w22, w10, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w22, w23, w22", + "orr w22, w24, w22", + "strb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w22, w10, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x10]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w10, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w22, w6, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w22, w6, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x6]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w22, w6, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w9, [x8, #36]", + "sub w22, w5, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w22, w5, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x5]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w22, w5, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #40]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #36]", + "ldr s2, [x9, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #40]", + "ldr s2, [x9, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #36]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #40]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #36]", + "add w22, w8, #0x18 (24)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #40]", + "ldr s2, [x9, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #36]", + "add w22, w8, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #40]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #36]", + "add w22, w8, #0x44 (68)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #40]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #36]", + "add w22, w8, #0x4c (76)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #40]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #36]", + "add w22, w8, #0x58 (88)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #40]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr w9, [x8, #112]", + "add w22, w8, #0x5c (92)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x7, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x9, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x7, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x7, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x20 (32)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x7, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x7]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x48 (72)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x7, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x50 (80)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x7]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x60 (96)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x9, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr w9, [x8, #36]", + "ldr s2, [x7, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w8, #0x54 (84)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w9, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w9, #0xc (12)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x9]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "orr w22, w22, w24", + "strb w22, [x28, #1298]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w22, w9, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldrb w22, [x28, #1298]", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w9, [x8, #112]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w9, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w21, w23, w21", + "orr w21, w22, w21", + "strb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w9, #0xc (12)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #68]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #72]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x9]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #76]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #80]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w9, #0x4 (4)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w9, [x8, #40]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w9, #0x8 (8)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #104]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #108]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w9, #0xc (12)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x9]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w9, w9, #0x10 (16)", + "str w9, [x8, #40]", + "add w5, w5, #0x10 (16)", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w6, w6, #0x10 (16)", + "add w10, w10, #0x10 (16)", + "add w21, w9, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w9, [x8, #112]", + "sub w9, w9, #0x10 (16)", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "str w9, [x8, #112]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w9, [x8, #36]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "sub w9, w9, #0x10 (16)", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "str w9, [x8, #36]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr w9, [x8, #124]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w11, w11, #0x10 (16)", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "subs w7, w7, #0x10 (16)", + "cfinv", + "cset w21, hs", + "mov x27, x9", + "subs w26, w9, #0x1 (1)", + "rmif x21, #63, #nzCv", + "mov x9, x26", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "str w9, [x8, #124]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w7, #0x18 (24)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w7, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #84]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #88]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #92]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #96]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w7, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "orr w21, w21, w22", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w7, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w22, w23, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "b.ne #+0x1c", + "ldr x0, pc+8", + "blr x0", + "unallocated (Unallocated)", + "udf #0x7f", + "unallocated (Unallocated)", + "udf #0x0" + ] + }, + "Block6": { + "ExpectedInstructionCount": 8104, + "x86Insts": [ + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x30]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0xc]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x34]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x1c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x38]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x2c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x3c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x3c]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x30]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x30]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x8]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x34]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x18]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x38]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x28]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x3c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x38]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x2c]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x30]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x4]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x34]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x14]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x38]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x24]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x3c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x34]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x28]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x30]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x34]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x10]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x38]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x20]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x3c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x30]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x24]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x20]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0xc]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x24]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x1c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x28]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x2c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x2c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x3c]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x20]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x20]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x8]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x24]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x18]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x28]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x28]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x2c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x38]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x1c]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x20]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x4]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x24]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x14]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x28]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x24]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x2c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x34]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x18]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x20]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x24]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x10]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x28]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x20]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x2c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x30]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x14]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x10]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0xc]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x14]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x1c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x18]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x2c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x1c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x3c]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x10]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x10]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x8]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x14]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x18]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x18]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x28]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x1c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x38]", + "fmulp", + "faddp", + "fstp dword [ebp + -0xc]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x10]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x4]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x14]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x14]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x18]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x24]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x1c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x34]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x10]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x14]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x10]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x18]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x20]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x1c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x30]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0xc]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x4]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x1c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x8]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x2c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0xc]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x3c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x8]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x4]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x18]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x8]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x28]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0xc]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x38]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x4]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x4]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x14]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x8]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x24]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0xc]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x34]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x4]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x10]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x8]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x20]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0xc]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x30]", + "fmulp", + "faddp", + "fld dword [ebp + -0x30]", + "fstp dword [esp + 0x40]", + "fld dword [ebp + -0x2c]", + "fstp dword [esp + 0x3c]", + "fld dword [ebp + -0x28]", + "fstp dword [esp + 0x38]", + "fld dword [ebp + -0x24]", + "fstp dword [esp + 0x34]", + "fld dword [ebp + -0x20]", + "fstp dword [esp + 0x30]", + "fld dword [ebp + -0x1c]", + "fstp dword [esp + 0x2c]", + "fld dword [ebp + -0x18]", + "fstp dword [esp + 0x28]", + "fld dword [ebp + -0x14]", + "fstp dword [esp + 0x24]", + "fld dword [ebp + -0x10]", + "fstp dword [esp + 0x20]", + "fld dword [ebp + -0xc]", + "fstp dword [esp + 0x1c]", + "fxch st5", + "fstp dword [esp + 0x18]", + "fxch st3", + "fstp dword [esp + 0x14]", + "fxch", + "fstp dword [esp + 0x10]", + "fstp dword [esp + 0xc]", + "fstp dword [esp + 0x8]", + "fstp dword [esp + 0x4]", + "mov dword [esp],ebx", + "call 0x0818d57a" + ], + "ExpectedArm64ASM": [ + "ldr w4, [x9, #16]", + "ldr s2, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s3, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x20, #0xffffffffffffffd0", + "sub w21, w9, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldr w4, [x9, #16]", + "ldr s2, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s3, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x21, #0xffffffffffffffd4", + "sub w22, w9, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr w4, [x9, #16]", + "ldr s2, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s3, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x22, #0xffffffffffffffd8", + "sub w23, w9, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldr w4, [x9, #16]", + "ldr s2, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x23, #0xffffffffffffffdc", + "sub w24, w9, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldr w4, [x9, #16]", + "ldr s2, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s3, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x24, #0xffffffffffffffe0", + "sub w25, w9, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x25]", + "ldr w4, [x9, #16]", + "ldr s2, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s3, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x25, #0xffffffffffffffe4", + "sub w12, w9, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldr w4, [x9, #16]", + "ldr s2, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s3, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x12, #0xffffffffffffffe8", + "sub w13, w9, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x13]", + "ldr w4, [x9, #16]", + "ldr s2, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x13, #0xffffffffffffffec", + "sub w14, w9, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x14]", + "ldr w4, [x9, #16]", + "ldr s2, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s3, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x14, #0xfffffffffffffff0", + "sub w15, w9, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x15]", + "ldr w4, [x9, #16]", + "ldr s2, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s3, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x15, #0xfffffffffffffff4", + "sub w16, w9, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr w4, [x9, #16]", + "ldr s2, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s3, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s3, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s4, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s4, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s5, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s4, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s5, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s4, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s5, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s4, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s5, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s5, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s6, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s5, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s6, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s5, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s6, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s5, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s6, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s6, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s7, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s6, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s7, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s6, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s7, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s6, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s7, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s7, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s8, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s7, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s8, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s7, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s8, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s7, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s8, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s8, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s9, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s8, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s9, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x9, #16]", + "ldr s8, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr w4, [x9, #12]", + "ldr s9, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x9, w20, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x9, w21, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x9, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x9, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x9, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x9, w25, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x9, w12, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x9, w13, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x9, w14, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x9, w15, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w8, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "mov w20, #0x0", + "add w21, w8, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w8, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "strb w20, [x28, #1017]", + "add w21, w8, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w8, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w8, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w8, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "str w7, [x8]", + "mov w21, #0x26fe", + "movk w21, #0x1, lsl #16", + "mov w22, #0xd118", + "movk w22, #0x818, lsl #16", + "add w22, w21, w22", + "str w21, [x8, #-4]!", + "strb w20, [x28, #1298]", + "ldr x0, [x28, #2304]", + "and x3, x22, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block7": { + "ExpectedInstructionCount": 8116, + "x86Insts": [ + "push ebp", + "mov ebp,esp", + "push ebx", + "sub esp,0x84", + "mov ebx,dword [ebp + 0x8]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x30]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0xc]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x34]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x1c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x38]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x2c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x3c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x3c]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x30]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x30]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x8]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x34]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x18]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x38]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x28]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x3c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x38]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x2c]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x30]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x4]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x34]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x14]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x38]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x24]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x3c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x34]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x28]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x30]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x34]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x10]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x38]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x20]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x3c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x30]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x24]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x20]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0xc]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x24]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x1c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x28]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x2c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x2c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x3c]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x20]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x20]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x8]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x24]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x18]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x28]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x28]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x2c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x38]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x1c]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x20]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x4]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x24]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x14]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x28]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x24]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x2c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x34]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x18]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x20]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x24]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x10]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x28]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x20]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x2c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x30]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x14]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x10]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0xc]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x14]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x1c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x18]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x2c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x1c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x3c]", + "fmulp", + "faddp", + "fstp dword [ebp + -0x10]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x10]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x8]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x14]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x18]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x18]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x28]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x1c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x38]", + "fmulp", + "faddp", + "fstp dword [ebp + -0xc]", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x10]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x4]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x14]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x14]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x18]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x24]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x1c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x34]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x10]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x14]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x10]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x18]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x20]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x1c]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x30]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0xc]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x4]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x1c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x8]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x2c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0xc]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x3c]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x8]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x4]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x18]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x8]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x28]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0xc]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x38]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x4]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x4]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x14]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x8]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x24]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0xc]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x34]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax]", + "fmulp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x4]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x10]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0x8]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x20]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x10]", + "fld dword [eax + 0xc]", + "mov eax,dword [ebp + 0xc]", + "fld dword [eax + 0x30]", + "fmulp", + "faddp", + "fld dword [ebp + -0x30]", + "fstp dword [esp + 0x40]", + "fld dword [ebp + -0x2c]", + "fstp dword [esp + 0x3c]", + "fld dword [ebp + -0x28]", + "fstp dword [esp + 0x38]", + "fld dword [ebp + -0x24]", + "fstp dword [esp + 0x34]", + "fld dword [ebp + -0x20]", + "fstp dword [esp + 0x30]", + "fld dword [ebp + -0x1c]", + "fstp dword [esp + 0x2c]", + "fld dword [ebp + -0x18]", + "fstp dword [esp + 0x28]", + "fld dword [ebp + -0x14]", + "fstp dword [esp + 0x24]", + "fld dword [ebp + -0x10]", + "fstp dword [esp + 0x20]", + "fld dword [ebp + -0xc]", + "fstp dword [esp + 0x1c]", + "fxch st5", + "fstp dword [esp + 0x18]", + "fxch st3", + "fstp dword [esp + 0x14]", + "fxch", + "fstp dword [esp + 0x10]", + "fstp dword [esp + 0xc]", + "fstp dword [esp + 0x8]", + "fstp dword [esp + 0x4]", + "mov dword [esp],ebx", + "call 0x0818d57a", + "mov eax,ebx", + "add esp,0x84", + "pop ebx", + "pop ebp", + "ret 0x4" + ], + "ExpectedArm64ASM": [ + "str w9, [x8, #-4]!", + "mov x9, x8", + "mov w20, w8", + "str w7, [x20, #-4]!", + "mov x21, x8", + "mov x8, x20", + "mov x27, x20", + "subs w26, w20, #0x84 (132)", + "cfinv", + "mov x8, x26", + "ldr w7, [x21, #8]", + "ldr w4, [x21, #16]", + "ldr s2, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s3, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x20, #0xffffffffffffffd0", + "sub w22, w21, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x22]", + "ldr w4, [x21, #16]", + "ldr s2, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s3, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x22, #0xffffffffffffffd4", + "sub w23, w21, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldr w4, [x21, #16]", + "ldr s2, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s3, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x23, #0xffffffffffffffd8", + "sub w24, w21, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldr w4, [x21, #16]", + "ldr s2, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x24, #0xffffffffffffffdc", + "sub w25, w21, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x25]", + "ldr w4, [x21, #16]", + "ldr s2, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s3, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x25, #0xffffffffffffffe0", + "sub w12, w21, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x12]", + "ldr w4, [x21, #16]", + "ldr s2, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s3, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x12, #0xffffffffffffffe4", + "sub w13, w21, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x13]", + "ldr w4, [x21, #16]", + "ldr s2, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s3, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x13, #0xffffffffffffffe8", + "sub w14, w21, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x14]", + "ldr w4, [x21, #16]", + "ldr s2, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x14, #0xffffffffffffffec", + "sub w15, w21, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x15]", + "ldr w4, [x21, #16]", + "ldr s2, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s3, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x15, #0xfffffffffffffff0", + "sub w16, w21, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x16]", + "ldr w4, [x21, #16]", + "ldr s2, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s3, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x16, #0xfffffffffffffff4", + "sub w17, w21, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x17]", + "ldr w4, [x21, #16]", + "ldr s2, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s3, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s3, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s4, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s4, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s5, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s4, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s5, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s4, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s5, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s4, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s5, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s5, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s6, [x4, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s5, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s6, [x4, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s5, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s6, [x4, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "mov x3, v5.d[0]", + "umov w4, v5.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s5, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s5", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s6, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s6, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s7, [x4, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s6, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s7, [x4, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s6, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s7, [x4, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "mov x3, v6.d[0]", + "umov w4, v6.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s6, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s6", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s7, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s7, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s8, [x4, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s7, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s8, [x4, #36]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s7, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s8, [x4, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "mov x3, v7.d[0]", + "umov w4, v7.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v6.16b, v6.16b, v6.16b", + "mov v6.d[0], x0", + "mov v6.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s7, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s7", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s8, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s8, [x4, #4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s9, [x4, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s8, [x4, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s9, [x4, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr w4, [x21, #16]", + "ldr s8, [x4, #12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "ldr w4, [x21, #12]", + "ldr s9, [x4, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s9", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v9.16b, v9.16b, v9.16b", + "mov v9.d[0], x0", + "mov v9.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "mov x3, v9.d[0]", + "umov w4, v9.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "mov x3, v8.d[0]", + "umov w4, v8.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v7.16b, v7.16b, v7.16b", + "mov v7.d[0], x0", + "mov v7.h[4], w1", + "ldr s8, [x21, w20, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w26, #0x40 (64)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x21, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w26, #0x3c (60)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x21, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w26, #0x38 (56)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x21, w24, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w26, #0x34 (52)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x21, w25, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w26, #0x30 (48)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x21, w12, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w26, #0x2c (44)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x21, w13, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w26, #0x28 (40)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x21, w14, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w26, #0x24 (36)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x21, w15, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w26, #0x20 (32)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "ldr s8, [x21, w16, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s8", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v8.16b, v8.16b, v8.16b", + "mov v8.d[0], x0", + "mov v8.h[4], w1", + "add w20, w26, #0x1c (28)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v8.d[0]", + "umov w2, v8.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s8, s0", + "str s8, [x20]", + "mov w20, #0x0", + "add w21, w26, #0x18 (24)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w26, #0x14 (20)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "strb w20, [x28, #1017]", + "add w21, w26, #0x10 (16)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v4.d[0]", + "umov w2, v4.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w26, #0xc (12)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v5.d[0]", + "umov w2, v5.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w26, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v6.d[0]", + "umov w2, v6.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "add w21, w26, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v7.d[0]", + "umov w2, v7.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "str w7, [x26]", + "mov w21, #0x2c09", + "movk w21, #0x1, lsl #16", + "mov w22, #0xd10b", + "movk w22, #0x818, lsl #16", + "add w22, w21, w22", + "mov w8, w26", + "str w21, [x8, #-4]!", + "strb w20, [x28, #1298]", + "ldr x0, [x28, #2304]", + "and x3, x22, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block8": { + "ExpectedInstructionCount": 8511, + "x86Insts": [ + "fadd dword [esp + 0x40]", + "lea edx,[ecx + ecx*0x2]", + "lea esi,[edx + ecx*0x2]", + "lea ebx,[ecx + -0x2]", + "fmul dword [esp + 0x74]", + "fld dword [esp + 0x34]", + "lea edi,[esi + ecx*0x2]", + "fadd dword [esp + 0x40]", + "fmul dword [esp + 0x74]", + "fld dword [esp + 0x38]", + "fsub dword [esp + 0x40]", + "fmul dword [esp + 0x78]", + "fstp dword [esp + 0x2c]", + "fld dword [esp + 0x3c]", + "fsub dword [esp + 0x40]", + "fmul dword [esp + 0x78]", + "fstp dword [esp + 0x28]", + "fld dword [eax + esi*0x4 + -0x8]", + "fadd dword [eax + ebx*0x4]", + "fld dword [eax + ecx*0x4 + -0x4]", + "fchs", + "fsub dword [eax + esi*0x4 + -0x4]", + "fld dword [eax + ebx*0x4]", + "fsub dword [eax + esi*0x4 + -0x8]", + "fstp dword [esp + 0x14]", + "fld dword [eax + esi*0x4 + -0x4]", + "fsub dword [eax + ecx*0x4 + -0x4]", + "fstp dword [esp + 0x1c]", + "fld dword [eax + edx*0x4 + -0x8]", + "fadd dword [eax + edi*0x4 + -0x8]", + "fld dword [eax + edx*0x4 + -0x4]", + "fadd dword [eax + edi*0x4 + -0x4]", + "fstp dword [esp + 0x10]", + "fld dword [eax + edx*0x4 + -0x8]", + "fsub dword [eax + edi*0x4 + -0x8]", + "fstp dword [esp + 0x20]", + "fld dword [eax + edx*0x4 + -0x4]", + "fsub dword [eax + edi*0x4 + -0x4]", + "fstp dword [esp + 0x18]", + "fld st0", + "fadd st0,st3", + "fstp dword [eax + ebx*0x4]", + "fld st1", + "fsub dword [esp + 0x10]", + "fstp dword [eax + ecx*0x4 + -0x4]", + "fxch st2", + "fsub st0,st2", + "fstp dword [eax + edx*0x4 + -0x8]", + "fstp st1", + "fld dword [esp + 0x10]", + "fadd st0,st1", + "fstp dword [eax + edx*0x4 + -0x4]", + "fstp st0", + "fld dword [esp + 0x18]", + "fadd dword [esp + 0x14]", + "fld dword [esp + 0x20]", + "fadd dword [esp + 0x1c]", + "fld st3", + "fmul st2", + "fld st3", + "fmul st2", + "fsubp", + "fstp dword [eax + esi*0x4 + -0x8]", + "fld st3", + "fmul st1", + "fld st3", + "fmul st3", + "faddp", + "fstp dword [eax + esi*0x4 + -0x4]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x18]", + "fld dword [esp + 0x1c]", + "fsub dword [esp + 0x20]", + "fld dword [esp + 0x28]", + "fmul st1", + "fld dword [esp + 0x2c]", + "fmul st3", + "faddp", + "fstp dword [eax + edi*0x4 + -0x8]", + "fld dword [esp + 0x2c]", + "fmul st1", + "fld dword [esp + 0x28]", + "fmul st3", + "fsubp", + "fstp dword [eax + edi*0x4 + -0x4]", + "fstp st0", + "fstp st0", + "fld dword [eax + ecx*0x4]", + "fadd dword [eax + esi*0x4]", + "fld dword [eax + ecx*0x4 + 0x4]", + "fchs", + "fsub dword [eax + esi*0x4 + 0x4]", + "fld dword [eax + ecx*0x4]", + "fsub dword [eax + esi*0x4]", + "fstp dword [esp + 0x14]", + "fld dword [eax + esi*0x4 + 0x4]", + "fsub dword [eax + ecx*0x4 + 0x4]", + "fstp dword [esp + 0x1c]", + "fld dword [eax + edi*0x4]", + "fadd dword [eax + edx*0x4]", + "fld dword [eax + edx*0x4 + 0x4]", + "fadd dword [eax + edi*0x4 + 0x4]", + "fstp dword [esp + 0x10]", + "fld dword [eax + edx*0x4]", + "fsub dword [eax + edi*0x4]", + "fstp dword [esp + 0x20]", + "fld dword [eax + edx*0x4 + 0x4]", + "fsub dword [eax + edi*0x4 + 0x4]", + "fstp dword [esp + 0x18]", + "fld st0", + "fadd st0,st3", + "fstp dword [eax + ecx*0x4]", + "fld st1", + "fsub dword [esp + 0x10]", + "fstp dword [eax + ecx*0x4 + 0x4]", + "fxch st2", + "fsub st0,st2", + "fstp dword [eax + edx*0x4]", + "fstp st1", + "fld dword [esp + 0x10]", + "fadd st0,st1", + "fstp dword [eax + edx*0x4 + 0x4]", + "fstp st0", + "fld dword [esp + 0x18]", + "fadd dword [esp + 0x14]", + "fld dword [esp + 0x20]", + "fadd dword [esp + 0x1c]", + "fld st1", + "fsub st0,st1", + "fmul dword [esp + 0x40]", + "fstp dword [eax + esi*0x4]", + "fadd st0,st1", + "fmul dword [esp + 0x40]", + "fstp dword [eax + esi*0x4 + 0x4]", + "fstp st0", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x18]", + "fld dword [esp + 0x1c]", + "fsub dword [esp + 0x20]", + "fld dword [esp + 0x40]", + "fchs", + "fld st1", + "fadd st0,st3", + "fmul st1", + "fstp dword [eax + edi*0x4]", + "fxch", + "fsub st0,st2", + "fmul st1", + "fstp dword [eax + edi*0x4 + 0x4]", + "fstp st0", + "fstp st0", + "fld dword [eax + ecx*0x4 + 0x8]", + "fadd dword [eax + esi*0x4 + 0x8]", + "fld dword [eax + ecx*0x4 + 0xc]", + "fchs", + "fsub dword [eax + esi*0x4 + 0xc]", + "fld dword [eax + ecx*0x4 + 0x8]", + "fsub dword [eax + esi*0x4 + 0x8]", + "fstp dword [esp + 0x14]", + "fld dword [eax + esi*0x4 + 0xc]", + "fsub dword [eax + ecx*0x4 + 0xc]", + "fstp dword [esp + 0x1c]", + "fld dword [eax + edi*0x4 + 0x8]", + "fadd dword [eax + edx*0x4 + 0x8]", + "fld dword [eax + edx*0x4 + 0xc]", + "fadd dword [eax + edi*0x4 + 0xc]", + "fstp dword [esp + 0x10]", + "fld dword [eax + edx*0x4 + 0x8]", + "fsub dword [eax + edi*0x4 + 0x8]", + "fstp dword [esp + 0x20]", + "fld dword [eax + edx*0x4 + 0xc]", + "fsub dword [eax + edi*0x4 + 0xc]", + "fstp dword [esp + 0x18]", + "fld st0", + "fadd st0,st3", + "fstp dword [eax + ecx*0x4 + 0x8]", + "fld st1", + "fsub dword [esp + 0x10]", + "fstp dword [eax + ecx*0x4 + 0xc]", + "fxch st2", + "fsub st0,st2", + "fstp dword [eax + edx*0x4 + 0x8]", + "fstp st1", + "fld dword [esp + 0x10]", + "fadd st0,st1", + "fstp dword [eax + edx*0x4 + 0xc]", + "fstp st0", + "fld dword [esp + 0x18]", + "fadd dword [esp + 0x14]", + "fld dword [esp + 0x20]", + "fadd dword [esp + 0x1c]", + "fld st2", + "fmul st2", + "fld st4", + "fmul st2", + "fsubp", + "fstp dword [eax + esi*0x4 + 0x8]", + "fxch st2", + "fmul st2", + "fxch st3", + "fmul st1", + "faddp st3,st0", + "fxch st2", + "fstp dword [eax + esi*0x4 + 0xc]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x14]", + "fsub dword [esp + 0x18]", + "fld dword [esp + 0x1c]", + "fsub dword [esp + 0x20]", + "fld dword [esp + 0x2c]", + "fmul st1", + "fld dword [esp + 0x28]", + "fmul st3", + "faddp", + "fstp dword [eax + edi*0x4 + 0x8]", + "fld dword [esp + 0x28]", + "fmul st1", + "fld dword [esp + 0x2c]", + "fmul st3", + "fsubp", + "fstp dword [eax + edi*0x4 + 0xc]", + "pop edi", + "pop esi", + "fstp st0", + "pop ebp", + "fstp st0", + "pop ebx", + "add esp,0x74", + "ret" + ], + "ExpectedArm64ASM": [ + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w6, w5, w5, lsl #1", + "add w10, w6, w5, lsl #1", + "sub w7, w5, #0x2 (2)", + "ldr s2, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w22, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w11, w10, w5, lsl #1", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x2c (44)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x28 (40)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, w7, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w23, w4, #0x4 (4)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "mov w23, #0x8000", + "fmov d2, x21", + "mov v2.d[1], x23", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w24, w4, #0x4 (4)", + "add w24, w24, w10, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, w7, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "sub w24, w4, #0x8 (8)", + "add w24, w24, w10, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w24, w4, #0x4 (4)", + "add w24, w24, w10, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "sub w24, w4, #0x4 (4)", + "add w24, w24, w5, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w24, w4, #0x8 (8)", + "add w24, w24, w6, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "sub w24, w4, #0x8 (8)", + "add w24, w24, w11, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w24, w4, #0x4 (4)", + "add w24, w24, w6, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "sub w24, w4, #0x4 (4)", + "add w24, w24, w11, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w24, w4, #0x8 (8)", + "add w24, w24, w6, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "sub w24, w4, #0x8 (8)", + "add w24, w24, w11, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x20 (32)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w24, w4, #0x4 (4)", + "add w24, w24, w6, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "sub w24, w4, #0x4 (4)", + "add w24, w24, w11, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x18 (24)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x3 (3)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, w7, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w24, w4, #0x4 (4)", + "add w24, w24, w5, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x2 (2)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w24, w4, #0x8 (8)", + "add w24, w24, w6, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w24, w22, w24", + "orr w24, w25, w24", + "strb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w24, w4, #0x4 (4)", + "add w24, w24, w6, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w20, #0x3 (3)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x2 (2)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w20, #0x3 (3)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x2 (2)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w24, w4, #0x8 (8)", + "add w24, w24, w10, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w24, w20, #0x3 (3)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w20, #0x3 (3)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x3 (3)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w24, w4, #0x4 (4)", + "add w24, w24, w10, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x3 (3)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w24, w4, #0x8 (8)", + "add w24, w24, w11, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x3 (3)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w24, w4, #0x4 (4)", + "add w24, w24, w11, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w24, w4, w5, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add w24, w4, w10, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, #0x4 (4)", + "add w24, w24, w5, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "fmov d2, x21", + "mov v2.d[1], x23", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, #0x4 (4)", + "add w24, w24, w10, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, w5, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add w24, w4, w10, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w24, w4, #0x4 (4)", + "add w24, w24, w10, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add w24, w4, #0x4 (4)", + "add w24, w24, w5, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w24, w4, w11, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add w24, w4, w6, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, #0x4 (4)", + "add w24, w24, w6, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add w24, w4, #0x4 (4)", + "add w24, w24, w11, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w24, w4, w6, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add w24, w4, w11, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x20 (32)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w24, w4, #0x4 (4)", + "add w24, w24, w6, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add w24, w4, #0x4 (4)", + "add w24, w24, w11, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w8, #0x18 (24)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x3 (3)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, w5, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, #0x4 (4)", + "add w24, w24, w5, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x2 (2)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, w6, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "ldrb w25, [x28, #1298]", + "lsl w24, w22, w24", + "orr w24, w25, w24", + "strb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, #0x4 (4)", + "add w24, w24, w6, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, w10, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, #0x4 (4)", + "add w24, w24, w10, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "fmov d2, x21", + "mov v2.d[1], x23", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x3 (3)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, w11, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w25, w20, #0x2 (2)", + "and w25, w25, #0x7", + "add x0, x28, x25, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, #0x4 (4)", + "add w24, w24, w11, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w25, w22, w20", + "bic w24, w24, w25", + "strb w24, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w24, w4, #0x8 (8)", + "add w24, w24, w5, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "add w24, w4, #0x8 (8)", + "add w24, w24, w10, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w24, w4, #0xc (12)", + "add w24, w24, w5, lsl #2", + "ldr s2, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w25, w22, w20", + "orr w24, w24, w25", + "strb w24, [x28, #1298]", + "fmov d2, x21", + "mov v2.d[1], x23", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0xc (12)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, #0xc (12)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0xc (12)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0xc (12)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0xc (12)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x20 (32)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, #0xc (12)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0xc (12)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x18 (24)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w5, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0xc (12)", + "add w23, w23, w5, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w23, w22, w23", + "orr w23, w24, w23", + "strb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0xc (12)", + "add w23, w23, w6, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x4 (4)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add w21, w4, #0xc (12)", + "add w21, w21, w10, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w4, #0x8 (8)", + "add w21, w21, w11, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #40]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w4, #0xc (12)", + "add w21, w21, w11, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w11, [x8]", + "add x8, x8, #0x4 (4)", + "ldr w10, [x8]", + "add x8, x8, #0x4 (4)", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w9, [x8]", + "add x8, x8, #0x4 (4)", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w7, [x8]", + "add x8, x8, #0x4 (4)", + "mvn w27, w8", + "adds w26, w8, #0x74 (116)", + "mov x8, x26", + "ldr w20, [x26]", + "add w8, w26, #0x4 (4)", + "ldr x0, [x28, #2304]", + "and x3, x20, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block9": { + "ExpectedInstructionCount": 8433, + "x86Insts": [ + "fadd dword [esp + 0x40]", + "lea edx,[ecx + ecx*0x2]", + "lea esi,[edx + ecx*0x2]", + "lea ebx,[ecx + -0x2]", + "fmul dword [esp + 0x74]", + "fld dword [esp + 0x34]", + "lea edi,[esi + ecx*0x2]", + "fadd dword [esp + 0x40]", + "fmul dword [esp + 0x74]", + "fld dword [esp + 0x38]", + "fsub dword [esp + 0x40]", + "fmul dword [esp + 0x78]", + "fstp dword [esp + 0x30]", + "fld dword [esp + 0x3c]", + "fsub dword [esp + 0x40]", + "fmul dword [esp + 0x78]", + "fstp dword [esp + 0x2c]", + "fld dword [eax + esi*0x4 + -0x8]", + "fadd dword [eax + ebx*0x4]", + "fld dword [eax + ecx*0x4 + -0x4]", + "fadd dword [eax + esi*0x4 + -0x4]", + "fld dword [eax + ebx*0x4]", + "fsub dword [eax + esi*0x4 + -0x8]", + "fstp dword [esp + 0x18]", + "fld dword [eax + ecx*0x4 + -0x4]", + "fsub dword [eax + esi*0x4 + -0x4]", + "fstp dword [esp + 0x1c]", + "fld dword [eax + edi*0x4 + -0x8]", + "fadd dword [eax + edx*0x4 + -0x8]", + "fld dword [eax + edx*0x4 + -0x4]", + "fadd dword [eax + edi*0x4 + -0x4]", + "fstp dword [esp + 0x10]", + "fld dword [eax + edx*0x4 + -0x8]", + "fsub dword [eax + edi*0x4 + -0x8]", + "fstp dword [esp + 0x20]", + "fld dword [eax + edx*0x4 + -0x4]", + "fsub dword [eax + edi*0x4 + -0x4]", + "fstp dword [esp + 0x14]", + "fld st0", + "fadd st0,st3", + "fstp dword [eax + ebx*0x4]", + "fld dword [esp + 0x10]", + "fadd st0,st2", + "fstp dword [eax + ecx*0x4 + -0x4]", + "fxch st2", + "fsub st0,st2", + "fstp dword [eax + edx*0x4 + -0x8]", + "fstp st1", + "fsub dword [esp + 0x10]", + "fstp dword [eax + edx*0x4 + -0x4]", + "fld dword [esp + 0x18]", + "fsub dword [esp + 0x14]", + "fld dword [esp + 0x20]", + "fadd dword [esp + 0x1c]", + "fld st3", + "fmul st2", + "fld st3", + "fmul st2", + "fsubp", + "fstp dword [eax + esi*0x4 + -0x8]", + "fld st3", + "fmul st1", + "fld st3", + "fmul st3", + "faddp", + "fstp dword [eax + esi*0x4 + -0x4]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x14]", + "fadd dword [esp + 0x18]", + "fld dword [esp + 0x1c]", + "fsub dword [esp + 0x20]", + "fld dword [esp + 0x2c]", + "fmul st1", + "fld dword [esp + 0x30]", + "fmul st3", + "faddp", + "fstp dword [eax + edi*0x4 + -0x8]", + "fld dword [esp + 0x30]", + "fmul st1", + "fld dword [esp + 0x2c]", + "fmul st3", + "fsubp", + "fstp dword [eax + edi*0x4 + -0x4]", + "fstp st0", + "fstp st0", + "fld dword [eax + ecx*0x4]", + "fadd dword [eax + esi*0x4]", + "fld dword [eax + ecx*0x4 + 0x4]", + "fadd dword [eax + esi*0x4 + 0x4]", + "fld dword [eax + ecx*0x4]", + "fsub dword [eax + esi*0x4]", + "fstp dword [esp + 0x18]", + "fld dword [eax + ecx*0x4 + 0x4]", + "fsub dword [eax + esi*0x4 + 0x4]", + "fstp dword [esp + 0x1c]", + "fld dword [eax + edx*0x4]", + "fadd dword [eax + edi*0x4]", + "fld dword [eax + edx*0x4 + 0x4]", + "fadd dword [eax + edi*0x4 + 0x4]", + "fstp dword [esp + 0x10]", + "fld dword [eax + edx*0x4]", + "fsub dword [eax + edi*0x4]", + "fstp dword [esp + 0x20]", + "fld dword [eax + edx*0x4 + 0x4]", + "fsub dword [eax + edi*0x4 + 0x4]", + "fstp dword [esp + 0x14]", + "fld st0", + "fadd st0,st3", + "fstp dword [eax + ecx*0x4]", + "fld dword [esp + 0x10]", + "fadd st0,st2", + "fstp dword [eax + ecx*0x4 + 0x4]", + "fxch st2", + "fsub st0,st2", + "fstp dword [eax + edx*0x4]", + "fstp st1", + "fsub dword [esp + 0x10]", + "fstp dword [eax + edx*0x4 + 0x4]", + "fld dword [esp + 0x18]", + "fsub dword [esp + 0x14]", + "fld dword [esp + 0x20]", + "fadd dword [esp + 0x1c]", + "fld st1", + "fsub st0,st1", + "fmul dword [esp + 0x40]", + "fstp dword [eax + esi*0x4]", + "fadd st0,st1", + "fmul dword [esp + 0x40]", + "fstp dword [eax + esi*0x4 + 0x4]", + "fstp st0", + "fld dword [esp + 0x14]", + "fadd dword [esp + 0x18]", + "fld dword [esp + 0x1c]", + "fsub dword [esp + 0x20]", + "fld dword [esp + 0x40]", + "fchs", + "fld st1", + "fadd st0,st3", + "fmul st1", + "fstp dword [eax + edi*0x4]", + "fxch", + "fsub st0,st2", + "fmul st1", + "fstp dword [eax + edi*0x4 + 0x4]", + "fstp st0", + "fstp st0", + "fld dword [eax + ecx*0x4 + 0x8]", + "fadd dword [eax + esi*0x4 + 0x8]", + "fld dword [eax + ecx*0x4 + 0xc]", + "fadd dword [eax + esi*0x4 + 0xc]", + "fld dword [eax + ecx*0x4 + 0x8]", + "fsub dword [eax + esi*0x4 + 0x8]", + "fstp dword [esp + 0x18]", + "fld dword [eax + ecx*0x4 + 0xc]", + "fsub dword [eax + esi*0x4 + 0xc]", + "fstp dword [esp + 0x1c]", + "fld dword [eax + edi*0x4 + 0x8]", + "fadd dword [eax + edx*0x4 + 0x8]", + "fld dword [eax + edi*0x4 + 0xc]", + "fadd dword [eax + edx*0x4 + 0xc]", + "fstp dword [esp + 0x10]", + "fld dword [eax + edx*0x4 + 0x8]", + "fsub dword [eax + edi*0x4 + 0x8]", + "fstp dword [esp + 0x20]", + "fld dword [eax + edx*0x4 + 0xc]", + "fsub dword [eax + edi*0x4 + 0xc]", + "fstp dword [esp + 0x14]", + "fld st0", + "fadd st0,st3", + "fstp dword [eax + ecx*0x4 + 0x8]", + "fld dword [esp + 0x10]", + "fadd st0,st2", + "fstp dword [eax + ecx*0x4 + 0xc]", + "fxch st2", + "fsub st0,st2", + "fstp dword [eax + edx*0x4 + 0x8]", + "fstp st1", + "fsub dword [esp + 0x10]", + "fstp dword [eax + edx*0x4 + 0xc]", + "fld dword [esp + 0x18]", + "fsub dword [esp + 0x14]", + "fld dword [esp + 0x20]", + "fadd dword [esp + 0x1c]", + "fld st2", + "fmul st2", + "fld st4", + "fmul st2", + "fsubp", + "fstp dword [eax + esi*0x4 + 0x8]", + "fxch st2", + "fmul st2", + "fxch st3", + "fmul st1", + "faddp st3,st0", + "fxch st2", + "fstp dword [eax + esi*0x4 + 0xc]", + "fstp st0", + "fstp st0", + "fld dword [esp + 0x14]", + "fadd dword [esp + 0x18]", + "fld dword [esp + 0x1c]", + "fsub dword [esp + 0x20]", + "fld dword [esp + 0x30]", + "fmul st1", + "fld dword [esp + 0x2c]", + "fmul st3", + "faddp", + "fstp dword [eax + edi*0x4 + 0x8]", + "fld dword [esp + 0x2c]", + "fmul st1", + "fld dword [esp + 0x30]", + "fmul st3", + "fsubp", + "fstp dword [eax + edi*0x4 + 0xc]", + "pop edi", + "pop esi", + "fstp st0", + "pop ebp", + "fstp st0", + "pop ebx", + "add esp,0x74", + "ret" + ], + "ExpectedArm64ASM": [ + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w6, w5, w5, lsl #1", + "add w10, w6, w5, lsl #1", + "sub w7, w5, #0x2 (2)", + "ldr s2, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #52]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w22, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w11, w10, w5, lsl #1", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #116]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #56]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x30 (48)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #60]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #120]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x2c (44)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, w7, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w23, w4, #0x4 (4)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "sub w23, w4, #0x4 (4)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, w7, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "sub w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x18 (24)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w23, w4, #0x4 (4)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "sub w23, w4, #0x4 (4)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w23, w4, #0x8 (8)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "sub w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w23, w4, #0x4 (4)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "sub w23, w4, #0x4 (4)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "sub w23, w4, #0x8 (8)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x20 (32)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w23, w4, #0x4 (4)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "sub w23, w4, #0x4 (4)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, w7, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w23, w4, #0x4 (4)", + "add w23, w23, w5, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w23, w22, w23", + "orr w23, w24, w23", + "strb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "sub w23, w4, #0x4 (4)", + "add w23, w23, w6, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w23, w4, #0x4 (4)", + "add w23, w23, w10, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w23, w4, #0x8 (8)", + "add w23, w23, w11, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "sub w23, w4, #0x4 (4)", + "add w23, w23, w11, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, w5, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, w5, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x18 (24)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x20 (32)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, w5, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w5, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, w6, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w23, w22, w23", + "orr w23, w24, w23", + "strb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w6, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, w10, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w10, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #64]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "mov w23, #0x8000", + "fmov d2, x21", + "mov v2.d[1], x23", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, w11, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x2 (2)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0x4 (4)", + "add w23, w23, w11, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0xc (12)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0xc (12)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x18 (24)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, #0xc (12)", + "add w23, w23, w5, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0xc (12)", + "add w23, w23, w10, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0xc (12)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0xc (12)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x10 (16)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x20 (32)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, #0xc (12)", + "add w23, w23, w6, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add w23, w4, #0xc (12)", + "add w23, w23, w11, lsl #2", + "ldr s2, [x23]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w8, #0x14 (20)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w5, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0xc (12)", + "add w23, w23, w5, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w6, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w24, [x28, #1298]", + "lsl w23, w22, w23", + "orr w23, w24, w23", + "strb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #16]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w4, #0xc (12)", + "add w23, w23, w6, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x4 (4)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w23, w23, w24", + "strb w23, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w23, w4, #0x8 (8)", + "add w23, w23, w10, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x3 (3)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w24, w20, #0x1 (1)", + "and w24, w24, #0x7", + "add x0, x28, x24, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w23, w23, w24", + "strb w23, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w23, w20, #0x2 (2)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "add x0, x28, x23, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]", + "add w21, w4, #0xc (12)", + "add w21, w21, w10, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #20]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #28]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1298]", + "ldr s2, [x8, #32]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w4, #0x8 (8)", + "add w21, w21, w11, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr s2, [x8, #44]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldr s2, [x8, #48]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add w21, w4, #0xc (12)", + "add w21, w21, w11, lsl #2", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x21]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w11, [x8]", + "add x8, x8, #0x4 (4)", + "ldr w10, [x8]", + "add x8, x8, #0x4 (4)", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w9, [x8]", + "add x8, x8, #0x4 (4)", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "ldr w7, [x8]", + "add x8, x8, #0x4 (4)", + "mvn w27, w8", + "adds w26, w8, #0x74 (116)", + "mov x8, x26", + "ldr w20, [x26]", + "add w8, w26, #0x4 (4)", + "ldr x0, [x28, #2304]", + "and x3, x20, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + }, + "Block10": { + "ExpectedInstructionCount": 6385, + "x86Insts": [ + "push ebp", + "mov ebp,esp", + "sub esp,0x14", + "mov eax,dword [ebp + 0x8]", + "add eax,0x78", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x38", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x8]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x7c", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x3c", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x4]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x78", + "mov edx,dword [ebp + 0x8]", + "add edx,0x78", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x38", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x7c", + "mov edx,dword [ebp + 0x8]", + "add edx,0x7c", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x3c", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "lea edx,[eax + 0x38]", + "mov eax,dword [ebp + -0x8]", + "mov dword [edx],eax", + "mov eax,dword [ebp + 0x8]", + "lea edx,[eax + 0x3c]", + "mov eax,dword [ebp + -0x4]", + "mov dword [edx],eax", + "mov eax,dword [ebp + 0x8]", + "add eax,0x70", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x30", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x8]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x74", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x34", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x4]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x70", + "mov edx,dword [ebp + 0x8]", + "add edx,0x70", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x30", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x74", + "mov edx,dword [ebp + 0x8]", + "add edx,0x74", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x34", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x30", + "fld dword [ebp + -0x8]", + "fld dword [0x08553140]", + "fmulp", + "fld dword [ebp + -0x4]", + "fld dword [0x08553144]", + "fmulp", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x34", + "fld dword [ebp + -0x8]", + "fld dword [0x08553148]", + "fmulp", + "fld dword [ebp + -0x4]", + "fld dword [0x08553140]", + "fmulp", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x68", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x28", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x8]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x6c", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x2c", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x4]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x68", + "mov edx,dword [ebp + 0x8]", + "add edx,0x68", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x28", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x6c", + "mov edx,dword [ebp + 0x8]", + "add edx,0x6c", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x2c", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x28", + "fld dword [ebp + -0x8]", + "fsub dword [ebp + -0x4]", + "fld dword [0x0855313c]", + "fmulp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x2c", + "fld dword [ebp + -0x8]", + "fadd dword [ebp + -0x4]", + "fld dword [0x0855313c]", + "fmulp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x60", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x20", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x8]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x64", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x24", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x4]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x60", + "mov edx,dword [ebp + 0x8]", + "add edx,0x60", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x20", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x64", + "mov edx,dword [ebp + 0x8]", + "add edx,0x64", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x24", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x20", + "fld dword [ebp + -0x8]", + "fld dword [0x08553148]", + "fmulp", + "fld dword [ebp + -0x4]", + "fld dword [0x0855314c]", + "fmulp", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x24", + "fld dword [ebp + -0x4]", + "fld dword [0x08553148]", + "fmulp", + "fld dword [ebp + -0x8]", + "fld dword [0x08553140]", + "fmulp", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x58", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x18", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x8]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x1c", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x5c", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x4]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x58", + "mov edx,dword [ebp + 0x8]", + "add edx,0x58", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x18", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x5c", + "mov edx,dword [ebp + 0x8]", + "add edx,0x5c", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x1c", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "lea edx,[eax + 0x18]", + "mov eax,dword [ebp + -0x4]", + "mov dword [edx],eax", + "mov eax,dword [ebp + 0x8]", + "lea edx,[eax + 0x1c]", + "mov eax,dword [ebp + -0x8]", + "mov dword [edx],eax", + "mov eax,dword [ebp + 0x8]", + "add eax,0x10", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x50", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x8]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x14", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x54", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x4]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x50", + "mov edx,dword [ebp + 0x8]", + "add edx,0x50", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x10", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x54", + "mov edx,dword [ebp + 0x8]", + "add edx,0x54", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x14", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x10", + "fld dword [ebp + -0x4]", + "fld dword [0x08553140]", + "fmulp", + "fld dword [ebp + -0x8]", + "fld dword [0x08553148]", + "fmulp", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x14", + "fld dword [ebp + -0x4]", + "fld dword [0x08553148]", + "fmulp", + "fld dword [ebp + -0x8]", + "fld dword [0x0855314c]", + "fmulp", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x8", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x48", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x8]", + "mov eax,dword [ebp + 0x8]", + "add eax,0xc", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x4c", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x4]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x48", + "mov edx,dword [ebp + 0x8]", + "add edx,0x48", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x8", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x4c", + "mov edx,dword [ebp + 0x8]", + "add edx,0x4c", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0xc", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x8", + "fld dword [ebp + -0x4]", + "fadd dword [ebp + -0x8]", + "fld dword [0x0855313c]", + "fmulp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0xc", + "fld dword [ebp + -0x4]", + "fsub dword [ebp + -0x8]", + "fld dword [0x0855313c]", + "fmulp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x40", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x8]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x4", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x44", + "fld dword [eax]", + "fsubp", + "fstp dword [ebp + -0x4]", + "mov eax,dword [ebp + 0x8]", + "lea edx,[eax + 0x40]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x40", + "fld dword [eax]", + "mov eax,dword [ebp + 0x8]", + "fld dword [eax]", + "faddp", + "fstp dword [edx]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x44", + "mov edx,dword [ebp + 0x8]", + "add edx,0x44", + "fld dword [edx]", + "mov edx,dword [ebp + 0x8]", + "add edx,0x4", + "fld dword [edx]", + "faddp", + "fstp dword [eax]", + "fld dword [ebp + -0x4]", + "fld dword [0x08553148]", + "fmulp", + "fld dword [ebp + -0x8]", + "fld dword [0x08553140]", + "fmulp", + "faddp", + "mov eax,dword [ebp + 0x8]", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "add eax,0x4", + "fld dword [ebp + -0x4]", + "fld dword [0x08553140]", + "fmulp", + "fld dword [ebp + -0x8]", + "fld dword [0x08553144]", + "fmulp", + "faddp", + "fstp dword [eax]", + "mov eax,dword [ebp + 0x8]", + "mov dword [esp],eax", + "call 0x0816de98", + "mov eax,dword [ebp + 0x8]", + "add eax,0x40", + "mov dword [esp],eax", + "call 0x0816de98", + "leave", + "ret" + ], + "ExpectedArm64ASM": [ + "str w9, [x8, #-4]!", + "mov x9, x8", + "sub w20, w8, #0x14 (20)", + "mov x21, x8", + "mov x8, x20", + "ldr w4, [x21, #8]", + "add w4, w4, #0x78 (120)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x38 (56)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x22, #0xfffffffffffffff8", + "sub w23, w21, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x23]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x7c (124)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x3c (60)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x23, #0xfffffffffffffffc", + "sub w24, w21, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x78 (120)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x78 (120)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x38 (56)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x7c (124)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x7c (124)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x3c (60)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w6, w4, #0x38 (56)", + "ldr w4, [x21, w22, sxtw]", + "str w4, [x6]", + "ldr w4, [x21, #8]", + "add w6, w4, #0x3c (60)", + "ldr w4, [x21, w23, sxtw]", + "str w4, [x6]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x70 (112)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x30 (48)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w24, w21, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x74 (116)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x34 (52)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w24, w21, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x24]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x70 (112)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x70 (112)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x30 (48)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x74 (116)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x74 (116)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x34 (52)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x30 (48)", + "ldr s2, [x21, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w24, #0x3140", + "movk w24, #0x855, lsl #16", + "ldr s3, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x21, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mov w25, #0x3144", + "movk w25, #0x855, lsl #16", + "ldr s4, [x25]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x34 (52)", + "ldr s2, [x21, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w12, #0x3148", + "movk w12, #0x855, lsl #16", + "ldr s3, [x12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x21, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x68 (104)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x28 (40)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w13, w21, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x13]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x6c (108)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x2c (44)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w13, w21, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x13]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x68 (104)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x68 (104)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x28 (40)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x6c (108)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x6c (108)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x2c (44)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x28 (40)", + "ldr s2, [x21, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x21, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w13, #0x313c", + "movk w13, #0x855, lsl #16", + "ldr s3, [x13]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x2c (44)", + "ldr s2, [x21, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x21, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x13]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x60 (96)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x20 (32)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w14, w21, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x14]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x64 (100)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x24 (36)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w14, w21, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x14]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x60 (96)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x60 (96)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x20 (32)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x64 (100)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x64 (100)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x24 (36)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x20 (32)", + "ldr s2, [x21, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x21, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mov w14, #0x314c", + "movk w14, #0x855, lsl #16", + "ldr s4, [x14]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x24 (36)", + "ldr s2, [x21, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x21, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x58 (88)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x18 (24)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w15, w21, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x15]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x1c (28)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x5c (92)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w15, w21, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x15]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x58 (88)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x58 (88)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x18 (24)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x5c (92)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x5c (92)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x1c (28)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w6, w4, #0x18 (24)", + "ldr w4, [x21, w23, sxtw]", + "str w4, [x6]", + "ldr w4, [x21, #8]", + "add w6, w4, #0x1c (28)", + "ldr w4, [x21, w22, sxtw]", + "str w4, [x6]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x10 (16)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x50 (80)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w15, w21, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x15]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x14 (20)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x54 (84)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w15, w21, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x15]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x50 (80)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x50 (80)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x10 (16)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x54 (84)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x54 (84)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x14 (20)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x10 (16)", + "ldr s2, [x21, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x21, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x14 (20)", + "ldr s2, [x21, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x21, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x14]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x8 (8)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x48 (72)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w14, w21, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x14]", + "ldr w4, [x21, #8]", + "add w4, w4, #0xc (12)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x4c (76)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w14, w21, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x14]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x48 (72)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x48 (72)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x8 (8)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x4c (76)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x4c (76)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0xc (12)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x8 (8)", + "ldr s2, [x21, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x21, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x13]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "add w4, w4, #0xc (12)", + "ldr s2, [x21, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x21, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x13]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x40 (64)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w13, w21, #0x8 (8)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x13]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x4 (4)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "add w4, w4, #0x44 (68)", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1672]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "sub w13, w21, #0x4 (4)", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x13]", + "ldr w4, [x21, #8]", + "add w6, w4, #0x40 (64)", + "ldr w4, [x21, #8]", + "add w4, w4, #0x40 (64)", + "ldr s2, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "ldr s3, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x6]", + "ldr w4, [x21, #8]", + "add w4, w4, #0x44 (68)", + "ldr w6, [x21, #8]", + "add w6, w6, #0x44 (68)", + "ldr s2, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w6, [x21, #8]", + "add w6, w6, #0x4 (4)", + "ldr s3, [x6]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr s2, [x21, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x12]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x21, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr w4, [x21, #8]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x4]", + "ldr w4, [x21, #8]", + "mov x27, x4", + "adds w26, w4, #0x4 (4)", + "mov x4, x26", + "ldr s2, [x21, w23, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s2", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x24]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldr s3, [x21, w22, sxtw]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s3", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "ldr s4, [x25]", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "fmov s0, s4", + "ldrh w0, [x28, #1296]", + "ldr x1, [x28, #1424]", + "blr x1", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1680]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1664]", + "blr x5", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #1000]", + "stp x4, x5, [x28, #280]", + "stp x6, x7, [x28, #296]", + "str x8, [x28, #312]", + "sub sp, sp, #0x80 (128)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "str x16, [x0], #16", + "stp x17, x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1440]", + "blr x3", + "ldr w4, [x28, #1000]", + "msr nzcv, x4", + "ldp x4, x5, [x28, #280]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x16, [sp], #16", + "ldp x17, x30, [sp], #16", + "fmov s2, s0", + "str s2, [x26]", + "ldr w4, [x21, #8]", + "str w4, [x20]", + "mov w21, #0x380a", + "movk w21, #0x1, lsl #16", + "mov w22, #0xda1c", + "movk w22, #0x816, lsl #16", + "add w22, w21, w22", + "mov w8, w20", + "str w21, [x8, #-4]!", + "ldrb w20, [x28, #1019]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1298]", + "mov w23, #0x1", + "lsl w20, w23, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1298]", + "ldr x0, [x28, #2304]", + "and x3, x22, #0xfffff", + "add x0, x0, x3, lsl #4", + "ldp x1, x0, [x0]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index 2c0051b9e1..fe0bb1d3a6 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -19,7 +19,6 @@ "0xd8 !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -48,6 +47,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -62,10 +62,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -90,7 +90,6 @@ "0xd8 !11b /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -119,6 +118,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -133,10 +133,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -161,7 +161,6 @@ "0xd8 !11b /2" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -190,6 +189,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -220,16 +221,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcomp dword [rax]": { @@ -238,7 +238,6 @@ "0xd8 !11b /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -267,6 +266,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -296,17 +297,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -323,7 +323,6 @@ "0xd8 !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -352,6 +351,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -394,7 +394,6 @@ "0xd8 !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -423,6 +422,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -465,7 +465,6 @@ "0xd8 !11b /6" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -494,6 +493,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -536,7 +536,6 @@ "0xd8 !11b /7" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -565,6 +564,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -602,15 +602,13 @@ ] }, "fadd st0, st0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "0xd8 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -626,10 +624,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -644,7 +642,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -655,11 +653,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -673,10 +671,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -702,11 +700,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -720,10 +718,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -749,11 +747,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -767,10 +765,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -796,11 +794,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -814,10 +812,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -843,11 +841,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -861,10 +859,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -890,11 +888,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -908,10 +906,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -937,11 +935,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -955,10 +953,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -978,15 +976,13 @@ ] }, "fmul st0, st0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "0xd8 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -1002,10 +998,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1020,7 +1016,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -1031,11 +1027,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1049,10 +1045,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1078,11 +1074,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1096,10 +1092,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1125,11 +1121,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1143,10 +1139,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1172,11 +1168,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1190,10 +1186,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1219,11 +1215,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1237,10 +1233,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1266,11 +1262,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1284,10 +1280,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1313,11 +1309,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1331,11 +1327,11 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1680]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", "msr nzcv, x4", @@ -1354,16 +1350,14 @@ ] }, "fcom st0, st0": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 43, "Comment": [ "0xd8 11b 0xd0 /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -1379,10 +1373,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1413,10 +1407,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1431,10 +1426,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1447,16 +1442,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcom st0, st2": { @@ -1466,10 +1460,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1484,10 +1479,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1500,16 +1495,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcom st0, st3": { @@ -1519,10 +1513,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1537,10 +1532,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1553,16 +1548,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcom st0, st4": { @@ -1572,10 +1566,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1590,10 +1585,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1606,16 +1601,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcom st0, st5": { @@ -1625,10 +1619,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1643,10 +1638,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1659,16 +1654,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcom st0, st6": { @@ -1678,10 +1672,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1696,10 +1691,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1712,16 +1707,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcom st0, st7": { @@ -1731,10 +1725,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1749,10 +1744,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1765,29 +1760,26 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcomp st0, st0": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 51, "Comment": [ "0xd8 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -1803,10 +1795,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1845,12 +1837,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1864,10 +1857,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1879,20 +1872,19 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "mov x23, x0", + "ubfx x24, x23, #1, #1", + "ubfx x25, x23, #0, #1", + "ubfx x23, x23, #2, #1", + "orr w24, w24, w23", + "orr w25, w25, w23", + "strb w24, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w23, [x28, #1018]", + "strb w25, [x28, #1022]", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -1906,11 +1898,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1924,13 +1917,13 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1560]", - "blr x5", - "ldr w4, [x28, #1000]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1560]", + "blr x5", + "ldr w4, [x28, #1000]", "msr nzcv, x4", "ldp x4, x5, [x28, #280]", "ldp x6, x7, [x28, #296]", @@ -1939,17 +1932,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -1967,11 +1959,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1985,10 +1978,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -2000,17 +1993,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -2028,11 +2020,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2046,10 +2039,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -2061,17 +2054,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -2089,11 +2081,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2107,10 +2100,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -2122,17 +2115,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -2150,11 +2142,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2168,10 +2161,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -2183,17 +2176,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -2211,11 +2203,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2229,10 +2222,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -2244,17 +2237,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -2266,15 +2258,13 @@ ] }, "fsub st0, st0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "0xd8 11b 0xe0 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -2308,7 +2298,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -2319,11 +2309,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2337,10 +2327,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2366,11 +2356,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2384,10 +2374,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2413,11 +2403,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2431,10 +2421,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2460,11 +2450,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2478,10 +2468,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2507,11 +2497,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2525,10 +2515,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2554,11 +2544,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2572,10 +2562,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2601,11 +2591,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2619,10 +2609,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2642,15 +2632,13 @@ ] }, "fsubr st0, st0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "0xd8 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -2666,10 +2654,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2684,7 +2672,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -3018,15 +3006,13 @@ ] }, "fdiv st0, st0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "0xd8 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -3060,7 +3046,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -3071,11 +3057,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3089,10 +3075,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3118,11 +3104,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3136,10 +3122,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3165,11 +3151,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3183,10 +3169,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3212,11 +3198,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3230,10 +3216,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3259,11 +3245,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3277,10 +3263,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3306,11 +3292,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3324,10 +3310,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3353,11 +3339,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3371,10 +3357,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3394,15 +3380,13 @@ ] }, "fdivr st0, st0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "0xd8 11b 0xf8 /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -3418,10 +3402,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3436,7 +3420,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -3775,7 +3759,6 @@ "0xd9 !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3804,16 +3787,17 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fst dword [rax]": { @@ -3901,14 +3885,15 @@ ] }, "fldenv [rax]": { - "ExpectedInstructionCount": 48, + "ExpectedInstructionCount": 50, "Comment": [ "0xd9 !11b /4" ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", "strh w20, [x28, #1296]", - "ldr w20, [x4, #4]", + "add x20, x4, #0x4 (4)", + "ldr w20, [x20]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #1019]", "ubfx w21, w20, #8, #1", @@ -3919,7 +3904,8 @@ "strb w22, [x28, #1017]", "strb w23, [x28, #1018]", "strb w20, [x28, #1022]", - "ldr w20, [x4, #8]", + "add x20, x4, #0x8 (8)", + "ldr w20, [x20]", "ubfx w21, w20, #0, #2", "mrs x22, nzcv", "cmp x21, #0x3 (3)", @@ -3967,75 +3953,81 @@ ] }, "fnstenv [rax]": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 70, "Comment": [ "0xd9 !11b /6" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1296]", - "str w20, [x4]", - "mov w20, #0x0", - "ldrb w21, [x28, #1019]", - "mov x0, x20", - "bfi x0, x21, #11, #3", - "mov x21, x0", - "ldrb w22, [x28, #1016]", - "ldrb w23, [x28, #1017]", - "ldrb w24, [x28, #1018]", - "ldrb w25, [x28, #1022]", - "orr x21, x21, x22, lsl #8", - "orr x21, x21, x23, lsl #9", - "orr x21, x21, x24, lsl #10", - "orr x21, x21, x25, lsl #14", - "str w21, [x4, #4]", - "ldrb w21, [x28, #1298]", - "and w22, w21, #0x1", - "mov w23, #0x3", - "mrs x24, nzcv", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "ldrh w22, [x28, #1296]", + "str w22, [x4]", + "add x22, x4, #0x4 (4)", + "mov x0, x21", + "bfi x0, x20, #11, #3", + "mov x20, x0", + "ldrb w23, [x28, #1016]", + "ldrb w24, [x28, #1017]", + "ldrb w25, [x28, #1018]", + "ldrb w30, [x28, #1022]", + "orr x20, x20, x23, lsl #8", + "orr x20, x20, x24, lsl #9", + "orr x20, x20, x25, lsl #10", + "orr x20, x20, x30, lsl #14", + "str w20, [x22]", + "add x20, x4, #0x8 (8)", + "ldrb w22, [x28, #1298]", + "and w23, w22, #0x1", + "mov w24, #0x3", + "mrs x25, nzcv", + "cmp x23, #0x0 (0)", + "csel x23, x24, x21, eq", + "orr w23, w21, w23", + "lsr w30, w22, #1", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #2", + "lsr w30, w22, #2", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #4", + "lsr w30, w22, #3", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #6", + "lsr w30, w22, #4", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #8", + "lsr w30, w22, #5", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #10", + "lsr w30, w22, #6", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #12", + "lsr w22, w22, #7", + "and w22, w22, #0x1", "cmp x22, #0x0 (0)", - "csel x22, x23, x20, eq", - "orr w22, w20, w22", - "lsr w25, w21, #1", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #2", - "lsr w25, w21, #2", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #4", - "lsr w25, w21, #3", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #6", - "lsr w25, w21, #4", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #8", - "lsr w25, w21, #5", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #10", - "lsr w25, w21, #6", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #12", - "lsr w21, w21, #7", - "and w21, w21, #0x1", - "cmp x21, #0x0 (0)", - "csel x21, x23, x20, eq", - "orr w21, w22, w21, lsl #14", - "str w21, [x4, #8]", - "str w20, [x4, #12]", - "str w20, [x4, #16]", - "str w20, [x4, #20]", - "str w20, [x4, #24]", - "msr nzcv, x24" + "csel x22, x24, x21, eq", + "orr w22, w23, w22, lsl #14", + "str w22, [x20]", + "add x20, x4, #0xc (12)", + "str w21, [x20]", + "add x20, x4, #0x10 (16)", + "str w21, [x20]", + "add x20, x4, #0x14 (20)", + "str w21, [x20]", + "add x20, x4, #0x18 (24)", + "str w21, [x20]", + "msr nzcv, x25" ] }, "fnstcw [rax]": { @@ -4049,26 +4041,24 @@ ] }, "fld st0": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": [ "0xd9 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st1": { @@ -4085,13 +4075,13 @@ "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st2": { @@ -4108,13 +4098,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st3": { @@ -4131,13 +4121,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st4": { @@ -4154,13 +4144,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st5": { @@ -4177,13 +4167,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st6": { @@ -4200,13 +4190,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st7": { @@ -4223,34 +4213,23 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fxch st0, st0": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 2, "Comment": [ "0xd9 11b 0xc8 /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", - "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "mov w20, #0x0", + "strb w20, [x28, #1017]" ] }, "fxch st0, st1": { @@ -4260,18 +4239,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st2": { @@ -4281,18 +4260,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st3": { @@ -4302,18 +4281,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st4": { @@ -4323,18 +4302,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st5": { @@ -4344,18 +4323,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st6": { @@ -4365,18 +4344,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st7": { @@ -4386,18 +4365,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fnop": { @@ -4413,14 +4392,14 @@ "0xd9 11b 0xe0 /4" ], "ExpectedArm64ASM": [ + "mov w20, #0x0", + "mov w21, #0x8000", + "fmov d2, x20", + "mov v2.d[1], x21", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "mov w21, #0x0", - "mov w22, #0x8000", - "fmov d3, x21", - "mov v3.d[1], x22", - "eor v2.16b, v2.16b, v3.16b", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -4431,14 +4410,14 @@ "0xd9 11b 0xe1 /4" ], "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "mov w21, #0x7fff", + "fmov d2, x20", + "mov v2.d[1], x21", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "mov x21, #0xffffffffffffffff", - "mov w22, #0x7fff", - "fmov d3, x21", - "mov v3.d[1], x22", - "and v2.16b, v2.16b, v3.16b", + "ldr q3, [x0, #1040]", + "and v2.16b, v3.16b, v2.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -4450,10 +4429,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "fmov d2, x21", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "mov w20, #0x0", - "fmov d3, x20", + "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -4466,10 +4445,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "mov x3, v3.d[0]", - "umov w4, v3.h[4]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -4481,15 +4460,15 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", + "mov x20, x0", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w22, w22, w20", + "orr w23, w23, w20", "strb w22, [x28, #1016]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]", + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]", "strb w23, [x28, #1022]" ] }, @@ -4523,18 +4502,18 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2576]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr q2, [x28, #2576]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldl2t": { @@ -4543,18 +4522,18 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2592]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr q2, [x28, #2592]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldl2e": { @@ -4563,18 +4542,18 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2608]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr q2, [x28, #2608]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldpi": { @@ -4583,18 +4562,18 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2624]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr q2, [x28, #2624]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldlg2": { @@ -4603,18 +4582,18 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2640]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr q2, [x28, #2640]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldln2": { @@ -4623,18 +4602,18 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2656]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr q2, [x28, #2656]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldz": { @@ -4643,18 +4622,18 @@ "0xd9 11b 0xee /5" ], "ExpectedArm64ASM": [ + "movi v2.2d, #0x0", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "movi v2.2d, #0x0", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "f2xm1": { @@ -4699,22 +4678,16 @@ ] }, "fyl2x": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 42, "Comment": [ "0xd9 11b 0xf1 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -4748,7 +4721,10 @@ "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fptan": { @@ -4758,16 +4734,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1298]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", - "strb w22, [x28, #1019]", + "mov w21, #0x0", + "ldr q2, [x28, #2576]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -4780,8 +4750,8 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", "ldr x3, [x28, #1600]", "blr x3", "ldr w4, [x28, #1000]", @@ -4793,35 +4763,35 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldr q3, [x28, #2576]", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "mov w22, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str q3, [x0, #1040]" + "ldrb w23, [x28, #1298]", + "lsl w20, w22, w20", + "orr w20, w23, w20", + "strb w20, [x28, #1298]", + "strb w21, [x28, #1018]" ] }, "fpatan": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 42, "Comment": [ "0xd9 11b 0xf3 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -4855,7 +4825,10 @@ "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fxtract": { @@ -4865,14 +4838,6 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1298]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", - "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", @@ -4933,8 +4898,16 @@ "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fprem1": { @@ -4944,11 +4917,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -4980,10 +4954,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fdecstp": { @@ -5017,11 +4990,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -5053,32 +5027,21 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fyl2xp1": { - "ExpectedInstructionCount": 76, + "ExpectedInstructionCount": 77, "Comment": [ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2576]", "ldrb w20, [x28, #1019]", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "ldr q4, [x28, #2576]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5093,8 +5056,8 @@ "ldrh w0, [x28, #1296]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "mov x3, v4.d[0]", - "umov w4, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -5109,6 +5072,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5140,7 +5111,10 @@ "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fsqrt": { @@ -5185,22 +5159,17 @@ ] }, "fsincos": { - "ExpectedInstructionCount": 73, + "ExpectedInstructionCount": 79, "Comment": [ "0xd9 11b 0xfb /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1298]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", - "strb w22, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5213,8 +5182,8 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", "ldr x3, [x28, #1616]", "blr x3", "ldr w4, [x28, #1000]", @@ -5229,6 +5198,20 @@ "eor v3.16b, v3.16b, v3.16b", "mov v3.d[0], x0", "mov v3.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "mov w22, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w22, w22, w20", + "orr w22, w23, w22", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5257,12 +5240,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "frndint": { @@ -5313,10 +5293,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5360,6 +5340,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", @@ -5390,10 +5371,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fcos": { @@ -5403,6 +5383,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", @@ -5433,10 +5414,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fiadd dword [rax]": { @@ -5445,8 +5425,7 @@ "0xda !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5458,7 +5437,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5474,6 +5453,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5488,10 +5468,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -5516,8 +5496,7 @@ "0xda !11b /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5529,7 +5508,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5545,6 +5524,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5559,10 +5539,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -5587,8 +5567,7 @@ "0xda !11b /2" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5600,7 +5579,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5616,6 +5595,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5646,16 +5627,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "ficomp dword [rax]": { @@ -5664,8 +5644,7 @@ "0xda !11b /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5677,7 +5656,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5693,6 +5672,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5722,17 +5703,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -5749,8 +5729,7 @@ "0xda !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5762,7 +5741,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5778,6 +5757,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5820,8 +5800,7 @@ "0xda !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5833,7 +5812,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5849,6 +5828,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5891,8 +5871,7 @@ "0xda !11b /6" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5904,7 +5883,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5920,6 +5899,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5962,8 +5942,7 @@ "0xda !11b /7" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5975,7 +5954,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5991,6 +5970,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -6028,7 +6008,7 @@ ] }, "fcmovb st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xda 11b 0xc0 /0" ], @@ -6036,13 +6016,11 @@ "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6058,11 +6036,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6078,11 +6056,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6098,11 +6076,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6118,11 +6096,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6138,11 +6116,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6158,11 +6136,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6178,17 +6156,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcmove st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xda 11b 0xc8 /1" ], @@ -6196,13 +6174,11 @@ "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6218,11 +6194,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6238,11 +6214,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6258,11 +6234,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6278,11 +6254,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6298,11 +6274,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6318,11 +6294,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6338,17 +6314,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcmovbe st0, st0": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd0 /0" ], @@ -6358,13 +6334,11 @@ "csel x20, x20, x21, eq", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6382,11 +6356,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6404,11 +6378,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6426,11 +6400,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6448,11 +6422,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6470,11 +6444,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6492,11 +6466,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6514,17 +6488,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcmovu st0, st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xda 11b 0xd8 /1" ], @@ -6537,13 +6511,11 @@ "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6565,11 +6537,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6591,11 +6563,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6617,11 +6589,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6643,11 +6615,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6669,11 +6641,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6695,11 +6667,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6721,29 +6693,30 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" ] }, "fucompp": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 59, "Comment": [ "0xda 11b 0xe9 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -6757,10 +6730,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -6772,25 +6745,25 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1298]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "mov x23, x0", + "ubfx x24, x23, #1, #1", + "ubfx x25, x23, #0, #1", + "ubfx x23, x23, #2, #1", + "orr w24, w24, w23", + "orr w25, w25, w23", + "strb w24, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w23, [x28, #1018]", + "strb w25, [x28, #1022]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "strb w20, [x28, #1019]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -6803,40 +6776,40 @@ "0xdf !11b /5" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "mov w21, #0x0", + "sxtw x20, w20", + "mrs x22, nzcv", + "cmp x20, #0x0 (0)", + "mov w23, #0x8000", + "csel x23, x23, xzr, lt", + "cneg x20, x20, mi", + "mov w24, #0x3f", + "mov x0, #0x3f", + "clz x25, x20", + "sub x25, x0, x25", + "sub x24, x24, x25", + "lsl x25, x20, x24", + "mov w30, #0x403e", + "sub x24, x30, x24", + "cmp x20, #0x0 (0)", + "csel x20, x21, x24, eq", + "orr x20, x23, x20", + "fmov d2, x25", + "fmov d3, x20", + "mov v2.d[1], v3.d[0]", + "msr nzcv, x22", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr w21, [x4]", - "mov w22, #0x0", - "sxtw x21, w21", - "mrs x23, nzcv", - "cmp x21, #0x0 (0)", - "mov w24, #0x8000", - "csel x24, x24, xzr, lt", - "cneg x21, x21, mi", - "mov w25, #0x3f", - "mov x0, #0x3f", - "clz x30, x21", - "sub x30, x0, x30", - "sub x25, x25, x30", - "lsl x30, x21, x25", - "mov w18, #0x403e", - "sub x25, x18, x25", - "cmp x21, #0x0 (0)", - "csel x21, x22, x25, eq", - "orr x21, x24, x21", - "fmov d2, x30", - "fmov d3, x21", - "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "msr nzcv, x23" + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fisttp dword [rax]": { @@ -6975,22 +6948,22 @@ "0xdb !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr q2, [x4]", + "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fstp tword [rax]": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": [ "0xdb !11b /7" ], @@ -7000,7 +6973,8 @@ "ldr q2, [x0, #1040]", "str d2, [x4]", "mov x21, v2.d[1]", - "strh w21, [x4, #8]", + "add x22, x4, #0x8 (8)", + "strh w21, [x22]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -7012,7 +6986,7 @@ ] }, "fcmovnb st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xc0 /0" ], @@ -7020,13 +6994,11 @@ "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7042,11 +7014,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7062,11 +7034,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7082,11 +7054,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7102,11 +7074,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7122,11 +7094,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7142,11 +7114,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7162,17 +7134,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcmovne st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xc8 /1" ], @@ -7180,13 +7152,11 @@ "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7202,11 +7172,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7222,11 +7192,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7242,11 +7212,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7262,11 +7232,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7282,11 +7252,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7302,11 +7272,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7322,17 +7292,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcmovnbe st0, st0": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": [ "0xdb 11b 0xd0 /2" ], @@ -7341,13 +7311,11 @@ "csel x20, x20, xzr, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7364,11 +7332,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7385,11 +7353,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7406,11 +7374,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7427,11 +7395,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7448,11 +7416,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7469,11 +7437,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7490,17 +7458,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcmovnu st0, st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xdb 11b 0xd8 /3" ], @@ -7513,13 +7481,11 @@ "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7541,11 +7507,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7567,11 +7533,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7593,11 +7559,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7619,11 +7585,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7645,11 +7611,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7671,11 +7637,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7697,11 +7663,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7724,23 +7690,21 @@ "mov w21, #0x37f", "strh w21, [x28, #1296]", "strb w20, [x28, #1019]", + "strb w20, [x28, #1298]", "strb w20, [x28, #1016]", "strb w20, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w20, [x28, #1022]", - "strb w20, [x28, #1298]" + "strb w20, [x28, #1022]" ] }, "fucomi st0, st0": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 41, "Comment": [ "0xdb 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -7756,10 +7720,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -7789,10 +7753,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -7807,10 +7771,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -7840,10 +7804,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -7858,10 +7822,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -7891,10 +7855,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -7909,10 +7873,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -7942,10 +7906,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -7960,10 +7924,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -7993,10 +7957,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8011,10 +7975,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8044,10 +8008,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8062,10 +8026,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8095,10 +8059,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8113,10 +8077,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8140,15 +8104,13 @@ ] }, "fcomi st0, st0": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 41, "Comment": [ "0xdb 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -8164,10 +8126,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8197,10 +8159,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8215,10 +8177,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8248,10 +8210,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8266,10 +8228,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8299,10 +8261,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8317,10 +8279,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8350,10 +8312,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8368,10 +8330,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8401,10 +8363,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8419,10 +8381,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8452,10 +8414,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8470,10 +8432,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8503,10 +8465,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8521,10 +8483,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8553,7 +8515,6 @@ "0xdc !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -8582,6 +8543,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8596,10 +8558,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -8624,7 +8586,6 @@ "0xdc !11b /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -8653,6 +8614,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8667,10 +8629,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -8695,7 +8657,6 @@ "0xdc !11b /2" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -8724,6 +8685,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8754,16 +8717,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcomp qword [rax]": { @@ -8772,7 +8734,6 @@ "0xdc !11b /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -8801,6 +8762,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8830,17 +8793,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -8857,7 +8819,6 @@ "0xdc !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -8886,6 +8847,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8928,7 +8890,6 @@ "0xdc !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -8957,6 +8918,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8999,7 +8961,6 @@ "0xdc !11b /6" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -9028,6 +8989,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -9070,7 +9032,6 @@ "0xdc !11b /7" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -9099,6 +9060,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -9136,7 +9098,7 @@ ] }, "db 0xdc, 0xc0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "fadd st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -9144,9 +9106,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -9162,10 +9122,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9180,7 +9140,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -9209,10 +9169,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9256,10 +9216,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9303,10 +9263,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9350,10 +9310,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9397,10 +9357,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9444,10 +9404,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9491,10 +9451,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9514,7 +9474,7 @@ ] }, "db 0xdc, 0xc8": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "fmul st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -9522,9 +9482,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -9540,10 +9498,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9558,7 +9516,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -9587,10 +9545,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9634,10 +9592,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9681,10 +9639,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9728,10 +9686,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9775,10 +9733,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9822,10 +9780,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9869,10 +9827,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9892,7 +9850,7 @@ ] }, "db 0xdc, 0xe0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "fsubr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -9900,9 +9858,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -9918,10 +9874,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -9936,7 +9892,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -9947,10 +9903,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -9965,10 +9921,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -9983,7 +9939,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -9994,10 +9950,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10012,10 +9968,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -10030,7 +9986,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10041,10 +9997,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10059,10 +10015,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -10077,7 +10033,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10088,10 +10044,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10106,10 +10062,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -10124,7 +10080,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10135,10 +10091,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10153,10 +10109,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -10171,7 +10127,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10182,10 +10138,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10200,10 +10156,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -10218,7 +10174,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10229,10 +10185,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10247,10 +10203,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -10265,12 +10221,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "db 0xdc, 0xe8": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "fsub st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -10278,9 +10234,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -10314,7 +10268,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10648,7 +10602,7 @@ ] }, "db 0xdc, 0xf0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "fdivr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -10656,9 +10610,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -10674,10 +10626,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10692,7 +10644,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10703,10 +10655,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10721,10 +10673,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10739,7 +10691,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10750,10 +10702,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10768,10 +10720,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10786,7 +10738,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10797,10 +10749,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10815,10 +10767,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10833,7 +10785,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10844,10 +10796,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10862,10 +10814,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10880,7 +10832,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10891,10 +10843,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10909,10 +10861,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10927,7 +10879,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10938,10 +10890,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10956,10 +10908,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10974,7 +10926,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10985,10 +10937,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -11003,10 +10955,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -11021,12 +10973,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "db 0xdc, 0xf8": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "fdiv st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -11034,9 +10986,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -11070,7 +11020,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -11409,7 +11359,6 @@ "0xdd !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -11438,16 +11387,17 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fisttp qword [rax]": { @@ -11581,14 +11531,15 @@ ] }, "frstor [rax]": { - "ExpectedInstructionCount": 99, + "ExpectedInstructionCount": 110, "Comment": [ "0xdd !11b /4" ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", "strh w20, [x28, #1296]", - "ldr w20, [x4, #4]", + "add x20, x4, #0x4 (4)", + "ldr w20, [x20]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #1019]", "ubfx w22, w20, #8, #1", @@ -11599,7 +11550,8 @@ "strb w23, [x28, #1017]", "strb w24, [x28, #1018]", "strb w20, [x28, #1022]", - "ldr w20, [x4, #8]", + "add x20, x4, #0x8 (8)", + "ldr w20, [x20]", "ubfx w22, w20, #0, #2", "mrs x23, nzcv", "cmp x22, #0x3 (3)", @@ -11633,177 +11585,201 @@ "cset x20, ne", "orr w20, w22, w20, lsl #7", "strb w20, [x28, #1298]", - "mov x20, #0xffffffffffffffff", - "mov w22, #0xffff", - "fmov d2, x20", - "mov v2.d[1], x22", - "ldur q3, [x4, #28]", + "add x20, x4, #0x1c (28)", + "mov x22, #0xffffffffffffffff", + "mov w24, #0xffff", + "fmov d2, x22", + "mov v2.d[1], x24", + "ldr q3, [x20]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w21, #0x1 (1)", - "and w20, w20, #0x7", - "ldur q3, [x4, #38]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr q3, [x20]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldr q3, [x4, #48]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr q3, [x20]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldur q3, [x4, #58]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr q3, [x20]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldur q3, [x4, #68]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr q3, [x20]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldur q3, [x4, #78]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr q3, [x20]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldur q3, [x4, #88]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr q3, [x20]", "and v2.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldur d2, [x4, #98]", - "ldr h3, [x4, #106]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr d2, [x20]", + "add x20, x20, #0x8 (8)", + "ldr h3, [x20]", "mov v2.h[4], v3.h[0]", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x23" ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 111, + "ExpectedInstructionCount": 126, "Comment": [ "0xdd !11b /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "ldrh w21, [x28, #1296]", - "str w21, [x4]", "mov w21, #0x0", - "mov x22, x21", - "bfi x22, x20, #11, #3", - "ldrb w23, [x28, #1016]", - "ldrb w24, [x28, #1017]", - "ldrb w25, [x28, #1018]", - "ldrb w30, [x28, #1022]", - "orr x22, x22, x23, lsl #8", - "orr x22, x22, x24, lsl #9", - "orr x22, x22, x25, lsl #10", - "orr x22, x22, x30, lsl #14", - "str w22, [x4, #4]", - "ldrb w22, [x28, #1298]", - "and w23, w22, #0x1", - "mov w24, #0x3", - "mrs x25, nzcv", + "ldrh w22, [x28, #1296]", + "str w22, [x4]", + "add x22, x4, #0x4 (4)", + "mov x23, x21", + "bfi x23, x20, #11, #3", + "ldrb w24, [x28, #1016]", + "ldrb w25, [x28, #1017]", + "ldrb w30, [x28, #1018]", + "ldrb w18, [x28, #1022]", + "orr x23, x23, x24, lsl #8", + "orr x23, x23, x25, lsl #9", + "orr x23, x23, x30, lsl #10", + "orr x23, x23, x18, lsl #14", + "str w23, [x22]", + "add x22, x4, #0x8 (8)", + "ldrb w23, [x28, #1298]", + "and w24, w23, #0x1", + "mov w25, #0x3", + "mrs x30, nzcv", + "cmp x24, #0x0 (0)", + "csel x24, x25, x21, eq", + "orr w24, w21, w24", + "lsr w18, w23, #1", + "and w18, w18, #0x1", + "cmp x18, #0x0 (0)", + "csel x18, x25, x21, eq", + "orr w24, w24, w18, lsl #2", + "lsr w18, w23, #2", + "and w18, w18, #0x1", + "cmp x18, #0x0 (0)", + "csel x18, x25, x21, eq", + "orr w24, w24, w18, lsl #4", + "lsr w18, w23, #3", + "and w18, w18, #0x1", + "cmp x18, #0x0 (0)", + "csel x18, x25, x21, eq", + "orr w24, w24, w18, lsl #6", + "lsr w18, w23, #4", + "and w18, w18, #0x1", + "cmp x18, #0x0 (0)", + "csel x18, x25, x21, eq", + "orr w24, w24, w18, lsl #8", + "lsr w18, w23, #5", + "and w18, w18, #0x1", + "cmp x18, #0x0 (0)", + "csel x18, x25, x21, eq", + "orr w24, w24, w18, lsl #10", + "lsr w18, w23, #6", + "and w18, w18, #0x1", + "cmp x18, #0x0 (0)", + "csel x18, x25, x21, eq", + "orr w24, w24, w18, lsl #12", + "lsr w23, w23, #7", + "and w23, w23, #0x1", "cmp x23, #0x0 (0)", - "csel x23, x24, x21, eq", - "orr w23, w21, w23", - "lsr w30, w22, #1", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #2", - "lsr w30, w22, #2", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #4", - "lsr w30, w22, #3", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #6", - "lsr w30, w22, #4", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #8", - "lsr w30, w22, #5", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #10", - "lsr w30, w22, #6", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #12", - "lsr w22, w22, #7", - "and w22, w22, #0x1", - "cmp x22, #0x0 (0)", - "csel x22, x24, x21, eq", - "orr w22, w23, w22, lsl #14", - "str w22, [x4, #8]", - "str w21, [x4, #12]", - "str w21, [x4, #16]", - "str w21, [x4, #20]", - "str w21, [x4, #24]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "stur q2, [x4, #28]", + "csel x23, x25, x21, eq", + "orr w23, w24, w23, lsl #14", + "str w23, [x22]", + "add x22, x4, #0xc (12)", + "str w21, [x22]", + "add x22, x4, #0x10 (16)", + "str w21, [x22]", + "add x22, x4, #0x14 (20)", + "str w21, [x22]", + "add x22, x4, #0x18 (24)", + "str w21, [x22]", + "add x22, x4, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "stur q2, [x4, #38]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "str q2, [x4, #48]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "stur q2, [x4, #58]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "stur q2, [x4, #68]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "stur q2, [x4, #78]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "stur q2, [x4, #88]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "stur d2, [x4, #98]", + "str d2, [x22]", + "add x20, x22, #0x8 (8)", "dup v2.8h, v2.h[4]", - "str h2, [x4, #106]", + "str h2, [x20]", "mov w20, #0x37f", "strh w20, [x28, #1296]", "strb w21, [x28, #1019]", + "strb w21, [x28, #1298]", "strb w21, [x28, #1016]", "strb w21, [x28, #1017]", "strb w21, [x28, #1018]", "strb w21, [x28, #1022]", - "strb w21, [x28, #1298]", - "msr nzcv, x25" + "msr nzcv, x30" ] }, "fnstsw [rax]": { @@ -11812,14 +11788,14 @@ "0xdd !11b /7" ], "ExpectedArm64ASM": [ - "mov w20, #0x0", - "ldrb w21, [x28, #1019]", - "bfi x20, x21, #11, #3", - "ldrb w21, [x28, #1016]", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "bfi x21, x20, #11, #3", + "ldrb w20, [x28, #1016]", "ldrb w22, [x28, #1017]", "ldrb w23, [x28, #1018]", "ldrb w24, [x28, #1022]", - "orr x20, x20, x21, lsl #8", + "orr x20, x21, x20, lsl #8", "orr x20, x20, x22, lsl #9", "orr x20, x20, x23, lsl #10", "orr x20, x20, x24, lsl #14", @@ -11827,18 +11803,16 @@ ] }, "ffree st0": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": [ "0xdd 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w20, w20, #0x0 (0)", - "and w20, w20, #0x7", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w20, w22, w20", - "bic w20, w21, w20", + "mov w21, #0x1", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "bic w20, w22, w20", "strb w20, [x28, #1298]" ] }, @@ -11955,24 +11929,11 @@ ] }, "fst st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 0, "Comment": [ "0xdd 11b 0xd0 /2" ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", - "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", - "strb w20, [x28, #1298]" - ] + "ExpectedArm64ASM": [] }, "fst st1": { "ExpectedInstructionCount": 12, @@ -11981,16 +11942,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "mov w21, #0x1", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", - "lsl w21, w21, w22", - "orr w20, w20, w21", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", "strb w20, [x28, #1298]" ] }, @@ -12001,16 +11962,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -12021,16 +11982,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -12041,16 +12002,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -12061,16 +12022,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -12081,16 +12042,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -12101,43 +12062,36 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, "fstp st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 11, "Comment": [ "0xdd 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w21, w23, w21", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", - "lsl w22, w23, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", + "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "bic w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fstp st1": { @@ -12147,11 +12101,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", "ldrb w23, [x28, #1298]", @@ -12173,10 +12127,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w22, [x28, #1298]", @@ -12199,10 +12153,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w22, [x28, #1298]", @@ -12225,10 +12179,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w22, [x28, #1298]", @@ -12251,10 +12205,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w22, [x28, #1298]", @@ -12277,10 +12231,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w22, [x28, #1298]", @@ -12303,10 +12257,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w22, [x28, #1298]", @@ -12323,16 +12277,14 @@ ] }, "fucom st0": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 43, "Comment": [ "0xdd 11b 0xe0 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -12348,10 +12300,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12382,10 +12334,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12400,10 +12353,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12416,16 +12369,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucom st2": { @@ -12435,10 +12387,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12453,10 +12406,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12469,16 +12422,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucom st3": { @@ -12488,10 +12440,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12506,10 +12459,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12522,16 +12475,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucom st4": { @@ -12541,10 +12493,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12559,10 +12512,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12575,16 +12528,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucom st5": { @@ -12594,10 +12546,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12612,10 +12565,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12628,16 +12581,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucom st6": { @@ -12647,10 +12599,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12665,10 +12618,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12681,16 +12634,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucom st7": { @@ -12700,10 +12652,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12718,10 +12671,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12734,29 +12687,26 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucomp st0": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 51, "Comment": [ "0xdd 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -12772,10 +12722,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12814,12 +12764,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -12833,10 +12784,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12848,20 +12799,19 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "mov x23, x0", + "ubfx x24, x23, #1, #1", + "ubfx x25, x23, #0, #1", + "ubfx x23, x23, #2, #1", + "orr w24, w24, w23", + "orr w25, w25, w23", + "strb w24, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w23, [x28, #1018]", + "strb w25, [x28, #1022]", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -12875,11 +12825,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -12893,10 +12844,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12908,17 +12859,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -12936,11 +12886,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -12954,10 +12905,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12969,17 +12920,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -12997,11 +12947,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -13015,10 +12966,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -13030,17 +12981,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -13058,11 +13008,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -13076,10 +13027,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -13091,17 +13042,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -13119,11 +13069,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -13137,10 +13088,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -13152,17 +13103,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -13180,11 +13130,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -13198,10 +13149,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -13213,17 +13164,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -13240,8 +13190,7 @@ "0xde !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13253,7 +13202,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13269,6 +13218,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13283,10 +13233,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -13311,8 +13261,7 @@ "0xde !11b /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13324,7 +13273,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13340,6 +13289,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13354,10 +13304,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -13382,8 +13332,7 @@ "0xde !11b /2" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13395,7 +13344,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13411,6 +13360,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13441,16 +13392,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "ficomp word [rax]": { @@ -13459,8 +13409,7 @@ "0xde !11b /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13472,7 +13421,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13488,6 +13437,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13511,23 +13462,22 @@ "ldr w4, [x28, #1000]", "msr nzcv, x4", "ldp x4, x5, [x28, #280]", - "ldp x6, x7, [x28, #296]", - "ldr x8, [x28, #312]", - "ldp x16, x17, [x28, #376]", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "ldp x6, x7, [x28, #296]", + "ldr x8, [x28, #312]", + "ldp x16, x17, [x28, #376]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ldr x30, [sp], #16", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -13544,8 +13494,7 @@ "0xde !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13557,7 +13506,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13573,6 +13522,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13615,8 +13565,7 @@ "0xde !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13628,7 +13577,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13644,6 +13593,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13686,8 +13636,7 @@ "0xde !11b /6" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13699,7 +13648,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13715,6 +13664,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13757,8 +13707,7 @@ "0xde !11b /7" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13770,7 +13719,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13786,6 +13735,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13823,15 +13773,13 @@ ] }, "faddp st0": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 45, "Comment": [ "0xd8 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -13847,10 +13795,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -13865,16 +13813,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st1": { @@ -13903,10 +13851,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -13921,15 +13869,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st2": { @@ -13957,10 +13905,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -13975,16 +13923,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st3": { @@ -14012,10 +13960,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -14030,16 +13978,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st4": { @@ -14067,10 +14015,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -14085,16 +14033,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st5": { @@ -14122,10 +14070,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -14140,16 +14088,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st6": { @@ -14177,10 +14125,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -14195,16 +14143,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st7": { @@ -14232,10 +14180,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -14250,28 +14198,26 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st0": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 45, "Comment": [ "0xde 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -14287,10 +14233,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14305,16 +14251,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st1": { @@ -14343,10 +14289,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14361,15 +14307,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st2": { @@ -14397,10 +14343,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14415,16 +14361,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st3": { @@ -14452,10 +14398,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14470,16 +14416,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st4": { @@ -14507,10 +14453,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14525,16 +14471,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st5": { @@ -14562,10 +14508,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14580,16 +14526,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st6": { @@ -14617,10 +14563,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14635,16 +14581,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st7": { @@ -14672,10 +14618,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14690,31 +14636,32 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fcompp": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 59, "Comment": [ "0xde 11b 0xd9 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -14728,10 +14675,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -14743,25 +14690,25 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1298]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "mov x23, x0", + "ubfx x24, x23, #1, #1", + "ubfx x25, x23, #0, #1", + "ubfx x23, x23, #2, #1", + "orr w24, w24, w23", + "orr w25, w25, w23", + "strb w24, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w23, [x28, #1018]", + "strb w25, [x28, #1022]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "strb w20, [x28, #1019]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -14769,7 +14716,7 @@ ] }, "db 0xde, 0xe0": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 45, "Comment": [ "fsubrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -14777,9 +14724,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -14795,10 +14740,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -14813,16 +14758,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st1, st0": { @@ -14832,12 +14777,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -14851,10 +14796,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -14869,15 +14814,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st2, st0": { @@ -14887,11 +14832,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -14905,10 +14850,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -14923,16 +14868,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st3, st0": { @@ -14942,11 +14887,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -14960,10 +14905,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -14978,16 +14923,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st4, st0": { @@ -14997,11 +14942,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15015,10 +14960,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -15033,16 +14978,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st5, st0": { @@ -15052,11 +14997,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15070,10 +15015,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -15088,16 +15033,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st6, st0": { @@ -15107,11 +15052,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15125,10 +15070,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -15143,16 +15088,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st7, st0": { @@ -15162,11 +15107,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15180,10 +15125,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -15198,20 +15143,20 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "db 0xde, 0xe8": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 45, "Comment": [ "fsubp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -15219,9 +15164,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -15255,16 +15198,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st1, st0": { @@ -15311,15 +15254,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st2, st0": { @@ -15365,16 +15308,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st3, st0": { @@ -15420,16 +15363,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st4, st0": { @@ -15475,16 +15418,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st5, st0": { @@ -15530,16 +15473,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st6, st0": { @@ -15585,16 +15528,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st7, st0": { @@ -15640,20 +15583,20 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "db 0xde, 0xf0": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 45, "Comment": [ "fdivrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -15661,9 +15604,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -15679,10 +15620,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -15697,16 +15638,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st1, st0": { @@ -15716,12 +15657,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15735,10 +15676,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -15753,15 +15694,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st2, st0": { @@ -15771,11 +15712,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15789,10 +15730,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -15807,16 +15748,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st3, st0": { @@ -15826,11 +15767,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15844,10 +15785,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -15862,16 +15803,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st4, st0": { @@ -15881,11 +15822,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15899,10 +15840,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -15917,16 +15858,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st5, st0": { @@ -15936,11 +15877,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15954,10 +15895,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -15972,16 +15913,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st6, st0": { @@ -15991,11 +15932,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -16009,10 +15950,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -16027,16 +15968,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st7, st0": { @@ -16046,11 +15987,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -16064,10 +16005,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -16082,20 +16023,20 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "db 0xde, 0xf8": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 45, "Comment": [ "fdivp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -16103,9 +16044,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -16139,16 +16078,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st1, st0": { @@ -16195,15 +16134,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st2, st0": { @@ -16249,16 +16188,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st3, st0": { @@ -16304,16 +16243,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st4, st0": { @@ -16359,16 +16298,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st5, st0": { @@ -16414,16 +16353,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st6, st0": { @@ -16469,16 +16408,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st7, st0": { @@ -16524,16 +16463,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fild word [rax]": { @@ -16542,40 +16481,40 @@ "0xdf !11b /0" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "mov w21, #0x0", + "sxth x20, w20", + "mrs x22, nzcv", + "cmp x20, #0x0 (0)", + "mov w23, #0x8000", + "csel x23, x23, xzr, lt", + "cneg x20, x20, mi", + "mov w24, #0x3f", + "mov x0, #0x3f", + "clz x25, x20", + "sub x25, x0, x25", + "sub x24, x24, x25", + "lsl x25, x20, x24", + "mov w30, #0x403e", + "sub x24, x30, x24", + "cmp x20, #0x0 (0)", + "csel x20, x21, x24, eq", + "orr x20, x23, x20", + "fmov d2, x25", + "fmov d3, x20", + "mov v2.d[1], v3.d[0]", + "msr nzcv, x22", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldrh w21, [x4]", - "mov w22, #0x0", - "sxth x21, w21", - "mrs x23, nzcv", - "cmp x21, #0x0 (0)", - "mov w24, #0x8000", - "csel x24, x24, xzr, lt", - "cneg x21, x21, mi", - "mov w25, #0x3f", - "mov x0, #0x3f", - "clz x30, x21", - "sub x30, x0, x30", - "sub x25, x25, x30", - "lsl x30, x21, x25", - "mov w18, #0x403e", - "sub x25, x18, x25", - "cmp x21, #0x0 (0)", - "csel x21, x22, x25, eq", - "orr x21, x24, x21", - "fmov d2, x30", - "fmov d3, x21", - "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "msr nzcv, x23" + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fisttp word [rax]": { @@ -16714,15 +16653,6 @@ "0xdf !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", - "strb w20, [x28, #1019]", "ldr q2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -16752,8 +16682,17 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fbstp tword [rax]": { @@ -16908,14 +16847,14 @@ "0xdf 11b 0xe0 /4" ], "ExpectedArm64ASM": [ - "mov w20, #0x0", - "ldrb w21, [x28, #1019]", - "bfi x20, x21, #11, #3", - "ldrb w21, [x28, #1016]", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "bfi x21, x20, #11, #3", + "ldrb w20, [x28, #1016]", "ldrb w22, [x28, #1017]", "ldrb w23, [x28, #1018]", "ldrb w24, [x28, #1022]", - "orr x20, x20, x21, lsl #8", + "orr x20, x21, x20, lsl #8", "orr x20, x20, x22, lsl #9", "orr x20, x20, x23, lsl #10", "orr x20, x20, x24, lsl #14", @@ -16923,15 +16862,13 @@ ] }, "fucomip st0": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 49, "Comment": [ "0xdf 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -16947,10 +16884,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -16988,12 +16925,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17007,10 +16944,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17047,11 +16984,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17065,10 +17002,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17106,11 +17043,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17124,10 +17061,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17165,11 +17102,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17183,10 +17120,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17224,11 +17161,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17242,10 +17179,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17283,11 +17220,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17301,10 +17238,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17342,11 +17279,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17360,10 +17297,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17395,15 +17332,13 @@ ] }, "fcomip st0": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 49, "Comment": [ "0xdf 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -17419,10 +17354,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17460,12 +17395,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17479,10 +17414,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17519,11 +17454,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17537,10 +17472,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17578,11 +17513,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17596,10 +17531,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17637,11 +17572,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17655,10 +17590,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17696,11 +17631,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17714,10 +17649,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17755,11 +17690,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17773,10 +17708,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17814,11 +17749,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17832,10 +17767,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index 3a84afc127..a0f3e7806a 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -21,12 +21,12 @@ "0xd8 !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -37,12 +37,12 @@ "0xd8 !11b /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -53,21 +53,21 @@ "0xd8 !11b /2" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcomp dword [rax]": { @@ -76,25 +76,25 @@ "0xd8 !11b /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -107,9 +107,9 @@ "0xd8 !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d3, d2", @@ -123,9 +123,9 @@ "0xd8 !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", @@ -139,9 +139,9 @@ "0xd8 !11b /6" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d3, d2", @@ -155,9 +155,9 @@ "0xd8 !11b /7" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", @@ -166,20 +166,18 @@ ] }, "fadd st0, st0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0xd8 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fadd d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -190,13 +188,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -208,13 +206,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -226,13 +224,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -244,13 +242,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -262,13 +260,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -280,13 +278,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -298,32 +296,30 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "fmul st0, st0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0xd8 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fmul d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -334,13 +330,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -352,13 +348,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -370,13 +366,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -388,13 +384,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -406,13 +402,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -424,13 +420,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -442,28 +438,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "fcom st0, st0": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": [ "0xd8 11b 0xd0 /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -485,22 +479,22 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st2": { @@ -510,22 +504,22 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st3": { @@ -535,22 +529,22 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st4": { @@ -560,22 +554,22 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st5": { @@ -585,22 +579,22 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st6": { @@ -610,22 +604,22 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st7": { @@ -635,35 +629,33 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcomp st0, st0": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": [ "0xd8 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -693,26 +685,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "mov w21, #0x0", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -726,26 +718,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -759,26 +751,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -792,26 +784,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -825,26 +817,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -858,26 +850,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -891,26 +883,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -918,20 +910,18 @@ ] }, "fsub st0, st0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0xd8 11b 0xe0 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -942,13 +932,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -960,13 +950,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -978,13 +968,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -996,13 +986,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1014,13 +1004,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1032,13 +1022,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1050,32 +1040,30 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "fsubr st0, st0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0xd8 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -1206,20 +1194,18 @@ ] }, "fdiv st0, st0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0xd8 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -1230,13 +1216,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1248,13 +1234,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1266,13 +1252,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1284,13 +1270,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1302,13 +1288,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1320,13 +1306,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1338,32 +1324,30 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "fdivr st0, st0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0xd8 11b 0xf8 /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -1499,19 +1483,19 @@ "0xd9 !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fst dword [rax]": { @@ -1524,7 +1508,7 @@ "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "fcvt s2, d2", - "str s2, [x4]" + "str d2, [x4]" ] }, "fstp dword [rax]": { @@ -1537,7 +1521,7 @@ "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "fcvt s2, d2", - "str s2, [x4]", + "str d2, [x4]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -1631,75 +1615,81 @@ ] }, "fnstenv [rax]": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 70, "Comment": [ "0xd9 !11b /6" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1296]", - "str w20, [x4]", - "mov w20, #0x0", - "ldrb w21, [x28, #1019]", - "mov x0, x20", - "bfi x0, x21, #11, #3", - "mov x21, x0", - "ldrb w22, [x28, #1016]", - "ldrb w23, [x28, #1017]", - "ldrb w24, [x28, #1018]", - "ldrb w25, [x28, #1022]", - "orr x21, x21, x22, lsl #8", - "orr x21, x21, x23, lsl #9", - "orr x21, x21, x24, lsl #10", - "orr x21, x21, x25, lsl #14", - "str w21, [x4, #4]", - "ldrb w21, [x28, #1298]", - "and w22, w21, #0x1", - "mov w23, #0x3", - "mrs x24, nzcv", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "ldrh w22, [x28, #1296]", + "str w22, [x4]", + "add x22, x4, #0x4 (4)", + "mov x0, x21", + "bfi x0, x20, #11, #3", + "mov x20, x0", + "ldrb w23, [x28, #1016]", + "ldrb w24, [x28, #1017]", + "ldrb w25, [x28, #1018]", + "ldrb w30, [x28, #1022]", + "orr x20, x20, x23, lsl #8", + "orr x20, x20, x24, lsl #9", + "orr x20, x20, x25, lsl #10", + "orr x20, x20, x30, lsl #14", + "str w20, [x22]", + "add x20, x4, #0x8 (8)", + "ldrb w22, [x28, #1298]", + "and w23, w22, #0x1", + "mov w24, #0x3", + "mrs x25, nzcv", + "cmp x23, #0x0 (0)", + "csel x23, x24, x21, eq", + "orr w23, w21, w23", + "lsr w30, w22, #1", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #2", + "lsr w30, w22, #2", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #4", + "lsr w30, w22, #3", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #6", + "lsr w30, w22, #4", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #8", + "lsr w30, w22, #5", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #10", + "lsr w30, w22, #6", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #12", + "lsr w22, w22, #7", + "and w22, w22, #0x1", "cmp x22, #0x0 (0)", - "csel x22, x23, x20, eq", - "orr w22, w20, w22", - "lsr w25, w21, #1", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #2", - "lsr w25, w21, #2", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #4", - "lsr w25, w21, #3", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #6", - "lsr w25, w21, #4", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #8", - "lsr w25, w21, #5", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #10", - "lsr w25, w21, #6", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #12", - "lsr w21, w21, #7", - "and w21, w21, #0x1", - "cmp x21, #0x0 (0)", - "csel x21, x23, x20, eq", - "orr w21, w22, w21, lsl #14", - "str w21, [x4, #8]", - "str w20, [x4, #12]", - "str w20, [x4, #16]", - "str w20, [x4, #20]", - "str w20, [x4, #24]", - "msr nzcv, x24" + "csel x22, x24, x21, eq", + "orr w22, w23, w22, lsl #14", + "str w22, [x20]", + "add x20, x4, #0xc (12)", + "str w21, [x20]", + "add x20, x4, #0x10 (16)", + "str w21, [x20]", + "add x20, x4, #0x14 (20)", + "str w21, [x20]", + "add x20, x4, #0x18 (24)", + "str w21, [x20]", + "msr nzcv, x25" ] }, "fnstcw [rax]": { @@ -1713,26 +1703,24 @@ ] }, "fld st0": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": [ "0xd9 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st1": { @@ -1749,13 +1737,13 @@ "ldr d2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st2": { @@ -1772,13 +1760,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st3": { @@ -1795,13 +1783,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st4": { @@ -1818,13 +1806,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st5": { @@ -1841,13 +1829,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st6": { @@ -1864,13 +1852,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st7": { @@ -1887,34 +1875,23 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fxch st0, st0": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 2, "Comment": [ "0xd9 11b 0xc8 /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", - "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "mov w20, #0x0", + "strb w20, [x28, #1017]" ] }, "fxch st0, st1": { @@ -1924,18 +1901,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st2": { @@ -1945,18 +1922,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st3": { @@ -1966,18 +1943,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st4": { @@ -1987,18 +1964,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st5": { @@ -2008,18 +1985,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st6": { @@ -2029,18 +2006,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st7": { @@ -2050,18 +2027,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fnop": { @@ -2106,23 +2083,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "fmov d2, x21", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #1040]", - "mov w20, #0x0", - "fmov d3, x20", - "fcmp d2, d3", - "cset w21, vs", + "ldr d3, [x0, #1040]", + "fcmp d3, d2", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fxam": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xd9 11b 0xe5 /4" ], @@ -2135,16 +2112,14 @@ "strb w21, [x28, #1017]", "ldrb w21, [x28, #1298]", "lsr w20, w21, w20", - "mov w21, #0x1", "and w20, w20, #0x1", - "mov w22, #0x0", - "mrs x23, nzcv", + "mrs x21, nzcv", "cmp x20, #0x1 (1)", - "csel x21, x22, x21, eq", - "strb w21, [x28, #1016]", + "cset x22, ne", + "strb w22, [x28, #1016]", "strb w20, [x28, #1018]", - "strb w21, [x28, #1022]", - "msr nzcv, x23" + "strb w22, [x28, #1022]", + "msr nzcv, x21" ] }, "fld1": { @@ -2153,19 +2128,19 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ + "mov x20, #0x3ff0000000000000", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x3ff0000000000000", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldl2t": { @@ -2174,22 +2149,22 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ + "mov x20, #0xa372", + "movk x20, #0x979, lsl #16", + "movk x20, #0x934f, lsl #32", + "movk x20, #0x400a, lsl #48", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0xa372", - "movk x21, #0x979, lsl #16", - "movk x21, #0x934f, lsl #32", - "movk x21, #0x400a, lsl #48", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldl2e": { @@ -2198,22 +2173,22 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ + "mov x20, #0x82fe", + "movk x20, #0x652b, lsl #16", + "movk x20, #0x1547, lsl #32", + "movk x20, #0x3ff7, lsl #48", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x82fe", - "movk x21, #0x652b, lsl #16", - "movk x21, #0x1547, lsl #32", - "movk x21, #0x3ff7, lsl #48", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldpi": { @@ -2222,22 +2197,22 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ + "mov x20, #0x2d18", + "movk x20, #0x5444, lsl #16", + "movk x20, #0x21fb, lsl #32", + "movk x20, #0x4009, lsl #48", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x2d18", - "movk x21, #0x5444, lsl #16", - "movk x21, #0x21fb, lsl #32", - "movk x21, #0x4009, lsl #48", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldlg2": { @@ -2246,22 +2221,22 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ + "mov x20, #0x79ff", + "movk x20, #0x509f, lsl #16", + "movk x20, #0x4413, lsl #32", + "movk x20, #0x3fd3, lsl #48", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x79ff", - "movk x21, #0x509f, lsl #16", - "movk x21, #0x4413, lsl #32", - "movk x21, #0x3fd3, lsl #48", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldln2": { @@ -2270,22 +2245,22 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ + "mov x20, #0x39ef", + "movk x20, #0xfefa, lsl #16", + "movk x20, #0x2e42, lsl #32", + "movk x20, #0x3fe6, lsl #48", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x39ef", - "movk x21, #0xfefa, lsl #16", - "movk x21, #0x2e42, lsl #32", - "movk x21, #0x3fe6, lsl #48", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldz": { @@ -2294,19 +2269,19 @@ "0xd9 11b 0xee /5" ], "ExpectedArm64ASM": [ + "mov w20, #0x0", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov w21, #0x0", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "f2xm1": { @@ -2374,22 +2349,16 @@ ] }, "fyl2x": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 64, "Comment": [ "0xd9 11b 0xf1 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v2.8b", @@ -2445,7 +2414,10 @@ "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fptan": { @@ -2455,16 +2427,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1298]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", - "strb w22, [x28, #1019]", + "mov w21, #0x0", + "mov x22, #0x3ff0000000000000", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #1040]", + "ldr d3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2489,7 +2456,7 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov v0.8b, v2.8b", + "mov v0.8b, v3.8b", "ldrh w0, [x28, #1296]", "ldr x1, [x28, #1752]", "blr x1", @@ -2515,34 +2482,33 @@ "ldp x19, x29, [x28, #392]", "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", - "mov v2.8b, v0.8b", - "mov x21, #0x3ff0000000000000", - "fmov d3, x21", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "mov v3.8b, v0.8b", + "add x0, x28, x20, lsl #4", + "str d3, [x0, #1040]", + "mov w22, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str d3, [x0, #1040]" + "ldrb w23, [x28, #1298]", + "lsl w20, w22, w20", + "orr w20, w23, w20", + "strb w20, [x28, #1298]", + "strb w21, [x28, #1018]" ] }, "fpatan": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 64, "Comment": [ "0xd9 11b 0xf3 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v3.8b", @@ -2598,7 +2564,10 @@ "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fxtract": { @@ -2608,28 +2577,28 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1298]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", - "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "mov x21, v2.d[0]", - "and x23, x21, #0x7ff0000000000000", - "lsr x23, x23, #52", - "sub x23, x23, #0x3ff (1023)", - "scvtf d2, x23", + "and x22, x21, #0x7ff0000000000000", + "lsr x22, x22, #52", + "sub x22, x22, #0x3ff (1023)", + "scvtf d2, x22", "and x21, x21, #0x800fffffffffffff", "orr x21, x21, #0x3ff0000000000000", "fmov d3, x21", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str d3, [x0, #1040]" + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str d3, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fprem1": { @@ -2639,11 +2608,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v2.8b", "mov v1.8b, v3.8b", @@ -2697,10 +2667,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fdecstp": { @@ -2734,11 +2703,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v2.8b", "mov v1.8b, v3.8b", @@ -2792,34 +2762,31 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fyl2xp1": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Comment": [ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ + "mov x20, #0x3ff0000000000000", + "fmov d2, x20", "ldrb w20, [x28, #1019]", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #1040]", + "fadd d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", - "mov x20, #0x3ff0000000000000", - "fmov d4, x20", - "fadd d2, d2, d4", "mov v0.8b, v2.8b", "mov v1.8b, v3.8b", "mrs x0, nzcv", @@ -2873,7 +2840,10 @@ "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fsqrt": { @@ -2891,22 +2861,17 @@ ] }, "fsincos": { - "ExpectedInstructionCount": 119, + "ExpectedInstructionCount": 125, "Comment": [ "0xd9 11b 0xfb /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1298]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", - "strb w22, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2931,7 +2896,7 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov v0.8b, v2.8b", + "mov v0.8b, v3.8b", "ldrh w0, [x28, #1296]", "ldr x1, [x28, #1736]", "blr x1", @@ -2958,6 +2923,20 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v3.8b, v0.8b", + "add x0, x28, x20, lsl #4", + "str d3, [x0, #1040]", + "mov w22, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w22, w22, w20", + "orr w22, w23, w22", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -3009,12 +2988,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str d3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "frndint": { @@ -3038,10 +3014,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v2.8b", @@ -3107,6 +3083,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "mrs x0, nzcv", @@ -3160,10 +3137,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fcos": { @@ -3173,6 +3149,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "mrs x0, nzcv", @@ -3226,10 +3203,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fiadd dword [rax]": { @@ -3238,12 +3214,12 @@ "0xda !11b /0" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -3254,12 +3230,12 @@ "0xda !11b /1" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -3270,21 +3246,21 @@ "0xda !11b /2" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "ficomp dword [rax]": { @@ -3293,25 +3269,25 @@ "0xda !11b /3" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -3324,9 +3300,9 @@ "0xda !11b /4" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d3, d2", @@ -3340,9 +3316,9 @@ "0xda !11b /5" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", @@ -3356,9 +3332,9 @@ "0xda !11b /6" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d3, d2", @@ -3372,9 +3348,9 @@ "0xda !11b /7" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", @@ -3383,7 +3359,7 @@ ] }, "fcmovb st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xda 11b 0xc0 /0" ], @@ -3391,15 +3367,13 @@ "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st1": { @@ -3413,13 +3387,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st2": { @@ -3433,13 +3407,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st3": { @@ -3453,13 +3427,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st4": { @@ -3473,13 +3447,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st5": { @@ -3493,13 +3467,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st6": { @@ -3513,13 +3487,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st7": { @@ -3533,17 +3507,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmove st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xda 11b 0xc8 /1" ], @@ -3551,15 +3525,13 @@ "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st1": { @@ -3573,13 +3545,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st2": { @@ -3593,13 +3565,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st3": { @@ -3613,13 +3585,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st4": { @@ -3633,13 +3605,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st5": { @@ -3653,13 +3625,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st6": { @@ -3673,13 +3645,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st7": { @@ -3693,17 +3665,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st0": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd0 /0" ], @@ -3713,15 +3685,13 @@ "csel x20, x20, x21, eq", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st1": { @@ -3737,13 +3707,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st2": { @@ -3759,13 +3729,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st3": { @@ -3781,13 +3751,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st4": { @@ -3803,13 +3773,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st5": { @@ -3825,13 +3795,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st6": { @@ -3847,13 +3817,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st7": { @@ -3869,17 +3839,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovu st0, st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xda 11b 0xd8 /1" ], @@ -3892,15 +3862,13 @@ "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -3920,13 +3888,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -3946,13 +3914,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -3972,13 +3940,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -3998,13 +3966,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4024,13 +3992,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4050,13 +4018,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4076,48 +4044,49 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, "fucompp": { - "ExpectedInstructionCount": 30, + "ExpectedInstructionCount": 31, "Comment": [ "0xda 11b 0xe9 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "mov w21, #0x0", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "strb w20, [x28, #1019]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -4130,19 +4099,19 @@ "0xdf !11b /5" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fisttp dword [rax]": { @@ -4208,7 +4177,6 @@ "0xdb !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr q2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -4236,16 +4204,17 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v2.8b, v0.8b", + "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fstp tword [rax]": { @@ -4298,7 +4267,7 @@ ] }, "fcmovnb st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xc0 /0" ], @@ -4306,15 +4275,13 @@ "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st1": { @@ -4328,13 +4295,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st2": { @@ -4348,13 +4315,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st3": { @@ -4368,13 +4335,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st4": { @@ -4388,13 +4355,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st5": { @@ -4408,13 +4375,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st6": { @@ -4428,13 +4395,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st7": { @@ -4448,17 +4415,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovne st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xc8 /1" ], @@ -4466,15 +4433,13 @@ "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st1": { @@ -4488,13 +4453,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st2": { @@ -4508,13 +4473,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st3": { @@ -4528,13 +4493,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st4": { @@ -4548,13 +4513,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st5": { @@ -4568,13 +4533,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st6": { @@ -4588,13 +4553,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st7": { @@ -4608,17 +4573,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st0": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": [ "0xdb 11b 0xd0 /2" ], @@ -4627,15 +4592,13 @@ "csel x20, x20, xzr, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st1": { @@ -4650,13 +4613,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st2": { @@ -4671,13 +4634,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st3": { @@ -4692,13 +4655,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st4": { @@ -4713,13 +4676,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st5": { @@ -4734,13 +4697,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st6": { @@ -4755,13 +4718,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st7": { @@ -4776,17 +4739,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnu st0, st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xdb 11b 0xd8 /3" ], @@ -4799,15 +4762,13 @@ "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4827,13 +4788,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4853,13 +4814,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4879,13 +4840,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4905,13 +4866,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4931,13 +4892,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4957,13 +4918,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4983,13 +4944,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -5017,23 +4978,21 @@ "msr fpcr, x0", "strh w20, [x28, #1296]", "strb w21, [x28, #1019]", + "strb w21, [x28, #1298]", "strb w21, [x28, #1016]", "strb w21, [x28, #1017]", "strb w21, [x28, #1018]", - "strb w21, [x28, #1022]", - "strb w21, [x28, #1298]" + "strb w21, [x28, #1022]" ] }, "fucomi st0, st0": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": [ "0xdb 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -5177,15 +5136,13 @@ ] }, "fcomi st0, st0": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": [ "0xdb 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -5334,11 +5291,11 @@ "0xdc !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -5349,11 +5306,11 @@ "0xdc !11b /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -5364,20 +5321,20 @@ "0xdc !11b /2" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcomp qword [rax]": { @@ -5386,24 +5343,24 @@ "0xdc !11b /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -5416,8 +5373,8 @@ "0xdc !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d3, d2", @@ -5431,8 +5388,8 @@ "0xdc !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", @@ -5446,8 +5403,8 @@ "0xdc !11b /6" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d3, d2", @@ -5461,8 +5418,8 @@ "0xdc !11b /7" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", @@ -5471,7 +5428,7 @@ ] }, "db 0xdc, 0xc0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "fadd st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -5479,14 +5436,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fadd d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5503,7 +5458,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5521,7 +5476,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5539,7 +5494,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5557,7 +5512,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5575,7 +5530,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5593,7 +5548,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5611,13 +5566,13 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] }, "db 0xdc, 0xc8": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "fmul st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -5625,14 +5580,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fmul d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5649,7 +5602,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5667,7 +5620,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5685,7 +5638,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5703,7 +5656,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5721,7 +5674,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5739,7 +5692,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5757,13 +5710,13 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] }, "db 0xdc, 0xe0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "fsubr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -5771,14 +5724,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5789,14 +5740,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5807,14 +5758,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5825,14 +5776,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5843,14 +5794,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5861,14 +5812,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5879,14 +5830,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5897,19 +5848,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "db 0xdc, 0xe8": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "fsub st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -5917,14 +5868,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6055,7 +6004,7 @@ ] }, "db 0xdc, 0xf0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "fdivr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -6063,14 +6012,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6081,14 +6028,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6099,14 +6046,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6117,14 +6064,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6135,14 +6082,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6153,14 +6100,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6171,14 +6118,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6189,19 +6136,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "db 0xdc, 0xf8": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "fdiv st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -6209,14 +6156,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6352,18 +6297,18 @@ "0xdd !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fisttp qword [rax]": { @@ -6751,9 +6696,9 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "ldrh w21, [x28, #1296]", - "str w21, [x4]", "mov w21, #0x0", + "ldrh w22, [x28, #1296]", + "str w22, [x4]", "mov x22, x21", "bfi x22, x20, #11, #3", "ldrb w23, [x28, #1016]", @@ -7071,11 +7016,11 @@ "mov w20, #0x37f", "strh w20, [x28, #1296]", "strb w21, [x28, #1019]", + "strb w21, [x28, #1298]", "strb w21, [x28, #1016]", "strb w21, [x28, #1017]", "strb w21, [x28, #1018]", "strb w21, [x28, #1022]", - "strb w21, [x28, #1298]", "msr nzcv, x25" ] }, @@ -7085,14 +7030,14 @@ "0xdd !11b /7" ], "ExpectedArm64ASM": [ - "mov w20, #0x0", - "ldrb w21, [x28, #1019]", - "bfi x20, x21, #11, #3", - "ldrb w21, [x28, #1016]", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "bfi x21, x20, #11, #3", + "ldrb w20, [x28, #1016]", "ldrb w22, [x28, #1017]", "ldrb w23, [x28, #1018]", "ldrb w24, [x28, #1022]", - "orr x20, x20, x21, lsl #8", + "orr x20, x21, x20, lsl #8", "orr x20, x20, x22, lsl #9", "orr x20, x20, x23, lsl #10", "orr x20, x20, x24, lsl #14", @@ -7100,18 +7045,16 @@ ] }, "ffree st0": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": [ "0xdd 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w20, w20, #0x0 (0)", - "and w20, w20, #0x7", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w20, w22, w20", - "bic w20, w21, w20", + "mov w21, #0x1", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "bic w20, w22, w20", "strb w20, [x28, #1298]" ] }, @@ -7228,24 +7171,11 @@ ] }, "fst st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 0, "Comment": [ "0xdd 11b 0xd0 /2" ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", - "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", - "strb w20, [x28, #1298]" - ] + "ExpectedArm64ASM": [] }, "fst st1": { "ExpectedInstructionCount": 12, @@ -7254,16 +7184,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", - "lsl w21, w21, w22", - "orr w20, w20, w21", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", "strb w20, [x28, #1298]" ] }, @@ -7274,16 +7204,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldr d2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -7294,16 +7224,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldr d2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -7314,16 +7244,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldr d2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -7334,16 +7264,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldr d2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -7354,16 +7284,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldr d2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -7374,43 +7304,36 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldr d2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, "fstp st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 11, "Comment": [ "0xdd 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w21, w23, w21", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", - "lsl w22, w23, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", + "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "bic w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fstp st1": { @@ -7420,13 +7343,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w23, [x28, #1298]", "lsl w22, w21, w22", "orr w22, w23, w22", @@ -7446,12 +7369,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w22, [x28, #1298]", "mov w23, #0x1", "lsl w21, w23, w21", @@ -7472,12 +7395,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w22, [x28, #1298]", "mov w23, #0x1", "lsl w21, w23, w21", @@ -7498,12 +7421,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w22, [x28, #1298]", "mov w23, #0x1", "lsl w21, w23, w21", @@ -7524,12 +7447,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w22, [x28, #1298]", "mov w23, #0x1", "lsl w21, w23, w21", @@ -7550,12 +7473,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w22, [x28, #1298]", "mov w23, #0x1", "lsl w21, w23, w21", @@ -7576,12 +7499,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w22, [x28, #1298]", "mov w23, #0x1", "lsl w21, w23, w21", @@ -7596,16 +7519,14 @@ ] }, "fucom st0": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": [ "0xdd 11b 0xe0 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -7627,22 +7548,22 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st2": { @@ -7652,22 +7573,22 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st3": { @@ -7677,22 +7598,22 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st4": { @@ -7702,22 +7623,22 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st5": { @@ -7727,22 +7648,22 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st6": { @@ -7752,22 +7673,22 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st7": { @@ -7777,35 +7698,33 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucomp st0": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": [ "0xdd 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -7835,26 +7754,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "mov w21, #0x0", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -7868,26 +7787,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -7901,26 +7820,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -7934,26 +7853,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -7967,26 +7886,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8000,26 +7919,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8033,26 +7952,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8065,13 +7984,13 @@ "0xde !11b /0" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -8082,13 +8001,13 @@ "0xde !11b /1" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -8099,22 +8018,22 @@ "0xde !11b /2" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "axflag", "cset w22, lo", "strb w22, [x28, #1016]", "cset w22, eq", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "ficomp word [rax]": { @@ -8123,26 +8042,26 @@ "0xde !11b /3" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8155,10 +8074,10 @@ "0xde !11b /4" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d3, d2", @@ -8172,10 +8091,10 @@ "0xde !11b /5" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", @@ -8189,10 +8108,10 @@ "0xde !11b /6" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d3, d2", @@ -8206,10 +8125,10 @@ "0xde !11b /7" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", @@ -8218,29 +8137,27 @@ ] }, "faddp st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xd8 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st1": { @@ -8257,16 +8174,16 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w23, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st2": { @@ -8282,17 +8199,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st3": { @@ -8308,17 +8225,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st4": { @@ -8334,17 +8251,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st5": { @@ -8360,17 +8277,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st6": { @@ -8386,17 +8303,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st7": { @@ -8412,43 +8329,41 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xde 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st1": { @@ -8465,16 +8380,16 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w23, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st2": { @@ -8490,17 +8405,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st3": { @@ -8516,17 +8431,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st4": { @@ -8542,17 +8457,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st5": { @@ -8568,17 +8483,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st6": { @@ -8594,17 +8509,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st7": { @@ -8620,51 +8535,52 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fcompp": { - "ExpectedInstructionCount": 30, + "ExpectedInstructionCount": 31, "Comment": [ "0xde 11b 0xd9 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "mov w21, #0x0", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", "cset w23, vs", "axflag", "cset w24, lo", "strb w24, [x28, #1016]", "cset w24, eq", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "strb w20, [x28, #1019]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8672,7 +8588,7 @@ ] }, "db 0xde, 0xe0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "fsubrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -8680,23 +8596,21 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st1, st0": { @@ -8706,23 +8620,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w23, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st2, st0": { @@ -8732,23 +8646,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st3, st0": { @@ -8758,23 +8672,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st4, st0": { @@ -8784,23 +8698,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st5, st0": { @@ -8810,23 +8724,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st6, st0": { @@ -8836,23 +8750,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st7, st0": { @@ -8862,27 +8776,27 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "db 0xde, 0xe8": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "fsubp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -8890,23 +8804,21 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st1, st0": { @@ -8924,15 +8836,15 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st2, st0": { @@ -8949,16 +8861,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st3, st0": { @@ -8975,16 +8887,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st4, st0": { @@ -9001,16 +8913,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st5, st0": { @@ -9027,16 +8939,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st6, st0": { @@ -9053,16 +8965,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st7, st0": { @@ -9079,20 +8991,20 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "db 0xde, 0xf0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "fdivrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -9100,23 +9012,21 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st1, st0": { @@ -9126,23 +9036,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w23, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st2, st0": { @@ -9152,23 +9062,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", + "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fdivrp st3, st0": { @@ -9178,23 +9088,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st4, st0": { @@ -9204,23 +9114,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st5, st0": { @@ -9230,23 +9140,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st6, st0": { @@ -9256,23 +9166,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st7, st0": { @@ -9282,27 +9192,27 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "db 0xde, 0xf8": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "fdivp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -9310,23 +9220,21 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st1, st0": { @@ -9344,15 +9252,15 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st2, st0": { @@ -9369,16 +9277,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st3, st0": { @@ -9395,16 +9303,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st4, st0": { @@ -9421,16 +9329,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st5, st0": { @@ -9447,16 +9355,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st6, st0": { @@ -9473,16 +9381,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st7, st0": { @@ -9499,16 +9407,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fild word [rax]": { @@ -9517,20 +9425,20 @@ "0xdf !11b /0" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fisttp word [rax]": { @@ -9596,15 +9504,6 @@ "0xdf !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", - "strb w20, [x28, #1019]", "ldr q2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -9660,8 +9559,17 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v2.8b, v0.8b", + "ldrb w20, [x28, #1019]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fbstp tword [rax]": { @@ -9843,14 +9751,14 @@ "0xdf 11b 0xe0 /4" ], "ExpectedArm64ASM": [ - "mov w20, #0x0", - "ldrb w21, [x28, #1019]", - "bfi x20, x21, #11, #3", - "ldrb w21, [x28, #1016]", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "bfi x21, x20, #11, #3", + "ldrb w20, [x28, #1016]", "ldrb w22, [x28, #1017]", "ldrb w23, [x28, #1018]", "ldrb w24, [x28, #1022]", - "orr x20, x20, x21, lsl #8", + "orr x20, x21, x20, lsl #8", "orr x20, x20, x22, lsl #9", "orr x20, x20, x23, lsl #10", "orr x20, x20, x24, lsl #14", @@ -9858,15 +9766,13 @@ ] }, "fucomip st0": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": [ "0xdf 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -10074,15 +9980,13 @@ ] }, "fcomip st0": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": [ "0xdf 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 6495349765..9f4a5a58e0 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -2361,6 +2361,14 @@ "mov w4, w20" ] }, + "lea eax, [eax + 1]": { + "ExpectedInstructionCount": 2, + "Comment": "Increment without flag setting.", + "ExpectedArm64ASM": [ + "add x20, x4, #0x1 (1)", + "mov w4, w20" + ] + }, "mov cs, ax": { "ExpectedInstructionCount": 4, "Skip": "Yes", diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index e678f584bb..420f10bb05 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -1705,11 +1705,11 @@ "mov w21, #0x37f", "strh w21, [x28, #1296]", "strb w20, [x28, #1019]", + "strb w20, [x28, #1298]", "strb w20, [x28, #1016]", "strb w20, [x28, #1017]", "strb w20, [x28, #1018]", "strb w20, [x28, #1022]", - "strb w20, [x28, #1298]", "movi v2.2d, #0x0", "str q2, [x28, #1040]", "str q2, [x28, #1056]", diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index e7efc45c6c..3b020ee7d5 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -18,7 +18,6 @@ "0xd8 !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -47,6 +46,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -61,10 +61,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -89,7 +89,6 @@ "0xd8 !11b /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -118,6 +117,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -132,10 +132,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -160,7 +160,6 @@ "0xd8 !11b /2" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -189,6 +188,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -219,16 +220,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcomp dword [rax]": { @@ -237,7 +237,6 @@ "0xd8 !11b /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -266,6 +265,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -295,17 +296,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -322,7 +322,6 @@ "0xd8 !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -351,6 +350,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -393,7 +393,6 @@ "0xd8 !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -422,6 +421,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -464,7 +464,6 @@ "0xd8 !11b /6" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -493,6 +492,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -535,7 +535,6 @@ "0xd8 !11b /7" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -564,6 +563,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -601,15 +601,13 @@ ] }, "fadd st0, st0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "0xd8 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -625,10 +623,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -643,7 +641,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -654,11 +652,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -672,10 +670,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -701,11 +699,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -719,10 +717,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -748,11 +746,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -766,10 +764,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -795,11 +793,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -813,10 +811,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -842,11 +840,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -860,10 +858,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -889,11 +887,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -907,10 +905,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -936,11 +934,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -954,10 +952,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -977,15 +975,13 @@ ] }, "fmul st0, st0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "0xd8 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -1001,10 +997,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1019,7 +1015,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -1030,11 +1026,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1048,10 +1044,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1077,11 +1073,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1095,10 +1091,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1124,11 +1120,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1142,10 +1138,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1171,11 +1167,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1189,10 +1185,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1218,11 +1214,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1236,10 +1232,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1265,11 +1261,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1283,10 +1279,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -1312,11 +1308,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1330,11 +1326,11 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1680]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", "msr nzcv, x4", @@ -1353,16 +1349,14 @@ ] }, "fcom st0, st0": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 43, "Comment": [ "0xd8 11b 0xd0 /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -1378,10 +1372,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1412,10 +1406,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1430,10 +1425,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1446,16 +1441,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcom st0, st2": { @@ -1465,10 +1459,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1483,10 +1478,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1499,16 +1494,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcom st0, st3": { @@ -1518,10 +1512,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1536,10 +1531,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1552,16 +1547,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcom st0, st4": { @@ -1571,10 +1565,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1589,10 +1584,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1605,16 +1600,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcom st0, st5": { @@ -1624,10 +1618,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1642,10 +1637,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1658,16 +1653,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcom st0, st6": { @@ -1677,10 +1671,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1695,10 +1690,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1711,16 +1706,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcom st0, st7": { @@ -1730,10 +1724,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -1748,10 +1743,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1764,29 +1759,26 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcomp st0, st0": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 51, "Comment": [ "0xd8 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -1802,10 +1794,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1844,12 +1836,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1863,10 +1856,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1878,20 +1871,19 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "mov x23, x0", + "ubfx x24, x23, #1, #1", + "ubfx x25, x23, #0, #1", + "ubfx x23, x23, #2, #1", + "orr w24, w24, w23", + "orr w25, w25, w23", + "strb w24, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w23, [x28, #1018]", + "strb w25, [x28, #1022]", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -1905,11 +1897,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1923,10 +1916,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1938,17 +1931,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -1966,11 +1958,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1984,10 +1977,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -1999,17 +1992,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -2027,11 +2019,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2045,10 +2038,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -2060,17 +2053,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -2088,11 +2080,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2106,10 +2099,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -2121,17 +2114,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -2149,11 +2141,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2167,10 +2160,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -2182,17 +2175,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -2210,11 +2202,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2228,10 +2221,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -2243,17 +2236,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -2265,15 +2257,13 @@ ] }, "fsub st0, st0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "0xd8 11b 0xe0 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -2307,7 +2297,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -2318,11 +2308,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2336,10 +2326,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2365,11 +2355,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2383,10 +2373,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2412,11 +2402,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2430,10 +2420,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2459,11 +2449,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2477,10 +2467,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2506,11 +2496,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2524,10 +2514,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2553,11 +2543,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2571,10 +2561,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2600,11 +2590,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -2618,10 +2608,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2641,15 +2631,13 @@ ] }, "fsubr st0, st0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "0xd8 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -2665,10 +2653,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -2683,7 +2671,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -3017,15 +3005,13 @@ ] }, "fdiv st0, st0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "0xd8 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -3059,7 +3045,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -3070,11 +3056,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3088,10 +3074,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3117,11 +3103,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3135,10 +3121,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3164,11 +3150,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3182,10 +3168,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3211,11 +3197,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3229,10 +3215,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3258,11 +3244,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3276,10 +3262,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3305,11 +3291,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3323,10 +3309,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3352,11 +3338,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3370,10 +3356,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3393,15 +3379,13 @@ ] }, "fdivr st0, st0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "0xd8 11b 0xf8 /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -3417,10 +3401,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -3435,7 +3419,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -3774,7 +3758,6 @@ "0xd9 !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -3803,16 +3786,17 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fst dword [rax]": { @@ -3900,14 +3884,15 @@ ] }, "fldenv [rax]": { - "ExpectedInstructionCount": 48, + "ExpectedInstructionCount": 50, "Comment": [ "0xd9 !11b /4" ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", "strh w20, [x28, #1296]", - "ldr w20, [x4, #4]", + "add x20, x4, #0x4 (4)", + "ldr w20, [x20]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #1019]", "ubfx w21, w20, #8, #1", @@ -3918,7 +3903,8 @@ "strb w22, [x28, #1017]", "strb w23, [x28, #1018]", "strb w20, [x28, #1022]", - "ldr w20, [x4, #8]", + "add x20, x4, #0x8 (8)", + "ldr w20, [x20]", "ubfx w21, w20, #0, #2", "mrs x22, nzcv", "cmp x21, #0x3 (3)", @@ -3966,75 +3952,81 @@ ] }, "fnstenv [rax]": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 70, "Comment": [ "0xd9 !11b /6" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1296]", - "str w20, [x4]", - "mov w20, #0x0", - "ldrb w21, [x28, #1019]", - "mov x0, x20", - "bfi x0, x21, #11, #3", - "mov x21, x0", - "ldrb w22, [x28, #1016]", - "ldrb w23, [x28, #1017]", - "ldrb w24, [x28, #1018]", - "ldrb w25, [x28, #1022]", - "orr x21, x21, x22, lsl #8", - "orr x21, x21, x23, lsl #9", - "orr x21, x21, x24, lsl #10", - "orr x21, x21, x25, lsl #14", - "str w21, [x4, #4]", - "ldrb w21, [x28, #1298]", - "and w22, w21, #0x1", - "mov w23, #0x3", - "mrs x24, nzcv", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "ldrh w22, [x28, #1296]", + "str w22, [x4]", + "add x22, x4, #0x4 (4)", + "mov x0, x21", + "bfi x0, x20, #11, #3", + "mov x20, x0", + "ldrb w23, [x28, #1016]", + "ldrb w24, [x28, #1017]", + "ldrb w25, [x28, #1018]", + "ldrb w30, [x28, #1022]", + "orr x20, x20, x23, lsl #8", + "orr x20, x20, x24, lsl #9", + "orr x20, x20, x25, lsl #10", + "orr x20, x20, x30, lsl #14", + "str w20, [x22]", + "add x20, x4, #0x8 (8)", + "ldrb w22, [x28, #1298]", + "and w23, w22, #0x1", + "mov w24, #0x3", + "mrs x25, nzcv", + "cmp x23, #0x0 (0)", + "csel x23, x24, x21, eq", + "orr w23, w21, w23", + "lsr w30, w22, #1", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #2", + "lsr w30, w22, #2", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #4", + "lsr w30, w22, #3", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #6", + "lsr w30, w22, #4", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #8", + "lsr w30, w22, #5", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #10", + "lsr w30, w22, #6", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #12", + "lsr w22, w22, #7", + "and w22, w22, #0x1", "cmp x22, #0x0 (0)", - "csel x22, x23, x20, eq", - "orr w22, w20, w22", - "lsr w25, w21, #1", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #2", - "lsr w25, w21, #2", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #4", - "lsr w25, w21, #3", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #6", - "lsr w25, w21, #4", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #8", - "lsr w25, w21, #5", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #10", - "lsr w25, w21, #6", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #12", - "lsr w21, w21, #7", - "and w21, w21, #0x1", - "cmp x21, #0x0 (0)", - "csel x21, x23, x20, eq", - "orr w21, w22, w21, lsl #14", - "str w21, [x4, #8]", - "str w20, [x4, #12]", - "str w20, [x4, #16]", - "str w20, [x4, #20]", - "str w20, [x4, #24]", - "msr nzcv, x24" + "csel x22, x24, x21, eq", + "orr w22, w23, w22, lsl #14", + "str w22, [x20]", + "add x20, x4, #0xc (12)", + "str w21, [x20]", + "add x20, x4, #0x10 (16)", + "str w21, [x20]", + "add x20, x4, #0x14 (20)", + "str w21, [x20]", + "add x20, x4, #0x18 (24)", + "str w21, [x20]", + "msr nzcv, x25" ] }, "fnstcw [rax]": { @@ -4048,26 +4040,24 @@ ] }, "fld st0": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": [ "0xd9 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st1": { @@ -4084,13 +4074,13 @@ "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st2": { @@ -4107,13 +4097,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st3": { @@ -4130,13 +4120,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st4": { @@ -4153,13 +4143,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st5": { @@ -4176,13 +4166,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st6": { @@ -4199,13 +4189,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st7": { @@ -4222,34 +4212,23 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fxch st0, st0": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 2, "Comment": [ "0xd9 11b 0xc8 /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", - "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "mov w20, #0x0", + "strb w20, [x28, #1017]" ] }, "fxch st0, st1": { @@ -4259,18 +4238,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st2": { @@ -4280,18 +4259,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st3": { @@ -4301,18 +4280,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st4": { @@ -4322,18 +4301,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st5": { @@ -4343,18 +4322,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st6": { @@ -4364,18 +4343,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st7": { @@ -4385,18 +4364,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fnop": { @@ -4412,14 +4391,14 @@ "0xd9 11b 0xe0 /4" ], "ExpectedArm64ASM": [ + "mov w20, #0x0", + "mov w21, #0x8000", + "fmov d2, x20", + "mov v2.d[1], x21", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "mov w21, #0x0", - "mov w22, #0x8000", - "fmov d3, x21", - "mov v3.d[1], x22", - "eor v2.16b, v2.16b, v3.16b", + "ldr q3, [x0, #1040]", + "eor v2.16b, v3.16b, v2.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -4430,14 +4409,14 @@ "0xd9 11b 0xe1 /4" ], "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "mov w21, #0x7fff", + "fmov d2, x20", + "mov v2.d[1], x21", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "mov x21, #0xffffffffffffffff", - "mov w22, #0x7fff", - "fmov d3, x21", - "mov v3.d[1], x22", - "and v2.16b, v2.16b, v3.16b", + "ldr q3, [x0, #1040]", + "and v2.16b, v3.16b, v2.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -4449,10 +4428,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "fmov d2, x21", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "mov w20, #0x0", - "fmov d3, x20", + "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -4465,10 +4444,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "mov x3, v3.d[0]", - "umov w4, v3.h[4]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -4480,15 +4459,15 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", + "mov x20, x0", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w22, w22, w20", + "orr w23, w23, w20", "strb w22, [x28, #1016]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]", + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]", "strb w23, [x28, #1022]" ] }, @@ -4522,18 +4501,18 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2576]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr q2, [x28, #2576]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldl2t": { @@ -4542,18 +4521,18 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2592]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr q2, [x28, #2592]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldl2e": { @@ -4562,18 +4541,18 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2608]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr q2, [x28, #2608]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldpi": { @@ -4582,18 +4561,18 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2624]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr q2, [x28, #2624]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldlg2": { @@ -4602,18 +4581,18 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2640]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr q2, [x28, #2640]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldln2": { @@ -4622,18 +4601,18 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2656]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr q2, [x28, #2656]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldz": { @@ -4642,18 +4621,18 @@ "0xd9 11b 0xee /5" ], "ExpectedArm64ASM": [ + "movi v2.2d, #0x0", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "movi v2.2d, #0x0", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "f2xm1": { @@ -4698,22 +4677,16 @@ ] }, "fyl2x": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 42, "Comment": [ "0xd9 11b 0xf1 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -4747,7 +4720,10 @@ "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fptan": { @@ -4757,16 +4733,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1298]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", - "strb w22, [x28, #1019]", + "mov w21, #0x0", + "ldr q2, [x28, #2576]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", + "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -4779,8 +4749,8 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", "ldr x3, [x28, #1600]", "blr x3", "ldr w4, [x28, #1000]", @@ -4792,35 +4762,35 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldr q3, [x28, #2576]", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "mov w22, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str q3, [x0, #1040]" + "ldrb w23, [x28, #1298]", + "lsl w20, w22, w20", + "orr w20, w23, w20", + "strb w20, [x28, #1298]", + "strb w21, [x28, #1018]" ] }, "fpatan": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 42, "Comment": [ "0xd9 11b 0xf3 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -4854,7 +4824,10 @@ "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fxtract": { @@ -4864,14 +4837,6 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1298]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", - "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", @@ -4932,8 +4897,16 @@ "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fprem1": { @@ -4943,11 +4916,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -4979,10 +4953,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fdecstp": { @@ -5016,11 +4989,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -5052,32 +5026,21 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fyl2xp1": { - "ExpectedInstructionCount": 76, + "ExpectedInstructionCount": 77, "Comment": [ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ + "ldr q2, [x28, #2576]", "ldrb w20, [x28, #1019]", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", - "ldr q4, [x28, #2576]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5092,8 +5055,8 @@ "ldrh w0, [x28, #1296]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "mov x3, v4.d[0]", - "umov w4, v4.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -5108,6 +5071,14 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5139,7 +5110,10 @@ "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fsqrt": { @@ -5184,22 +5158,17 @@ ] }, "fsincos": { - "ExpectedInstructionCount": 73, + "ExpectedInstructionCount": 79, "Comment": [ "0xd9 11b 0xfb /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1298]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", - "strb w22, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5212,8 +5181,8 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", "ldr x3, [x28, #1616]", "blr x3", "ldr w4, [x28, #1000]", @@ -5228,6 +5197,20 @@ "eor v3.16b, v3.16b, v3.16b", "mov v3.d[0], x0", "mov v3.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #1040]", + "mov w22, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w22, w22, w20", + "orr w22, w23, w22", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5256,12 +5239,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "frndint": { @@ -5312,10 +5292,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5359,6 +5339,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", @@ -5389,10 +5370,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fcos": { @@ -5402,6 +5382,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", @@ -5432,10 +5413,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fiadd dword [rax]": { @@ -5444,8 +5424,7 @@ "0xda !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5457,7 +5436,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5473,6 +5452,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5487,10 +5467,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -5515,8 +5495,7 @@ "0xda !11b /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5528,7 +5507,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5544,6 +5523,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5558,10 +5538,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -5586,8 +5566,7 @@ "0xda !11b /2" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5599,7 +5578,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5615,6 +5594,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5645,16 +5626,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "ficomp dword [rax]": { @@ -5663,8 +5643,7 @@ "0xda !11b /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5676,7 +5655,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5692,6 +5671,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5721,17 +5702,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -5748,8 +5728,7 @@ "0xda !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5761,7 +5740,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5777,6 +5756,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5819,8 +5799,7 @@ "0xda !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5832,7 +5811,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5848,6 +5827,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5890,8 +5870,7 @@ "0xda !11b /6" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5903,7 +5882,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5919,6 +5898,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -5961,8 +5941,7 @@ "0xda !11b /7" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", + "ldr w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -5974,7 +5953,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "mov w1, w21", + "mov w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1576]", "blr x2", @@ -5990,6 +5969,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -6027,7 +6007,7 @@ ] }, "fcmovb st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xda 11b 0xc0 /0" ], @@ -6035,13 +6015,11 @@ "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6057,11 +6035,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6077,11 +6055,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6096,12 +6074,12 @@ "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6117,11 +6095,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6137,11 +6115,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6157,11 +6135,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6177,17 +6155,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcmove st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xda 11b 0xc8 /1" ], @@ -6195,13 +6173,11 @@ "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6217,11 +6193,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6237,11 +6213,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6257,11 +6233,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6277,11 +6253,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6297,11 +6273,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6317,11 +6293,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6337,17 +6313,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcmovbe st0, st0": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd0 /0" ], @@ -6357,13 +6333,11 @@ "csel x20, x20, x21, eq", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6381,11 +6355,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6403,11 +6377,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6425,11 +6399,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6447,11 +6421,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6469,11 +6443,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6491,11 +6465,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -6513,17 +6487,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcmovu st0, st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xda 11b 0xd8 /1" ], @@ -6536,13 +6510,11 @@ "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6564,11 +6536,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6590,11 +6562,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6616,11 +6588,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6642,11 +6614,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6668,11 +6640,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6694,11 +6666,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -6720,29 +6692,30 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" ] }, "fucompp": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 59, "Comment": [ "0xda 11b 0xe9 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -6756,10 +6729,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -6771,25 +6744,25 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1298]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "mov x23, x0", + "ubfx x24, x23, #1, #1", + "ubfx x25, x23, #0, #1", + "ubfx x23, x23, #2, #1", + "orr w24, w24, w23", + "orr w25, w25, w23", + "strb w24, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w23, [x28, #1018]", + "strb w25, [x28, #1022]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "strb w20, [x28, #1019]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -6802,40 +6775,40 @@ "0xdf !11b /5" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "mov w21, #0x0", + "sxtw x20, w20", + "mrs x22, nzcv", + "cmp x20, #0x0 (0)", + "mov w23, #0x8000", + "csel x23, x23, xzr, lt", + "cneg x20, x20, mi", + "mov w24, #0x3f", + "mov x0, #0x3f", + "clz x25, x20", + "sub x25, x0, x25", + "sub x24, x24, x25", + "lsl x25, x20, x24", + "mov w30, #0x403e", + "sub x24, x30, x24", + "cmp x20, #0x0 (0)", + "csel x20, x21, x24, eq", + "orr x20, x23, x20", + "fmov d2, x25", + "fmov d3, x20", + "mov v2.d[1], v3.d[0]", + "msr nzcv, x22", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr w21, [x4]", - "mov w22, #0x0", - "sxtw x21, w21", - "mrs x23, nzcv", - "cmp x21, #0x0 (0)", - "mov w24, #0x8000", - "csel x24, x24, xzr, lt", - "cneg x21, x21, mi", - "mov w25, #0x3f", - "mov x0, #0x3f", - "clz x30, x21", - "sub x30, x0, x30", - "sub x25, x25, x30", - "lsl x30, x21, x25", - "mov w18, #0x403e", - "sub x25, x18, x25", - "cmp x21, #0x0 (0)", - "csel x21, x22, x25, eq", - "orr x21, x24, x21", - "fmov d2, x30", - "fmov d3, x21", - "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "msr nzcv, x23" + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fisttp dword [rax]": { @@ -6974,22 +6947,22 @@ "0xdb !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr q2, [x4]", + "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fstp tword [rax]": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": [ "0xdb !11b /7" ], @@ -6999,7 +6972,8 @@ "ldr q2, [x0, #1040]", "str d2, [x4]", "mov x21, v2.d[1]", - "strh w21, [x4, #8]", + "add x22, x4, #0x8 (8)", + "strh w21, [x22]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -7011,7 +6985,7 @@ ] }, "fcmovnb st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xc0 /0" ], @@ -7019,13 +6993,11 @@ "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7041,11 +7013,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7061,11 +7033,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7081,11 +7053,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7101,11 +7073,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7121,11 +7093,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7141,11 +7113,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7161,17 +7133,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcmovne st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xc8 /1" ], @@ -7179,13 +7151,11 @@ "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7201,11 +7171,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7221,11 +7191,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7241,11 +7211,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7261,11 +7231,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7281,11 +7251,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7301,11 +7271,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7321,17 +7291,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcmovnbe st0, st0": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": [ "0xdb 11b 0xd0 /2" ], @@ -7340,13 +7310,11 @@ "csel x20, x20, xzr, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7363,11 +7331,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7384,11 +7352,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7405,11 +7373,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7426,11 +7394,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7447,11 +7415,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7468,11 +7436,11 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] @@ -7489,17 +7457,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "fcmovnu st0, st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xdb 11b 0xd8 /3" ], @@ -7512,13 +7480,11 @@ "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7540,11 +7506,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7566,11 +7532,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7592,11 +7558,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7618,11 +7584,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7644,11 +7610,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7670,11 +7636,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7696,11 +7662,11 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", + "ldr q3, [x0, #1040]", + "add x0, x28, x20, lsl #4", "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x21" @@ -7723,23 +7689,21 @@ "mov w21, #0x37f", "strh w21, [x28, #1296]", "strb w20, [x28, #1019]", + "strb w20, [x28, #1298]", "strb w20, [x28, #1016]", "strb w20, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w20, [x28, #1022]", - "strb w20, [x28, #1298]" + "strb w20, [x28, #1022]" ] }, "fucomi st0, st0": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 42, "Comment": [ "0xdb 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -7755,10 +7719,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -7789,10 +7753,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -7807,10 +7771,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -7841,10 +7805,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -7859,10 +7823,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -7893,10 +7857,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -7911,10 +7875,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -7945,10 +7909,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -7963,10 +7927,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -7997,10 +7961,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8015,10 +7979,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8049,10 +8013,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8067,10 +8031,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8101,10 +8065,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8119,10 +8083,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8147,15 +8111,13 @@ ] }, "fcomi st0, st0": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 42, "Comment": [ "0xdb 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -8171,10 +8133,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8205,10 +8167,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8223,10 +8185,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8257,10 +8219,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8275,10 +8237,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8309,10 +8271,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8327,10 +8289,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8361,10 +8323,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8379,10 +8341,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8413,10 +8375,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8429,12 +8391,12 @@ "mov x0, sp", "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "str x30, [x0], #16", - "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "str x30, [x0], #16", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8465,10 +8427,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8483,10 +8445,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8517,10 +8479,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8535,10 +8497,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -8568,7 +8530,6 @@ "0xdc !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -8597,6 +8558,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8611,10 +8573,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -8639,7 +8601,6 @@ "0xdc !11b /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -8668,6 +8629,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8682,10 +8644,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -8710,7 +8672,6 @@ "0xdc !11b /2" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -8739,6 +8700,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8769,16 +8732,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fcomp qword [rax]": { @@ -8787,7 +8749,6 @@ "0xdc !11b /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -8816,6 +8777,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8845,17 +8808,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -8872,7 +8834,6 @@ "0xdc !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -8901,6 +8862,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -8943,7 +8905,6 @@ "0xdc !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -8972,6 +8933,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -9014,7 +8976,6 @@ "0xdc !11b /6" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -9043,6 +9004,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -9085,7 +9047,6 @@ "0xdc !11b /7" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -9114,6 +9075,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -9151,7 +9113,7 @@ ] }, "db 0xdc, 0xc0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "fadd st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -9159,9 +9121,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -9177,10 +9137,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9195,7 +9155,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -9224,10 +9184,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9271,10 +9231,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9318,10 +9278,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9365,10 +9325,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9412,10 +9372,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9459,10 +9419,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9506,10 +9466,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -9529,7 +9489,7 @@ ] }, "db 0xdc, 0xc8": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "fmul st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -9537,9 +9497,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -9555,10 +9513,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9573,7 +9531,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -9602,10 +9560,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9649,10 +9607,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9696,10 +9654,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9743,10 +9701,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9790,10 +9748,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9837,10 +9795,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9884,10 +9842,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -9907,7 +9865,7 @@ ] }, "db 0xdc, 0xe0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "fsubr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -9915,9 +9873,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -9933,10 +9889,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -9951,7 +9907,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -9960,12 +9916,12 @@ "Comment": [ "0xdc 11b 0xe1 /4" ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -9980,10 +9936,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -9998,7 +9954,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10009,10 +9965,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10027,10 +9983,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -10045,7 +10001,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10056,10 +10012,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10074,10 +10030,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -10092,7 +10048,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10103,10 +10059,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10121,10 +10077,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -10139,7 +10095,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10150,10 +10106,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10168,10 +10124,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -10186,7 +10142,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10197,10 +10153,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10215,10 +10171,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -10233,7 +10189,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10244,10 +10200,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10262,10 +10218,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -10280,12 +10236,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "db 0xdc, 0xe8": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "fsub st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -10293,9 +10249,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -10329,7 +10283,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10663,7 +10617,7 @@ ] }, "db 0xdc, 0xf0": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "fdivr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -10671,9 +10625,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -10689,10 +10641,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10707,7 +10659,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10718,10 +10670,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10736,10 +10688,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10754,7 +10706,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10765,10 +10717,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10783,10 +10735,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10801,7 +10753,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10812,10 +10764,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10830,10 +10782,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10848,7 +10800,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10859,10 +10811,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10877,10 +10829,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10895,7 +10847,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10906,10 +10858,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10924,10 +10876,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10942,7 +10894,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -10953,10 +10905,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -10971,10 +10923,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -10989,7 +10941,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -11000,10 +10952,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -11018,10 +10970,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -11036,12 +10988,12 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, "db 0xdc, 0xf8": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": [ "fdiv st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -11049,9 +11001,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -11085,7 +11035,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" ] }, @@ -11424,7 +11374,6 @@ "0xdd !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -11453,16 +11402,17 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", + "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fisttp qword [rax]": { @@ -11596,14 +11546,15 @@ ] }, "frstor [rax]": { - "ExpectedInstructionCount": 99, + "ExpectedInstructionCount": 110, "Comment": [ "0xdd !11b /4" ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", "strh w20, [x28, #1296]", - "ldr w20, [x4, #4]", + "add x20, x4, #0x4 (4)", + "ldr w20, [x20]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #1019]", "ubfx w22, w20, #8, #1", @@ -11614,7 +11565,8 @@ "strb w23, [x28, #1017]", "strb w24, [x28, #1018]", "strb w20, [x28, #1022]", - "ldr w20, [x4, #8]", + "add x20, x4, #0x8 (8)", + "ldr w20, [x20]", "ubfx w22, w20, #0, #2", "mrs x23, nzcv", "cmp x22, #0x3 (3)", @@ -11648,177 +11600,201 @@ "cset x20, ne", "orr w20, w22, w20, lsl #7", "strb w20, [x28, #1298]", - "mov x20, #0xffffffffffffffff", - "mov w22, #0xffff", - "fmov d2, x20", - "mov v2.d[1], x22", - "ldur q3, [x4, #28]", + "add x20, x4, #0x1c (28)", + "mov x22, #0xffffffffffffffff", + "mov w24, #0xffff", + "fmov d2, x22", + "mov v2.d[1], x24", + "ldr q3, [x20]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w21, #0x1 (1)", - "and w20, w20, #0x7", - "ldur q3, [x4, #38]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr q3, [x20]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldr q3, [x4, #48]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr q3, [x20]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldur q3, [x4, #58]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr q3, [x20]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldur q3, [x4, #68]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr q3, [x20]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldur q3, [x4, #78]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr q3, [x20]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldur q3, [x4, #88]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr q3, [x20]", "and v2.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldur d2, [x4, #98]", - "ldr h3, [x4, #106]", + "add x20, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldr d2, [x20]", + "add x20, x20, #0x8 (8)", + "ldr h3, [x20]", "mov v2.h[4], v3.h[0]", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "msr nzcv, x23" ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 111, + "ExpectedInstructionCount": 126, "Comment": [ "0xdd !11b /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "ldrh w21, [x28, #1296]", - "str w21, [x4]", "mov w21, #0x0", - "mov x22, x21", - "bfi x22, x20, #11, #3", - "ldrb w23, [x28, #1016]", - "ldrb w24, [x28, #1017]", - "ldrb w25, [x28, #1018]", - "ldrb w30, [x28, #1022]", - "orr x22, x22, x23, lsl #8", - "orr x22, x22, x24, lsl #9", - "orr x22, x22, x25, lsl #10", - "orr x22, x22, x30, lsl #14", - "str w22, [x4, #4]", - "ldrb w22, [x28, #1298]", - "and w23, w22, #0x1", - "mov w24, #0x3", - "mrs x25, nzcv", + "ldrh w22, [x28, #1296]", + "str w22, [x4]", + "add x22, x4, #0x4 (4)", + "mov x23, x21", + "bfi x23, x20, #11, #3", + "ldrb w24, [x28, #1016]", + "ldrb w25, [x28, #1017]", + "ldrb w30, [x28, #1018]", + "ldrb w18, [x28, #1022]", + "orr x23, x23, x24, lsl #8", + "orr x23, x23, x25, lsl #9", + "orr x23, x23, x30, lsl #10", + "orr x23, x23, x18, lsl #14", + "str w23, [x22]", + "add x22, x4, #0x8 (8)", + "ldrb w23, [x28, #1298]", + "and w24, w23, #0x1", + "mov w25, #0x3", + "mrs x30, nzcv", + "cmp x24, #0x0 (0)", + "csel x24, x25, x21, eq", + "orr w24, w21, w24", + "lsr w18, w23, #1", + "and w18, w18, #0x1", + "cmp x18, #0x0 (0)", + "csel x18, x25, x21, eq", + "orr w24, w24, w18, lsl #2", + "lsr w18, w23, #2", + "and w18, w18, #0x1", + "cmp x18, #0x0 (0)", + "csel x18, x25, x21, eq", + "orr w24, w24, w18, lsl #4", + "lsr w18, w23, #3", + "and w18, w18, #0x1", + "cmp x18, #0x0 (0)", + "csel x18, x25, x21, eq", + "orr w24, w24, w18, lsl #6", + "lsr w18, w23, #4", + "and w18, w18, #0x1", + "cmp x18, #0x0 (0)", + "csel x18, x25, x21, eq", + "orr w24, w24, w18, lsl #8", + "lsr w18, w23, #5", + "and w18, w18, #0x1", + "cmp x18, #0x0 (0)", + "csel x18, x25, x21, eq", + "orr w24, w24, w18, lsl #10", + "lsr w18, w23, #6", + "and w18, w18, #0x1", + "cmp x18, #0x0 (0)", + "csel x18, x25, x21, eq", + "orr w24, w24, w18, lsl #12", + "lsr w23, w23, #7", + "and w23, w23, #0x1", "cmp x23, #0x0 (0)", - "csel x23, x24, x21, eq", - "orr w23, w21, w23", - "lsr w30, w22, #1", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #2", - "lsr w30, w22, #2", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #4", - "lsr w30, w22, #3", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #6", - "lsr w30, w22, #4", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #8", - "lsr w30, w22, #5", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #10", - "lsr w30, w22, #6", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #12", - "lsr w22, w22, #7", - "and w22, w22, #0x1", - "cmp x22, #0x0 (0)", - "csel x22, x24, x21, eq", - "orr w22, w23, w22, lsl #14", - "str w22, [x4, #8]", - "str w21, [x4, #12]", - "str w21, [x4, #16]", - "str w21, [x4, #20]", - "str w21, [x4, #24]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "stur q2, [x4, #28]", + "csel x23, x25, x21, eq", + "orr w23, w24, w23, lsl #14", + "str w23, [x22]", + "add x22, x4, #0xc (12)", + "str w21, [x22]", + "add x22, x4, #0x10 (16)", + "str w21, [x22]", + "add x22, x4, #0x14 (20)", + "str w21, [x22]", + "add x22, x4, #0x18 (24)", + "str w21, [x22]", + "add x22, x4, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "stur q2, [x4, #38]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "str q2, [x4, #48]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "stur q2, [x4, #58]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "stur q2, [x4, #68]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "stur q2, [x4, #78]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "stur q2, [x4, #88]", + "str q2, [x22]", + "add x22, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "stur d2, [x4, #98]", + "str d2, [x22]", + "add x20, x22, #0x8 (8)", "dup v2.8h, v2.h[4]", - "str h2, [x4, #106]", + "str h2, [x20]", "mov w20, #0x37f", "strh w20, [x28, #1296]", "strb w21, [x28, #1019]", + "strb w21, [x28, #1298]", "strb w21, [x28, #1016]", "strb w21, [x28, #1017]", "strb w21, [x28, #1018]", "strb w21, [x28, #1022]", - "strb w21, [x28, #1298]", - "msr nzcv, x25" + "msr nzcv, x30" ] }, "fnstsw [rax]": { @@ -11827,14 +11803,14 @@ "0xdd !11b /7" ], "ExpectedArm64ASM": [ - "mov w20, #0x0", - "ldrb w21, [x28, #1019]", - "bfi x20, x21, #11, #3", - "ldrb w21, [x28, #1016]", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "bfi x21, x20, #11, #3", + "ldrb w20, [x28, #1016]", "ldrb w22, [x28, #1017]", "ldrb w23, [x28, #1018]", "ldrb w24, [x28, #1022]", - "orr x20, x20, x21, lsl #8", + "orr x20, x21, x20, lsl #8", "orr x20, x20, x22, lsl #9", "orr x20, x20, x23, lsl #10", "orr x20, x20, x24, lsl #14", @@ -11842,18 +11818,16 @@ ] }, "ffree st0": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": [ "0xdd 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w20, w20, #0x0 (0)", - "and w20, w20, #0x7", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w20, w22, w20", - "bic w20, w21, w20", + "mov w21, #0x1", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "bic w20, w22, w20", "strb w20, [x28, #1298]" ] }, @@ -11970,24 +11944,11 @@ ] }, "fst st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 0, "Comment": [ "0xdd 11b 0xd0 /2" ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", - "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", - "strb w20, [x28, #1298]" - ] + "ExpectedArm64ASM": [] }, "fst st1": { "ExpectedInstructionCount": 12, @@ -11996,16 +11957,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "mov w21, #0x1", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", - "lsl w21, w21, w22", - "orr w20, w20, w21", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", "strb w20, [x28, #1298]" ] }, @@ -12016,16 +11977,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -12036,16 +11997,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -12056,16 +12017,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -12076,16 +12037,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -12096,16 +12057,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -12116,43 +12077,36 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, "fstp st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 11, "Comment": [ "0xdd 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w21, w23, w21", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", - "lsl w22, w23, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", + "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "bic w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fstp st1": { @@ -12162,11 +12116,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x22, lsl #4", "str q2, [x0, #1040]", "ldrb w23, [x28, #1298]", @@ -12188,10 +12142,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w22, [x28, #1298]", @@ -12214,10 +12168,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w22, [x28, #1298]", @@ -12240,10 +12194,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w22, [x28, #1298]", @@ -12266,10 +12220,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w22, [x28, #1298]", @@ -12292,10 +12246,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w22, [x28, #1298]", @@ -12318,10 +12272,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w22, [x28, #1298]", @@ -12338,16 +12292,14 @@ ] }, "fucom st0": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 43, "Comment": [ "0xdd 11b 0xe0 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -12363,10 +12315,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12397,10 +12349,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12415,10 +12368,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12431,16 +12384,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucom st2": { @@ -12450,10 +12402,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12468,10 +12421,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12484,16 +12437,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucom st3": { @@ -12503,10 +12455,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12521,10 +12474,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12537,16 +12490,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucom st4": { @@ -12556,10 +12508,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12574,10 +12527,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12590,16 +12543,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucom st5": { @@ -12609,10 +12561,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12627,10 +12580,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12643,16 +12596,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucom st6": { @@ -12662,10 +12614,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12680,10 +12633,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12696,16 +12649,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucom st7": { @@ -12715,10 +12667,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -12733,10 +12686,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12749,29 +12702,26 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "fucomp st0": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 51, "Comment": [ "0xdd 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -12787,10 +12737,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12829,12 +12779,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -12848,10 +12799,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12863,20 +12814,19 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "mov x23, x0", + "ubfx x24, x23, #1, #1", + "ubfx x25, x23, #0, #1", + "ubfx x23, x23, #2, #1", + "orr w24, w24, w23", + "orr w25, w25, w23", + "strb w24, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w23, [x28, #1018]", + "strb w25, [x28, #1022]", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -12890,11 +12840,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -12908,10 +12859,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12923,17 +12874,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -12951,11 +12901,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -12968,11 +12919,11 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "ldrh w0, [x28, #1296]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -12984,17 +12935,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -13012,11 +12962,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -13030,10 +12981,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -13045,17 +12996,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -13073,11 +13023,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -13091,10 +13042,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -13106,17 +13057,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -13134,11 +13084,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -13152,10 +13103,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -13167,17 +13118,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -13195,11 +13145,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -13213,10 +13164,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -13228,17 +13179,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -13255,8 +13205,7 @@ "0xde !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13268,7 +13217,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13284,6 +13233,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13298,10 +13248,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -13326,8 +13276,7 @@ "0xde !11b /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13339,7 +13288,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13355,6 +13304,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13369,10 +13319,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -13397,8 +13347,7 @@ "0xde !11b /2" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13410,7 +13359,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13426,6 +13375,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13456,16 +13407,15 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov x20, x0", - "ubfx x21, x20, #1, #1", - "ubfx x22, x20, #0, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", "ubfx x20, x20, #2, #1", - "orr w21, w21, w20", "orr w22, w22, w20", - "strb w21, [x28, #1016]", - "mov w21, #0x0", + "orr w23, w23, w20", + "strb w22, [x28, #1016]", "strb w21, [x28, #1017]", "strb w20, [x28, #1018]", - "strb w22, [x28, #1022]" + "strb w23, [x28, #1022]" ] }, "ficomp word [rax]": { @@ -13474,8 +13424,7 @@ "0xde !11b /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13487,7 +13436,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13503,6 +13452,8 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13532,17 +13483,16 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x21, x0", - "ubfx x22, x21, #1, #1", - "ubfx x23, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w22, w22, w21", - "orr w23, w23, w21", - "strb w22, [x28, #1016]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", - "strb w21, [x28, #1018]", - "strb w23, [x28, #1022]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -13559,8 +13509,7 @@ "0xde !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13572,7 +13521,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13588,6 +13537,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13630,8 +13580,7 @@ "0xde !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13643,7 +13592,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13659,6 +13608,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13701,8 +13651,7 @@ "0xde !11b /6" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13714,7 +13663,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13730,6 +13679,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13772,8 +13722,7 @@ "0xde !11b /7" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", + "ldrh w20, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -13785,7 +13734,7 @@ "st1 {v2.2d, v3.2d}, [x0], #32", "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", - "sxth w1, w21", + "sxth w1, w20", "ldrh w0, [x28, #1296]", "ldr x2, [x28, #1568]", "blr x2", @@ -13801,6 +13750,7 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", @@ -13838,15 +13788,13 @@ ] }, "faddp st0": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 45, "Comment": [ "0xd8 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -13862,10 +13810,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -13880,16 +13828,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st1": { @@ -13918,10 +13866,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -13936,15 +13884,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st2": { @@ -13972,10 +13920,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -13990,16 +13938,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st3": { @@ -14027,10 +13975,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -14045,16 +13993,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st4": { @@ -14082,10 +14030,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -14100,16 +14048,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st5": { @@ -14137,10 +14085,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -14155,16 +14103,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st6": { @@ -14192,10 +14140,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -14210,16 +14158,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st7": { @@ -14247,10 +14195,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1664]", "blr x5", "ldr w4, [x28, #1000]", @@ -14265,28 +14213,26 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st0": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 45, "Comment": [ "0xde 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -14302,10 +14248,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14320,16 +14266,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st1": { @@ -14358,10 +14304,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14376,15 +14322,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st2": { @@ -14412,10 +14358,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14430,16 +14376,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st3": { @@ -14467,10 +14413,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14485,16 +14431,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fmulp st4": { @@ -14522,10 +14468,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14540,16 +14486,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st5": { @@ -14577,10 +14523,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14595,16 +14541,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st6": { @@ -14632,10 +14578,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14650,16 +14596,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st7": { @@ -14687,10 +14633,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1680]", "blr x5", "ldr w4, [x28, #1000]", @@ -14705,31 +14651,32 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fcompp": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 59, "Comment": [ "0xde 11b 0xd9 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -14743,10 +14690,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -14758,25 +14705,25 @@ "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", - "mov w23, #0x0", - "strb w23, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1298]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "mov x23, x0", + "ubfx x24, x23, #1, #1", + "ubfx x25, x23, #0, #1", + "ubfx x23, x23, #2, #1", + "orr w24, w24, w23", + "orr w25, w25, w23", + "strb w24, [x28, #1016]", + "strb w21, [x28, #1017]", + "strb w23, [x28, #1018]", + "strb w25, [x28, #1022]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "strb w20, [x28, #1019]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -14784,7 +14731,7 @@ ] }, "db 0xde, 0xe0": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 45, "Comment": [ "fsubrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -14792,9 +14739,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -14810,10 +14755,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -14828,16 +14773,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st1, st0": { @@ -14847,12 +14792,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -14866,10 +14811,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -14884,15 +14829,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st2, st0": { @@ -14902,11 +14847,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -14920,10 +14865,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -14938,16 +14883,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st3, st0": { @@ -14957,11 +14902,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -14975,10 +14920,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -14993,16 +14938,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st4, st0": { @@ -15012,11 +14957,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15030,10 +14975,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -15048,16 +14993,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st5, st0": { @@ -15067,11 +15012,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15085,10 +15030,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -15103,16 +15048,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st6, st0": { @@ -15122,11 +15067,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15140,10 +15085,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -15158,16 +15103,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st7, st0": { @@ -15177,11 +15122,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15195,10 +15140,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1672]", "blr x5", "ldr w4, [x28, #1000]", @@ -15213,20 +15158,20 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "db 0xde, 0xe8": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 45, "Comment": [ "fsubp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -15234,9 +15179,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -15270,16 +15213,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st1, st0": { @@ -15326,15 +15269,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st2, st0": { @@ -15380,16 +15323,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st3, st0": { @@ -15435,16 +15378,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st4, st0": { @@ -15490,16 +15433,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st5, st0": { @@ -15545,16 +15488,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st6, st0": { @@ -15600,16 +15543,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st7, st0": { @@ -15655,20 +15598,20 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "db 0xde, 0xf0": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 45, "Comment": [ "fdivrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -15676,9 +15619,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -15694,10 +15635,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -15712,16 +15653,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st1, st0": { @@ -15731,12 +15672,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15750,10 +15691,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -15768,15 +15709,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st2, st0": { @@ -15786,11 +15727,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15804,10 +15745,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -15822,16 +15763,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st3, st0": { @@ -15841,11 +15782,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15859,10 +15800,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -15877,16 +15818,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st4, st0": { @@ -15896,11 +15837,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15914,10 +15855,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -15932,16 +15873,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st5, st0": { @@ -15951,11 +15892,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -15969,10 +15910,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -15987,16 +15928,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st6, st0": { @@ -16006,11 +15947,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -16024,10 +15965,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -16042,16 +15983,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st7, st0": { @@ -16061,11 +16002,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -16079,10 +16020,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1688]", "blr x5", "ldr w4, [x28, #1000]", @@ -16097,20 +16038,20 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "db 0xde, 0xf8": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 45, "Comment": [ "fdivp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -16118,9 +16059,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -16154,16 +16093,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st1, st0": { @@ -16210,15 +16149,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st2, st0": { @@ -16264,16 +16203,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st3, st0": { @@ -16319,16 +16258,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st4, st0": { @@ -16374,16 +16313,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st5, st0": { @@ -16429,16 +16368,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st6, st0": { @@ -16484,16 +16423,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st7, st0": { @@ -16539,16 +16478,16 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fild word [rax]": { @@ -16557,40 +16496,40 @@ "0xdf !11b /0" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "mov w21, #0x0", + "sxth x20, w20", + "mrs x22, nzcv", + "cmp x20, #0x0 (0)", + "mov w23, #0x8000", + "csel x23, x23, xzr, lt", + "cneg x20, x20, mi", + "mov w24, #0x3f", + "mov x0, #0x3f", + "clz x25, x20", + "sub x25, x0, x25", + "sub x24, x24, x25", + "lsl x25, x20, x24", + "mov w30, #0x403e", + "sub x24, x30, x24", + "cmp x20, #0x0 (0)", + "csel x20, x21, x24, eq", + "orr x20, x23, x20", + "fmov d2, x25", + "fmov d3, x20", + "mov v2.d[1], v3.d[0]", + "msr nzcv, x22", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldrh w21, [x4]", - "mov w22, #0x0", - "sxth x21, w21", - "mrs x23, nzcv", - "cmp x21, #0x0 (0)", - "mov w24, #0x8000", - "csel x24, x24, xzr, lt", - "cneg x21, x21, mi", - "mov w25, #0x3f", - "mov x0, #0x3f", - "clz x30, x21", - "sub x30, x0, x30", - "sub x25, x25, x30", - "lsl x30, x21, x25", - "mov w18, #0x403e", - "sub x25, x18, x25", - "cmp x21, #0x0 (0)", - "csel x21, x22, x25, eq", - "orr x21, x24, x21", - "fmov d2, x30", - "fmov d3, x21", - "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "msr nzcv, x23" + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fisttp word [rax]": { @@ -16729,15 +16668,6 @@ "0xdf !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", - "strb w20, [x28, #1019]", "ldr q2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -16767,8 +16697,17 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", + "ldrb w20, [x28, #1019]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fbstp tword [rax]": { @@ -16923,14 +16862,14 @@ "0xdf 11b 0xe0 /4" ], "ExpectedArm64ASM": [ - "mov w20, #0x0", - "ldrb w21, [x28, #1019]", - "bfi x20, x21, #11, #3", - "ldrb w21, [x28, #1016]", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "bfi x21, x20, #11, #3", + "ldrb w20, [x28, #1016]", "ldrb w22, [x28, #1017]", "ldrb w23, [x28, #1018]", "ldrb w24, [x28, #1022]", - "orr x20, x20, x21, lsl #8", + "orr x20, x21, x20, lsl #8", "orr x20, x20, x22, lsl #9", "orr x20, x20, x23, lsl #10", "orr x20, x20, x24, lsl #14", @@ -16938,15 +16877,13 @@ ] }, "fucomip st0": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 50, "Comment": [ "0xdf 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -16962,10 +16899,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17004,12 +16941,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17023,10 +16960,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17064,11 +17001,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17082,10 +17019,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17124,11 +17061,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17142,10 +17079,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17184,11 +17121,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17202,10 +17139,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17244,11 +17181,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17262,10 +17199,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17304,11 +17241,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17322,10 +17259,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17364,11 +17301,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17382,10 +17319,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17418,15 +17355,13 @@ ] }, "fcomip st0": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 50, "Comment": [ "0xdf 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -17442,10 +17377,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17484,12 +17419,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17503,10 +17438,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17544,11 +17479,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17562,10 +17497,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17604,11 +17539,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17622,10 +17557,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17664,11 +17599,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17682,10 +17617,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17724,11 +17659,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17742,10 +17677,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17784,11 +17719,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17802,10 +17737,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", @@ -17844,11 +17779,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -17862,10 +17797,10 @@ "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", "str x30, [x0], #16", "ldrh w0, [x28, #1296]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", "ldr x5, [x28, #1560]", "blr x5", "ldr w4, [x28, #1000]", diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index e8de0d8769..621028a55b 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -20,12 +20,12 @@ "0xd8 !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -36,12 +36,12 @@ "0xd8 !11b /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -52,22 +52,22 @@ "0xd8 !11b /2" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcomp dword [rax]": { @@ -76,14 +76,14 @@ "0xd8 !11b /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -91,11 +91,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -108,9 +108,9 @@ "0xd8 !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d3, d2", @@ -124,9 +124,9 @@ "0xd8 !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", @@ -140,9 +140,9 @@ "0xd8 !11b /6" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d3, d2", @@ -156,9 +156,9 @@ "0xd8 !11b /7" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", @@ -167,20 +167,18 @@ ] }, "fadd st0, st0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0xd8 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fadd d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -191,13 +189,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -209,13 +207,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -227,13 +225,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -245,13 +243,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -263,13 +261,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -281,13 +279,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -299,32 +297,30 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "fmul st0, st0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0xd8 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fmul d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -335,13 +331,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -353,13 +349,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -371,13 +367,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -389,13 +385,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -407,13 +403,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -425,13 +421,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -443,28 +439,26 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "fcom st0, st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xd8 11b 0xd0 /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -487,23 +481,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st2": { @@ -513,23 +507,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st3": { @@ -539,23 +533,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st4": { @@ -565,23 +559,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st5": { @@ -591,23 +585,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st6": { @@ -617,23 +611,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcom st0, st7": { @@ -643,36 +637,34 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcomp st0, st0": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 24, "Comment": [ "0xd8 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -703,15 +695,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "mov w21, #0x0", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -719,11 +711,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -737,15 +729,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -753,11 +745,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -771,15 +763,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -787,11 +779,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -805,15 +797,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -821,11 +813,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -839,15 +831,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -855,11 +847,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -873,15 +865,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -889,11 +881,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -907,15 +899,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -923,11 +915,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -935,20 +927,18 @@ ] }, "fsub st0, st0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0xd8 11b 0xe0 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -959,13 +949,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -977,13 +967,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -995,13 +985,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1013,13 +1003,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1031,13 +1021,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1049,13 +1039,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1067,32 +1057,30 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", + "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "fsubr st0, st0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0xd8 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -1223,20 +1211,18 @@ ] }, "fdiv st0, st0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0xd8 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -1247,13 +1233,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1265,13 +1251,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1283,13 +1269,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1301,13 +1287,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1319,13 +1305,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1337,13 +1323,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -1355,32 +1341,30 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", + "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "fdivr st0, st0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0xd8 11b 0xf8 /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -1516,19 +1500,19 @@ "0xd9 !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr s2, [x4]", "fcvt d2, s2", + "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fst dword [rax]": { @@ -1541,7 +1525,7 @@ "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "fcvt s2, d2", - "str s2, [x4]" + "str d2, [x4]" ] }, "fstp dword [rax]": { @@ -1554,7 +1538,7 @@ "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "fcvt s2, d2", - "str s2, [x4]", + "str d2, [x4]", "ldrb w21, [x28, #1298]", "mov w22, #0x1", "lsl w22, w22, w20", @@ -1648,75 +1632,81 @@ ] }, "fnstenv [rax]": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 70, "Comment": [ "0xd9 !11b /6" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1296]", - "str w20, [x4]", - "mov w20, #0x0", - "ldrb w21, [x28, #1019]", - "mov x0, x20", - "bfi x0, x21, #11, #3", - "mov x21, x0", - "ldrb w22, [x28, #1016]", - "ldrb w23, [x28, #1017]", - "ldrb w24, [x28, #1018]", - "ldrb w25, [x28, #1022]", - "orr x21, x21, x22, lsl #8", - "orr x21, x21, x23, lsl #9", - "orr x21, x21, x24, lsl #10", - "orr x21, x21, x25, lsl #14", - "str w21, [x4, #4]", - "ldrb w21, [x28, #1298]", - "and w22, w21, #0x1", - "mov w23, #0x3", - "mrs x24, nzcv", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "ldrh w22, [x28, #1296]", + "str w22, [x4]", + "add x22, x4, #0x4 (4)", + "mov x0, x21", + "bfi x0, x20, #11, #3", + "mov x20, x0", + "ldrb w23, [x28, #1016]", + "ldrb w24, [x28, #1017]", + "ldrb w25, [x28, #1018]", + "ldrb w30, [x28, #1022]", + "orr x20, x20, x23, lsl #8", + "orr x20, x20, x24, lsl #9", + "orr x20, x20, x25, lsl #10", + "orr x20, x20, x30, lsl #14", + "str w20, [x22]", + "add x20, x4, #0x8 (8)", + "ldrb w22, [x28, #1298]", + "and w23, w22, #0x1", + "mov w24, #0x3", + "mrs x25, nzcv", + "cmp x23, #0x0 (0)", + "csel x23, x24, x21, eq", + "orr w23, w21, w23", + "lsr w30, w22, #1", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #2", + "lsr w30, w22, #2", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #4", + "lsr w30, w22, #3", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #6", + "lsr w30, w22, #4", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #8", + "lsr w30, w22, #5", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #10", + "lsr w30, w22, #6", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #12", + "lsr w22, w22, #7", + "and w22, w22, #0x1", "cmp x22, #0x0 (0)", - "csel x22, x23, x20, eq", - "orr w22, w20, w22", - "lsr w25, w21, #1", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #2", - "lsr w25, w21, #2", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #4", - "lsr w25, w21, #3", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #6", - "lsr w25, w21, #4", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #8", - "lsr w25, w21, #5", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #10", - "lsr w25, w21, #6", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #12", - "lsr w21, w21, #7", - "and w21, w21, #0x1", - "cmp x21, #0x0 (0)", - "csel x21, x23, x20, eq", - "orr w21, w22, w21, lsl #14", - "str w21, [x4, #8]", - "str w20, [x4, #12]", - "str w20, [x4, #16]", - "str w20, [x4, #20]", - "str w20, [x4, #24]", - "msr nzcv, x24" + "csel x22, x24, x21, eq", + "orr w22, w23, w22, lsl #14", + "str w22, [x20]", + "add x20, x4, #0xc (12)", + "str w21, [x20]", + "add x20, x4, #0x10 (16)", + "str w21, [x20]", + "add x20, x4, #0x14 (20)", + "str w21, [x20]", + "add x20, x4, #0x18 (24)", + "str w21, [x20]", + "msr nzcv, x25" ] }, "fnstcw [rax]": { @@ -1730,26 +1720,24 @@ ] }, "fld st0": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": [ "0xd9 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st1": { @@ -1766,13 +1754,13 @@ "ldr d2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st2": { @@ -1789,13 +1777,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st3": { @@ -1812,13 +1800,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st4": { @@ -1835,13 +1823,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st5": { @@ -1858,13 +1846,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st6": { @@ -1881,13 +1869,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fld st7": { @@ -1904,34 +1892,23 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fxch st0, st0": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 2, "Comment": [ "0xd9 11b 0xc8 /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "ldr q3, [x0, #1040]", - "strb w21, [x28, #1017]", - "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "mov w20, #0x0", + "strb w20, [x28, #1017]" ] }, "fxch st0, st1": { @@ -1941,18 +1918,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st2": { @@ -1962,18 +1939,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st3": { @@ -1983,18 +1960,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st4": { @@ -2004,18 +1981,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st5": { @@ -2025,18 +2002,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st6": { @@ -2046,18 +2023,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fxch st0, st7": { @@ -2067,18 +2044,18 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #1040]", - "mov w22, #0x0", - "strb w22, [x28, #1017]", + "ldr d2, [x0, #1040]", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str d3, [x0, #1040]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1017]" ] }, "fnop": { @@ -2123,24 +2100,24 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "fmov d2, x21", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #1040]", - "mov w20, #0x0", - "fmov d3, x20", - "fcmp d2, d3", - "cset w21, vs", + "ldr d3, [x0, #1040]", + "fcmp d3, d2", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fxam": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xd9 11b 0xe5 /4" ], @@ -2153,16 +2130,14 @@ "strb w21, [x28, #1017]", "ldrb w21, [x28, #1298]", "lsr w20, w21, w20", - "mov w21, #0x1", "and w20, w20, #0x1", - "mov w22, #0x0", - "mrs x23, nzcv", + "mrs x21, nzcv", "cmp x20, #0x1 (1)", - "csel x21, x22, x21, eq", - "strb w21, [x28, #1016]", + "cset x22, ne", + "strb w22, [x28, #1016]", "strb w20, [x28, #1018]", - "strb w21, [x28, #1022]", - "msr nzcv, x23" + "strb w22, [x28, #1022]", + "msr nzcv, x21" ] }, "fld1": { @@ -2171,19 +2146,19 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ + "mov x20, #0x3ff0000000000000", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x3ff0000000000000", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldl2t": { @@ -2192,22 +2167,22 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ + "mov x20, #0xa372", + "movk x20, #0x979, lsl #16", + "movk x20, #0x934f, lsl #32", + "movk x20, #0x400a, lsl #48", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0xa372", - "movk x21, #0x979, lsl #16", - "movk x21, #0x934f, lsl #32", - "movk x21, #0x400a, lsl #48", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldl2e": { @@ -2216,22 +2191,22 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ + "mov x20, #0x82fe", + "movk x20, #0x652b, lsl #16", + "movk x20, #0x1547, lsl #32", + "movk x20, #0x3ff7, lsl #48", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x82fe", - "movk x21, #0x652b, lsl #16", - "movk x21, #0x1547, lsl #32", - "movk x21, #0x3ff7, lsl #48", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldpi": { @@ -2240,22 +2215,22 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ + "mov x20, #0x2d18", + "movk x20, #0x5444, lsl #16", + "movk x20, #0x21fb, lsl #32", + "movk x20, #0x4009, lsl #48", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x2d18", - "movk x21, #0x5444, lsl #16", - "movk x21, #0x21fb, lsl #32", - "movk x21, #0x4009, lsl #48", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldlg2": { @@ -2264,22 +2239,22 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ + "mov x20, #0x79ff", + "movk x20, #0x509f, lsl #16", + "movk x20, #0x4413, lsl #32", + "movk x20, #0x3fd3, lsl #48", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x79ff", - "movk x21, #0x509f, lsl #16", - "movk x21, #0x4413, lsl #32", - "movk x21, #0x3fd3, lsl #48", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldln2": { @@ -2288,22 +2263,22 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ + "mov x20, #0x39ef", + "movk x20, #0xfefa, lsl #16", + "movk x20, #0x2e42, lsl #32", + "movk x20, #0x3fe6, lsl #48", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x39ef", - "movk x21, #0xfefa, lsl #16", - "movk x21, #0x2e42, lsl #32", - "movk x21, #0x3fe6, lsl #48", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fldz": { @@ -2312,19 +2287,19 @@ "0xd9 11b 0xee /5" ], "ExpectedArm64ASM": [ + "mov w20, #0x0", + "fmov d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov w21, #0x0", - "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "f2xm1": { @@ -2392,22 +2367,16 @@ ] }, "fyl2x": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 64, "Comment": [ "0xd9 11b 0xf1 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v2.8b", @@ -2463,7 +2432,10 @@ "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fptan": { @@ -2473,16 +2445,11 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1298]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", - "strb w22, [x28, #1019]", + "mov w21, #0x0", + "mov x22, #0x3ff0000000000000", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #1040]", + "ldr d3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2507,7 +2474,7 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov v0.8b, v2.8b", + "mov v0.8b, v3.8b", "ldrh w0, [x28, #1296]", "ldr x1, [x28, #1752]", "blr x1", @@ -2533,34 +2500,33 @@ "ldp x19, x29, [x28, #392]", "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", - "mov v2.8b, v0.8b", - "mov x21, #0x3ff0000000000000", - "fmov d3, x21", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "mov v3.8b, v0.8b", + "add x0, x28, x20, lsl #4", + "str d3, [x0, #1040]", + "mov w22, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str d3, [x0, #1040]" + "ldrb w23, [x28, #1298]", + "lsl w20, w22, w20", + "orr w20, w23, w20", + "strb w20, [x28, #1298]", + "strb w21, [x28, #1018]" ] }, "fpatan": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 64, "Comment": [ "0xd9 11b 0xf3 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v3.8b", @@ -2616,7 +2582,10 @@ "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fxtract": { @@ -2626,28 +2595,28 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1298]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", - "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "mov x21, v2.d[0]", - "and x23, x21, #0x7ff0000000000000", - "lsr x23, x23, #52", - "sub x23, x23, #0x3ff (1023)", - "scvtf d2, x23", + "and x22, x21, #0x7ff0000000000000", + "lsr x22, x22, #52", + "sub x22, x22, #0x3ff (1023)", + "scvtf d2, x22", "and x21, x21, #0x800fffffffffffff", "orr x21, x21, #0x3ff0000000000000", "fmov d3, x21", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str d3, [x0, #1040]" + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str d3, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fprem1": { @@ -2657,11 +2626,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v2.8b", "mov v1.8b, v3.8b", @@ -2715,10 +2685,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fdecstp": { @@ -2752,11 +2721,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v2.8b", "mov v1.8b, v3.8b", @@ -2810,34 +2780,31 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fyl2xp1": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Comment": [ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ + "mov x20, #0x3ff0000000000000", + "fmov d2, x20", "ldrb w20, [x28, #1019]", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #1040]", + "fadd d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", - "mov x20, #0x3ff0000000000000", - "fmov d4, x20", - "fadd d2, d2, d4", "mov v0.8b, v2.8b", "mov v1.8b, v3.8b", "mrs x0, nzcv", @@ -2891,7 +2858,10 @@ "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fsqrt": { @@ -2909,22 +2879,17 @@ ] }, "fsincos": { - "ExpectedInstructionCount": 119, + "ExpectedInstructionCount": 125, "Comment": [ "0xd9 11b 0xfb /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1298]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", - "strb w22, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2949,7 +2914,7 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov v0.8b, v2.8b", + "mov v0.8b, v3.8b", "ldrh w0, [x28, #1296]", "ldr x1, [x28, #1736]", "blr x1", @@ -2976,6 +2941,20 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v3.8b, v0.8b", + "add x0, x28, x20, lsl #4", + "str d3, [x0, #1040]", + "mov w22, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w23, [x28, #1298]", + "lsl w22, w22, w20", + "orr w22, w23, w22", + "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -3027,12 +3006,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str d3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "frndint": { @@ -3056,10 +3032,10 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v2.8b", @@ -3125,6 +3101,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "mrs x0, nzcv", @@ -3178,10 +3155,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fcos": { @@ -3191,6 +3167,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "mrs x0, nzcv", @@ -3244,10 +3221,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1018]" ] }, "fiadd dword [rax]": { @@ -3256,12 +3232,12 @@ "0xda !11b /0" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -3272,12 +3248,12 @@ "0xda !11b /1" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -3288,22 +3264,22 @@ "0xda !11b /2" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "ficomp dword [rax]": { @@ -3312,14 +3288,14 @@ "0xda !11b /3" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -3327,11 +3303,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -3344,9 +3320,9 @@ "0xda !11b /4" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d3, d2", @@ -3360,9 +3336,9 @@ "0xda !11b /5" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", @@ -3376,9 +3352,9 @@ "0xda !11b /6" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d3, d2", @@ -3392,9 +3368,9 @@ "0xda !11b /7" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", @@ -3403,7 +3379,7 @@ ] }, "fcmovb st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xda 11b 0xc0 /0" ], @@ -3411,15 +3387,13 @@ "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st1": { @@ -3433,13 +3407,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st2": { @@ -3453,13 +3427,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st3": { @@ -3473,13 +3447,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st4": { @@ -3493,13 +3467,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st5": { @@ -3513,13 +3487,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st6": { @@ -3533,13 +3507,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovb st0, st7": { @@ -3553,17 +3527,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmove st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xda 11b 0xc8 /1" ], @@ -3571,15 +3545,13 @@ "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st1": { @@ -3593,13 +3565,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st2": { @@ -3613,13 +3585,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st3": { @@ -3633,13 +3605,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st4": { @@ -3653,13 +3625,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st5": { @@ -3673,13 +3645,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st6": { @@ -3693,13 +3665,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmove st0, st7": { @@ -3713,17 +3685,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st0": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd0 /0" ], @@ -3733,15 +3705,13 @@ "csel x20, x20, x21, eq", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st1": { @@ -3757,13 +3727,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st2": { @@ -3779,13 +3749,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st3": { @@ -3801,13 +3771,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st4": { @@ -3823,13 +3793,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st5": { @@ -3845,13 +3815,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st6": { @@ -3867,13 +3837,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovbe st0, st7": { @@ -3889,17 +3859,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovu st0, st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xda 11b 0xd8 /1" ], @@ -3912,15 +3882,13 @@ "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -3940,13 +3908,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -3966,13 +3934,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -3992,13 +3960,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4018,13 +3986,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4044,13 +4012,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4070,13 +4038,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4096,32 +4064,32 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, "fucompp": { - "ExpectedInstructionCount": 31, + "ExpectedInstructionCount": 32, "Comment": [ "0xda 11b 0xe9 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "mov w21, #0x0", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -4129,16 +4097,17 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "strb w20, [x28, #1019]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -4151,19 +4120,19 @@ "0xdf !11b /5" ], "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fisttp dword [rax]": { @@ -4229,7 +4198,6 @@ "0xdb !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr q2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -4257,16 +4225,17 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v2.8b, v0.8b", + "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fstp tword [rax]": { @@ -4319,7 +4288,7 @@ ] }, "fcmovnb st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xc0 /0" ], @@ -4327,15 +4296,13 @@ "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st1": { @@ -4349,13 +4316,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st2": { @@ -4369,13 +4336,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st3": { @@ -4389,13 +4356,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st4": { @@ -4409,13 +4376,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st5": { @@ -4429,13 +4396,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st6": { @@ -4449,13 +4416,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovnb st0, st7": { @@ -4469,17 +4436,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]" ] }, "fcmovne st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xc8 /1" ], @@ -4487,15 +4454,13 @@ "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st1": { @@ -4509,13 +4474,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st2": { @@ -4529,13 +4494,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st3": { @@ -4549,13 +4514,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st4": { @@ -4569,13 +4534,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st5": { @@ -4589,13 +4554,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st6": { @@ -4609,13 +4574,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovne st0, st7": { @@ -4629,17 +4594,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st0": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": [ "0xdb 11b 0xd0 /2" ], @@ -4648,15 +4613,13 @@ "csel x20, x20, xzr, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st1": { @@ -4671,13 +4634,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st2": { @@ -4692,13 +4655,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st3": { @@ -4713,13 +4676,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st4": { @@ -4734,13 +4697,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st5": { @@ -4755,13 +4718,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st6": { @@ -4776,13 +4739,13 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovnbe st0, st7": { @@ -4797,17 +4760,17 @@ "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", + "add x0, x28, x20, lsl #4", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str d2, [x0, #1040]" ] }, "fcmovnu st0, st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xdb 11b 0xd8 /3" ], @@ -4820,15 +4783,13 @@ "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4848,13 +4809,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4874,13 +4835,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4900,13 +4861,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4926,13 +4887,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4952,13 +4913,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -4978,13 +4939,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -5004,13 +4965,13 @@ "ldrb w20, [x28, #1019]", "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #1040]", - "bsl v2.16b, v4.16b, v3.16b", + "ldr d3, [x0, #1040]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]", + "ldr d4, [x0, #1040]", + "bsl v2.16b, v3.16b, v4.16b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", "msr nzcv, x21" ] }, @@ -5038,23 +4999,21 @@ "msr fpcr, x0", "strh w20, [x28, #1296]", "strb w21, [x28, #1019]", + "strb w21, [x28, #1298]", "strb w21, [x28, #1016]", "strb w21, [x28, #1017]", "strb w21, [x28, #1018]", - "strb w21, [x28, #1022]", - "strb w21, [x28, #1298]" + "strb w21, [x28, #1022]" ] }, "fucomi st0, st0": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": [ "0xdb 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -5246,15 +5205,13 @@ ] }, "fcomi st0, st0": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": [ "0xdb 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -5451,11 +5408,11 @@ "0xdc !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -5466,11 +5423,11 @@ "0xdc !11b /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -5481,21 +5438,21 @@ "0xdc !11b /2" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fcomp qword [rax]": { @@ -5504,13 +5461,13 @@ "0xdc !11b /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -5518,11 +5475,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -5535,8 +5492,8 @@ "0xdc !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d3, d2", @@ -5550,8 +5507,8 @@ "0xdc !11b /5" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", @@ -5565,8 +5522,8 @@ "0xdc !11b /6" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d3, d2", @@ -5580,8 +5537,8 @@ "0xdc !11b /7" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", @@ -5590,7 +5547,7 @@ ] }, "db 0xdc, 0xc0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "fadd st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -5598,14 +5555,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fadd d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5622,7 +5577,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5640,7 +5595,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5658,7 +5613,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5676,7 +5631,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5694,7 +5649,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5712,7 +5667,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5730,13 +5685,13 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] }, "db 0xdc, 0xc8": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "fmul st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -5744,14 +5699,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fmul d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5768,7 +5721,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5786,7 +5739,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5804,7 +5757,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5822,7 +5775,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5840,7 +5793,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5858,7 +5811,7 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] @@ -5876,13 +5829,13 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]" ] }, "db 0xdc, 0xe0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "fsubr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -5890,14 +5843,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5908,14 +5859,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5926,14 +5877,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5944,14 +5895,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5962,14 +5913,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5980,14 +5931,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -5998,14 +5949,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6016,19 +5967,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "db 0xdc, 0xe8": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "fsub st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -6036,14 +5987,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6174,7 +6123,7 @@ ] }, "db 0xdc, 0xf0": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "fdivr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -6182,14 +6131,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6200,14 +6147,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6218,14 +6165,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6236,14 +6183,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6254,14 +6201,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6272,14 +6219,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6290,14 +6237,14 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6308,19 +6255,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "add x0, x28, x21, lsl #4", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, "db 0xdc, 0xf8": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "fdiv st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -6328,14 +6275,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] }, @@ -6471,18 +6416,18 @@ "0xdd !11b /0" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", "ldr d2, [x4]", + "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fisttp qword [rax]": { @@ -6870,9 +6815,9 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "ldrh w21, [x28, #1296]", - "str w21, [x4]", "mov w21, #0x0", + "ldrh w22, [x28, #1296]", + "str w22, [x4]", "mov x22, x21", "bfi x22, x20, #11, #3", "ldrb w23, [x28, #1016]", @@ -7190,11 +7135,11 @@ "mov w20, #0x37f", "strh w20, [x28, #1296]", "strb w21, [x28, #1019]", + "strb w21, [x28, #1298]", "strb w21, [x28, #1016]", "strb w21, [x28, #1017]", "strb w21, [x28, #1018]", "strb w21, [x28, #1022]", - "strb w21, [x28, #1298]", "msr nzcv, x25" ] }, @@ -7204,14 +7149,14 @@ "0xdd !11b /7" ], "ExpectedArm64ASM": [ - "mov w20, #0x0", - "ldrb w21, [x28, #1019]", - "bfi x20, x21, #11, #3", - "ldrb w21, [x28, #1016]", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "bfi x21, x20, #11, #3", + "ldrb w20, [x28, #1016]", "ldrb w22, [x28, #1017]", "ldrb w23, [x28, #1018]", "ldrb w24, [x28, #1022]", - "orr x20, x20, x21, lsl #8", + "orr x20, x21, x20, lsl #8", "orr x20, x20, x22, lsl #9", "orr x20, x20, x23, lsl #10", "orr x20, x20, x24, lsl #14", @@ -7219,18 +7164,16 @@ ] }, "ffree st0": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": [ "0xdd 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w20, w20, #0x0 (0)", - "and w20, w20, #0x7", - "ldrb w21, [x28, #1298]", - "mov w22, #0x1", - "lsl w20, w22, w20", - "bic w20, w21, w20", + "mov w21, #0x1", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "bic w20, w22, w20", "strb w20, [x28, #1298]" ] }, @@ -7347,24 +7290,11 @@ ] }, "fst st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 0, "Comment": [ "0xdd 11b 0xd0 /2" ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", - "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", - "strb w20, [x28, #1298]" - ] + "ExpectedArm64ASM": [] }, "fst st1": { "ExpectedInstructionCount": 12, @@ -7373,16 +7303,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", - "lsl w21, w21, w22", - "orr w20, w20, w21", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", "strb w20, [x28, #1298]" ] }, @@ -7393,16 +7323,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldr d2, [x0, #1040]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -7413,16 +7343,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldr d2, [x0, #1040]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -7433,16 +7363,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldr d2, [x0, #1040]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -7453,16 +7383,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldr d2, [x0, #1040]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -7473,16 +7403,16 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldr d2, [x0, #1040]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, @@ -7493,43 +7423,36 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w20, [x28, #1298]", + "ldr d2, [x0, #1040]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", "mov w22, #0x1", - "lsl w21, w22, w21", - "orr w20, w20, w21", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1298]" ] }, "fstp st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 11, "Comment": [ "0xdd 11b 0xd8 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w21, w23, w21", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", - "lsl w22, w23, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1298]", + "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "bic w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fstp st1": { @@ -7539,13 +7462,13 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w23, [x28, #1298]", "lsl w22, w21, w22", "orr w22, w23, w22", @@ -7565,12 +7488,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w22, [x28, #1298]", "mov w23, #0x1", "lsl w21, w23, w21", @@ -7591,12 +7514,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w22, [x28, #1298]", "mov w23, #0x1", "lsl w21, w23, w21", @@ -7617,12 +7540,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w22, [x28, #1298]", "mov w23, #0x1", "lsl w21, w23, w21", @@ -7643,12 +7566,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w22, [x28, #1298]", "mov w23, #0x1", "lsl w21, w23, w21", @@ -7669,12 +7592,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w22, [x28, #1298]", "mov w23, #0x1", "lsl w21, w23, w21", @@ -7695,12 +7618,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #1040]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]", + "str d2, [x0, #1040]", "ldrb w22, [x28, #1298]", "mov w23, #0x1", "lsl w21, w23, w21", @@ -7715,16 +7638,14 @@ ] }, "fucom st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xdd 11b 0xe0 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -7747,23 +7668,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st2": { @@ -7773,23 +7694,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st3": { @@ -7799,23 +7720,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st4": { @@ -7825,23 +7746,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st5": { @@ -7851,23 +7772,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st6": { @@ -7877,23 +7798,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucom st7": { @@ -7903,36 +7824,34 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "fucomp st0": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 24, "Comment": [ "0xdd 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", "mov w21, #0x0", - "add w22, w20, #0x0 (0)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -7963,15 +7882,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "mov w21, #0x0", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -7979,11 +7898,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -7997,15 +7916,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x2 (2)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -8013,11 +7932,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8031,15 +7950,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x3 (3)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -8047,11 +7966,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8065,15 +7984,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x4 (4)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -8081,11 +8000,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8099,15 +8018,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x5 (5)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -8115,11 +8034,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8133,15 +8052,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x6 (6)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -8149,11 +8068,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8167,15 +8086,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "mov w21, #0x0", + "add w22, w20, #0x7 (7)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -8183,11 +8102,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8200,13 +8119,13 @@ "0xde !11b /0" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", + "fadd d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -8217,13 +8136,13 @@ "0xde !11b /1" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", + "fmul d2, d2, d3", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]" ] @@ -8234,23 +8153,23 @@ "0xde !11b /2" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w20, #0x0", - "cset w21, vs", + "cset w20, vs", "cset w22, eq", "cset w23, mi", - "orr w23, w23, w21", + "orr w23, w23, w20", "strb w23, [x28, #1016]", - "orr w22, w22, w21", + "orr w22, w22, w20", "strb w22, [x28, #1022]", - "strb w20, [x28, #1017]", - "strb w21, [x28, #1018]" + "strb w21, [x28, #1017]", + "strb w20, [x28, #1018]" ] }, "ficomp word [rax]": { @@ -8259,15 +8178,15 @@ "0xde !11b /3" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", + "mov w21, #0x0", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w21, #0x1", - "mov w22, #0x0", + "mov w22, #0x1", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -8275,11 +8194,11 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1298]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8292,10 +8211,10 @@ "0xde !11b /4" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d3, d2", @@ -8309,10 +8228,10 @@ "0xde !11b /5" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", @@ -8326,10 +8245,10 @@ "0xde !11b /6" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d3, d2", @@ -8343,10 +8262,10 @@ "0xde !11b /7" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, w21", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", @@ -8355,29 +8274,27 @@ ] }, "faddp st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xd8 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st1": { @@ -8394,16 +8311,16 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w23, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st2": { @@ -8419,17 +8336,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st3": { @@ -8445,17 +8362,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st4": { @@ -8471,17 +8388,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st5": { @@ -8497,17 +8414,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st6": { @@ -8523,17 +8440,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fadd d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "faddp st7": { @@ -8549,43 +8466,41 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fadd d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", + "fadd d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]" ] }, "fmulp st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "0xde 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st1": { @@ -8602,16 +8517,16 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w23, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st2": { @@ -8627,17 +8542,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st3": { @@ -8653,17 +8568,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st4": { @@ -8679,17 +8594,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st5": { @@ -8705,17 +8620,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st6": { @@ -8731,17 +8646,17 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fmulp st7": { @@ -8757,35 +8672,35 @@ "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fmul d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fmul d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fcompp": { - "ExpectedInstructionCount": 31, + "ExpectedInstructionCount": 32, "Comment": [ "0xde 11b 0xd9 /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "mov w21, #0x0", + "mov w22, #0x1", + "add w23, w20, #0x1 (1)", + "and w23, w23, #0x7", + "add x0, x28, x23, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "mov w22, #0x0", "cset w23, vs", "cset w24, eq", "cset w25, mi", @@ -8793,16 +8708,17 @@ "strb w25, [x28, #1016]", "orr w24, w24, w23", "strb w24, [x28, #1022]", - "strb w22, [x28, #1017]", + "strb w21, [x28, #1017]", "strb w23, [x28, #1018]", - "ldrb w22, [x28, #1298]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "ldrb w21, [x28, #1298]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "strb w20, [x28, #1019]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8810,7 +8726,7 @@ ] }, "db 0xde, 0xe0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "fsubrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -8818,23 +8734,21 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st1, st0": { @@ -8844,23 +8758,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w23, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st2, st0": { @@ -8870,23 +8784,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st3, st0": { @@ -8896,23 +8810,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st4, st0": { @@ -8922,23 +8836,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st5, st0": { @@ -8948,23 +8862,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st6, st0": { @@ -8974,23 +8888,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubrp st7, st0": { @@ -9000,27 +8914,27 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fsub d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "db 0xde, 0xe8": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "fsubp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -9028,23 +8942,21 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st1, st0": { @@ -9062,15 +8974,15 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st2, st0": { @@ -9087,16 +8999,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st3, st0": { @@ -9113,16 +9025,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st4, st0": { @@ -9139,16 +9051,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st5, st0": { @@ -9165,16 +9077,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st6, st0": { @@ -9191,16 +9103,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fsubp st7, st0": { @@ -9217,20 +9129,20 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "db 0xde, 0xf0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "fdivrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -9238,23 +9150,21 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st1, st0": { @@ -9264,23 +9174,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "mov w21, #0x1", "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w23, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st2, st0": { @@ -9290,23 +9200,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st3, st0": { @@ -9316,23 +9226,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st4, st0": { @@ -9342,23 +9252,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st5, st0": { @@ -9368,23 +9278,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st6, st0": { @@ -9394,23 +9304,23 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivrp st7, st0": { @@ -9420,27 +9330,27 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #1040]", "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #1040]", - "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", - "fdiv d2, d3, d2", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "db 0xde, 0xf8": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": [ "fdivp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -9448,23 +9358,21 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st1, st0": { @@ -9482,15 +9390,15 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w23, [x28, #1298]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", - "bic w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st2, st0": { @@ -9507,16 +9415,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st3, st0": { @@ -9533,16 +9441,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st4, st0": { @@ -9559,16 +9467,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st5, st0": { @@ -9585,16 +9493,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st6, st0": { @@ -9611,16 +9519,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fdivp st7, st0": { @@ -9637,16 +9545,16 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1298]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1298]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #1040]", + "ldrb w21, [x28, #1298]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "strb w20, [x28, #1019]" ] }, "fild word [rax]": { @@ -9655,20 +9563,20 @@ "0xdf !11b /0" ], "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "scvtf d2, x20", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fisttp word [rax]": { @@ -9734,15 +9642,6 @@ "0xdf !11b /4" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "ldrb w22, [x28, #1298]", - "lsl w21, w21, w20", - "orr w21, w22, w21", - "strb w21, [x28, #1298]", - "strb w20, [x28, #1019]", "ldr q2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -9798,8 +9697,17 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v2.8b, v0.8b", + "ldrb w20, [x28, #1019]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "ldrb w22, [x28, #1298]", + "lsl w20, w21, w20", + "orr w20, w22, w20", + "strb w20, [x28, #1298]" ] }, "fbstp tword [rax]": { @@ -9981,14 +9889,14 @@ "0xdf 11b 0xe0 /4" ], "ExpectedArm64ASM": [ - "mov w20, #0x0", - "ldrb w21, [x28, #1019]", - "bfi x20, x21, #11, #3", - "ldrb w21, [x28, #1016]", + "ldrb w20, [x28, #1019]", + "mov w21, #0x0", + "bfi x21, x20, #11, #3", + "ldrb w20, [x28, #1016]", "ldrb w22, [x28, #1017]", "ldrb w23, [x28, #1018]", "ldrb w24, [x28, #1022]", - "orr x20, x20, x21, lsl #8", + "orr x20, x21, x20, lsl #8", "orr x20, x20, x22, lsl #9", "orr x20, x20, x23, lsl #10", "orr x20, x20, x24, lsl #14", @@ -9996,15 +9904,13 @@ ] }, "fucomip st0": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": [ "0xdf 11b 0xe8 /5" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", @@ -10260,15 +10166,13 @@ ] }, "fcomip st0": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": [ "0xdf 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", + "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]",