From 0c327157153364fdee6c99b996a5ab7c06995261 Mon Sep 17 00:00:00 2001
From: Paulo Matos <pmatos@igalia.com>
Date: Fri, 29 Nov 2024 11:04:53 +0100
Subject: [PATCH] Update generation of stores using SVE

---
 .../Source/Interface/IR/Passes/x87StackOptimizationPass.cpp  | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp
index ca0798a6d9..b80a98483c 100644
--- a/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp
+++ b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp
@@ -5,8 +5,8 @@
 #include "Interface/IR/PassManager.h"
 #include "FEXCore/IR/IR.h"
 #include "FEXCore/Utils/Profiler.h"
-#include "FEXCore/fextl/deque.h"
 #include "FEXCore/Core/HostFeatures.h"
+#include "CodeEmitter/Emitter.h"
 
 #include <array>
 #include <cstddef>
@@ -824,7 +824,8 @@ void X87StackOptimization::Run(IREmitter* Emit) {
             }
             if (Op->StoreSize == OpSize::f80Bit) { // Part of code from StoreResult_WithOpSize()
               if (Features.SupportsSVE128) {
-                IREmit->_StoreMem(FPRClass, OpSize::f80Bit, AddrNode, StackNode);
+                auto PReg = IREmit->_InitPredicate(OpSize::i16Bit, FEXCore::ToUnderlying(ARMEmitter::PredicatePattern::SVE_VL5));
+                IREmit->_StoreMemPredicate(FPRClass, OpSize::i16Bit, StackNode, PReg, AddrNode);
               } else {
                 // For X87 extended doubles, split before storing
                 IREmit->_StoreMem(FPRClass, OpSize::i64Bit, AddrNode, StackNode);