-
Notifications
You must be signed in to change notification settings - Fork 6
/
.gitignore
177 lines (158 loc) · 2.63 KB
/
.gitignore
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
build/
### Xilinx ###
# gitignore template for Xilinx Vivado Design Suite
# website: https://www.xilinx.com/support/download.html
# [home]
*.jou
*.log
*.debug
*.str
*.zip
*.tmp
*.rst
*.os
*.js
*.pb
*.dcp
*.hwdef
*.vds
*.veo
*.wdf
*.vdi
*.dmp
*.rpx
*.rpt
*_stub.v
*_stub.vhdl
*_funcsim.v
*_funcsim.vhdl
.project
# [dir]
*.cache
.metadata
*.data
*.ipdefs
.Xil
*.sdk
*.hw
*.ip_user_files
### IP synth
*_synth_*
.jobs
### project synth
*/*.runs/synth*/*.xml
*/*.runs/synth*/*.txt
*/*.runs/synth*/*.sh
*/*.runs/synth*/*.tcl
*/*.runs/synth*/*.bat
*/*.runs/synth*/*.xdc
!*/*.runs/synth*/*utilization*.rpt
*.runs/synth*/*.xml
*.runs/synth*/*.txt
*.runs/synth*/*.sh
*.runs/synth*/*.tcl
*.runs/synth*/*.bat
*.runs/synth*/*.xdc
!*.runs/synth*/*utilization*.rpt
### project impl
*/*.runs/impl*/*.xml
*/*.runs/impl*/*.html
*/*.runs/impl*/*.txt
*/*.runs/impl*/*.sh
*/*.runs/impl*/*.tcl
*/*.runs/impl*/*.bat
!*/*.runs/impl*/*utilization*.rpt
*.runs/impl*/*.xml
*.runs/impl*/*.html
*.runs/impl*/*.txt
*.runs/impl*/*.sh
*.runs/impl*/*.tcl
*.runs/impl*/*.bat
!*.runs/impl*/*utilization*.rpt
### block design
*/*/bd/*/hdl
*/*/*/bd/*/hdl
*/*/bd/*/*.xdc
*/*/*/bd/*/*.xdc
*/*/bd/*/ip/*/*.xdc
*/*/*/bd/*/ip/*/*.xdc
*/*/bd/*/ip/*/*/
*/*/*/bd/*/ip/*/*/
*/*/bd/*/ip/*/*.vhd
*/*/*/bd/*/ip/*/*.vhd
*/*/bd/*/ip/*/*.xml
*/*/*/bd/*/ip/*/*.xml
*.c
*.h
*.vho
*.html
*/*/bd/*/ip/*/*.tcl
*/*/*/bd/*/ip/*/*.tcl
hw_handoff
ipshared
### XilinxVivado ###
#########################################################################################################
## This is an example .gitignore file for Vivado, please treat it as an example as
## it might not be complete. In addition, XAPP 1165 should be followed.
#########
!.gitignore
###########################################################################
## VIVADO
#Source files:
#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
!*.vhd
!*.v
!*.bd
!*.edif
#IP files
#.xci: IP-core property file with core container disabled
!*.xci
#*.dcp (checkpoint files: better be ignored!)
#!*.dcp
!*.vds
!*.pb
#All bd comments and layout coordinates are stored within .ui
!*.ui
!*.ooc
#System Generator
!*.mdl
!*.slx
!*.bxml
#Simulation logic analyzer
!*.wcfg
!*.coe
#MIG
!*.prj
!*.mem
#Project files
#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
#Do NOT ignore *.xpr files
!*.xpr
#Include *.xml files for 2013.4 or earlier version
!*.xml
#Constraint files
#Do NOT ignore *.xdc files
!*.xdc
#TCL - files
!*.tcl
#Journal - files
!*.jou
#Reports
!*.rpt
!*.txt
!*.vdi
#C-files
!*.c
!*.h
!*.elf
!*.bmm
!*.xmp
### Simulation Outputs
*/sim/csrc
*/sim/*.daidir
*/sim/*.fst
*/sim/*.tb
*/sim/*.tbi
*/sim/*.vpd
ucli.key
DVEfiles/