Merge branch 'master' into i1312-prepare-instruction-operands-and-enums

api/docs/release.dox

@@ -153,10 +153,11 @@ Further non-compatibility-affecting changes include:
  - Added new fields to #dr_os_version_info_t which contain the build number,
    edition, and Windows 10 release identifier.
  - Added the function instr_is_xsave().
- - Added the AVX-512 registers DR_REG_XMM16 - DR_REG_XMM31, DR_REG_YMM16 - DR_REG_YMM31
-   and their DR_REG_ZMM0 - DR_REG__ZMM31 siblings as well as DR_REG_K0 - DR_REG_K7.
- - Added the function reg_is_zmm().
- - Added the function reg_is_opmask().
+ - Added the type #dr_zmm_t.
+ - Added the type #dr_opmask_t.
+ - Added the define #MCXT_NUM_OPMASK_SLOTS for the number of AVX-512 OpMask registers.
+ - Added the AVX-512 registers #DR_REG_XMM16 - #DR_REG_XMM31, #DR_REG_YMM16 - #DR_REG_YMM31
+   and their #DR_REG_ZMM0 - #DR_REG_ZMM31 siblings as well as #DR_REG_K0 - #DR_REG_K7.
 
 **************************************************
 <hr>

core/arch/arch.h

@@ -1329,6 +1329,8 @@ void
 get_ymm_caller_saved(dr_zmm_t *ymm_caller_saved_buf);
 void
 get_zmm_caller_saved(dr_zmm_t *zmm_caller_saved_buf);
+void
+get_opmask_caller_saved(dr_opmask_t *opmask_caller_saved_buf);
 
 /* in encode.c */
 byte *

core/arch/arch_exports.h

@@ -59,6 +59,7 @@
 #    define XMM_REG_SIZE 16
 #    define YMM_REG_SIZE 32
 #    define ZMM_REG_SIZE 64
+#    define OPMASK_REG_SIZE 8
 #    define MCXT_SIMD_SLOT_SIZE ZMM_REG_SIZE
 #    define MCXT_TOTAL_SIMD_SLOTS_SIZE (MCXT_NUM_SIMD_SLOTS * MCXT_SIMD_SLOT_SIZE)
 /* Indicates OS support, not just processor support (xref i#1278) */

core/arch/arm/encode.c

@@ -759,9 +759,9 @@ encode_reset_it_block(dcontext_t *dcontext)
 void
 encode_debug_checks(void)
 {
-    CLIENT_ASSERT(sizeof(dr_reg_fixer) / sizeof(dr_reg_fixer[0]) == REG_LAST_ENUM + 1,
+    CLIENT_ASSERT(sizeof(dr_reg_fixer) / sizeof(dr_reg_fixer[0]) == DR_REG_LAST_ENUM + 1,
                   "internal register enum error");
-    CLIENT_ASSERT(sizeof(reg_names) / sizeof(reg_names[0]) == REG_LAST_ENUM + 1,
+    CLIENT_ASSERT(sizeof(reg_names) / sizeof(reg_names[0]) == DR_REG_LAST_ENUM + 1,
                   "reg_names missing an entry");
     CLIENT_ASSERT(sizeof(type_names) / sizeof(type_names[0]) == TYPE_BEYOND_LAST_ENUM,
                   "type_names missing an entry");

core/arch/x86/encode.c

@@ -149,48 +149,42 @@ const char *const reg_names[] = {
 
 /* Maps sub-registers to their containing register. */
 const reg_id_t dr_reg_fixer[] = {
-    REG_NULL,  REG_XAX,   REG_XCX,     REG_XDX,   REG_XBX,   REG_XSP,   REG_XBP,
-    REG_XSI,   REG_XDI,   REG_R8,      REG_R9,    REG_R10,   REG_R11,   REG_R12,
-    REG_R13,   REG_R14,   REG_R15,     REG_XAX,   REG_XCX,   REG_XDX,   REG_XBX,
-    REG_XSP,   REG_XBP,   REG_XSI,     REG_XDI,   REG_R8,    REG_R9,    REG_R10,
-    REG_R11,   REG_R12,   REG_R13,     REG_R14,   REG_R15,   REG_XAX,   REG_XCX,
-    REG_XDX,   REG_XBX,   REG_XSP,     REG_XBP,   REG_XSI,   REG_XDI,   REG_R8,
-    REG_R9,    REG_R10,   REG_R11,     REG_R12,   REG_R13,   REG_R14,   REG_R15,
-    REG_XAX,   REG_XCX,   REG_XDX,     REG_XBX,   REG_XAX,   REG_XCX,   REG_XDX,
-    REG_XBX,   REG_R8,    REG_R9,      REG_R10,   REG_R11,   REG_R12,   REG_R13,
-    REG_R14,   REG_R15,   REG_XSP,     REG_XBP,   REG_XSI,   REG_XDI, /* i#201 */
-    REG_MM0,   REG_MM1,   REG_MM2,     REG_MM3,   REG_MM4,   REG_MM5,   REG_MM6,
-    REG_MM7,   REG_ZMM0,  REG_ZMM1,    REG_ZMM2,  REG_ZMM3,  REG_ZMM4,  REG_ZMM5,
-    REG_ZMM6,  REG_ZMM7,  REG_ZMM8,    REG_ZMM9,  REG_ZMM10, REG_ZMM11, REG_ZMM12,
-    REG_ZMM13, REG_ZMM14, REG_ZMM15,   REG_ZMM16, REG_ZMM17, REG_ZMM18, REG_ZMM19,
-    REG_ZMM20, REG_ZMM21, REG_ZMM22,   REG_ZMM23, REG_ZMM24, REG_ZMM25, REG_ZMM26,
-    REG_ZMM27, REG_ZMM28, REG_ZMM29,   REG_ZMM30, REG_ZMM31, REG_ST0,   REG_ST1,
-    REG_ST2,   REG_ST3,   REG_ST4,     REG_ST5,   REG_ST6,   REG_ST7,   SEG_ES,
-    SEG_CS,    SEG_SS,    SEG_DS,      SEG_FS,    SEG_GS,    REG_DR0,   REG_DR1,
-    REG_DR2,   REG_DR3,   REG_DR4,     REG_DR5,   REG_DR6,   REG_DR7,   REG_DR8,
-    REG_DR9,   REG_DR10,  REG_DR11,    REG_DR12,  REG_DR13,  REG_DR14,  REG_DR15,
-    REG_CR0,   REG_CR1,   REG_CR2,     REG_CR3,   REG_CR4,   REG_CR5,   REG_CR6,
-    REG_CR7,   REG_CR8,   REG_CR9,     REG_CR10,  REG_CR11,  REG_CR12,  REG_CR13,
-    REG_CR14,  REG_CR15,  REG_INVALID, REG_ZMM0,  REG_ZMM1,  REG_ZMM2,  REG_ZMM3,
-    REG_ZMM4,  REG_ZMM5,  REG_ZMM6,    REG_ZMM7,  REG_ZMM8,  REG_ZMM9,  REG_ZMM10,
-    REG_ZMM11, REG_ZMM12, REG_ZMM13,   REG_ZMM14, REG_ZMM15, REG_ZMM16, REG_ZMM17,
-    REG_ZMM18, REG_ZMM19, REG_ZMM20,   REG_ZMM21, REG_ZMM22, REG_ZMM23, REG_ZMM24,
-    REG_ZMM25, REG_ZMM26, REG_ZMM27,   REG_ZMM28, REG_ZMM29, REG_ZMM30, REG_ZMM31,
-    REG_ZMM0,  REG_ZMM1,  REG_ZMM2,    REG_ZMM3,  REG_ZMM4,  REG_ZMM5,  REG_ZMM6,
-    REG_ZMM7,  REG_ZMM8,  REG_ZMM9,    REG_ZMM10, REG_ZMM11, REG_ZMM12, REG_ZMM13,
-    REG_ZMM14, REG_ZMM15, REG_ZMM16,   REG_ZMM17, REG_ZMM18, REG_ZMM19, REG_ZMM20,
-    REG_ZMM21, REG_ZMM22, REG_ZMM23,   REG_ZMM24, REG_ZMM25, REG_ZMM26, REG_ZMM27,
-    REG_ZMM28, REG_ZMM29, REG_ZMM30,   REG_ZMM31, REG_K0,    REG_K1,    REG_K2,
-    REG_K3,    REG_K4,    REG_K5,      REG_K6,    REG_K7,
+    DR_REG_NULL,  DR_REG_XAX,   DR_REG_XCX,   DR_REG_XDX,   DR_REG_XBX,     DR_REG_XSP,
+    DR_REG_XBP,   DR_REG_XSI,   DR_REG_XDI,   DR_REG_R8,    DR_REG_R9,      DR_REG_R10,
+    DR_REG_R11,   DR_REG_R12,   DR_REG_R13,   DR_REG_R14,   DR_REG_R15,     DR_REG_XAX,
+    DR_REG_XCX,   DR_REG_XDX,   DR_REG_XBX,   DR_REG_XSP,   DR_REG_XBP,     DR_REG_XSI,
+    DR_REG_XDI,   DR_REG_R8,    DR_REG_R9,    DR_REG_R10,   DR_REG_R11,     DR_REG_R12,
+    DR_REG_R13,   DR_REG_R14,   DR_REG_R15,   DR_REG_XAX,   DR_REG_XCX,     DR_REG_XDX,
+    DR_REG_XBX,   DR_REG_XSP,   DR_REG_XBP,   DR_REG_XSI,   DR_REG_XDI,     DR_REG_R8,
+    DR_REG_R9,    DR_REG_R10,   DR_REG_R11,   DR_REG_R12,   DR_REG_R13,     DR_REG_R14,
+    DR_REG_R15,   DR_REG_XAX,   DR_REG_XCX,   DR_REG_XDX,   DR_REG_XBX,     DR_REG_XAX,
+    DR_REG_XCX,   DR_REG_XDX,   DR_REG_XBX,   DR_REG_R8,    DR_REG_R9,      DR_REG_R10,
+    DR_REG_R11,   DR_REG_R12,   DR_REG_R13,   DR_REG_R14,   DR_REG_R15,     DR_REG_XSP,
+    DR_REG_XBP,   DR_REG_XSI,   DR_REG_XDI, /* i#201 */
+    DR_REG_MM0,   DR_REG_MM1,   DR_REG_MM2,   DR_REG_MM3,   DR_REG_MM4,     DR_REG_MM5,
+    DR_REG_MM6,   DR_REG_MM7,   DR_REG_YMM0,  DR_REG_YMM1,  DR_REG_YMM2,    DR_REG_YMM3,
+    DR_REG_YMM4,  DR_REG_YMM5,  DR_REG_YMM6,  DR_REG_YMM7,  DR_REG_YMM8,    DR_REG_YMM9,
+    DR_REG_YMM10, DR_REG_YMM11, DR_REG_YMM12, DR_REG_YMM13, DR_REG_YMM14,   DR_REG_YMM15,
+    DR_REG_ST0,   DR_REG_ST1,   DR_REG_ST2,   DR_REG_ST3,   DR_REG_ST4,     DR_REG_ST5,
+    DR_REG_ST6,   DR_REG_ST7,   DR_SEG_ES,    DR_SEG_CS,    DR_SEG_SS,      DR_SEG_DS,
+    DR_SEG_FS,    DR_SEG_GS,    DR_REG_DR0,   DR_REG_DR1,   DR_REG_DR2,     DR_REG_DR3,
+    DR_REG_DR4,   DR_REG_DR5,   DR_REG_DR6,   DR_REG_DR7,   DR_REG_DR8,     DR_REG_DR9,
+    DR_REG_DR10,  DR_REG_DR11,  DR_REG_DR12,  DR_REG_DR13,  DR_REG_DR14,    DR_REG_DR15,
+    DR_REG_CR0,   DR_REG_CR1,   DR_REG_CR2,   DR_REG_CR3,   DR_REG_CR4,     DR_REG_CR5,
+    DR_REG_CR6,   DR_REG_CR7,   DR_REG_CR8,   DR_REG_CR9,   DR_REG_CR10,    DR_REG_CR11,
+    DR_REG_CR12,  DR_REG_CR13,  DR_REG_CR14,  DR_REG_CR15,  DR_REG_INVALID, DR_REG_YMM0,
+    DR_REG_YMM1,  DR_REG_YMM2,  DR_REG_YMM3,  DR_REG_YMM4,  DR_REG_YMM5,    DR_REG_YMM6,
+    DR_REG_YMM7,  DR_REG_YMM8,  DR_REG_YMM9,  DR_REG_YMM10, DR_REG_YMM11,   DR_REG_YMM12,
+    DR_REG_YMM13, DR_REG_YMM14, DR_REG_YMM15,
 };
 
 #ifdef DEBUG
 void
 encode_debug_checks(void)
 {
-    CLIENT_ASSERT(sizeof(dr_reg_fixer) / sizeof(dr_reg_fixer[0]) == REG_LAST_ENUM + 1,
+    CLIENT_ASSERT(sizeof(dr_reg_fixer) / sizeof(dr_reg_fixer[0]) == DR_REG_LAST_ENUM + 1,
                   "internal register enum error");
-    CLIENT_ASSERT(sizeof(reg_names) / sizeof(reg_names[0]) == REG_LAST_ENUM + 1,
+    CLIENT_ASSERT(sizeof(reg_names) / sizeof(reg_names[0]) == DR_REG_LAST_ENUM + 1,
                   "reg_names missing an entry");
     CLIENT_ASSERT(sizeof(type_names) / sizeof(type_names[0]) == TYPE_BEYOND_LAST_ENUM,
                   "type_names missing an entry");

core/arch/x86/x86.asm

@@ -2371,6 +2371,38 @@ GLOBAL_LABEL(get_zmm_caller_saved:)
         ret
         END_FUNC(get_zmm_caller_saved)
 
+/* void get_opmask_caller_saved(byte *opmask_caller_saved_buf)
+ *   stores the values of k0 through k7 consecutively in 8 byte slots each into
+ *   opmask_caller_saved_buf. opmask_caller_saved_buf need not be 8-byte aligned.
+ *   The caller must ensure that the underlying processor supports AVX-512!
+ *   XXX i#1312: Eventually this routine must dynamically switch the instructions
+ *   used dependent on whether AVX512BW is enabled or not (2 bytes vs. 8 bytes
+ *   OpMask registers).
+ */
+        DECLARE_FUNC(get_opmask_caller_saved)
+GLOBAL_LABEL(get_opmask_caller_saved:)
+        mov      REG_XAX, ARG1
+       /*
+        * c5 f8 91 00       kmovw  %k0,(%rax)
+        * c5 f8 91 48 08    kmovw  %k1,0x8(%rax)
+        * c5 f8 91 50 10    kmovw  %k2,0x10(%rax)
+        * c5 f8 91 58 18    kmovw  %k3,0x18(%rax)
+        * c5 f8 91 60 20    kmovw  %k4,0x20(%rax)
+        * c5 f8 91 68 28    kmovw  %k5,0x28(%rax)
+        * c5 f8 91 70 30    kmovw  %k6,0x30(%rax)
+        * c5 f8 91 78 38    kmovw  %k7,0x38(%rax)
+        */
+        RAW(c5) RAW(f8) RAW(91) RAW(00)
+        RAW(c5) RAW(f8) RAW(91) RAW(48) RAW(08)
+        RAW(c5) RAW(f8) RAW(91) RAW(50) RAW(10)
+        RAW(c5) RAW(f8) RAW(91) RAW(58) RAW(18)
+        RAW(c5) RAW(f8) RAW(91) RAW(60) RAW(20)
+        RAW(c5) RAW(f8) RAW(91) RAW(68) RAW(28)
+        RAW(c5) RAW(f8) RAW(91) RAW(70) RAW(30)
+        RAW(c5) RAW(f8) RAW(91) RAW(78) RAW(38)
+        ret
+        END_FUNC(get_opmask_caller_saved)
+
 /* void hashlookup_null_handler(void)
  * PR 305731: if the app targets NULL, it ends up here, which indirects
  * through hashlookup_null_target to end up in an ibl miss routine.

core/arch/x86_code_test.c

@@ -324,6 +324,73 @@ unit_test_get_zmm_caller_saved()
         0);
 }
 
+static void
+unit_test_get_opmask_caller_saved()
+{
+    /* While DynamoRIO's dr_opmask_t type is 8 bytes, the actual machine register is
+     * really only 8 bytes if the processor and OS support AVX512BW. Otherwise it is
+     * 2 Bytes.
+     */
+    dr_opmask_t ref_buffer[MCXT_NUM_OPMASK_SLOTS];
+    dr_opmask_t get_buffer[MCXT_NUM_OPMASK_SLOTS];
+    ASSERT(sizeof(dr_opmask_t) == OPMASK_REG_SIZE);
+    uint base = 0x0000348e;
+
+#        ifdef __AVX512BW__
+    /* i#1312: Modern AVX-512 machines support AVX512BW which extends the OpMask registers
+     * to 8 bytes. The right compile flags must then to be used to compile this test, and
+     * the type will be __mmask64. Also DynamoRIO's get_opmask_caller_saved has to
+     * dynamically switch dependent on a proc_ flag indicating AVX512BW is enabled.
+     */
+#            error "Unimplemented. Should test using __mmask64 instructions."
+#        else
+    ASSERT(MCXT_NUM_OPMASK_SLOTS == 8);
+    register __mmask16 k0 asm("k0");
+    register __mmask16 k1 asm("k1");
+    register __mmask16 k2 asm("k2");
+    register __mmask16 k3 asm("k3");
+    register __mmask16 k4 asm("k4");
+    register __mmask16 k5 asm("k5");
+    register __mmask16 k6 asm("k6");
+    register __mmask16 k7 asm("k7");
+#        endif
+
+    for (int regno = 0; regno < MCXT_NUM_OPMASK_SLOTS; ++regno) {
+        get_buffer[regno] = 0;
+        ref_buffer[regno] = base++;
+    }
+
+#        define MAKE_OPMASK_REG(num) k##num
+#        define MOVE_TO_OPMASK(buf, num) \
+            asm volatile("kmovw %1, %0" : "=k"(MAKE_OPMASK_REG(num)) : "m"(buf[num]) :);
+
+    MOVE_TO_OPMASK(ref_buffer, 0)
+    MOVE_TO_OPMASK(ref_buffer, 1)
+    MOVE_TO_OPMASK(ref_buffer, 2)
+    MOVE_TO_OPMASK(ref_buffer, 3)
+    MOVE_TO_OPMASK(ref_buffer, 4)
+    MOVE_TO_OPMASK(ref_buffer, 5)
+    MOVE_TO_OPMASK(ref_buffer, 6)
+    MOVE_TO_OPMASK(ref_buffer, 7)
+
+    get_opmask_caller_saved(get_buffer);
+
+    /* Barrier, as described in unit_test_get_zmm_caller_saved. */
+    asm volatile("" ::: "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7");
+
+    for (int regno = 0; regno < MCXT_NUM_OPMASK_SLOTS; ++regno) {
+        print_file(STDERR, "K%d ref\n:", regno);
+        dump_buffer_as_bytes(STDERR, &ref_buffer[regno], sizeof(ref_buffer[regno]),
+                             DUMP_RAW | DUMP_DWORD);
+        print_file(STDERR, "\nK%d get\n:", regno);
+        dump_buffer_as_bytes(STDERR, &get_buffer[regno], sizeof(get_buffer[regno]),
+                             DUMP_RAW | DUMP_DWORD);
+        print_file(STDERR, "\n");
+    }
+    EXPECT(memcmp(ref_buffer, get_buffer, MCXT_NUM_OPMASK_SLOTS * sizeof(dr_opmask_t)),
+           0);
+}
+
 #    endif
 
 void
@@ -338,6 +405,7 @@ unit_test_asm(dcontext_t *dc)
 #        endif
 #        ifdef __AVX512F__
     unit_test_get_zmm_caller_saved();
+    unit_test_get_opmask_caller_saved();
 #        endif
 #    endif
 }

core/lib/globals_shared.h

@@ -1838,6 +1838,14 @@ typedef union _dr_zmm_t {
     reg_t reg[IF_X64_ELSE(8, 16)]; /**< Representation as 8 or 16 registers. */
 } dr_zmm_t;
 
+/** AVX-512 OpMask (k-)register. */
+#ifdef AVOID_API_EXPORT
+/* The register may be only 16 bits wide on systems without AVX512BW, but can be up to
+ * MAX_KL = 64 bits.
+ */
+#endif
+typedef uint64 dr_opmask_t;
+
 #if defined(AARCHXX)
 /**
  * 128-bit ARM SIMD Vn register.
@@ -1873,6 +1881,10 @@ typedef union _dr_simd_t {
 #    define PRE_SIMD_PADDING                                       \
         0 /**< Bytes of padding before xmm/ymm dr_mcontext_t slots \
            */
+#    define MCXT_NUM_OPMASK_SLOTS                                    \
+        0 /**< Number of 16-64-bit OpMask Kn slots in dr_mcontext_t, \
+           * if architecture supports.                               \
+           */
 
 #elif defined(X86)
 
@@ -1906,7 +1918,10 @@ typedef union _dr_simd_t {
 #        define PRE_XMM_PADDING \
             24 /**< Bytes of padding before xmm/ymm dr_mcontext_t slots */
 #    endif
-
+#    define MCXT_NUM_OPMASK_SLOTS                                    \
+        8 /**< Number of 16-64-bit OpMask Kn slots in dr_mcontext_t, \
+           * if architecture supports.                               \
+           */
 #else
 #    error NYI
 #endif /* AARCHXX/X86 */

ext/drcovlib/modules.c

@@ -1,5 +1,5 @@
 /* ***************************************************************************
- * Copyright (c) 2012-2017 Google, Inc.  All rights reserved.
+ * Copyright (c) 2012-2019 Google, Inc.  All rights reserved.
  * ***************************************************************************/
 
 /*
@@ -595,7 +595,7 @@ drmodtrack_offline_read(file_t file, const char *map, OUT const char **next_line
                         OUT void **handle, OUT uint *num_mods)
 {
     module_read_info_t *info = NULL;
-    uint i;
+    uint i, mods_parsed = 0;
     uint64 file_size;
     size_t map_size = 0;
     const char *buf, *map_start;
@@ -644,6 +644,7 @@ drmodtrack_offline_read(file_t file, const char *map, OUT const char **next_line
     info->mod = (module_read_entry_t *)dr_global_alloc(*num_mods * sizeof(*info->mod));
 
     /* module lists */
+    mods_parsed = 0;
     for (i = 0; i < *num_mods; i++) {
         uint mod_id;
         if (version == 1) {
@@ -692,6 +693,7 @@ drmodtrack_offline_read(file_t file, const char *map, OUT const char **next_line
                 buf = module_parse_cb(buf, &info->mod[i].custom);
             if (buf == NULL)
                 goto read_error;
+            ++mods_parsed;
             info->mod[i].path = info->mod[i].path_buf;
             if (dr_sscanf(buf, " %[^\n\r]", info->mod[i].path) != 1)
                 goto read_error;
@@ -706,6 +708,10 @@ drmodtrack_offline_read(file_t file, const char *map, OUT const char **next_line
     return DRCOVLIB_SUCCESS;
 
 read_error:
+    if (module_free_cb != NULL) {
+        for (i = 0; i < mods_parsed; i++)
+            module_free_cb(info->mod[i].custom);
+    }
     if (info != NULL) {
         dr_global_free(info->mod, *num_mods * sizeof(*info->mod));
         dr_global_free(info, sizeof(*info));

suite/runsuite.cmake

@@ -1,5 +1,5 @@
 # **********************************************************
-# Copyright (c) 2010-2018 Google, Inc.    All rights reserved.
+# Copyright (c) 2010-2019 Google, Inc.    All rights reserved.
 # Copyright (c) 2009-2010 VMware, Inc.    All rights reserved.
 # **********************************************************
 
@@ -262,7 +262,9 @@ endif ()
 
 # for short suite, don't build tests for builds that don't run tests
 # (since building takes forever on windows): so we only turn
-# on BUILD_TESTS for TEST_LONG or debug-internal-{32,64}
+# on BUILD_TESTS for TEST_LONG or debug-internal-{32,64}. BUILD_TESTS is
+# also turned on for release-external-64, but ctest will run with label
+# RUN_IN_RELEASE.
 
 if (NOT cross_aarchxx_linux_only AND NOT cross_android_only)
   # For cross-arch execve test we need to "make install"
@@ -305,12 +307,16 @@ if (NOT cross_aarchxx_linux_only AND NOT cross_android_only)
   else ()
     set(32bit_path "")
   endif ()
+  set(orig_extra_ctest_args extra_ctest_args)
+  set(extra_ctest_args INCLUDE_LABEL RUN_IN_RELEASE)
   testbuild_ex("release-external-64" ON "
     DEBUG:BOOL=OFF
     INTERNAL:BOOL=OFF
+    BUILD_TESTS:BOOL=ON
     ${install_path_cache}
     ${32bit_path}
     " OFF ${arg_package} "${install_build_args}")
+  set(extra_ctest_args orig_extra_ctest_args)
   if (DO_ALL_BUILDS)
     # we rarely use internal release builds but keep them working in long
     # suite (not much burden) in case we need to tweak internal options
@@ -424,6 +430,7 @@ if (UNIX AND ARCH_IS_X86)
     INTERNAL:BOOL=OFF
     CMAKE_TOOLCHAIN_FILE:PATH=${CTEST_SOURCE_DIRECTORY}/make/toolchain-arm64.cmake
     " OFF ${arg_package} "")
+
   set(run_tests ${prev_run_tests})
   set(optional_cross_compile ${prev_optional_cross_compile})