Clock PLL configuration bugs

[calithameridi]

See issue #147 and PR #148. Similar bugs in Klipper cause clock pll_base misconfig in other build targets (e.g. STM32G4 is known to fail on 25 MHz HSE). May occur in other non-STM32 build targets?

Was going "at some point ... eventually" but might as well stop procrastinating putting this issue up in case someone else wants to solve this across the board.