README.md

HLS_FFT

Overview

This repository contains HLS code that calls the Xilinx FFT IP core from the FFT IP Library and a Python program to handle it.
The following environments were tested:

• Vivado 2022.1
• Vitis HLS 2022.1
• PYNQ-Z1 (PYNQ 2.5)

It appears that this repository is referenced on the Xilinx Q&A page. Thank you.

Usage

The following command will create the FFT IP core and block design for PYNQ-Z1. Replace with the version of Vivado installed on your machine.

source /tools/Xilinx/Vivado/<version>/settings64.sh
make all

After the make command finishes, launch the project with vivado vivado/fft.xpr. You can see the following block design.

The hardware drivers can be found in this notebook.

HLS design

Data input/output is as follows:

• The top function

  void hls_fft(fft_stream &input, fft_stream &output, unsigned size)

• The circuit is driven by the CTRL register(offset 0x00)

• size is a register(offset 0x10) that sets the number of FFT points with $size = log_2 POINT$
  This can be set to a value of 3~10 ( $2^3$ ~ $2^{10}$-Point FFT ).
  If you want to set more than that, change TWO_TO_THE_POWER_OF_N_MAX in the header file. The Xilinx FFT IP core allows $2^3$ ~ $2^{16}$-Point FFT.

• Data is transferred by DMA using the AXI4-Stream interface

• The FPGA logic input/output types can be numpy.csingle(float complex) or numpy.single(float)
  The default input/output is a float complex. You can switch between them by manipulating the #define directive in the header file.
  The FFT IP Library defines float complex types for input and output. Therefore, note that using float for inputs and outputs in FPGA logic (Uncomment USE_FLOAT in header file) requires type conversion in the FPGA logic, which may result in performance degradation.