diff --git a/booter/arm7/source/main.c b/booter/arm7/source/main.c
index 307f916dea..35c2151903 100644
--- a/booter/arm7/source/main.c
+++ b/booter/arm7/source/main.c
@@ -90,20 +90,20 @@ int main() {
 		// - We disable ADC NADC/MADC dividers, to share the DAC clock.
 		// This also prevents us from having to reconfigure the PLL multipliers
 		// for 32kHz/47kHz.
-		cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
+		// This produces low quality output
+		/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
 		cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_MDAC, CDC_CONTROL_CLOCK_ENABLE(2));
 		cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(1));
 		cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
 		cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
-		cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK);
+		cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK); */
 
-		/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
+		cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
 		cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
 
-			// Configure a PLL multiplier/divider of 15/2, and a NDAC/NADC divider of 5.
-			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 15);
-			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(5));
-		} */
+		// Configure a PLL multiplier/divider of 15/2, and a NDAC/NADC divider of 5.
+		cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 15);
+		cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(5));
 
 		REG_SNDEXTCNT = (REG_SNDEXTCNT & ~SNDEXTCNT_FREQ_47KHZ) | SNDEXTCNT_FREQ_47KHZ | SNDEXTCNT_ENABLE;
 		// REG_SNDEXTCNT |= SNDEXTCNT_ENABLE; // Enable sound output
diff --git a/booter_fc/arm7/source/main.c b/booter_fc/arm7/source/main.c
index f6d9116d42..16e66a8d9e 100644
--- a/booter_fc/arm7/source/main.c
+++ b/booter_fc/arm7/source/main.c
@@ -152,20 +152,20 @@ int main() {
 		// - We disable ADC NADC/MADC dividers, to share the DAC clock.
 		// This also prevents us from having to reconfigure the PLL multipliers
 		// for 32kHz/47kHz.
-		my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
+		// This produces low quality output
+		/* my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
 		my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_MDAC, CDC_CONTROL_CLOCK_ENABLE(2));
 		my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(1));
 		my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
 		my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
-		my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK);
+		my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK); */
 
-		/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
-		cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
+		my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
+		my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
 
-			// Configure a PLL multiplier/divider of 15/2, and a NDAC/NADC divider of 5.
-			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 15);
-			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(5));
-		} */
+		// Configure a PLL multiplier/divider of 15/2, and a NDAC/NADC divider of 5.
+		my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 15);
+		my_cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(5));
 
 		REG_SNDEXTCNT = (REG_SNDEXTCNT & ~SNDEXTCNT_FREQ_47KHZ) | SNDEXTCNT_FREQ_47KHZ | SNDEXTCNT_ENABLE;
 		// REG_SNDEXTCNT |= SNDEXTCNT_ENABLE; // Enable sound output
diff --git a/slot1launch/bootloader/source/main.arm7.c b/slot1launch/bootloader/source/main.arm7.c
index b30018fc8f..6cf2ef99c4 100644
--- a/slot1launch/bootloader/source/main.arm7.c
+++ b/slot1launch/bootloader/source/main.arm7.c
@@ -1027,15 +1027,16 @@ void arm7_main (void) {
 			// - We disable ADC NADC/MADC dividers, to share the DAC clock.
 			// This also prevents us from having to reconfigure the PLL multipliers
 			// for 32kHz/47kHz.
-			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
+			// This produces low quality output
+			/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
 			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_MDAC, CDC_CONTROL_CLOCK_ENABLE(2));
 			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(1));
 			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
 			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
 			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK);
 
-			/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
-			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
+			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
+			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE); */
 
 			if (soundFreq)
 			{
@@ -1048,7 +1049,7 @@ void arm7_main (void) {
 				// Configure a PLL multiplier/divider of 21/2, and a NDAC/NADC divider of 7.
 				cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(7));
 				cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 21);
-			} */
+			}
 
 			REG_SNDEXTCNT = (REG_SNDEXTCNT & ~SNDEXTCNT_FREQ_47KHZ) | (soundFreq ? SNDEXTCNT_FREQ_47KHZ : SNDEXTCNT_FREQ_32KHZ) | SNDEXTCNT_ENABLE;
 			// REG_SNDEXTCNT |= SNDEXTCNT_ENABLE; // Enable sound output
diff --git a/slot1launch/bootloaderAlt/source/main.arm7.c b/slot1launch/bootloaderAlt/source/main.arm7.c
index c010d0d335..0212d8889f 100644
--- a/slot1launch/bootloaderAlt/source/main.arm7.c
+++ b/slot1launch/bootloaderAlt/source/main.arm7.c
@@ -734,15 +734,16 @@ void arm7_main (void) {
 			// - We disable ADC NADC/MADC dividers, to share the DAC clock.
 			// This also prevents us from having to reconfigure the PLL multipliers
 			// for 32kHz/47kHz.
-			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
+			// This produces low quality output
+			/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_PR, 0);
 			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_MDAC, CDC_CONTROL_CLOCK_ENABLE(2));
 			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(1));
 			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
 			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
 			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_CLOCK_MUX, CDC_CONTROL_CLOCK_PLL_IN_MCLK | CDC_CONTROL_CLOCK_CODEC_IN_MCLK);
 
-			/* cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
-			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE);
+			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_MADC, CDC_CONTROL_CLOCK_DISABLE);
+			cdcWriteReg(CDC_CONTROL, CDC_CONTROL_ADC_NADC, CDC_CONTROL_CLOCK_DISABLE); */
 
 			if (soundFreq)
 			{
@@ -755,7 +756,7 @@ void arm7_main (void) {
 				// Configure a PLL multiplier/divider of 21/2, and a NDAC/NADC divider of 7.
 				cdcWriteReg(CDC_CONTROL, CDC_CONTROL_DAC_NDAC, CDC_CONTROL_CLOCK_ENABLE(7));
 				cdcWriteReg(CDC_CONTROL, CDC_CONTROL_PLL_J, 21);
-			} */
+			}
 
 			REG_SNDEXTCNT = (REG_SNDEXTCNT & ~SNDEXTCNT_FREQ_47KHZ) | (soundFreq ? SNDEXTCNT_FREQ_47KHZ : SNDEXTCNT_FREQ_32KHZ) | SNDEXTCNT_ENABLE;
 			// REG_SNDEXTCNT |= SNDEXTCNT_ENABLE; // Enable sound output