From eae0ea71224f8a63e05e7547adb7171e33133dcd Mon Sep 17 00:00:00 2001
From: Sudeep Mohanty <sudeep.mohanty@espressif.com>
Date: Mon, 28 Aug 2023 17:39:48 +0800
Subject: [PATCH] fix(ulp_riscv): Fixed the header inclusion dependency for
 ulp_riscv_register_ops.h

There are redefinition compilation warnings for the register operation
macros when a ULP program was compiled which included soc.h before
ulp_riscv_register_ops.h. This commit fixes the issues by delegating the
exclusion macro to the CMakeLists.txt file.

Closes: https://github.com/espressif/esp-idf/issues/12116
---
 components/ulp/cmake/CMakeLists.txt                             | 1 +
 .../ulp/ulp_riscv/ulp_core/include/ulp_riscv_adc_ulp_core.h     | 1 +
 components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h      | 2 +-
 .../ulp/ulp_riscv/ulp_core/include/ulp_riscv_register_ops.h     | 2 --
 .../ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h   | 1 +
 5 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/components/ulp/cmake/CMakeLists.txt b/components/ulp/cmake/CMakeLists.txt
index c097bcace77a..08b5af497f97 100644
--- a/components/ulp/cmake/CMakeLists.txt
+++ b/components/ulp/cmake/CMakeLists.txt
@@ -76,6 +76,7 @@ if(ULP_COCPU_IS_RISCV)
     target_link_options(${ULP_APP_NAME} PRIVATE SHELL:-T ${IDF_PATH}/components/ulp/ld/${IDF_TARGET}.peripherals.ld)
     target_link_options(${ULP_APP_NAME} PRIVATE "-Wl,--no-warn-rwx-segments")
     target_compile_definitions(${ULP_APP_NAME} PRIVATE IS_ULP_COCPU)
+    target_compile_definitions(${ULP_APP_NAME} PRIVATE ULP_RISCV_REGISTER_OPS)
 
 elseif(ULP_COCPU_IS_LP_CORE)
     list(APPEND ULP_S_SOURCES
diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_adc_ulp_core.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_adc_ulp_core.h
index 9c27834c12c7..5d189109f645 100644
--- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_adc_ulp_core.h
+++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_adc_ulp_core.h
@@ -6,6 +6,7 @@
 
 #pragma once
 
+#include "ulp_riscv_register_ops.h"
 #include "hal/adc_ll.h"
 
 #ifdef __cplusplus
diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h
index 6e02ea70f972..c675279152fc 100644
--- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h
+++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h
@@ -12,7 +12,7 @@ extern "C" {
 
 #include "soc/rtc_io_reg.h"
 #include "soc/sens_reg.h"
-
+#include "ulp_riscv_register_ops.h"
 
 typedef enum {
     GPIO_NUM_0 = 0,     /*!< GPIO0, input and output */
diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_register_ops.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_register_ops.h
index ce99f229ae6c..52e7925b8e6f 100644
--- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_register_ops.h
+++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_register_ops.h
@@ -5,13 +5,11 @@
  */
 
 #pragma once
-#define ULP_RISCV_REGISTER_OPS
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-
 //Registers Operation {{
 
 /*
diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h
index 2313567c33ad..86bdd504f520 100644
--- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h
+++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h
@@ -7,6 +7,7 @@
 #pragma once
 
 #include "esp_err.h"
+#include "ulp_riscv_register_ops.h"
 #include "hal/touch_sensor_types.h"
 
 #ifdef __cplusplus