readme.adoc

Verilog IP Bundle

vipbundle is a command line tool to bundle a Verilog IP into a package for use with an EDA toolchain. It currently targets Quartus with its tcl wrapping of components for use in the Qsys / Platform Designer tool.

Working principle

vipbundle parses a Verilog file looking for modules, and identifies their input and output ports. It then infers the kind of the provided interfaces based on the names of the ports (as described in InterfaceInference.hs). Currently supported interfaces are:

• Clock, for signal names matching the regex

  \\<(cs(i|o)|clk|CLK)(_(.*))?

• Reset, for signal names matching the regex

  \\<(rs(i|o)|rst|RST)(.*_(n|N))?(_(.*))?

• AXI4[{Lite,Stream}], for signal names matching the regex

  \\<ax(l|str)?([ms])_((.+)_)*(.+)

• Avalon memory mapped, for signal names matching the regex

  \\<av([ms])_((.+)_)*(.+)

• Irq, for signal names matching the regex

  \\<in([sr])(_(.*))?

• Ignored port for signal names matching the regex

  \\<(IGNORE|ignore)(.*)?

• Conduit, for all other signal names

For each interface found, vipbundle will generate the apropriate tcl code block to describe it to the Quartus toolchain. The generated .tcl file together with the Verilog file can be imported from within Quartus to make available the IP.

Usage

Usage: vipbundle [OPTION...] files...
  -o FILEPATH      --output-file=FILEPATH        specify a FILEPATH for the output file
  -f OUTPUTFORMAT  --output-format=OUTPUTFORMAT  specify desired OUTPUTFORMAT, one of quartus_ip_tcl, txt (default)
  -h               --help                        display help