diff --git a/src/hugr/validate.rs b/src/hugr/validate.rs
index 4002771f2..8bcf35df5 100644
--- a/src/hugr/validate.rs
+++ b/src/hugr/validate.rs
@@ -225,13 +225,17 @@ impl<'a> ValidationContext<'a> {
         let port_kind = optype.port_kind(port).unwrap();
         let dir = port.direction();
 
-        // Input ports and output linear ports must always be connected
         let mut links = self.hugr.graph.port_links(port_index).peekable();
         let must_be_connected = match dir {
+            // Incoming ports must be connected, except for state order ports, branch case nodes,
+            // and the input of some BasicBlocks.
             Direction::Incoming => {
-                port_kind.is_linear() || matches!(port_kind, EdgeKind::Static(_))
+                port_kind != EdgeKind::StateOrder
+                    && port_kind != EdgeKind::ControlFlow
+                    && optype.tag() != OpTag::Case
             }
-            Direction::Outgoing => port_kind.is_linear(),
+            // Linear values and cfg edges must be connected.
+            Direction::Outgoing => port_kind.is_linear() || optype.tag() == OpTag::BasicBlock,
         };
         if must_be_connected && links.peek().is_none() {
             return Err(ValidationError::UnconnectedPort {