Merge pull request eclipse-omr#6574 from BradleyWood/simdsupport

Make getSupportsOpCodeForAutoSIMD() statically accessible

compiler/aarch64/codegen/OMRCodeGenerator.cpp

@@ -615,7 +615,7 @@ int64_t OMR::ARM64::CodeGenerator::getSmallestPosConstThatMustBeMaterialized()
    }
 
 
-bool OMR::ARM64::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode)
+bool OMR::ARM64::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::CPU *cpu, TR::ILOpCode opcode)
    {
    TR_ASSERT_FATAL(opcode.isVectorOpCode(), "getSupportsOpCodeForAutoSIMD expects vector opcode\n");
 
@@ -665,6 +665,11 @@ bool OMR::ARM64::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode
    return false;
    }
 
+bool OMR::ARM64::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode)
+   {
+   return TR::CodeGenerator::getSupportsOpCodeForAutoSIMD(&self()->comp()->target().cpu, opcode);
+   }
+
 bool
 OMR::ARM64::CodeGenerator::directCallRequiresTrampoline(intptr_t targetAddress, intptr_t sourceAddress)
    {

compiler/aarch64/codegen/OMRCodeGenerator.hpp

@@ -422,7 +422,8 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator
    TR_GlobalRegisterNumber _gprLinkageGlobalRegisterNumbers[TR::RealRegister::NumRegisters]; // could be smaller
    TR_GlobalRegisterNumber _fprLinkageGlobalRegisterNumbers[TR::RealRegister::NumRegisters]; // could be smaller
 
-   bool getSupportsOpCodeForAutoSIMD(TR::ILOpCode);
+   static bool getSupportsOpCodeForAutoSIMD(TR::CPU *cpu, TR::ILOpCode opcode);
+   bool getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode);
 
    /**
     * @brief Answers whether a trampoline is required for a direct call instruction to

compiler/codegen/OMRCodeGenerator.hpp

@@ -1649,7 +1649,8 @@ class OMR_EXTENSIBLE CodeGenerator
    bool getSupportsAutoSIMD() { return _flags4.testAny(SupportsAutoSIMD);}
    void setSupportsAutoSIMD() { _flags4.set(SupportsAutoSIMD);}
 
-   bool getSupportsOpCodeForAutoSIMD(TR::ILOpCode) { return false; }
+   static bool getSupportsOpCodeForAutoSIMD(TR::CPU *cpu, TR::ILOpCode opcode) { return false; }
+   bool getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode) { return false; }
 
    bool removeRegisterHogsInLowerTreesWalk() { return _flags3.testAny(RemoveRegisterHogsInLowerTreesWalk);}
    void setRemoveRegisterHogsInLowerTreesWalk() { _flags3.set(RemoveRegisterHogsInLowerTreesWalk);}

compiler/p/codegen/OMRCodeGenerator.cpp

@@ -1760,7 +1760,7 @@ OMR::Power::CodeGenerator::freeAndResetTransientLongs()
 
 
 
-bool OMR::Power::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode)
+bool OMR::Power::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::CPU *cpu, TR::ILOpCode opcode)
    {
    TR_ASSERT_FATAL(opcode.isVectorOpCode(), "getSupportsOpCodeForAutoSIMD expects vector opcode\n");
 
@@ -1774,17 +1774,17 @@ bool OMR::Power::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode
                    "Unexpected vector element type\n");
 
    // alignment issues
-   if (!self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) &&
+   if (!cpu->isAtLeast(OMR_PROCESSOR_PPC_P8) &&
        et != TR::Double &&
        et != TR::Int64)
       return false;
 
-   if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) &&
+   if (cpu->isAtLeast(OMR_PROCESSOR_PPC_P8) &&
        (opcode.getVectorOperation() == TR::vadd || opcode.getVectorOperation() == TR::vsub || opcode.getVectorOperation() == TR::vmul || opcode.getVectorOperation() == TR::vabs || opcode.getVectorOperation() == TR::vmin || opcode.getVectorOperation() == TR::vmax) &&
        et == TR::Int64)
       return true;
 
-   if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) &&
+   if (cpu->isAtLeast(OMR_PROCESSOR_PPC_P8) &&
        (opcode.getVectorOperation() == TR::vmin || opcode.getVectorOperation() == TR::vmax) &&
        et == TR::Double)
       return true;
@@ -1859,6 +1859,11 @@ bool OMR::Power::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode
    return false;
    }
 
+bool OMR::Power::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode)
+   {
+   return TR::CodeGenerator::getSupportsOpCodeForAutoSIMD(&self()->comp()->target().cpu, opcode);
+   }
+
 bool
 OMR::Power::CodeGenerator::getSupportsEncodeUtf16LittleWithSurrogateTest()
    {

compiler/p/codegen/OMRCodeGenerator.hpp

@@ -282,7 +282,8 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator
       return false;
       }
 
-   bool getSupportsOpCodeForAutoSIMD(TR::ILOpCode);
+   static bool getSupportsOpCodeForAutoSIMD(TR::CPU *cpu, TR::ILOpCode opcode);
+   bool getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode);
 
    bool getSupportsEncodeUtf16LittleWithSurrogateTest();
 

compiler/x/codegen/OMRCodeGenerator.cpp

@@ -985,8 +985,7 @@ bool OMR::X86::CodeGenerator::supportsAddressRematerialization()         { stati
 #undef ALLOWED_TO_REMATERIALIZE
 #undef CAN_REMATERIALIZE
 
-bool
-OMR::X86::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode)
+bool OMR::X86::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::CPU *cpu, TR::ILOpCode opcode)
    {
    TR_ASSERT_FATAL(opcode.isVectorOpCode(), "getSupportsOpCodeForAutoSIMD expects vector opcode\n");
 
@@ -1008,8 +1007,7 @@ OMR::X86::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode)
       case TR::vsub:
          return ot.getVectorLength() == TR::VectorLength128;
       case TR::vmul:
-         TR_ASSERT_FATAL(self()->comp()->compileRelocatableCode() || self()->comp()->isOutOfProcessCompilation() || self()->comp()->compilePortableCode() || self()->getX86ProcessorInfo().supportsSSE4_1() == self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE4_1), "supportsSSE4_1() failed\n");
-         if (et == TR::Float || et == TR::Double || (et == TR::Int32 && self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE4_1)))
+         if (et == TR::Float || et == TR::Double || (et == TR::Int32 && cpu->supportsFeature(OMR_FEATURE_X86_SSE4_1)))
             return ot.getVectorLength() == TR::VectorLength128;
          else
             return false;
@@ -1034,11 +1032,11 @@ OMR::X86::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode)
          switch (ot.getVectorLength())
             {
             case TR::VectorLength512:
-               if (!self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_X86_AVX512F))
+               if (!cpu->supportsFeature(OMR_FEATURE_X86_AVX512F))
                   return false;
                return true;
             case TR::VectorLength256:
-               if (!self()->comp()->target().cpu.supportsAVX())
+               if (!cpu->supportsAVX())
                   return false;
                return true;
             case TR::VectorLength128:
@@ -1081,6 +1079,11 @@ OMR::X86::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode)
    return false;
    }
 
+bool
+OMR::X86::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode)
+   {
+   return TR::CodeGenerator::getSupportsOpCodeForAutoSIMD(&self()->comp()->target().cpu, opcode);
+   }
 
 bool
 OMR::X86::CodeGenerator::getSupportsEncodeUtf16LittleWithSurrogateTest()

compiler/x/codegen/OMRCodeGenerator.hpp

@@ -362,7 +362,9 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator
    bool hasComplexAddressingMode() { return true; }
    bool getSupportsBitOpCodes() { return true; }
 
-   bool getSupportsOpCodeForAutoSIMD(TR::ILOpCode);
+   static bool getSupportsOpCodeForAutoSIMD(TR::CPU *cpu, TR::ILOpCode opcode);
+   bool getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode);
+
    bool getSupportsEncodeUtf16LittleWithSurrogateTest();
    bool getSupportsEncodeUtf16BigWithSurrogateTest();
 

compiler/z/codegen/OMRCodeGenerator.cpp

@@ -4719,7 +4719,7 @@ bool OMR::Z::CodeGenerator::isDispInRange(int64_t disp)
    return (MINLONGDISP <= disp) && (disp <= MAXLONGDISP);
    }
 
-bool OMR::Z::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode)
+bool OMR::Z::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::CPU *cpu, TR::ILOpCode opcode, bool supportsVectorRegisters)
    {
    TR_ASSERT_FATAL(opcode.isVectorOpCode(), "getSupportsOpCodeForAutoSIMD expects vector opcode\n");
 
@@ -4736,8 +4736,7 @@ bool OMR::Z::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode)
     * Prior to z14, vector operations that operated on floating point numbers only supported
     * Doubles. On z14 and onward, Float type floating point numbers are supported as well.
     */
-   if (!self()->getSupportsVectorRegisters() ||
-         (et == TR::Float && !self()->comp()->target().cpu.getSupportsVectorFacilityEnhancement1()))
+   if (!supportsVectorRegisters || (et == TR::Float && !cpu->getSupportsVectorFacilityEnhancement1()))
       {
       return false;
       }
@@ -4788,6 +4787,11 @@ bool OMR::Z::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode)
    return false;
    }
 
+bool OMR::Z::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode)
+   {
+   return TR::CodeGenerator::getSupportsOpCodeForAutoSIMD(&self()->comp()->target().cpu, opcode, self()->getSupportsVectorRegisters());
+   }
+
 // simple syntactic test for matching direct loads when the caller knows (by some mechanism, e.g. _symRefsToCheckForKills) that
 // there is no intervening kill to the load memory
 bool

compiler/z/codegen/OMRCodeGenerator.hpp

@@ -746,7 +746,8 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator
 
    virtual bool isDispInRange(int64_t disp);
 
-   bool getSupportsOpCodeForAutoSIMD(TR::ILOpCode);
+   static bool getSupportsOpCodeForAutoSIMD(TR::CPU *cpu, TR::ILOpCode opcode, bool supportsVectorRegisters = true);
+   bool getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode);
 
    TR::Instruction *_ccInstruction;
    TR::Instruction* ccInstruction() { return _ccInstruction; }

fvtest/compilertriltest/VectorTest.cpp

@@ -31,30 +31,17 @@ TEST_P(ParameterizedVectorTest, VLoadStore) {
     TR::VectorLength vl = std::get<0>(GetParam());
     TR::DataTypes et = std::get<1>(GetParam());
 
-    //TODO: Re-enable this test on S390 after issue #1843 is resolved.
+    SKIP_IF(vl > TR::NumVectorLengths, MissingImplementation) << "Vector length is not supported by the target platform";
     SKIP_ON_S390(KnownBug) << "This test is currently disabled on Z platforms because not all Z platforms have vector support (issue #1843)";
     SKIP_ON_S390X(KnownBug) << "This test is currently disabled on Z platforms because not all Z platforms have vector support (issue #1843)";
-    SKIP_ON_RISCV(MissingImplementation);
 
-    if (vl != TR::VectorLength128) {
-        SKIP_ON_POWER(MissingImplementation);
-        SKIP_ON_ARM(MissingImplementation);
-    }
+    TR::DataType vt = TR::DataType::createVectorType(et, vl);
 
-#if defined(TR_TARGET_X86)
-    OMRProcessorDesc desc;
-    omrsysinfo_get_processor_description(&desc);
-    bool supportsAVX = omrsysinfo_processor_has_feature(&desc, OMR_FEATURE_X86_AVX);
-    bool supportsAVX512 = omrsysinfo_processor_has_feature(&desc, OMR_FEATURE_X86_AVX512F);
-
-    if (!supportsAVX && vl == TR::VectorLength256) {
-        SKIP_ON_X86(UnsupportedFeature) << "Cannot execute 256-bit vector test without AVX hardware";
-        SKIP_ON_HAMMER(UnsupportedFeature) << "Cannot execute 256-bit vector test without AVX hardware";
-    } else if (!supportsAVX512 && vl == TR::VectorLength512) {
-        SKIP_ON_X86(UnsupportedFeature) << "Cannot execute 512-bit vector test without AVX-512 hardware";
-        SKIP_ON_HAMMER(UnsupportedFeature) << "Cannot execute 512-bit vector test without AVX-512 hardware";
-    }
-#endif
+    TR::ILOpCode loadOp = TR::ILOpCode::createVectorOpCode(TR::vloadi, vt);
+    TR::ILOpCode storeOp = TR::ILOpCode::createVectorOpCode(TR::vstorei, vt);
+    TR::CPU cpu = TR::CPU::detect(privateOmrPortLibrary);
+    bool platformSupport = TR::CodeGenerator::getSupportsOpCodeForAutoSIMD(&cpu, loadOp) && TR::CodeGenerator::getSupportsOpCodeForAutoSIMD(&cpu, loadOp);
+    SKIP_IF(!platformSupport, MissingImplementation) << "Opcode is not supported by the target platform";
 
     char inputTrees[1024];
     char *formatStr = "(method return= NoType args=[Address,Address]   "
@@ -63,7 +50,6 @@ TEST_P(ParameterizedVectorTest, VLoadStore) {
                       "         (aload parm=0)                         "
                       "         (vloadi%s (aload parm=1)))             "
                       "     (return)))                                 ";
-    TR::DataType vt = TR::DataType::createVectorType(et, vl);
 
     sprintf(inputTrees, formatStr, vt.toString(), vt.toString());
     auto trees = parseString(inputTrees);