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arm-linux-tdep.c
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arm-linux-tdep.c
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/* GNU/Linux on ARM target support.
Copyright (C) 1999-2017 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "target.h"
#include "value.h"
#include "gdbtypes.h"
#include "floatformat.h"
#include "gdbcore.h"
#include "frame.h"
#include "regcache.h"
#include "doublest.h"
#include "solib-svr4.h"
#include "osabi.h"
#include "regset.h"
#include "trad-frame.h"
#include "tramp-frame.h"
#include "breakpoint.h"
#include "auxv.h"
#include "xml-syscall.h"
#include "arch/arm.h"
#include "arch/arm-get-next-pcs.h"
#include "arch/arm-linux.h"
#include "arm-tdep.h"
#include "arm-linux-tdep.h"
#include "linux-tdep.h"
#include "glibc-tdep.h"
#include "arch-utils.h"
#include "inferior.h"
#include "infrun.h"
#include "gdbthread.h"
#include "symfile.h"
#include "record-full.h"
#include "linux-record.h"
#include "cli/cli-utils.h"
#include "stap-probe.h"
#include "parser-defs.h"
#include "user-regs.h"
#include <ctype.h>
#include "elf/common.h"
extern int arm_apcs_32;
/* Under ARM GNU/Linux the traditional way of performing a breakpoint
is to execute a particular software interrupt, rather than use a
particular undefined instruction to provoke a trap. Upon exection
of the software interrupt the kernel stops the inferior with a
SIGTRAP, and wakes the debugger. */
static const gdb_byte arm_linux_arm_le_breakpoint[] = { 0x01, 0x00, 0x9f, 0xef };
static const gdb_byte arm_linux_arm_be_breakpoint[] = { 0xef, 0x9f, 0x00, 0x01 };
/* However, the EABI syscall interface (new in Nov. 2005) does not look at
the operand of the swi if old-ABI compatibility is disabled. Therefore,
use an undefined instruction instead. This is supported as of kernel
version 2.5.70 (May 2003), so should be a safe assumption for EABI
binaries. */
static const gdb_byte eabi_linux_arm_le_breakpoint[] = { 0xf0, 0x01, 0xf0, 0xe7 };
static const gdb_byte eabi_linux_arm_be_breakpoint[] = { 0xe7, 0xf0, 0x01, 0xf0 };
/* All the kernels which support Thumb support using a specific undefined
instruction for the Thumb breakpoint. */
static const gdb_byte arm_linux_thumb_be_breakpoint[] = {0xde, 0x01};
static const gdb_byte arm_linux_thumb_le_breakpoint[] = {0x01, 0xde};
/* Because the 16-bit Thumb breakpoint is affected by Thumb-2 IT blocks,
we must use a length-appropriate breakpoint for 32-bit Thumb
instructions. See also thumb_get_next_pc. */
static const gdb_byte arm_linux_thumb2_be_breakpoint[] = { 0xf7, 0xf0, 0xa0, 0x00 };
static const gdb_byte arm_linux_thumb2_le_breakpoint[] = { 0xf0, 0xf7, 0x00, 0xa0 };
/* Description of the longjmp buffer. The buffer is treated as an array of
elements of size ARM_LINUX_JB_ELEMENT_SIZE.
The location of saved registers in this buffer (in particular the PC
to use after longjmp is called) varies depending on the ABI (in
particular the FP model) and also (possibly) the C Library.
For glibc, eglibc, and uclibc the following holds: If the FP model is
SoftVFP or VFP (which implies EABI) then the PC is at offset 9 in the
buffer. This is also true for the SoftFPA model. However, for the FPA
model the PC is at offset 21 in the buffer. */
#define ARM_LINUX_JB_ELEMENT_SIZE INT_REGISTER_SIZE
#define ARM_LINUX_JB_PC_FPA 21
#define ARM_LINUX_JB_PC_EABI 9
/*
Dynamic Linking on ARM GNU/Linux
--------------------------------
Note: PLT = procedure linkage table
GOT = global offset table
As much as possible, ELF dynamic linking defers the resolution of
jump/call addresses until the last minute. The technique used is
inspired by the i386 ELF design, and is based on the following
constraints.
1) The calling technique should not force a change in the assembly
code produced for apps; it MAY cause changes in the way assembly
code is produced for position independent code (i.e. shared
libraries).
2) The technique must be such that all executable areas must not be
modified; and any modified areas must not be executed.
To do this, there are three steps involved in a typical jump:
1) in the code
2) through the PLT
3) using a pointer from the GOT
When the executable or library is first loaded, each GOT entry is
initialized to point to the code which implements dynamic name
resolution and code finding. This is normally a function in the
program interpreter (on ARM GNU/Linux this is usually
ld-linux.so.2, but it does not have to be). On the first
invocation, the function is located and the GOT entry is replaced
with the real function address. Subsequent calls go through steps
1, 2 and 3 and end up calling the real code.
1) In the code:
b function_call
bl function_call
This is typical ARM code using the 26 bit relative branch or branch
and link instructions. The target of the instruction
(function_call is usually the address of the function to be called.
In position independent code, the target of the instruction is
actually an entry in the PLT when calling functions in a shared
library. Note that this call is identical to a normal function
call, only the target differs.
2) In the PLT:
The PLT is a synthetic area, created by the linker. It exists in
both executables and libraries. It is an array of stubs, one per
imported function call. It looks like this:
PLT[0]:
str lr, [sp, #-4]! @push the return address (lr)
ldr lr, [pc, #16] @load from 6 words ahead
add lr, pc, lr @form an address for GOT[0]
ldr pc, [lr, #8]! @jump to the contents of that addr
The return address (lr) is pushed on the stack and used for
calculations. The load on the second line loads the lr with
&GOT[3] - . - 20. The addition on the third leaves:
lr = (&GOT[3] - . - 20) + (. + 8)
lr = (&GOT[3] - 12)
lr = &GOT[0]
On the fourth line, the pc and lr are both updated, so that:
pc = GOT[2]
lr = &GOT[0] + 8
= &GOT[2]
NOTE: PLT[0] borrows an offset .word from PLT[1]. This is a little
"tight", but allows us to keep all the PLT entries the same size.
PLT[n+1]:
ldr ip, [pc, #4] @load offset from gotoff
add ip, pc, ip @add the offset to the pc
ldr pc, [ip] @jump to that address
gotoff: .word GOT[n+3] - .
The load on the first line, gets an offset from the fourth word of
the PLT entry. The add on the second line makes ip = &GOT[n+3],
which contains either a pointer to PLT[0] (the fixup trampoline) or
a pointer to the actual code.
3) In the GOT:
The GOT contains helper pointers for both code (PLT) fixups and
data fixups. The first 3 entries of the GOT are special. The next
M entries (where M is the number of entries in the PLT) belong to
the PLT fixups. The next D (all remaining) entries belong to
various data fixups. The actual size of the GOT is 3 + M + D.
The GOT is also a synthetic area, created by the linker. It exists
in both executables and libraries. When the GOT is first
initialized , all the GOT entries relating to PLT fixups are
pointing to code back at PLT[0].
The special entries in the GOT are:
GOT[0] = linked list pointer used by the dynamic loader
GOT[1] = pointer to the reloc table for this module
GOT[2] = pointer to the fixup/resolver code
The first invocation of function call comes through and uses the
fixup/resolver code. On the entry to the fixup/resolver code:
ip = &GOT[n+3]
lr = &GOT[2]
stack[0] = return address (lr) of the function call
[r0, r1, r2, r3] are still the arguments to the function call
This is enough information for the fixup/resolver code to work
with. Before the fixup/resolver code returns, it actually calls
the requested function and repairs &GOT[n+3]. */
/* The constants below were determined by examining the following files
in the linux kernel sources:
arch/arm/kernel/signal.c
- see SWI_SYS_SIGRETURN and SWI_SYS_RT_SIGRETURN
include/asm-arm/unistd.h
- see __NR_sigreturn, __NR_rt_sigreturn, and __NR_SYSCALL_BASE */
#define ARM_LINUX_SIGRETURN_INSTR 0xef900077
#define ARM_LINUX_RT_SIGRETURN_INSTR 0xef9000ad
/* For ARM EABI, the syscall number is not in the SWI instruction
(instead it is loaded into r7). We recognize the pattern that
glibc uses... alternatively, we could arrange to do this by
function name, but they are not always exported. */
#define ARM_SET_R7_SIGRETURN 0xe3a07077
#define ARM_SET_R7_RT_SIGRETURN 0xe3a070ad
#define ARM_EABI_SYSCALL 0xef000000
/* Equivalent patterns for Thumb2. */
#define THUMB2_SET_R7_SIGRETURN1 0xf04f
#define THUMB2_SET_R7_SIGRETURN2 0x0777
#define THUMB2_SET_R7_RT_SIGRETURN1 0xf04f
#define THUMB2_SET_R7_RT_SIGRETURN2 0x07ad
#define THUMB2_EABI_SYSCALL 0xdf00
/* OABI syscall restart trampoline, used for EABI executables too
whenever OABI support has been enabled in the kernel. */
#define ARM_OABI_SYSCALL_RESTART_SYSCALL 0xef900000
#define ARM_LDR_PC_SP_12 0xe49df00c
#define ARM_LDR_PC_SP_4 0xe49df004
/* Syscall number for sigreturn. */
#define ARM_SIGRETURN 119
/* Syscall number for rt_sigreturn. */
#define ARM_RT_SIGRETURN 173
static CORE_ADDR
arm_linux_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self);
/* Operation function pointers for get_next_pcs. */
static struct arm_get_next_pcs_ops arm_linux_get_next_pcs_ops = {
arm_get_next_pcs_read_memory_unsigned_integer,
arm_linux_get_next_pcs_syscall_next_pc,
arm_get_next_pcs_addr_bits_remove,
arm_get_next_pcs_is_thumb,
arm_linux_get_next_pcs_fixup,
};
static void
arm_linux_sigtramp_cache (struct frame_info *this_frame,
struct trad_frame_cache *this_cache,
CORE_ADDR func, int regs_offset)
{
CORE_ADDR sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
CORE_ADDR base = sp + regs_offset;
int i;
for (i = 0; i < 16; i++)
trad_frame_set_reg_addr (this_cache, i, base + i * 4);
trad_frame_set_reg_addr (this_cache, ARM_PS_REGNUM, base + 16 * 4);
/* The VFP or iWMMXt registers may be saved on the stack, but there's
no reliable way to restore them (yet). */
/* Save a frame ID. */
trad_frame_set_id (this_cache, frame_id_build (sp, func));
}
/* See arm-linux.h for stack layout details. */
static void
arm_linux_sigreturn_init (const struct tramp_frame *self,
struct frame_info *this_frame,
struct trad_frame_cache *this_cache,
CORE_ADDR func)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
ULONGEST uc_flags = read_memory_unsigned_integer (sp, 4, byte_order);
if (uc_flags == ARM_NEW_SIGFRAME_MAGIC)
arm_linux_sigtramp_cache (this_frame, this_cache, func,
ARM_UCONTEXT_SIGCONTEXT
+ ARM_SIGCONTEXT_R0);
else
arm_linux_sigtramp_cache (this_frame, this_cache, func,
ARM_SIGCONTEXT_R0);
}
static void
arm_linux_rt_sigreturn_init (const struct tramp_frame *self,
struct frame_info *this_frame,
struct trad_frame_cache *this_cache,
CORE_ADDR func)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
ULONGEST pinfo = read_memory_unsigned_integer (sp, 4, byte_order);
if (pinfo == sp + ARM_OLD_RT_SIGFRAME_SIGINFO)
arm_linux_sigtramp_cache (this_frame, this_cache, func,
ARM_OLD_RT_SIGFRAME_UCONTEXT
+ ARM_UCONTEXT_SIGCONTEXT
+ ARM_SIGCONTEXT_R0);
else
arm_linux_sigtramp_cache (this_frame, this_cache, func,
ARM_NEW_RT_SIGFRAME_UCONTEXT
+ ARM_UCONTEXT_SIGCONTEXT
+ ARM_SIGCONTEXT_R0);
}
static void
arm_linux_restart_syscall_init (const struct tramp_frame *self,
struct frame_info *this_frame,
struct trad_frame_cache *this_cache,
CORE_ADDR func)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
CORE_ADDR sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
CORE_ADDR pc = get_frame_memory_unsigned (this_frame, sp, 4);
CORE_ADDR cpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM);
ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
int sp_offset;
/* There are two variants of this trampoline; with older kernels, the
stub is placed on the stack, while newer kernels use the stub from
the vector page. They are identical except that the older version
increments SP by 12 (to skip stored PC and the stub itself), while
the newer version increments SP only by 4 (just the stored PC). */
if (self->insn[1].bytes == ARM_LDR_PC_SP_4)
sp_offset = 4;
else
sp_offset = 12;
/* Update Thumb bit in CPSR. */
if (pc & 1)
cpsr |= t_bit;
else
cpsr &= ~t_bit;
/* Remove Thumb bit from PC. */
pc = gdbarch_addr_bits_remove (gdbarch, pc);
/* Save previous register values. */
trad_frame_set_reg_value (this_cache, ARM_SP_REGNUM, sp + sp_offset);
trad_frame_set_reg_value (this_cache, ARM_PC_REGNUM, pc);
trad_frame_set_reg_value (this_cache, ARM_PS_REGNUM, cpsr);
/* Save a frame ID. */
trad_frame_set_id (this_cache, frame_id_build (sp, func));
}
static struct tramp_frame arm_linux_sigreturn_tramp_frame = {
SIGTRAMP_FRAME,
4,
{
{ ARM_LINUX_SIGRETURN_INSTR, -1 },
{ TRAMP_SENTINEL_INSN }
},
arm_linux_sigreturn_init
};
static struct tramp_frame arm_linux_rt_sigreturn_tramp_frame = {
SIGTRAMP_FRAME,
4,
{
{ ARM_LINUX_RT_SIGRETURN_INSTR, -1 },
{ TRAMP_SENTINEL_INSN }
},
arm_linux_rt_sigreturn_init
};
static struct tramp_frame arm_eabi_linux_sigreturn_tramp_frame = {
SIGTRAMP_FRAME,
4,
{
{ ARM_SET_R7_SIGRETURN, -1 },
{ ARM_EABI_SYSCALL, -1 },
{ TRAMP_SENTINEL_INSN }
},
arm_linux_sigreturn_init
};
static struct tramp_frame arm_eabi_linux_rt_sigreturn_tramp_frame = {
SIGTRAMP_FRAME,
4,
{
{ ARM_SET_R7_RT_SIGRETURN, -1 },
{ ARM_EABI_SYSCALL, -1 },
{ TRAMP_SENTINEL_INSN }
},
arm_linux_rt_sigreturn_init
};
static struct tramp_frame thumb2_eabi_linux_sigreturn_tramp_frame = {
SIGTRAMP_FRAME,
2,
{
{ THUMB2_SET_R7_SIGRETURN1, -1 },
{ THUMB2_SET_R7_SIGRETURN2, -1 },
{ THUMB2_EABI_SYSCALL, -1 },
{ TRAMP_SENTINEL_INSN }
},
arm_linux_sigreturn_init
};
static struct tramp_frame thumb2_eabi_linux_rt_sigreturn_tramp_frame = {
SIGTRAMP_FRAME,
2,
{
{ THUMB2_SET_R7_RT_SIGRETURN1, -1 },
{ THUMB2_SET_R7_RT_SIGRETURN2, -1 },
{ THUMB2_EABI_SYSCALL, -1 },
{ TRAMP_SENTINEL_INSN }
},
arm_linux_rt_sigreturn_init
};
static struct tramp_frame arm_linux_restart_syscall_tramp_frame = {
NORMAL_FRAME,
4,
{
{ ARM_OABI_SYSCALL_RESTART_SYSCALL, -1 },
{ ARM_LDR_PC_SP_12, -1 },
{ TRAMP_SENTINEL_INSN }
},
arm_linux_restart_syscall_init
};
static struct tramp_frame arm_kernel_linux_restart_syscall_tramp_frame = {
NORMAL_FRAME,
4,
{
{ ARM_OABI_SYSCALL_RESTART_SYSCALL, -1 },
{ ARM_LDR_PC_SP_4, -1 },
{ TRAMP_SENTINEL_INSN }
},
arm_linux_restart_syscall_init
};
/* Core file and register set support. */
#define ARM_LINUX_SIZEOF_GREGSET (18 * INT_REGISTER_SIZE)
void
arm_linux_supply_gregset (const struct regset *regset,
struct regcache *regcache,
int regnum, const void *gregs_buf, size_t len)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
const gdb_byte *gregs = (const gdb_byte *) gregs_buf;
int regno;
CORE_ADDR reg_pc;
gdb_byte pc_buf[INT_REGISTER_SIZE];
for (regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++)
if (regnum == -1 || regnum == regno)
regcache_raw_supply (regcache, regno,
gregs + INT_REGISTER_SIZE * regno);
if (regnum == ARM_PS_REGNUM || regnum == -1)
{
if (arm_apcs_32)
regcache_raw_supply (regcache, ARM_PS_REGNUM,
gregs + INT_REGISTER_SIZE * ARM_CPSR_GREGNUM);
else
regcache_raw_supply (regcache, ARM_PS_REGNUM,
gregs + INT_REGISTER_SIZE * ARM_PC_REGNUM);
}
if (regnum == ARM_PC_REGNUM || regnum == -1)
{
reg_pc = extract_unsigned_integer (gregs
+ INT_REGISTER_SIZE * ARM_PC_REGNUM,
INT_REGISTER_SIZE, byte_order);
reg_pc = gdbarch_addr_bits_remove (gdbarch, reg_pc);
store_unsigned_integer (pc_buf, INT_REGISTER_SIZE, byte_order, reg_pc);
regcache_raw_supply (regcache, ARM_PC_REGNUM, pc_buf);
}
}
void
arm_linux_collect_gregset (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *gregs_buf, size_t len)
{
gdb_byte *gregs = (gdb_byte *) gregs_buf;
int regno;
for (regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++)
if (regnum == -1 || regnum == regno)
regcache_raw_collect (regcache, regno,
gregs + INT_REGISTER_SIZE * regno);
if (regnum == ARM_PS_REGNUM || regnum == -1)
{
if (arm_apcs_32)
regcache_raw_collect (regcache, ARM_PS_REGNUM,
gregs + INT_REGISTER_SIZE * ARM_CPSR_GREGNUM);
else
regcache_raw_collect (regcache, ARM_PS_REGNUM,
gregs + INT_REGISTER_SIZE * ARM_PC_REGNUM);
}
if (regnum == ARM_PC_REGNUM || regnum == -1)
regcache_raw_collect (regcache, ARM_PC_REGNUM,
gregs + INT_REGISTER_SIZE * ARM_PC_REGNUM);
}
/* Support for register format used by the NWFPE FPA emulator. */
#define typeNone 0x00
#define typeSingle 0x01
#define typeDouble 0x02
#define typeExtended 0x03
void
supply_nwfpe_register (struct regcache *regcache, int regno,
const gdb_byte *regs)
{
const gdb_byte *reg_data;
gdb_byte reg_tag;
gdb_byte buf[FP_REGISTER_SIZE];
reg_data = regs + (regno - ARM_F0_REGNUM) * FP_REGISTER_SIZE;
reg_tag = regs[(regno - ARM_F0_REGNUM) + NWFPE_TAGS_OFFSET];
memset (buf, 0, FP_REGISTER_SIZE);
switch (reg_tag)
{
case typeSingle:
memcpy (buf, reg_data, 4);
break;
case typeDouble:
memcpy (buf, reg_data + 4, 4);
memcpy (buf + 4, reg_data, 4);
break;
case typeExtended:
/* We want sign and exponent, then least significant bits,
then most significant. NWFPE does sign, most, least. */
memcpy (buf, reg_data, 4);
memcpy (buf + 4, reg_data + 8, 4);
memcpy (buf + 8, reg_data + 4, 4);
break;
default:
break;
}
regcache_raw_supply (regcache, regno, buf);
}
void
collect_nwfpe_register (const struct regcache *regcache, int regno,
gdb_byte *regs)
{
gdb_byte *reg_data;
gdb_byte reg_tag;
gdb_byte buf[FP_REGISTER_SIZE];
regcache_raw_collect (regcache, regno, buf);
/* NOTE drow/2006-06-07: This code uses the tag already in the
register buffer. I've preserved that when moving the code
from the native file to the target file. But this doesn't
always make sense. */
reg_data = regs + (regno - ARM_F0_REGNUM) * FP_REGISTER_SIZE;
reg_tag = regs[(regno - ARM_F0_REGNUM) + NWFPE_TAGS_OFFSET];
switch (reg_tag)
{
case typeSingle:
memcpy (reg_data, buf, 4);
break;
case typeDouble:
memcpy (reg_data, buf + 4, 4);
memcpy (reg_data + 4, buf, 4);
break;
case typeExtended:
memcpy (reg_data, buf, 4);
memcpy (reg_data + 4, buf + 8, 4);
memcpy (reg_data + 8, buf + 4, 4);
break;
default:
break;
}
}
void
arm_linux_supply_nwfpe (const struct regset *regset,
struct regcache *regcache,
int regnum, const void *regs_buf, size_t len)
{
const gdb_byte *regs = (const gdb_byte *) regs_buf;
int regno;
if (regnum == ARM_FPS_REGNUM || regnum == -1)
regcache_raw_supply (regcache, ARM_FPS_REGNUM,
regs + NWFPE_FPSR_OFFSET);
for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++)
if (regnum == -1 || regnum == regno)
supply_nwfpe_register (regcache, regno, regs);
}
void
arm_linux_collect_nwfpe (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *regs_buf, size_t len)
{
gdb_byte *regs = (gdb_byte *) regs_buf;
int regno;
for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++)
if (regnum == -1 || regnum == regno)
collect_nwfpe_register (regcache, regno, regs);
if (regnum == ARM_FPS_REGNUM || regnum == -1)
regcache_raw_collect (regcache, ARM_FPS_REGNUM,
regs + INT_REGISTER_SIZE * ARM_FPS_REGNUM);
}
/* Support VFP register format. */
#define ARM_LINUX_SIZEOF_VFP (32 * 8 + 4)
static void
arm_linux_supply_vfp (const struct regset *regset,
struct regcache *regcache,
int regnum, const void *regs_buf, size_t len)
{
const gdb_byte *regs = (const gdb_byte *) regs_buf;
int regno;
if (regnum == ARM_FPSCR_REGNUM || regnum == -1)
regcache_raw_supply (regcache, ARM_FPSCR_REGNUM, regs + 32 * 8);
for (regno = ARM_D0_REGNUM; regno <= ARM_D31_REGNUM; regno++)
if (regnum == -1 || regnum == regno)
regcache_raw_supply (regcache, regno,
regs + (regno - ARM_D0_REGNUM) * 8);
}
static void
arm_linux_collect_vfp (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *regs_buf, size_t len)
{
gdb_byte *regs = (gdb_byte *) regs_buf;
int regno;
if (regnum == ARM_FPSCR_REGNUM || regnum == -1)
regcache_raw_collect (regcache, ARM_FPSCR_REGNUM, regs + 32 * 8);
for (regno = ARM_D0_REGNUM; regno <= ARM_D31_REGNUM; regno++)
if (regnum == -1 || regnum == regno)
regcache_raw_collect (regcache, regno,
regs + (regno - ARM_D0_REGNUM) * 8);
}
static const struct regset arm_linux_gregset =
{
NULL, arm_linux_supply_gregset, arm_linux_collect_gregset
};
static const struct regset arm_linux_fpregset =
{
NULL, arm_linux_supply_nwfpe, arm_linux_collect_nwfpe
};
static const struct regset arm_linux_vfpregset =
{
NULL, arm_linux_supply_vfp, arm_linux_collect_vfp
};
/* Iterate over core file register note sections. */
static void
arm_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
iterate_over_regset_sections_cb *cb,
void *cb_data,
const struct regcache *regcache)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
cb (".reg", ARM_LINUX_SIZEOF_GREGSET, &arm_linux_gregset, NULL, cb_data);
if (tdep->vfp_register_count > 0)
cb (".reg-arm-vfp", ARM_LINUX_SIZEOF_VFP, &arm_linux_vfpregset,
"VFP floating-point", cb_data);
else if (tdep->have_fpa_registers)
cb (".reg2", ARM_LINUX_SIZEOF_NWFPE, &arm_linux_fpregset,
"FPA floating-point", cb_data);
}
/* Determine target description from core file. */
static const struct target_desc *
arm_linux_core_read_description (struct gdbarch *gdbarch,
struct target_ops *target,
bfd *abfd)
{
CORE_ADDR arm_hwcap = 0;
if (target_auxv_search (target, AT_HWCAP, &arm_hwcap) != 1)
return NULL;
if (arm_hwcap & HWCAP_VFP)
{
/* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support
Neon with VFPv3-D32. */
if (arm_hwcap & HWCAP_NEON)
return tdesc_arm_with_neon;
else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3)
return tdesc_arm_with_vfpv3;
else
return tdesc_arm_with_vfpv2;
}
return NULL;
}
/* Copy the value of next pc of sigreturn and rt_sigrturn into PC,
return 1. In addition, set IS_THUMB depending on whether we
will return to ARM or Thumb code. Return 0 if it is not a
rt_sigreturn/sigreturn syscall. */
static int
arm_linux_sigreturn_return_addr (struct frame_info *frame,
unsigned long svc_number,
CORE_ADDR *pc, int *is_thumb)
{
/* Is this a sigreturn or rt_sigreturn syscall? */
if (svc_number == 119 || svc_number == 173)
{
if (get_frame_type (frame) == SIGTRAMP_FRAME)
{
ULONGEST t_bit = arm_psr_thumb_bit (frame_unwind_arch (frame));
CORE_ADDR cpsr
= frame_unwind_register_unsigned (frame, ARM_PS_REGNUM);
*is_thumb = (cpsr & t_bit) != 0;
*pc = frame_unwind_caller_pc (frame);
return 1;
}
}
return 0;
}
/* Find the value of the next PC after a sigreturn or rt_sigreturn syscall
based on current processor state. In addition, set IS_THUMB depending
on whether we will return to ARM or Thumb code. */
static CORE_ADDR
arm_linux_sigreturn_next_pc (struct regcache *regcache,
unsigned long svc_number, int *is_thumb)
{
ULONGEST sp;
unsigned long sp_data;
CORE_ADDR next_pc = 0;
struct gdbarch *gdbarch = get_regcache_arch (regcache);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int pc_offset = 0;
int is_sigreturn = 0;
CORE_ADDR cpsr;
gdb_assert (svc_number == ARM_SIGRETURN
|| svc_number == ARM_RT_SIGRETURN);
is_sigreturn = (svc_number == ARM_SIGRETURN);
regcache_cooked_read_unsigned (regcache, ARM_SP_REGNUM, &sp);
sp_data = read_memory_unsigned_integer (sp, 4, byte_order);
pc_offset = arm_linux_sigreturn_next_pc_offset (sp, sp_data, svc_number,
is_sigreturn);
next_pc = read_memory_unsigned_integer (sp + pc_offset, 4, byte_order);
/* Set IS_THUMB according the CPSR saved on the stack. */
cpsr = read_memory_unsigned_integer (sp + pc_offset + 4, 4, byte_order);
*is_thumb = ((cpsr & arm_psr_thumb_bit (gdbarch)) != 0);
return next_pc;
}
/* At a ptrace syscall-stop, return the syscall number. This either
comes from the SWI instruction (OABI) or from r7 (EABI).
When the function fails, it should return -1. */
static LONGEST
arm_linux_get_syscall_number (struct gdbarch *gdbarch,
ptid_t ptid)
{
struct regcache *regs = get_thread_regcache (ptid);
ULONGEST pc;
ULONGEST cpsr;
ULONGEST t_bit = arm_psr_thumb_bit (gdbarch);
int is_thumb;
ULONGEST svc_number = -1;
regcache_cooked_read_unsigned (regs, ARM_PC_REGNUM, &pc);
regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &cpsr);
is_thumb = (cpsr & t_bit) != 0;
if (is_thumb)
{
regcache_cooked_read_unsigned (regs, 7, &svc_number);
}
else
{
enum bfd_endian byte_order_for_code =
gdbarch_byte_order_for_code (gdbarch);
/* PC gets incremented before the syscall-stop, so read the
previous instruction. */
unsigned long this_instr =
read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
unsigned long svc_operand = (0x00ffffff & this_instr);
if (svc_operand)
{
/* OABI */
svc_number = svc_operand - 0x900000;
}
else
{
/* EABI */
regcache_cooked_read_unsigned (regs, 7, &svc_number);
}
}
return svc_number;
}
static CORE_ADDR
arm_linux_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self)
{
CORE_ADDR next_pc = 0;
CORE_ADDR pc = regcache_read_pc (self->regcache);
int is_thumb = arm_is_thumb (self->regcache);
ULONGEST svc_number = 0;
if (is_thumb)
{
svc_number = regcache_raw_get_unsigned (self->regcache, 7);
next_pc = pc + 2;
}
else
{
struct gdbarch *gdbarch = get_regcache_arch (self->regcache);
enum bfd_endian byte_order_for_code =
gdbarch_byte_order_for_code (gdbarch);
unsigned long this_instr =
read_memory_unsigned_integer (pc, 4, byte_order_for_code);
unsigned long svc_operand = (0x00ffffff & this_instr);
if (svc_operand) /* OABI. */
{
svc_number = svc_operand - 0x900000;
}
else /* EABI. */
{
svc_number = regcache_raw_get_unsigned (self->regcache, 7);
}
next_pc = pc + 4;
}
if (svc_number == ARM_SIGRETURN || svc_number == ARM_RT_SIGRETURN)
{
/* SIGRETURN or RT_SIGRETURN may affect the arm thumb mode, so
update IS_THUMB. */
next_pc = arm_linux_sigreturn_next_pc (self->regcache, svc_number,
&is_thumb);
}
/* Addresses for calling Thumb functions have the bit 0 set. */
if (is_thumb)
next_pc = MAKE_THUMB_ADDR (next_pc);
return next_pc;
}
/* Insert a single step breakpoint at the next executed instruction. */
static std::vector<CORE_ADDR>
arm_linux_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct arm_get_next_pcs next_pcs_ctx;
/* If the target does have hardware single step, GDB doesn't have
to bother software single step. */
if (target_can_do_single_step () == 1)
return {};
arm_get_next_pcs_ctor (&next_pcs_ctx,
&arm_linux_get_next_pcs_ops,
gdbarch_byte_order (gdbarch),
gdbarch_byte_order_for_code (gdbarch),
1,
regcache);
std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx);
for (CORE_ADDR &pc_ref : next_pcs)
pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref);
return next_pcs;
}
/* Support for displaced stepping of Linux SVC instructions. */
static void
arm_linux_cleanup_svc (struct gdbarch *gdbarch,
struct regcache *regs,
struct displaced_step_closure *dsc)
{
ULONGEST apparent_pc;
int within_scratch;
regcache_cooked_read_unsigned (regs, ARM_PC_REGNUM, &apparent_pc);
within_scratch = (apparent_pc >= dsc->scratch_base
&& apparent_pc < (dsc->scratch_base
+ DISPLACED_MODIFIED_INSNS * 4 + 4));
if (debug_displaced)
{
fprintf_unfiltered (gdb_stdlog, "displaced: PC is apparently %.8lx after "
"SVC step ", (unsigned long) apparent_pc);
if (within_scratch)
fprintf_unfiltered (gdb_stdlog, "(within scratch space)\n");
else
fprintf_unfiltered (gdb_stdlog, "(outside scratch space)\n");
}
if (within_scratch)
displaced_write_reg (regs, dsc, ARM_PC_REGNUM,
dsc->insn_addr + dsc->insn_size, BRANCH_WRITE_PC);
}
static int
arm_linux_copy_svc (struct gdbarch *gdbarch, struct regcache *regs,
struct displaced_step_closure *dsc)
{
CORE_ADDR return_to = 0;
struct frame_info *frame;
unsigned int svc_number = displaced_read_reg (regs, dsc, 7);
int is_sigreturn = 0;
int is_thumb;
frame = get_current_frame ();
is_sigreturn = arm_linux_sigreturn_return_addr(frame, svc_number,
&return_to, &is_thumb);
if (is_sigreturn)
{
struct symtab_and_line sal;
if (debug_displaced)