Skip to content

Latest commit

 

History

History
43 lines (21 loc) · 679 Bytes

README.md

File metadata and controls

43 lines (21 loc) · 679 Bytes

Circuit Paths

Finding all possible paths between input and output in a given Combinational Circuit.

Requirements

Usage

pip3 install -r requirements.txt

python3 main.py

Information

Input: Verilog file with Gate Level Modelling

Output: All paths from input to output of the circuit described by the Verilog file

(Optional: Graph of the circuit can also be exported)

Sample Output

Output

Sample Output Graphs

C17 ISCAS85

C17

Full Adder

Full Adder