diff --git a/TESTS/mbedmicro-rtos-mbed/MemoryPool/main.cpp b/TESTS/mbedmicro-rtos-mbed/MemoryPool/main.cpp index 30e335873a1..c020eac83f1 100644 --- a/TESTS/mbedmicro-rtos-mbed/MemoryPool/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/MemoryPool/main.cpp @@ -450,38 +450,6 @@ void test_mem_pool_free_realloc_first_complex(AllocType atype) } } -/* Robustness checks for free() function. - * - * Given block from the MemoryPool has been successfully deallocated. - * When free operation is executed on this block again. - * Then operation fails with osErrorResource status. - * - * */ -void test_mem_pool_free_on_freed_block() -{ - MemoryPool mem_pool; - int *p_block; - osStatus status; - - /* Allocate memory block. */ - p_block = mem_pool.alloc(); - - /* Show that memory pool block has been allocated. */ - TEST_ASSERT_NOT_NULL(p_block); - - /* Free memory block. */ - status = mem_pool.free(p_block); - - /* Check operation status. */ - TEST_ASSERT_EQUAL(osOK, status); - - /* Free memory block again. */ - status = mem_pool.free(p_block); - - /* Check operation status. */ - TEST_ASSERT_EQUAL(osErrorResource, status); -} - /* Robustness checks for free() function. * Function under test is called with invalid parameters. * @@ -601,7 +569,6 @@ Case cases[] = { Case("Test: fail (out of free blocks).", test_mem_pool_alloc_fail_wrapper), - Case("Test: free() - robust (free block twice).", test_mem_pool_free_on_freed_block), Case("Test: free() - robust (free called with invalid param - NULL).", free_block_invalid_parameter_null), Case("Test: free() - robust (free called with invalid param).", free_block_invalid_parameter) }; diff --git a/TESTS/mbedmicro-rtos-mbed/mail/main.cpp b/TESTS/mbedmicro-rtos-mbed/mail/main.cpp index 8594c88565c..f4d0907de66 100644 --- a/TESTS/mbedmicro-rtos-mbed/mail/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/mail/main.cpp @@ -265,28 +265,6 @@ void test_free_null() TEST_ASSERT_EQUAL(osErrorParameter, status); } -/** Test same message memory deallocation twice - - Given an empty mailbox - Then allocate message memory - When try to free it second time - Then it return appropriate error code - */ -void test_free_twice() -{ - osStatus status; - Mail mail_box; - - uint32_t *mail = mail_box.alloc(); - TEST_ASSERT_NOT_EQUAL(NULL, mail); - - status = mail_box.free(mail); - TEST_ASSERT_EQUAL(osOK, status); - - status = mail_box.free(mail); - TEST_ASSERT_EQUAL(osErrorResource, status); -} - /** Test get from empty mailbox with timeout set Given an empty mailbox @@ -515,7 +493,6 @@ Case cases[] = { Case("Test message send order", test_order), Case("Test get with timeout on empty mailbox", test_get_empty_timeout), Case("Test get without timeout on empty mailbox", test_get_empty_no_timeout), - Case("Test message free twice", test_free_twice), Case("Test null message free", test_free_null), Case("Test invalid message free", test_free_wrong), Case("Test message send/receive single thread and order", test_single_thread_order), diff --git a/cmsis/TARGET_CORTEX_A/cmsis_gcc.h b/cmsis/TARGET_CORTEX_A/cmsis_gcc.h index 5ac93d12c6c..4f464627a1d 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_gcc.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_gcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.0.1 - * @date 07. Sep 2017 + * @version V1.0.2 + * @date 09. April 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -450,7 +450,9 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + #if __has_builtin(__builtin_arm_get_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ return __builtin_arm_get_fpscr(); #else @@ -473,7 +475,9 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + #if __has_builtin(__builtin_arm_set_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ __builtin_arm_set_fpscr(fpscr); #else diff --git a/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h b/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h index a441e2d85bd..6ca1cd448f1 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.5 - * @date 10. January 2018 + * @version V5.0.6 + * @date 02. March 2018 ******************************************************************************/ //------------------------------------------------------------------------------ diff --git a/cmsis/TARGET_CORTEX_A/core_ca.h b/cmsis/TARGET_CORTEX_A/core_ca.h index c7c4b511f9c..dbe9794d4fe 100644 --- a/cmsis/TARGET_CORTEX_A/core_ca.h +++ b/cmsis/TARGET_CORTEX_A/core_ca.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_ca.h * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File - * @version V1.00 - * @date 22. Feb 2017 + * @version V1.0.1 + * @date 07. May 2018 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -1284,8 +1284,6 @@ __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) } else { // INTID 0-15 Software Generated Interrupt GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); - // Forward the interrupt to the CPU interface that requested it - GICDistributor->SGIR = (IRQn | 0x02000000U); } } diff --git a/cmsis/TARGET_CORTEX_M/cmsis_armcc.h b/cmsis/TARGET_CORTEX_M/cmsis_armcc.h index 093d35b9e5c..4d9d0645d3f 100644 --- a/cmsis/TARGET_CORTEX_M/cmsis_armcc.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_armcc.h @@ -337,8 +337,6 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. @@ -372,9 +370,6 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) #endif } -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - /*@} end of CMSIS_Core_RegAccFunctions */ diff --git a/cmsis/TARGET_CORTEX_M/cmsis_armclang.h b/cmsis/TARGET_CORTEX_M/cmsis_armclang.h index 5c4c20e8777..162a400ea1b 100644 --- a/cmsis/TARGET_CORTEX_M/cmsis_armclang.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_armclang.h @@ -237,7 +237,7 @@ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); @@ -252,7 +252,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSP(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); @@ -291,7 +291,7 @@ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); @@ -306,7 +306,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSP(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); @@ -346,7 +346,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); @@ -581,7 +581,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif @@ -603,7 +603,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif @@ -669,7 +669,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif @@ -691,7 +691,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif @@ -742,10 +742,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. @@ -770,10 +766,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) #define __set_FPSCR(x) ((void)(x)) #endif -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - /*@} end of CMSIS_Core_RegAccFunctions */ diff --git a/cmsis/TARGET_CORTEX_M/cmsis_gcc.h b/cmsis/TARGET_CORTEX_M/cmsis_gcc.h index 5d0f07e8acc..2d9db15a5de 100644 --- a/cmsis/TARGET_CORTEX_M/cmsis_gcc.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_gcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file - * @version V5.0.3 - * @date 16. January 2018 + * @version V5.0.4 + * @date 09. April 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -246,7 +246,7 @@ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); @@ -261,7 +261,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSP(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); @@ -300,7 +300,7 @@ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); @@ -315,7 +315,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSP(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); @@ -355,7 +355,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); @@ -596,7 +596,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif @@ -617,7 +617,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif @@ -683,7 +683,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif @@ -705,7 +705,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif @@ -758,9 +758,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. @@ -770,7 +767,9 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ return __builtin_arm_get_fpscr(); #else @@ -794,7 +793,9 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ __builtin_arm_set_fpscr(fpscr); #else @@ -805,10 +806,6 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) #endif } -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - /*@} end of CMSIS_Core_RegAccFunctions */ diff --git a/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h b/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h index edcaee3d4ab..931db1d5141 100644 --- a/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.5 - * @date 10. January 2018 + * @version V5.0.7 + * @date 19. June 2018 ******************************************************************************/ //------------------------------------------------------------------------------ @@ -340,8 +340,17 @@ __packed struct __iar_u32 { uint32_t v; }; #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) @@ -716,12 +725,25 @@ __packed struct __iar_u32 { uint32_t v; }; __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) { uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif return res; } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif } __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) @@ -826,78 +848,78 @@ __packed struct __iar_u32 { uint32_t v; }; __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) { uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { - __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { - __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { - __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } diff --git a/cmsis/TARGET_CORTEX_M/core_armv8mbl.h b/cmsis/TARGET_CORTEX_M/core_armv8mbl.h index 47a39893ace..251e4ede3a9 100644 --- a/cmsis/TARGET_CORTEX_M/core_armv8mbl.h +++ b/cmsis/TARGET_CORTEX_M/core_armv8mbl.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_armv8mbl.h * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.0.7 + * @date 22. June 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -59,7 +59,7 @@ \ingroup Cortex_ARMv8MBL @{ */ - + #include "cmsis_version.h" /* CMSIS definitions */ @@ -415,6 +415,9 @@ typedef struct #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ @@ -721,8 +724,8 @@ typedef struct */ typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; @@ -730,26 +733,18 @@ typedef struct uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -772,68 +767,25 @@ typedef struct #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ @@ -845,22 +797,16 @@ typedef struct #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1239,8 +1185,8 @@ typedef struct #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ @@ -1266,12 +1212,36 @@ typedef struct #define NVIC_USER_IRQ_OFFSET 16 +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt @@ -1512,6 +1482,58 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) } +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. @@ -1556,7 +1578,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void __NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ diff --git a/cmsis/TARGET_CORTEX_M/core_armv8mml.h b/cmsis/TARGET_CORTEX_M/core_armv8mml.h index 0951a1f7812..3a3148ea314 100644 --- a/cmsis/TARGET_CORTEX_M/core_armv8mml.h +++ b/cmsis/TARGET_CORTEX_M/core_armv8mml.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_armv8mml.h * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.0.7 + * @date 06. July 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS Armv8MML definitions */ #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ @@ -90,12 +90,12 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - + #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -113,7 +113,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -130,18 +130,18 @@ #else #define __FPU_USED 0U #endif - + #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - + #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -159,12 +159,12 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - + #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -568,6 +568,9 @@ typedef struct #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ @@ -1383,8 +1386,8 @@ typedef struct */ typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; @@ -1392,26 +1395,18 @@ typedef struct uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1434,68 +1429,25 @@ typedef struct #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ @@ -1507,22 +1459,16 @@ typedef struct #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1587,8 +1533,8 @@ typedef struct #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ @@ -2136,6 +2082,27 @@ typedef struct #define NVIC_USER_IRQ_OFFSET 16 +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + /** \brief Set Priority Grouping @@ -2495,7 +2462,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void __NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ diff --git a/cmsis/TARGET_CORTEX_M/core_cm0.h b/cmsis/TARGET_CORTEX_M/core_cm0.h index a3f1b9ac330..f929bba07b7 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm0.h +++ b/cmsis/TARGET_CORTEX_M/core_cm0.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 10. January 2018 + * @version V5.0.5 + * @date 28. May 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -572,8 +572,8 @@ typedef struct #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ @@ -599,12 +599,20 @@ typedef struct #define NVIC_USER_IRQ_OFFSET 16 +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt @@ -757,6 +765,59 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) } +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. @@ -792,7 +853,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void __NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ diff --git a/cmsis/TARGET_CORTEX_M/core_cm0plus.h b/cmsis/TARGET_CORTEX_M/core_cm0plus.h index f8f30c3496a..424011ac363 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm0plus.h +++ b/cmsis/TARGET_CORTEX_M/core_cm0plus.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.0.6 + * @date 28. May 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -690,8 +690,8 @@ typedef struct #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ @@ -717,12 +717,20 @@ typedef struct #define NVIC_USER_IRQ_OFFSET 16 +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt @@ -875,6 +883,58 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) } +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. @@ -920,7 +980,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void __NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ diff --git a/cmsis/TARGET_CORTEX_M/core_cm1.h b/cmsis/TARGET_CORTEX_M/core_cm1.h new file mode 100644 index 00000000000..0ed678e3b8d --- /dev/null +++ b/cmsis/TARGET_CORTEX_M/core_cm1.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 23. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/cmsis/TARGET_CORTEX_M/core_cm23.h b/cmsis/TARGET_CORTEX_M/core_cm23.h index 7d1d478af2a..acbc5dfea2a 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm23.h +++ b/cmsis/TARGET_CORTEX_M/core_cm23.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm23.h * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.0.7 + * @date 22. June 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -68,7 +68,7 @@ #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ -#define __CORTEX_M (23U) /*!< Cortex-M Core */ +#define __CORTEX_M (23U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all @@ -415,6 +415,9 @@ typedef struct #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ @@ -721,7 +724,7 @@ typedef struct */ typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ @@ -730,29 +733,26 @@ typedef struct uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -775,6 +775,9 @@ typedef struct #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ @@ -782,61 +785,79 @@ typedef struct #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ @@ -848,22 +869,19 @@ typedef struct #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1269,12 +1287,36 @@ typedef struct #define NVIC_USER_IRQ_OFFSET 16 +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt @@ -1515,6 +1557,58 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) } +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. @@ -1559,7 +1653,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void __NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ diff --git a/cmsis/TARGET_CORTEX_M/core_cm3.h b/cmsis/TARGET_CORTEX_M/core_cm3.h index a2c0d080572..74bff64be4f 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm3.h +++ b/cmsis/TARGET_CORTEX_M/core_cm3.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 + * @version V5.0.8 + * @date 04. June 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM3 definitions */ #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ @@ -995,7 +995,7 @@ typedef struct */ typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ @@ -1006,7 +1006,7 @@ typedef struct __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; @@ -1022,11 +1022,8 @@ typedef struct } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1079,8 +1076,11 @@ typedef struct #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ @@ -1105,12 +1105,15 @@ typedef struct #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ @@ -1132,12 +1135,12 @@ typedef struct #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1459,6 +1462,11 @@ typedef struct #define NVIC_USER_IRQ_OFFSET 16 +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + /** \brief Set Priority Grouping @@ -1751,7 +1759,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void __NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ diff --git a/cmsis/TARGET_CORTEX_M/core_cm33.h b/cmsis/TARGET_CORTEX_M/core_cm33.h index b1efbcae7c7..6cd2db77fe3 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm33.h +++ b/cmsis/TARGET_CORTEX_M/core_cm33.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm33.h * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 + * @version V5.0.9 + * @date 06. July 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -61,14 +61,14 @@ */ #include "cmsis_version.h" - + /* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ -#define __CORTEX_M (33U) /*!< Cortex-M Core */ +#define __CORTEX_M (33U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. @@ -90,7 +90,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -113,7 +113,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -136,7 +136,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -159,7 +159,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -568,6 +568,9 @@ typedef struct #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ @@ -1383,7 +1386,7 @@ typedef struct */ typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ @@ -1392,29 +1395,26 @@ typedef struct uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1437,6 +1437,9 @@ typedef struct #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ @@ -1444,61 +1447,79 @@ typedef struct #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ @@ -1510,22 +1531,19 @@ typedef struct #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1590,8 +1608,8 @@ typedef struct #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ @@ -2139,6 +2157,27 @@ typedef struct #define NVIC_USER_IRQ_OFFSET 16 +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + /** \brief Set Priority Grouping @@ -2498,7 +2537,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void __NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ diff --git a/cmsis/TARGET_CORTEX_M/core_cm4.h b/cmsis/TARGET_CORTEX_M/core_cm4.h index a11a3817a23..7d56873532c 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm4.h +++ b/cmsis/TARGET_CORTEX_M/core_cm4.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 + * @version V5.0.8 + * @date 04. June 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ @@ -1060,7 +1060,7 @@ typedef struct */ typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ @@ -1071,7 +1071,7 @@ typedef struct __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; @@ -1087,11 +1087,8 @@ typedef struct } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1144,8 +1141,11 @@ typedef struct #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ @@ -1170,12 +1170,15 @@ typedef struct #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ @@ -1197,12 +1200,12 @@ typedef struct #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1633,6 +1636,14 @@ typedef struct #define NVIC_USER_IRQ_OFFSET 16 +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + /** \brief Set Priority Grouping @@ -1925,7 +1936,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void __NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ diff --git a/cmsis/TARGET_CORTEX_M/core_cm7.h b/cmsis/TARGET_CORTEX_M/core_cm7.h index 1fe53bf012f..a14dc623b76 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm7.h +++ b/cmsis/TARGET_CORTEX_M/core_cm7.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 + * @version V5.0.8 + * @date 04. June 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -62,7 +62,7 @@ #include "cmsis_version.h" -/* CMSIS CM7 definitions */ +/* CMSIS CM7 definitions */ #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ @@ -1265,7 +1265,7 @@ typedef struct */ typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ @@ -1276,7 +1276,7 @@ typedef struct __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; @@ -1292,11 +1292,8 @@ typedef struct } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1349,8 +1346,11 @@ typedef struct #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ @@ -1375,12 +1375,15 @@ typedef struct #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ @@ -1402,12 +1405,12 @@ typedef struct #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1841,6 +1844,14 @@ typedef struct #define NVIC_USER_IRQ_OFFSET 16 +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + /** \brief Set Priority Grouping @@ -2133,7 +2144,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void __NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ @@ -2308,9 +2319,9 @@ __STATIC_INLINE void SCB_EnableDCache (void) __STATIC_INLINE void SCB_DisableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - register uint32_t ccsidr; - register uint32_t sets; - register uint32_t ways; + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); diff --git a/cmsis/TARGET_CORTEX_M/core_cmSecureAccess.h b/cmsis/TARGET_CORTEX_M/core_cmSecureAccess.h deleted file mode 100644 index 1fa367bb018..00000000000 --- a/cmsis/TARGET_CORTEX_M/core_cmSecureAccess.h +++ /dev/null @@ -1,119 +0,0 @@ -/**************************************************************************//** - * @file core_cmSecureAccess.h - * @brief CMSIS Cortex-M Core Secure Access Header File - * @version XXX - * @date 10. June 2016 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2016 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CM_SECURE_ACCESS_H -#define __CORE_CM_SECURE_ACCESS_H - - -/* ########################### Core Secure Access ########################### */ - -/* Insecure fallback implementation. */ - -/** Set the value at the target address. - * - * Equivalent to: `*address = value`. - * @param address[in] Target address - * @param value[in] Value to write at the address location. - */ -#define SECURE_WRITE(address, value) \ - *(address) = (value) - -/** Get the value at the target address. - * - * @param address[in] Target address - * @returns The value `*address`. - */ -#define SECURE_READ(address) \ - (*(address)) - -/** Get the selected bits at the target address. - * - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - * @returns The value `*address & mask`. - */ -#define SECURE_BITS_GET(address, mask) \ - (*(address) & (mask)) - -/** Check the selected bits at the target address. - * - * @param address[in] Address at which to check the bits - * @param mask[in] Bits to select out of the target address - * @returns The value `((*address & mask) == mask)`. - */ -#define SECURE_BITS_CHECK(address, mask) \ - ((*(address) & (mask)) == (mask)) - -/** Set the selected bits to 1 at the target address. - * - * Equivalent to: `*address |= mask`. - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - */ -#define SECURE_BITS_SET(address, mask) \ - *(address) |= (mask) - -/** Clear the selected bits at the target address. - * - * Equivalent to: `*address &= ~mask`. - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - */ -#define SECURE_BITS_CLEAR(address, mask) \ - *(address) &= ~(mask) - -/** Set the selected bits at the target address to the given value. - * - * Equivalent to: `*address = (*address & ~mask) | (value & mask)`. - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - * @param value[in] Value to write at the address location. Note: The value - * must be already shifted to the correct bit position - */ -#define SECURE_BITS_SET_VALUE(address, mask, value) \ - *(address) = (*(address) & ~(mask)) | ((value) & (mask)) - -/** Toggle the selected bits at the target address. - * - * Equivalent to: `*address ^= mask`. - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - */ -#define SECURE_BITS_TOGGLE(address, mask) \ - *(address) ^= (mask) - -#endif /* __CORE_CM_SECURE_ACCESS_H */ diff --git a/cmsis/TARGET_CORTEX_M/core_sc000.h b/cmsis/TARGET_CORTEX_M/core_sc000.h index 9aab5e5b3ea..9b67c92f3b9 100644 --- a/cmsis/TARGET_CORTEX_M/core_sc000.h +++ b/cmsis/TARGET_CORTEX_M/core_sc000.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 10. January 2018 + * @version V5.0.5 + * @date 28. May 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -727,6 +727,12 @@ typedef struct #define NVIC_USER_IRQ_OFFSET 16 +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) @@ -920,7 +926,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void __NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ diff --git a/cmsis/TARGET_CORTEX_M/core_sc300.h b/cmsis/TARGET_CORTEX_M/core_sc300.h index a569ef2acec..3e8a47109a7 100644 --- a/cmsis/TARGET_CORTEX_M/core_sc300.h +++ b/cmsis/TARGET_CORTEX_M/core_sc300.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 10. January 2018 + * @version V5.0.6 + * @date 04. June 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -977,7 +977,7 @@ typedef struct */ typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ @@ -988,7 +988,7 @@ typedef struct __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; @@ -1058,8 +1058,11 @@ typedef struct #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ @@ -1084,12 +1087,15 @@ typedef struct #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ @@ -1111,12 +1117,12 @@ typedef struct #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1436,6 +1442,12 @@ typedef struct #define NVIC_USER_IRQ_OFFSET 16 +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + /** \brief Set Priority Grouping @@ -1728,7 +1740,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void __NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ diff --git a/cmsis/TARGET_CORTEX_M/mbed_tz_context.c b/cmsis/TARGET_CORTEX_M/mbed_tz_context.c index 66acb4442d1..8e9541f75dc 100644 --- a/cmsis/TARGET_CORTEX_M/mbed_tz_context.c +++ b/cmsis/TARGET_CORTEX_M/mbed_tz_context.c @@ -20,17 +20,8 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - * - * ---------------------------------------------------------------------------- - * - * $Date: 15. October 2016 - * $Revision: 1.1.0 - * - * Project: TrustZone for ARMv8-M - * Title: Context Management for ARMv8-M TrustZone - Sample implementation - * - *---------------------------------------------------------------------------*/ - + */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "RTE_Components.h" diff --git a/cmsis/TARGET_CORTEX_M/mpu_armv7.h b/cmsis/TARGET_CORTEX_M/mpu_armv7.h index aa180c9e596..01422033d08 100644 --- a/cmsis/TARGET_CORTEX_M/mpu_armv7.h +++ b/cmsis/TARGET_CORTEX_M/mpu_armv7.h @@ -31,41 +31,41 @@ #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) - -#define ARM_MPU_AP_NONE 0U -#define ARM_MPU_AP_PRIV 1U -#define ARM_MPU_AP_URO 2U -#define ARM_MPU_AP_FULL 3U -#define ARM_MPU_AP_PRO 5U -#define ARM_MPU_AP_RO 6U +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access /** MPU Region Base Address Register Value * @@ -77,6 +77,34 @@ ((Region) & MPU_RBAR_REGION_Msk) | \ (MPU_RBAR_VALID_Msk)) +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + /** * MPU Region Attribute and Size Register Value * @@ -90,15 +118,60 @@ * \param Size Region size of the region to be configured, for example 4K, 8K. */ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ - (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ - (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ - (MPU_RASR_ENABLE_Msk)) + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U /** diff --git a/cmsis/TARGET_CORTEX_M/mpu_armv8.h b/cmsis/TARGET_CORTEX_M/mpu_armv8.h index 0ccfc74fe5b..62571da5b87 100644 --- a/cmsis/TARGET_CORTEX_M/mpu_armv8.h +++ b/cmsis/TARGET_CORTEX_M/mpu_armv8.h @@ -87,7 +87,7 @@ * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. */ #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - ((BASE & MPU_RBAR_BASE_Pos) | \ + ((BASE & MPU_RBAR_BASE_Msk) | \ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) diff --git a/rtos/TARGET_CORTEX/SysTimer.cpp b/rtos/TARGET_CORTEX/SysTimer.cpp index d3bcfc689a0..662e6d09df3 100644 --- a/rtos/TARGET_CORTEX/SysTimer.cpp +++ b/rtos/TARGET_CORTEX/SysTimer.cpp @@ -46,6 +46,10 @@ extern "C" { extern "C" IRQn_Type mbed_get_m0_tick_irqn(void); #endif +#if defined(TARGET_CORTEX_A) +extern "C" IRQn_ID_t mbed_get_a9_tick_irqn(void); +#endif + namespace rtos { namespace internal { diff --git a/rtos/TARGET_CORTEX/mbed_rtx_conf.h b/rtos/TARGET_CORTEX/mbed_rtx_conf.h index 3b4f3ec9914..3bc1ca86224 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_conf.h +++ b/rtos/TARGET_CORTEX/mbed_rtx_conf.h @@ -97,7 +97,7 @@ #define EVR_RTX_MEMORY_BLOCK_ALLOC_DISABLE #define EVR_RTX_MEMORY_BLOCK_FREE_DISABLE #define EVR_RTX_KERNEL_INITIALIZE_DISABLE -#define EVR_RTX_KERNEL_INITIALIZE_COMPLETED_DISABLE +#define EVR_RTX_KERNEL_INITIALIZED_DISABLE #define EVR_RTX_KERNEL_GET_INFO_DISABLE #define EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE #define EVR_RTX_KERNEL_GET_STATE_DISABLE diff --git a/rtos/TARGET_CORTEX/rtx5/Include/cmsis_os2.h b/rtos/TARGET_CORTEX/rtx5/Include/cmsis_os2.h index 295499fae57..e0b602c79a0 100644 --- a/rtos/TARGET_CORTEX/rtx5/Include/cmsis_os2.h +++ b/rtos/TARGET_CORTEX/rtx5/Include/cmsis_os2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -17,12 +17,15 @@ * * ---------------------------------------------------------------------- * - * $Date: 30. October 2017 - * $Revision: V2.1.2 + * $Date: 18. June 2018 + * $Revision: V2.1.3 * * Project: CMSIS-RTOS2 API * Title: cmsis_os2.h header file * + * Version 2.1.3 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osThreadGetId * Version 2.1.2 * Additional functions allowed to be called from Interrupt Service Routines: * - osKernelGetInfo, osKernelGetState @@ -366,11 +369,10 @@ uint32_t osKernelGetSysTimerFreq (void); /// \param[in] attr thread attributes; NULL: default values. /// \return thread ID for reference by other functions or NULL in case of error. osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr); -osThreadId_t osThreadContextNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr, void *context); /// Get name of a thread. /// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. -/// \return name as NULL terminated string. +/// \return name as null-terminated string. const char *osThreadGetName (osThreadId_t thread_id); /// Return the thread ID of the current running thread. @@ -496,7 +498,7 @@ osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, /// Get name of a timer. /// \param[in] timer_id timer ID obtained by \ref osTimerNew. -/// \return name as NULL terminated string. +/// \return name as null-terminated string. const char *osTimerGetName (osTimerId_t timer_id); /// Start or restart a timer. @@ -530,7 +532,7 @@ osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr); /// Get name of an Event Flags object. /// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. -/// \return name as NULL terminated string. +/// \return name as null-terminated string. const char *osEventFlagsGetName (osEventFlagsId_t ef_id); /// Set the specified Event Flags. @@ -573,7 +575,7 @@ osMutexId_t osMutexNew (const osMutexAttr_t *attr); /// Get name of a Mutex object. /// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. -/// \return name as NULL terminated string. +/// \return name as null-terminated string. const char *osMutexGetName (osMutexId_t mutex_id); /// Acquire a Mutex or timeout if it is locked. @@ -609,7 +611,7 @@ osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, cons /// Get name of a Semaphore object. /// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. -/// \return name as NULL terminated string. +/// \return name as null-terminated string. const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id); /// Acquire a Semaphore token or timeout if no tokens are available. @@ -645,7 +647,7 @@ osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, con /// Get name of a Memory Pool object. /// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. -/// \return name as NULL terminated string. +/// \return name as null-terminated string. const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id); /// Allocate a memory block from a Memory Pool. @@ -697,7 +699,7 @@ osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, con /// Get name of a Message Queue object. /// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. -/// \return name as NULL terminated string. +/// \return name as null-terminated string. const char *osMessageQueueGetName (osMessageQueueId_t mq_id); /// Put a Message into a Queue or timeout if Queue is full. diff --git a/rtos/TARGET_CORTEX/rtx5/Include/os_tick.h b/rtos/TARGET_CORTEX/rtx5/Include/os_tick.h index 45fad1b7fe4..8f7cdf667b1 100644 --- a/rtos/TARGET_CORTEX/rtx5/Include/os_tick.h +++ b/rtos/TARGET_CORTEX/rtx5/Include/os_tick.h @@ -26,9 +26,6 @@ #define OS_TICK_H #include -#if defined(TARGET_CORTEX_A) -#include "irq_ctrl.h" -#endif /// IRQ Handler. #ifndef IRQHANDLER_T @@ -36,44 +33,39 @@ typedef void (*IRQHandler_t) (void); #endif -/// Setup OS Tick. +/// Setup OS Tick timer to generate periodic RTOS Kernel Ticks /// \param[in] freq tick frequency in Hz /// \param[in] handler tick IRQ handler /// \return 0 on success, -1 on error. int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler); -/// Enable OS Tick. +/// Enable OS Tick timer interrupt void OS_Tick_Enable (void); -/// Disable OS Tick. +/// Disable OS Tick timer interrupt void OS_Tick_Disable (void); -/// Acknowledge OS Tick IRQ. +/// Acknowledge execution of OS Tick timer interrupt void OS_Tick_AcknowledgeIRQ (void); -/// Get OS Tick IRQ number. -/// \return OS Tick IRQ number. +/// Get OS Tick timer IRQ number +/// \return OS Tick IRQ number int32_t OS_Tick_GetIRQn (void); -/// Get OS Tick clock. -/// \return OS Tick clock in Hz. +/// Get OS Tick timer clock frequency +/// \return OS Tick timer clock frequency in Hz uint32_t OS_Tick_GetClock (void); -/// Get OS Tick interval. -/// \return OS Tick interval. +/// Get OS Tick timer interval reload value +/// \return OS Tick timer interval reload value uint32_t OS_Tick_GetInterval (void); -/// Get OS Tick count value. -/// \return OS Tick count value. +/// Get OS Tick timer counter value +/// \return OS Tick timer counter value uint32_t OS_Tick_GetCount (void); -/// Get OS Tick overflow status. +/// Get OS Tick timer overflow status /// \return OS Tick overflow status (1 - overflow, 0 - no overflow). uint32_t OS_Tick_GetOverflow (void); -/// Get Cortex-A9 OS Timer interrupt number -/// \returns Cortex-A9 OS Timer interrupt number (134) -#if defined(TARGET_CORTEX_A) -IRQn_ID_t mbed_get_a9_tick_irqn(void); -#endif #endif /* OS_TICK_H */ diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.h b/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.h index 4ba2de85ca3..98b7a572e0b 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.h @@ -17,7 +17,7 @@ * * ----------------------------------------------------------------------------- * - * $Revision: V5.3.0 + * $Revision: V5.4.0 * * Project: CMSIS-RTOS RTX * Title: RTX Configuration definitions @@ -40,9 +40,9 @@ // System Configuration // ======================= -// Global Dynamic Memory size [bytes] <0-1073741824:8> -// Defines the combined global dynamic memory size. -// Default: 4096 +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 #ifndef OS_DYNAMIC_MEM_SIZE #define OS_DYNAMIC_MEM_SIZE 4096 #endif @@ -79,67 +79,8 @@ #define OS_ISR_FIFO_QUEUE 16 #endif -// Event Recording -// Configures events recording. - -// Memory Management -// Enables Memory Management events recording. -#ifndef OS_EVR_MEMORY -#define OS_EVR_MEMORY 1 -#endif - -// Kernel -// Enables Kernel events recording. -#ifndef OS_EVR_KERNEL -#define OS_EVR_KERNEL 1 -#endif - -// Thread -// Enables Thread events recording. -#ifndef OS_EVR_THREAD -#define OS_EVR_THREAD 1 -#endif - -// Timer -// Enables Timer events recording. -#ifndef OS_EVR_TIMER -#define OS_EVR_TIMER 1 -#endif - -// Event Flags -// Enables Event Flags events recording. -#ifndef OS_EVR_EVFLAGS -#define OS_EVR_EVFLAGS 1 -#endif - -// Mutex -// Enables Mutex events recording. -#ifndef OS_EVR_MUTEX -#define OS_EVR_MUTEX 1 -#endif - -// Semaphore -// Enables Semaphore events recording. -#ifndef OS_EVR_SEMAPHORE -#define OS_EVR_SEMAPHORE 1 -#endif - -// Memory Pool -// Enables Memory Pool events recording. -#ifndef OS_EVR_MEMPOOL -#define OS_EVR_MEMPOOL 1 -#endif - -// Message Queue -// Enables Message Queue events recording. -#ifndef OS_EVR_MSGQUEUE -#define OS_EVR_MSGQUEUE 1 -#endif - -// - // Object Memory usage counters -// Enables object memory usage counters. +// Enables object memory usage counters (requires RTX source variant). #ifndef OS_OBJ_MEM_USAGE #define OS_OBJ_MEM_USAGE 0 #endif @@ -202,14 +143,14 @@ #endif // Stack overrun checking -// Enable stack overrun checks at thread switch. +// Enables stack overrun check at thread switch. // Enabling this option increases slightly the execution time of a thread switch. #ifndef OS_STACK_CHECK #define OS_STACK_CHECK 1 #endif // Stack usage watermark -// Initialize thread stack with watermark pattern for analyzing stack usage. +// Initializes thread stack with watermark pattern for analyzing stack usage. // Enabling this option increases significantly the execution time of thread creation. #ifndef OS_STACK_WATERMARK #define OS_STACK_WATERMARK 0 @@ -396,6 +337,200 @@ // +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + // Number of Threads which use standard C/C++ library libspace // (when thread specific memory allocation is not used). #if (OS_THREAD_OBJ_MEM == 0) diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_evr.h b/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_evr.h index 456d57e9cfd..9e1dcf633c3 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_evr.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_evr.h @@ -30,6 +30,41 @@ #include "RTX_Config.h" // RTX Configuration #include "rtx_os.h" // RTX OS definitions +#include "RTE_Components.h" + +#ifdef RTE_Compiler_EventRecorder + +#include "EventRecorder.h" +#include "EventRecorderConf.h" + +#if ((defined(OS_EVR_INIT) && (OS_EVR_INIT != 0)) || (EVENT_TIMESTAMP_SOURCE == 2)) +#ifndef EVR_RTX_KERNEL_GET_STATE_DISABLE +#define EVR_RTX_KERNEL_GET_STATE_DISABLE +#endif +#endif + +#if (EVENT_TIMESTAMP_SOURCE == 2) +#ifndef EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE +#define EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE +#endif +#ifndef EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE +#define EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE +#endif +#endif + +/// RTOS component number +#define EvtRtxMemoryNo (0xF0U) +#define EvtRtxKernelNo (0xF1U) +#define EvtRtxThreadNo (0xF2U) +#define EvtRtxTimerNo (0xF3U) +#define EvtRtxEventFlagsNo (0xF4U) +#define EvtRtxMutexNo (0xF5U) +#define EvtRtxSemaphoreNo (0xF6U) +#define EvtRtxMemoryPoolNo (0xF7U) +#define EvtRtxMessageQueueNo (0xF8U) + +#endif // RTE_Compiler_EventRecorder + /// Extended Status codes #define osRtxErrorKernelNotReady (-7) @@ -150,10 +185,10 @@ extern void EvrRtxKernelInitialize (void); /** \brief Event on successful RTOS kernel initialize (Op) */ -#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_COMPLETED_DISABLE)) -extern void EvrRtxKernelInitializeCompleted (void); +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZED_DISABLE)) +extern void EvrRtxKernelInitialized (void); #else -#define EvrRtxKernelInitializeCompleted() +#define EvrRtxKernelInitialized() #endif /** @@ -373,11 +408,12 @@ extern void EvrRtxThreadNew (osThreadFunc_t func, void *argument, const osThread \brief Event on successful thread create (Op) \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. \param[in] thread_addr thread entry address. + \param[in] name pointer to thread object name. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_CREATED_DISABLE)) -extern void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr); +extern void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr, const char *name); #else -#define EvrRtxThreadCreated(thread_id, thread_addr) +#define EvrRtxThreadCreated(thread_id, thread_addr, name) #endif /** @@ -1165,7 +1201,7 @@ extern void EvrRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_PENDING_DISABLE)) extern void EvrRtxMutexAcquirePending (osMutexId_t mutex_id, uint32_t timeout); #else -#define EvrRtxMutexAcquirePending(mutex_id, timeout) +#define EvrRtxMutexAcquirePending(mutex_id, timeout); #endif /** @@ -1318,7 +1354,7 @@ extern void EvrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeo #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_PENDING_DISABLE)) extern void EvrRtxSemaphoreAcquirePending (osSemaphoreId_t semaphore_id, uint32_t timeout); #else -#define EvrRtxSemaphoreAcquirePending(semaphore_id, timeout) +#define EvrRtxSemaphoreAcquirePending(semaphore_id, timeout); #endif /** @@ -1334,11 +1370,12 @@ extern void EvrRtxSemaphoreAcquireTimeout (osSemaphoreId_t semaphore_id); /** \brief Event on successful semaphore acquire (Op) \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] tokens number of available tokens. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE)) -extern void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id); +extern void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id, uint32_t tokens); #else -#define EvrRtxSemaphoreAcquired(semaphore_id) +#define EvrRtxSemaphoreAcquired(semaphore_id, tokens) #endif /** @@ -1364,11 +1401,12 @@ extern void EvrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id); /** \brief Event on successful semaphore release (Op) \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] tokens number of available tokens. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASED_DISABLE)) -extern void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id); +extern void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id, uint32_t tokens); #else -#define EvrRtxSemaphoreReleased(semaphore_id) +#define EvrRtxSemaphoreReleased(semaphore_id, tokens) #endif /** diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_os.h b/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_os.h index d173917c535..e571fa43317 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_os.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_os.h @@ -37,9 +37,9 @@ extern "C" /// Kernel Information -#define osRtxVersionAPI 20010002 ///< API version (2.1.2) -#define osRtxVersionKernel 50030000 ///< Kernel version (5.3.0) -#define osRtxKernelId "RTX V5.3.0" ///< Kernel identification string +#define osRtxVersionAPI 20010003 ///< API version (2.1.3) +#define osRtxVersionKernel 50040000 ///< Kernel version (5.4.0) +#define osRtxKernelId "RTX V5.4.0" ///< Kernel identification string // ==== Common definitions ==== @@ -55,10 +55,6 @@ extern "C" #define osRtxIdMessage 0x07U #define osRtxIdMessageQueue 0x08U -/// Object State definitions (except for Threads and Timers) -#define osRtxObjectInactive 0x00U -#define osRtxObjectActive 0x01U - /// Object Flags definitions #define osRtxFlagSystemObject 0x01U #define osRtxFlagSystemMemory 0x02U @@ -127,7 +123,9 @@ typedef struct osRtxThread_s { uint32_t sp; ///< Current Stack Pointer uint32_t thread_addr; ///< Thread entry address uint32_t tz_memory; ///< TrustZone Memory Identifier - void *context; ///< Context for OsEventObserver objects +#ifdef RTX_TF_M_EXTENSION + uint32_t tz_module; ///< TrustZone Module Identifier +#endif } osRtxThread_t; @@ -167,7 +165,7 @@ typedef struct osRtxTimer_s { /// Event Flags Control Block typedef struct { uint8_t id; ///< Object Identifier - uint8_t state; ///< Object State + uint8_t reserved_state; ///< Object State (not used) uint8_t flags; ///< Object Flags uint8_t reserved; const char *name; ///< Object Name @@ -181,7 +179,7 @@ typedef struct { /// Mutex Control Block typedef struct osRtxMutex_s { uint8_t id; ///< Object Identifier - uint8_t state; ///< Object State + uint8_t reserved_state; ///< Object State (not used) uint8_t flags; ///< Object Flags uint8_t attr; ///< Object Attributes const char *name; ///< Object Name @@ -199,7 +197,7 @@ typedef struct osRtxMutex_s { /// Semaphore Control Block typedef struct { uint8_t id; ///< Object Identifier - uint8_t state; ///< Object State + uint8_t reserved_state; ///< Object State (not used) uint8_t flags; ///< Object Flags uint8_t reserved; const char *name; ///< Object Name @@ -224,7 +222,7 @@ typedef struct { /// Memory Pool Control Block typedef struct { uint8_t id; ///< Object Identifier - uint8_t state; ///< Object State + uint8_t reserved_state; ///< Object State (not used) uint8_t flags; ///< Object Flags uint8_t reserved; const char *name; ///< Object Name @@ -238,7 +236,7 @@ typedef struct { /// Message Control Block typedef struct osRtxMessage_s { uint8_t id; ///< Object Identifier - uint8_t state; ///< Object State + uint8_t reserved_state; ///< Object State (not used) uint8_t flags; ///< Object Flags uint8_t priority; ///< Message Priority struct osRtxMessage_s *prev; ///< Pointer to previous Message @@ -248,7 +246,7 @@ typedef struct osRtxMessage_s { /// Message Queue Control Block typedef struct { uint8_t id; ///< Object Identifier - uint8_t state; ///< Object State + uint8_t reserved_state; ///< Object State (not used) uint8_t flags; ///< Object Flags uint8_t reserved; const char *name; ///< Object Name @@ -411,6 +409,11 @@ extern void SVC_Handler (void); extern void PendSV_Handler (void); extern void SysTick_Handler (void); +/// OS Trusted Firmware M Extension +#ifdef RTX_TF_M_EXTENSION +extern uint32_t osRtxTzGetModuleId (void); +#endif + // ==== OS External Configuration ==== diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M3/irq_cm3.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M3/irq_cm3.S index 0b99b2f3193..95c5c156cf2 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M3/irq_cm3.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M3/irq_cm3.S @@ -77,15 +77,6 @@ SVC_ContextSave: STR R12,[R1,#TCB_SP_OFS] // Store SP SVC_ContextSwitch: - /* The call to thread_switch_helper can clobber R2 and R3, but we don't - * want to clobber R2 or R3. We can't save R2 and R3 to the stack (as - * the stack we save them onto is likely to be inaccessible after the - * call to thread_switch_helper). So, we just re-obtain the values from - * osRtxInfo again. */ - BL thread_switch_helper - LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run - LDM R3,{R1,R2} // Load osRtxInfo.thread.run: curr & next - STR R2,[R3] // osRtxInfo.thread.run: curr = next SVC_ContextRestore: diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S index c027a712607..cd59935afb0 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S @@ -94,15 +94,6 @@ SVC_ContextSave: STRB LR, [R1,#TCB_SF_OFS] // Store stack frame information SVC_ContextSwitch: - /* The call to thread_switch_helper can clobber R2 and R3, but we don't - * want to clobber R2 or R3. We can't save R2 and R3 to the stack (as - * the stack we save them onto is likely to be inaccessible after the - * call to thread_switch_helper). So, we just re-obtain the values from - * osRtxInfo again. */ - BL thread_switch_helper - LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run - LDM R3,{R1,R2} // Load osRtxInfo.thread.run: curr & next - STR R2,[R3] // osRtxInfo.thread.run: curr = next SVC_ContextRestore: diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rt_OsEventObserver.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rt_OsEventObserver.c deleted file mode 100644 index 09c1eed91d0..00000000000 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rt_OsEventObserver.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * Project: CMSIS-RTOS RTX - * Title: OS Event Observer - * - * ----------------------------------------------------------------------------- - */ -#include "rt_OsEventObserver.h" - -const OsEventObserver *osEventObs; - -void osRegisterForOsEvents(const OsEventObserver *observer) -{ - static uint8_t has_been_called = 0; - if (has_been_called) { - return; - } - has_been_called = 1; - - osEventObs = observer; -} diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rt_OsEventObserver.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rt_OsEventObserver.h deleted file mode 100644 index 899f319029f..00000000000 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rt_OsEventObserver.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * Project: CMSIS-RTOS RTX - * Title: OS Event Observer - * - * ----------------------------------------------------------------------------- - */ -#ifndef _RT_OS_EVENT_OBSERVER_H -#define _RT_OS_EVENT_OBSERVER_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - uint32_t version; - void (*pre_start)(void); - void *(*thread_create)(int thread_id, void *context); - void (*thread_destroy)(void *context); - void (*thread_switch)(void *context); -} OsEventObserver; -extern const OsEventObserver *osEventObs; - -void osRegisterForOsEvents(const OsEventObserver *observer); - -#ifdef __cplusplus -}; -#endif - -#endif - -/** @}*/ diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h index c30dac7b506..e367c19276c 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h @@ -728,66 +728,6 @@ __STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) { } #endif -/// atomic Access Operation: Increment (32-bit) if Less Than -/// \param[in] mem Memory address -/// \param[in] max Maximum value -/// \return Previous value -#if defined(__CC_ARM) -static __asm uint32_t atomic_inc32_lt (uint32_t *mem, uint32_t max) { - push {r4,lr} - mov r2,r0 -1 - ldrex r0,[r2] - cmp r1,r0 - bhi %F2 - clrex - pop {r4,pc} -2 - adds r4,r0,#1 - strex r3,r4,[r2] - cmp r3,#0 - bne %B1 - pop {r4,pc} -} -#else -__STATIC_INLINE uint32_t atomic_inc32_lt (uint32_t *mem, uint32_t max) { -#ifdef __ICCARM__ -#pragma diag_suppress=Pe550 -#endif - register uint32_t val, res; -#ifdef __ICCARM__ -#pragma diag_default=Pe550 -#endif - register uint32_t ret; - - __ASM volatile ( -#ifndef __ICCARM__ - ".syntax unified\n\t" -#endif - "1:\n\t" - "ldrex %[ret],[%[mem]]\n\t" - "cmp %[max],%[ret]\n\t" - "bhi 2f\n\t" - "clrex\n\t" - "b 3f\n" - "2:\n\t" - "adds %[val],%[ret],#1\n\t" - "strex %[res],%[val],[%[mem]]\n\t" - "cmp %[res],#0\n\t" - "bne 1b\n" - "3:" - : [ret] "=&l" (ret), - [val] "=&l" (val), - [res] "=&l" (res) - : [mem] "l" (mem), - [max] "l" (max) - : "cc", "memory" - ); - - return ret; -} -#endif - /// Atomic Access Operation: Increment (16-bit) if Less Than /// \param[in] mem Memory address /// \param[in] max Maximum value @@ -905,6 +845,52 @@ __STATIC_INLINE uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) { } #endif +/// Atomic Access Operation: Decrement (32-bit) +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_dec32 (uint32_t *mem) { + mov r2,r0 +1 + ldrex r0,[r2] + subs r1,r0,#1 + strex r3,r1,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_dec32 (uint32_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "subs %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + /// Atomic Access Operation: Decrement (32-bit) if Not Zero /// \param[in] mem Memory address /// \return Previous value diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_cm.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_cm.h index a04aefd9606..04eb86964fb 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_cm.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_cm.h @@ -802,67 +802,6 @@ __STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) { } #endif -/// atomic Access Operation: Increment (32-bit) if Less Than -/// \param[in] mem Memory address -/// \param[in] max Maximum value -/// \return Previous value -#if defined(__CC_ARM) -static __asm uint32_t atomic_inc32_lt (uint32_t *mem, uint32_t max) { - push {r4,lr} - mov r2,r0 -1 - ldrex r0,[r2] - cmp r1,r0 - bhi %F2 - clrex - pop {r4,pc} -2 - adds r4,r0,#1 - strex r3,r4,[r2] - cbz r3,%F3 - b %B1 -3 - pop {r4,pc} -} -#else -__STATIC_INLINE uint32_t atomic_inc32_lt (uint32_t *mem, uint32_t max) { -#ifdef __ICCARM__ -#pragma diag_suppress=Pe550 -#endif - register uint32_t val, res; -#ifdef __ICCARM__ -#pragma diag_default=Pe550 -#endif - register uint32_t ret; - - __ASM volatile ( -#ifndef __ICCARM__ - ".syntax unified\n\t" -#endif - "1:\n\t" - "ldrex %[ret],[%[mem]]\n\t" - "cmp %[max],%[ret]\n\t" - "bhi 2f\n\t" - "clrex\n\t" - "b 3f\n" - "2:\n\t" - "adds %[val],%[ret],#1\n\t" - "strex %[res],%[val],[%[mem]]\n\t" - "cbz %[res],3f\n\t" - "b 1b\n" - "3:" - : [ret] "=&l" (ret), - [val] "=&l" (val), - [res] "=&l" (res) - : [mem] "l" (mem), - [max] "l" (max) - : "cc", "memory" - ); - - return ret; -} -#endif - /// Atomic Access Operation: Increment (16-bit) if Less Than /// \param[in] mem Memory address /// \param[in] max Maximum value @@ -983,6 +922,54 @@ __STATIC_INLINE uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) { } #endif +/// Atomic Access Operation: Decrement (32-bit) +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_dec32 (uint32_t *mem) { + mov r2,r0 +1 + ldrex r0,[r2] + subs r1,r0,#1 + strex r3,r1,[r2] + cbz r3,%F2 + b %B1 +2 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_dec32 (uint32_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "subs %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cbz %[res],2f\n\t" + "b 1b\n" + "2:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + /// Atomic Access Operation: Decrement (32-bit) if Not Zero /// \param[in] mem Memory address /// \return Previous value diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_delay.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_delay.c index ada82ac6f35..7eb30f67b10 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_delay.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_delay.c @@ -46,16 +46,14 @@ static osStatus_t svcRtxDelay (uint32_t ticks) { static osStatus_t svcRtxDelayUntil (uint32_t ticks) { ticks -= osRtxInfo.kernel.tick; - if (ticks == 0xFFFFFFFFU) { + if ((ticks == 0U) || (ticks > 0x7FFFFFFFU)) { EvrRtxThreadError(NULL, (int32_t)osErrorParameter); //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorParameter; } - if (ticks != 0U) { - if (!osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks)) { - EvrRtxThreadDelayCompleted(); - } + if (!osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks)) { + EvrRtxThreadDelayCompleted(); } return osOK; diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evflags.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evflags.c index e02560a4224..fcd79057efd 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evflags.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evflags.c @@ -143,11 +143,6 @@ static void osRtxEventFlagsPostProcess (os_event_flags_t *ef) { os_thread_t *thread_next; uint32_t event_flags; - if (ef->state == osRtxObjectInactive) { - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return; - } - // Check if Threads are waiting for Event Flags thread = ef->thread_list; while (thread != NULL) { @@ -223,7 +218,6 @@ static osEventFlagsId_t svcRtxEventFlagsNew (const osEventFlagsAttr_t *attr) { if (ef != NULL) { // Initialize control block ef->id = osRtxIdEventFlags; - ef->state = osRtxObjectActive; ef->flags = flags; ef->name = name; ef->thread_list = NULL; @@ -252,13 +246,6 @@ static const char *svcRtxEventFlagsGetName (osEventFlagsId_t ef_id) { return NULL; } - // Check object state - if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsGetName(ef, NULL); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return NULL; - } - EvrRtxEventFlagsGetName(ef, ef->name); return ef->name; @@ -281,13 +268,6 @@ static uint32_t svcRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { return ((uint32_t)osErrorParameter); } - // Check object state - if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsError(ef, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return ((uint32_t)osErrorResource); - } - // Set Event Flags event_flags = EventFlagsSet(ef, flags); @@ -329,13 +309,6 @@ static uint32_t svcRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) { return ((uint32_t)osErrorParameter); } - // Check object state - if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsError(ef, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return ((uint32_t)osErrorResource); - } - // Clear Event Flags event_flags = EventFlagsClear(ef, flags); @@ -356,13 +329,6 @@ static uint32_t svcRtxEventFlagsGet (osEventFlagsId_t ef_id) { return 0U; } - // Check object state - if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsGet(ef, 0U); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return 0U; - } - EvrRtxEventFlagsGet(ef, ef->event_flags); return ef->event_flags; @@ -391,13 +357,6 @@ static uint32_t svcRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, ui return ((uint32_t)osErrorParameter); } - // Check object state - if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsError(ef, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return ((uint32_t)osErrorResource); - } - // Check Event Flags event_flags = EventFlagsCheck(ef, flags, options); if (event_flags != 0U) { @@ -438,16 +397,6 @@ static osStatus_t svcRtxEventFlagsDelete (osEventFlagsId_t ef_id) { return osErrorParameter; } - // Check object state - if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsError(ef, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - - // Mark object as inactive - ef->state = osRtxObjectInactive; - // Unblock waiting threads if (ef->thread_list != NULL) { do { @@ -457,6 +406,9 @@ static osStatus_t svcRtxEventFlagsDelete (osEventFlagsId_t ef_id) { osRtxThreadDispatch(NULL); } + // Mark object as invalid + ef->id = osRtxIdInvalid; + // Free object memory if ((ef->flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.event_flags != NULL) { @@ -503,13 +455,6 @@ uint32_t isrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { return ((uint32_t)osErrorParameter); } - // Check object state - if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsError(ef, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return ((uint32_t)osErrorResource); - } - // Set Event Flags event_flags = EventFlagsSet(ef, flags); @@ -536,13 +481,6 @@ uint32_t isrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t return ((uint32_t)osErrorParameter); } - // Check object state - if (ef->state == osRtxObjectInactive) { - EvrRtxEventFlagsError(ef, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return ((uint32_t)osErrorResource); - } - // Check Event Flags event_flags = EventFlagsCheck(ef, flags, options); if (event_flags != 0U) { diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evr.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evr.c index 4148efa5bf0..beb885fc22f 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evr.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evr.c @@ -27,27 +27,10 @@ #include "cmsis_compiler.h" #include "rtx_evr.h" // RTX Event Recorder definitions -#ifndef RTE_COMPONENTS_H -#include "RTE_Components.h" -#endif - #ifdef RTE_Compiler_EventRecorder //lint -e923 -e9074 -e9078 -emacro((835,845),EventID) [MISRA Note 13] -#include "EventRecorder.h" // Keil::Compiler:Event Recorder - -/// RTOS component number -#define EvtRtxMemoryNo (0xF0U) -#define EvtRtxKernelNo (0xF1U) -#define EvtRtxThreadNo (0xF2U) -#define EvtRtxTimerNo (0xF3U) -#define EvtRtxEventFlagsNo (0xF4U) -#define EvtRtxMutexNo (0xF5U) -#define EvtRtxSemaphoreNo (0xF6U) -#define EvtRtxMemoryPoolNo (0xF7U) -#define EvtRtxMessageQueueNo (0xF8U) - /// Event IDs for "RTX Memory Management" #define EvtRtxMemoryInit EventID(EventLevelOp, EvtRtxMemoryNo, 0x00U) #define EvtRtxMemoryAlloc EventID(EventLevelOp, EvtRtxMemoryNo, 0x01U) @@ -59,10 +42,9 @@ /// Event IDs for "RTX Kernel" #define EvtRtxKernelError EventID(EventLevelError, EvtRtxKernelNo, 0x00U) #define EvtRtxKernelInitialize EventID(EventLevelAPI, EvtRtxKernelNo, 0x01U) -#define EvtRtxKernelInitializeCompleted EventID(EventLevelOp, EvtRtxKernelNo, 0x02U) +#define EvtRtxKernelInitialized EventID(EventLevelOp, EvtRtxKernelNo, 0x02U) #define EvtRtxKernelGetInfo EventID(EventLevelAPI, EvtRtxKernelNo, 0x03U) #define EvtRtxKernelInfoRetrieved EventID(EventLevelOp, EvtRtxKernelNo, 0x04U) -#define EvtRtxKernelInfoRetrieved_Detail EventID(EventLevelDetail, EvtRtxKernelNo, 0x05U) #define EvtRtxKernelGetState EventID(EventLevelAPI, EvtRtxKernelNo, 0x06U) #define EvtRtxKernelStart EventID(EventLevelAPI, EvtRtxKernelNo, 0x07U) #define EvtRtxKernelStarted EventID(EventLevelOp, EvtRtxKernelNo, 0x08U) @@ -85,9 +67,9 @@ #define EvtRtxThreadError EventID(EventLevelError, EvtRtxThreadNo, 0x00U) #define EvtRtxThreadNew EventID(EventLevelAPI, EvtRtxThreadNo, 0x01U) #define EvtRtxThreadNew_Detail EventID(EventLevelDetail, EvtRtxThreadNo, 0x02U) -#define EvtRtxThreadCreated EventID(EventLevelOp, EvtRtxThreadNo, 0x03U) +#define EvtRtxThreadCreated_Addr EventID(EventLevelOp, EvtRtxThreadNo, 0x03U) +#define EvtRtxThreadCreated_Name EventID(EventLevelOp, EvtRtxThreadNo, 0x2CU) #define EvtRtxThreadGetName EventID(EventLevelAPI, EvtRtxThreadNo, 0x04U) -#define EvtRtxThreadGetName_Detail EventID(EventLevelDetail, EvtRtxThreadNo, 0x05U) #define EvtRtxThreadGetId EventID(EventLevelAPI, EvtRtxThreadNo, 0x06U) #define EvtRtxThreadGetState EventID(EventLevelAPI, EvtRtxThreadNo, 0x07U) #define EvtRtxThreadGetStackSize EventID(EventLevelAPI, EvtRtxThreadNo, 0x08U) @@ -134,7 +116,6 @@ #define EvtRtxTimerNew_Detail EventID(EventLevelDetail, EvtRtxTimerNo, 0x03U) #define EvtRtxTimerCreated EventID(EventLevelOp, EvtRtxTimerNo, 0x04U) #define EvtRtxTimerGetName EventID(EventLevelAPI, EvtRtxTimerNo, 0x05U) -#define EvtRtxTimerGetName_Detail EventID(EventLevelDetail, EvtRtxTimerNo, 0x06U) #define EvtRtxTimerStart EventID(EventLevelAPI, EvtRtxTimerNo, 0x07U) #define EvtRtxTimerStarted EventID(EventLevelOp, EvtRtxTimerNo, 0x08U) #define EvtRtxTimerStop EventID(EventLevelAPI, EvtRtxTimerNo, 0x09U) @@ -149,7 +130,6 @@ #define EvtRtxEventFlagsNew_Detail EventID(EventLevelDetail, EvtRtxEventFlagsNo, 0x02U) #define EvtRtxEventFlagsCreated EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x03U) #define EvtRtxEventFlagsGetName EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x04U) -#define EvtRtxEventFlagsGetName_Detail EventID(EventLevelDetail, EvtRtxEventFlagsNo, 0x05U) #define EvtRtxEventFlagsSet EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x06U) #define EvtRtxEventFlagsSetDone EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x07U) #define EvtRtxEventFlagsClear EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x08U) @@ -169,10 +149,9 @@ #define EvtRtxMutexNew_Detail EventID(EventLevelDetail, EvtRtxMutexNo, 0x02U) #define EvtRtxMutexCreated EventID(EventLevelOp, EvtRtxMutexNo, 0x03U) #define EvtRtxMutexGetName EventID(EventLevelAPI, EvtRtxMutexNo, 0x04U) -#define EvtRtxMutexGetName_Detail EventID(EventLevelDetail, EvtRtxMutexNo, 0x05U) #define EvtRtxMutexAcquire EventID(EventLevelAPI, EvtRtxMutexNo, 0x06U) -#define EvtRtxMutexAcquirePending EventID(EventLevelError, EvtRtxMutexNo, 0x07U) -#define EvtRtxMutexAcquireTimeout EventID(EventLevelError, EvtRtxMutexNo, 0x08U) +#define EvtRtxMutexAcquirePending EventID(EventLevelOp, EvtRtxMutexNo, 0x07U) +#define EvtRtxMutexAcquireTimeout EventID(EventLevelOp, EvtRtxMutexNo, 0x08U) #define EvtRtxMutexAcquired EventID(EventLevelOp, EvtRtxMutexNo, 0x09U) #define EvtRtxMutexNotAcquired EventID(EventLevelOp, EvtRtxMutexNo, 0x0AU) #define EvtRtxMutexRelease EventID(EventLevelAPI, EvtRtxMutexNo, 0x0BU) @@ -187,7 +166,6 @@ #define EvtRtxSemaphoreNew_Detail EventID(EventLevelDetail, EvtRtxSemaphoreNo, 0x02U) #define EvtRtxSemaphoreCreated EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x03U) #define EvtRtxSemaphoreGetName EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x04U) -#define EvtRtxSemaphoreGetName_Detail EventID(EventLevelDetail, EvtRtxSemaphoreNo, 0x05U) #define EvtRtxSemaphoreAcquire EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x06U) #define EvtRtxSemaphoreAcquirePending EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x07U) #define EvtRtxSemaphoreAcquireTimeout EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x08U) @@ -205,7 +183,6 @@ #define EvtRtxMemoryPoolNew_Detail EventID(EventLevelDetail, EvtRtxMemoryPoolNo, 0x02U) #define EvtRtxMemoryPoolCreated EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x03U) #define EvtRtxMemoryPoolGetName EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x04U) -#define EvtRtxMemoryPoolGetName_Detail EventID(EventLevelDetail, EvtRtxMemoryPoolNo, 0x05U) #define EvtRtxMemoryPoolAlloc EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x06U) #define EvtRtxMemoryPoolAllocPending EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x07U) #define EvtRtxMemoryPoolAllocTimeout EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x08U) @@ -227,7 +204,6 @@ #define EvtRtxMessageQueueNew_Detail EventID(EventLevelDetail, EvtRtxMessageQueueNo, 0x02U) #define EvtRtxMessageQueueCreated EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x03U) #define EvtRtxMessageQueueGetName EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x04U) -#define EvtRtxMessageQueueGetName_Detail EventID(EventLevelDetail, EvtRtxMessageQueueNo, 0x05U) #define EvtRtxMessageQueuePut EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x06U) #define EvtRtxMessageQueuePutPending EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x07U) #define EvtRtxMessageQueuePutTimeout EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x08U) @@ -350,10 +326,10 @@ __WEAK void EvrRtxKernelInitialize (void) { } #endif -#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_COMPLETED_DISABLE)) -__WEAK void EvrRtxKernelInitializeCompleted (void) { +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZED_DISABLE)) +__WEAK void EvrRtxKernelInitialized (void) { #if defined(RTE_Compiler_EventRecorder) - (void)EventRecord2(EvtRtxKernelInitializeCompleted, 0U, 0U); + (void)EventRecord2(EvtRtxKernelInitialized, 0U, 0U); #else #endif } @@ -374,10 +350,7 @@ __WEAK void EvrRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE)) __WEAK void EvrRtxKernelInfoRetrieved (osVersion_t *version, char *id_buf) { #if defined(RTE_Compiler_EventRecorder) - (void)EventRecord2(EvtRtxKernelInfoRetrieved, (uint32_t)version, (uint32_t)id_buf); - if (id_buf != NULL) { - (void)EventRecordData(EvtRtxKernelInfoRetrieved_Detail, id_buf, strlen(id_buf)); - } + (void)EventRecord4(EvtRtxKernelInfoRetrieved, (uint32_t)version->api, (uint32_t)version->kernel, (uint32_t)id_buf, 0U); #else (void)version; (void)id_buf; @@ -579,12 +552,17 @@ __WEAK void EvrRtxThreadNew (osThreadFunc_t func, void *argument, const osThread #endif #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_CREATED_DISABLE)) -__WEAK void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr) { +__WEAK void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr, const char *name) { #if defined(RTE_Compiler_EventRecorder) - (void)EventRecord2(EvtRtxThreadCreated, (uint32_t)thread_id, thread_addr); + if (name != NULL) { + (void)EventRecord2(EvtRtxThreadCreated_Name, (uint32_t)thread_id, (uint32_t)name); + } else { + (void)EventRecord2(EvtRtxThreadCreated_Addr, (uint32_t)thread_id, thread_addr); + } #else (void)thread_id; (void)thread_addr; + (void)name; #endif } #endif @@ -593,9 +571,6 @@ __WEAK void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr) { __WEAK void EvrRtxThreadGetName (osThreadId_t thread_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) (void)EventRecord2(EvtRtxThreadGetName, (uint32_t)thread_id, (uint32_t)name); - if (name != NULL) { - (void)EventRecordData(EvtRtxThreadGetName_Detail, name, strlen(name)); - } #else (void)thread_id; (void)name; @@ -1051,9 +1026,6 @@ __WEAK void EvrRtxTimerCreated (osTimerId_t timer_id, const char *name) { __WEAK void EvrRtxTimerGetName (osTimerId_t timer_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) (void)EventRecord2(EvtRtxTimerGetName, (uint32_t)timer_id, (uint32_t)name); - if (name != NULL) { - (void)EventRecordData(EvtRtxTimerGetName_Detail, name, strlen(name)); - } #else (void)timer_id; (void)name; @@ -1175,9 +1147,6 @@ __WEAK void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id, const char *name) { __WEAK void EvrRtxEventFlagsGetName (osEventFlagsId_t ef_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) (void)EventRecord2(EvtRtxEventFlagsGetName, (uint32_t)ef_id, (uint32_t)name); - if (name != NULL) { - (void)EventRecordData(EvtRtxEventFlagsGetName_Detail, name, strlen(name)); - } #else (void)ef_id; (void)name; @@ -1363,9 +1332,6 @@ __WEAK void EvrRtxMutexCreated (osMutexId_t mutex_id, const char *name) { __WEAK void EvrRtxMutexGetName (osMutexId_t mutex_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) (void)EventRecord2(EvtRtxMutexGetName, (uint32_t)mutex_id, (uint32_t)name); - if (name != NULL) { - (void)EventRecordData(EvtRtxMutexGetName_Detail, name, strlen(name)); - } #else (void)mutex_id; (void)name; @@ -1522,9 +1488,6 @@ __WEAK void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id, const char *na __WEAK void EvrRtxSemaphoreGetName (osSemaphoreId_t semaphore_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) (void)EventRecord2(EvtRtxSemaphoreGetName, (uint32_t)semaphore_id, (uint32_t)name); - if (name != NULL) { - (void)EventRecordData(EvtRtxSemaphoreGetName_Detail, name, strlen(name)); - } #else #endif (void)semaphore_id; @@ -1565,11 +1528,12 @@ __WEAK void EvrRtxSemaphoreAcquireTimeout (osSemaphoreId_t semaphore_id) { #endif #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE)) -__WEAK void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id) { +__WEAK void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id, uint32_t tokens) { #if defined(RTE_Compiler_EventRecorder) - (void)EventRecord2(EvtRtxSemaphoreAcquired, (uint32_t)semaphore_id, 0U); + (void)EventRecord2(EvtRtxSemaphoreAcquired, (uint32_t)semaphore_id, tokens); #else (void)semaphore_id; + (void)tokens; #endif } #endif @@ -1595,11 +1559,12 @@ __WEAK void EvrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) { #endif #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASED_DISABLE)) -__WEAK void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id) { +__WEAK void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id, uint32_t tokens) { #if defined(RTE_Compiler_EventRecorder) - (void)EventRecord2(EvtRtxSemaphoreReleased, (uint32_t)semaphore_id, 0U); + (void)EventRecord2(EvtRtxSemaphoreReleased, (uint32_t)semaphore_id, tokens); #else (void)semaphore_id; + (void)tokens; #endif } #endif @@ -1679,9 +1644,6 @@ __WEAK void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id, const char *name) { __WEAK void EvrRtxMemoryPoolGetName (osMemoryPoolId_t mp_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) (void)EventRecord2(EvtRtxMemoryPoolGetName, (uint32_t)mp_id, (uint32_t)name); - if (name != NULL) { - (void)EventRecordData(EvtRtxMemoryPoolGetName_Detail, name, strlen(name)); - } #else (void)mp_id; (void)name; @@ -1883,9 +1845,6 @@ __WEAK void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id, const char *nam __WEAK void EvrRtxMessageQueueGetName (osMessageQueueId_t mq_id, const char *name) { #if defined(RTE_Compiler_EventRecorder) (void)EventRecord2(EvtRtxMessageQueueGetName, (uint32_t)mq_id, (uint32_t)name); - if (name != NULL) { - (void)EventRecordData(EvtRtxMessageQueueGetName_Detail, name, strlen(name)); - } #else (void)mq_id; (void)name; diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_kernel.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_kernel.c index 685ae5c73f7..2d8b6c3cc67 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_kernel.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_kernel.c @@ -24,7 +24,6 @@ */ #include "rtx_lib.h" -#include "rt_OsEventObserver.h" // OS Runtime Information @@ -71,7 +70,7 @@ static void KernelUnblock (void) { static osStatus_t svcRtxKernelInitialize (void) { if (osRtxInfo.kernel.state == osRtxKernelReady) { - EvrRtxKernelInitializeCompleted(); + EvrRtxKernelInitialized(); //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osOK; } @@ -198,7 +197,7 @@ static osStatus_t svcRtxKernelInitialize (void) { osRtxInfo.kernel.state = osRtxKernelReady; - EvrRtxKernelInitializeCompleted(); + EvrRtxKernelInitialized(); return osOK; } @@ -293,7 +292,7 @@ static osStatus_t svcRtxKernelStart (void) { /// Lock the RTOS Kernel scheduler. /// \note API identical to osKernelLock -int32_t svcRtxKernelLock (void) { +static int32_t svcRtxKernelLock (void) { int32_t lock; switch (osRtxInfo.kernel.state) { @@ -313,10 +312,10 @@ int32_t svcRtxKernelLock (void) { } return lock; } - + /// Unlock the RTOS Kernel scheduler. /// \note API identical to osKernelUnlock -int32_t svcRtxKernelUnlock (void) { +static int32_t svcRtxKernelUnlock (void) { int32_t lock; switch (osRtxInfo.kernel.state) { @@ -431,7 +430,7 @@ static void svcRtxKernelResume (uint32_t sleep_ticks) { thread->delay = 1U; do { osRtxThreadDelayTick(); - if (delay == 0U) { + if (delay == 0U) { break; } delay--; @@ -529,12 +528,23 @@ SVC0_0 (KernelGetSysTimerFreq, uint32_t) //lint --flb "Library End" +// ==== Library functions ==== + +/// RTOS Kernel Pre-Initialization Hook +//lint -esym(759,osRtxKernelPreInit) "Prototype in header" +//lint -esym(765,osRtxKernelPreInit) "Global scope (can be overridden)" +//lint -esym(522,osRtxKernelPreInit) "Can be overridden (do not lack side-effects)" +__WEAK void osRtxKernelPreInit (void) { +} + + // ==== Public API ==== /// Initialize the RTOS Kernel. osStatus_t osKernelInitialize (void) { osStatus_t status; + osRtxKernelPreInit(); EvrRtxKernelInitialize(); if (IsIrqMode() || IsIrqMasked()) { EvrRtxKernelError((int32_t)osErrorISR); @@ -550,7 +560,7 @@ osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size osStatus_t status; EvrRtxKernelGetInfo(version, id_buf, id_size); - if (IsPrivileged() || IsIrqMode() || IsIrqMasked()) { + if (IsIrqMode() || IsIrqMasked() || IsPrivileged()) { status = svcRtxKernelGetInfo(version, id_buf, id_size); } else { status = __svcKernelGetInfo(version, id_buf, id_size); @@ -562,7 +572,7 @@ osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size osKernelState_t osKernelGetState (void) { osKernelState_t state; - if (IsPrivileged() || IsIrqMode() || IsIrqMasked()) { + if (IsIrqMode() || IsIrqMasked() || IsPrivileged()) { state = svcRtxKernelGetState(); } else { state = __svcKernelGetState(); @@ -579,13 +589,6 @@ osStatus_t osKernelStart (void) { EvrRtxKernelError((int32_t)osErrorISR); status = osErrorISR; } else { - /* Call the pre-start event (from unprivileged mode) if the handler exists - * and the kernel is not running. */ - /* FIXME osEventObs needs to be readable but not writable from unprivileged - * code. */ - if (osKernelGetState() != osKernelRunning && osEventObs && osEventObs->pre_start) { - osEventObs->pre_start(); - } status = __svcKernelStart(); } return status; @@ -604,7 +607,7 @@ int32_t osKernelLock (void) { } return lock; } - + /// Unlock the RTOS Kernel scheduler. int32_t osKernelUnlock (void) { int32_t lock; diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.c index 58f67f375cb..8fe704f80eb 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.c @@ -27,6 +27,12 @@ #include "RTX_Config.h" #include "rtx_os.h" +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#include "EventRecorderConf.h" +#endif +#include "rtx_evr.h" + // System Configuration // ==================== @@ -106,8 +112,8 @@ __attribute__((section(".bss.os.thread.stack"))); // Stack overrun checking #if (OS_STACK_CHECK == 0) // Override library function -void osRtxThreadStackCheck (void); -void osRtxThreadStackCheck (void) {} +extern void osRtxThreadStackCheck (void); + void osRtxThreadStackCheck (void) {} #endif @@ -219,7 +225,7 @@ static const osMessageQueueAttr_t os_timer_mq_attr = { #else extern void osRtxTimerThread (void *argument); - void osRtxTimerThread (void *argument) {} + void osRtxTimerThread (void *argument) { (void)argument; } #endif // ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0)) @@ -347,6 +353,55 @@ __attribute__((section(".bss.os.msgqueue.mem"))); #endif // (OS_MSGQUEUE_OBJ_MEM != 0) +// Event Recorder Configuration +// ============================ + +#if (defined(OS_EVR_INIT) && (OS_EVR_INIT != 0)) + +#if defined(RTE_Compiler_EventRecorder) + +// Event Recorder Initialize +__STATIC_INLINE void evr_initialize (void) { + + (void)EventRecorderInitialize(OS_EVR_LEVEL, (uint32_t)OS_EVR_START); + +#if ((OS_EVR_MEMORY_FILTER & 0x80U) != 0U) + (void)EventRecorderEnable(OS_EVR_MEMORY_FILTER & 0x0FU, EvtRtxMemoryNo, EvtRtxMemoryNo); +#endif +#if ((OS_EVR_KERNEL_FILTER & 0x80U) != 0U) + (void)EventRecorderEnable(OS_EVR_KERNEL_FILTER & 0x0FU, EvtRtxKernelNo, EvtRtxKernelNo); +#endif +#if ((OS_EVR_THREAD_FILTER & 0x80U) != 0U) + (void)EventRecorderEnable(OS_EVR_THREAD_FILTER & 0x0FU, EvtRtxThreadNo, EvtRtxThreadNo); +#endif +#if ((OS_EVR_TIMER_FILTER & 0x80U) != 0U) + (void)EventRecorderEnable(OS_EVR_TIMER_FILTER & 0x0FU, EvtRtxTimerNo, EvtRtxTimerNo); +#endif +#if ((OS_EVR_EVFLAGS_FILTER & 0x80U) != 0U) + (void)EventRecorderEnable(OS_EVR_EVFLAGS_FILTER & 0x0FU, EvtRtxEventFlagsNo, EvtRtxEventFlagsNo); +#endif +#if ((OS_EVR_MUTEX_FILTER & 0x80U) != 0U) + (void)EventRecorderEnable(OS_EVR_MUTEX_FILTER & 0x0FU, EvtRtxMutexNo, EvtRtxMutexNo); +#endif +#if ((OS_EVR_SEMAPHORE_FILTER & 0x80U) != 0U) + (void)EventRecorderEnable(OS_EVR_SEMAPHORE_FILTER & 0x0FU, EvtRtxSemaphoreNo, EvtRtxSemaphoreNo); +#endif +#if ((OS_EVR_MEMPOOL_FILTER & 0x80U) != 0U) + (void)EventRecorderEnable(OS_EVR_MEMPOOL_FILTER & 0x0FU, EvtRtxMemoryPoolNo, EvtRtxMemoryPoolNo); +#endif +#if ((OS_EVR_MSGQUEUE_FILTER & 0x80U) != 0U) + (void)EventRecorderEnable(OS_EVR_MSGQUEUE_FILTER & 0x0FU, EvtRtxMessageQueueNo, EvtRtxMessageQueueNo); +#endif +} + +#else +#warning "Event Recorder cannot be initialized (Event Recorder component is not selected)!" +#define evr_initialize() +#endif + +#endif // (OS_EVR_INIT != 0) + + // OS Configuration // ================ @@ -607,6 +662,20 @@ __WEAK void software_init_hook (void) { #endif +// OS Hooks +// ======== + +// RTOS Kernel Pre-Initialization Hook +void osRtxKernelPreInit (void); +void osRtxKernelPreInit (void) { +#if (defined(OS_EVR_INIT) && (OS_EVR_INIT != 0)) + if (osKernelGetState() == osKernelInactive) { + evr_initialize(); + } +#endif +} + + // C/C++ Standard Library Multithreading Interface // =============================================== diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.h index 1fd876c1489..cd223ed13be 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.h @@ -173,6 +173,9 @@ __STATIC_INLINE void osRtxThreadSetRunning (os_thread_t *thread) { // ==== Library functions ==== +// Kernel Library functions +extern void osRtxKernelPreInit (void); + // Thread Library functions extern void osRtxThreadListPut (os_object_t *object, os_thread_t *thread); extern os_thread_t *osRtxThreadListGet (os_object_t *object); diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mempool.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mempool.c index 849b156d14c..f7a18723d27 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mempool.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mempool.c @@ -93,25 +93,20 @@ void *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info) { #if (EXCLUSIVE_ACCESS == 0) __disable_irq(); - if (mp_info->used_blocks < mp_info->max_blocks) { + block = mp_info->block_free; + if (block != NULL) { + //lint --e{9079} --e{9087} "conversion from pointer to void to pointer to other type" + mp_info->block_free = *((void **)block); mp_info->used_blocks++; - block = mp_info->block_free; - if (block != NULL) { - //lint --e{9079} --e{9087} "conversion from pointer to void to pointer to other type" - mp_info->block_free = *((void **)block); - } - } else { - block = NULL; } if (primask == 0U) { __enable_irq(); } #else - if (atomic_inc32_lt(&mp_info->used_blocks, mp_info->max_blocks) < mp_info->max_blocks) { - block = atomic_link_get(&mp_info->block_free); - } else { - block = NULL; + block = atomic_link_get(&mp_info->block_free); + if (block != NULL) { + (void)atomic_inc32(&mp_info->used_blocks); } #endif @@ -128,7 +123,6 @@ osStatus_t osRtxMemoryPoolFree (os_mp_info_t *mp_info, void *block) { #if (EXCLUSIVE_ACCESS == 0) uint32_t primask = __get_PRIMASK(); #endif - osStatus_t status; //lint -e{946} "Relational operator applied to pointers" if ((mp_info == NULL) || (block < mp_info->block_base) || (block >= mp_info->block_lim)) { @@ -140,31 +134,22 @@ osStatus_t osRtxMemoryPoolFree (os_mp_info_t *mp_info, void *block) { #if (EXCLUSIVE_ACCESS == 0) __disable_irq(); - if (mp_info->used_blocks != 0U) { - mp_info->used_blocks--; - //lint --e{9079} --e{9087} "conversion from pointer to void to pointer to other type" - *((void **)block) = mp_info->block_free; - mp_info->block_free = block; - status = osOK; - } else { - status = osErrorResource; - } + //lint --e{9079} --e{9087} "conversion from pointer to void to pointer to other type" + *((void **)block) = mp_info->block_free; + mp_info->block_free = block; + mp_info->used_blocks--; if (primask == 0U) { __enable_irq(); } #else - if (atomic_dec32_nz(&mp_info->used_blocks) != 0U) { - atomic_link_put(&mp_info->block_free, block); - status = osOK; - } else { - status = osErrorResource; - } + atomic_link_put(&mp_info->block_free, block); + (void)atomic_dec32(&mp_info->used_blocks); #endif - EvrRtxMemoryBlockFree(mp_info, block, (int32_t)status); + EvrRtxMemoryBlockFree(mp_info, block, (int32_t)osOK); - return status; + return osOK; } @@ -176,11 +161,6 @@ static void osRtxMemoryPoolPostProcess (os_memory_pool_t *mp) { void *block; os_thread_t *thread; - if (mp->state == osRtxObjectInactive) { - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return; - } - // Check if Thread is waiting to allocate memory if (mp->thread_list != NULL) { // Allocate memory @@ -317,7 +297,6 @@ static osMemoryPoolId_t svcRtxMemoryPoolNew (uint32_t block_count, uint32_t bloc if (mp != NULL) { // Initialize control block mp->id = osRtxIdMemoryPool; - mp->state = osRtxObjectActive; mp->flags = flags; mp->name = name; mp->thread_list = NULL; @@ -346,13 +325,6 @@ static const char *svcRtxMemoryPoolGetName (osMemoryPoolId_t mp_id) { return NULL; } - // Check object state - if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolGetName(mp, NULL); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return NULL; - } - EvrRtxMemoryPoolGetName(mp, mp->name); return mp->name; @@ -371,13 +343,6 @@ static void *svcRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { return NULL; } - // Check object state - if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolError(mp, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return NULL; - } - // Allocate memory block = osRtxMemoryPoolAlloc(&mp->mp_info); if (block != NULL) { @@ -415,13 +380,6 @@ static osStatus_t svcRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { return osErrorParameter; } - // Check object state - if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolError(mp, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - // Free memory status = osRtxMemoryPoolFree(&mp->mp_info, block); if (status == osOK) { @@ -457,13 +415,6 @@ static uint32_t svcRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) { return 0U; } - // Check object state - if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolGetCapacity(mp, 0U); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return 0U; - } - EvrRtxMemoryPoolGetCapacity(mp, mp->mp_info.max_blocks); return mp->mp_info.max_blocks; @@ -481,13 +432,6 @@ static uint32_t svcRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) { return 0U; } - // Check object state - if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolGetBlockSize(mp, 0U); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return 0U; - } - EvrRtxMemoryPoolGetBlockSize(mp, mp->mp_info.block_size); return mp->mp_info.block_size; @@ -505,13 +449,6 @@ static uint32_t svcRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id) { return 0U; } - // Check object state - if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolGetCount(mp, 0U); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return 0U; - } - EvrRtxMemoryPoolGetCount(mp, mp->mp_info.used_blocks); return mp->mp_info.used_blocks; @@ -529,13 +466,6 @@ static uint32_t svcRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id) { return 0U; } - // Check object state - if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolGetSpace(mp, 0U); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return 0U; - } - EvrRtxMemoryPoolGetSpace(mp, mp->mp_info.max_blocks - mp->mp_info.used_blocks); return (mp->mp_info.max_blocks - mp->mp_info.used_blocks); @@ -554,16 +484,6 @@ static osStatus_t svcRtxMemoryPoolDelete (osMemoryPoolId_t mp_id) { return osErrorParameter; } - // Check object state - if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolError(mp, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - - // Mark object as inactive - mp->state = osRtxObjectInactive; - // Unblock waiting threads if (mp->thread_list != NULL) { do { @@ -573,6 +493,9 @@ static osStatus_t svcRtxMemoryPoolDelete (osMemoryPoolId_t mp_id) { osRtxThreadDispatch(NULL); } + // Mark object as invalid + mp->id = osRtxIdInvalid; + // Free data memory if ((mp->flags & osRtxFlagSystemMemory) != 0U) { (void)osRtxMemoryFree(osRtxInfo.mem.mp_data, mp->mp_info.block_base); @@ -625,13 +548,6 @@ void *isrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { return NULL; } - // Check object state - if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolError(mp, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return NULL; - } - // Allocate memory block = osRtxMemoryPoolAlloc(&mp->mp_info); if (block == NULL) { @@ -657,13 +573,6 @@ osStatus_t isrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { return osErrorParameter; } - // Check object state - if (mp->state == osRtxObjectInactive) { - EvrRtxMemoryPoolError(mp, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - // Free memory status = osRtxMemoryPoolFree(&mp->mp_info, block); if (status == osOK) { diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_msgqueue.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_msgqueue.c index 9fbffdb824b..0e3531ad060 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_msgqueue.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_msgqueue.c @@ -168,22 +168,13 @@ static void osRtxMessageQueuePostProcess (os_message_t *msg) { const void *ptr_src; void *ptr_dst; - if (msg->state == osRtxObjectInactive) { - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return; - } - if (msg->flags != 0U) { // Remove Message //lint -e{9079} -e{9087} "cast between pointers to different object types" mq = *((os_message_queue_t **)(void *)&msg[1]); - if (mq->state == osRtxObjectInactive) { - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return; - } MessageQueueRemove(mq, msg); // Free memory - msg->state = osRtxObjectInactive; + msg->id = osRtxIdInvalid; (void)osRtxMemoryPoolFree(&mq->mp_info, msg); // Check if Thread is waiting to send a Message if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessagePut)) { @@ -201,7 +192,6 @@ static void osRtxMessageQueuePostProcess (os_message_t *msg) { memcpy(&msg0[1], ptr_src, mq->msg_size); // Store Message into Queue msg0->id = osRtxIdMessage; - msg0->state = osRtxObjectActive; msg0->flags = 0U; msg0->priority = (uint8_t)reg[3]; MessageQueuePut(mq, msg0); @@ -212,10 +202,6 @@ static void osRtxMessageQueuePostProcess (os_message_t *msg) { // New Message //lint -e{9079} -e{9087} "cast between pointers to different object types" mq = (void *)msg->next; - if (mq->state == osRtxObjectInactive) { - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return; - } //lint -e{9087} "cast between pointers to different object types" ptr_src = (const void *)msg->prev; // Check if Thread is waiting to receive a Message @@ -235,7 +221,7 @@ static void osRtxMessageQueuePostProcess (os_message_t *msg) { } EvrRtxMessageQueueRetrieved(mq, ptr_dst); // Free memory - msg->state = osRtxObjectInactive; + msg->id = osRtxIdInvalid; (void)osRtxMemoryPoolFree(&mq->mp_info, msg); } else { EvrRtxMessageQueueInserted(mq, ptr_src); @@ -364,7 +350,6 @@ static osMessageQueueId_t svcRtxMessageQueueNew (uint32_t msg_count, uint32_t ms if (mq != NULL) { // Initialize control block mq->id = osRtxIdMessageQueue; - mq->state = osRtxObjectActive; mq->flags = flags; mq->name = name; mq->thread_list = NULL; @@ -397,13 +382,6 @@ static const char *svcRtxMessageQueueGetName (osMessageQueueId_t mq_id) { return NULL; } - // Check object state - if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueGetName(mq, NULL); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return NULL; - } - EvrRtxMessageQueueGetName(mq, mq->name); return mq->name; @@ -426,13 +404,6 @@ static osStatus_t svcRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *m return osErrorParameter; } - // Check object state - if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueError(mq, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - // Check if Thread is waiting to receive a Message if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessageGet)) { EvrRtxMessageQueueInserted(mq, msg_ptr); @@ -459,7 +430,6 @@ static osStatus_t svcRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *m memcpy(&msg[1], msg_ptr, mq->msg_size); // Put Message into Queue msg->id = osRtxIdMessage; - msg->state = osRtxObjectActive; msg->flags = 0U; msg->priority = msg_prio; MessageQueuePut(mq, msg); @@ -510,13 +480,6 @@ static osStatus_t svcRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr return osErrorParameter; } - // Check object state - if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueError(mq, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - // Get Message from Queue msg = MessageQueueGet(mq); if (msg != NULL) { @@ -528,7 +491,7 @@ static osStatus_t svcRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr } EvrRtxMessageQueueRetrieved(mq, msg_ptr); // Free memory - msg->state = osRtxObjectInactive; + msg->id = osRtxIdInvalid; (void)osRtxMemoryPoolFree(&mq->mp_info, msg); // Check if Thread is waiting to send a Message if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessagePut)) { @@ -546,7 +509,6 @@ static osStatus_t svcRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr memcpy(&msg[1], ptr, mq->msg_size); // Store Message into Queue msg->id = osRtxIdMessage; - msg->state = osRtxObjectActive; msg->flags = 0U; msg->priority = (uint8_t)reg[3]; MessageQueuePut(mq, msg); @@ -593,13 +555,6 @@ static uint32_t svcRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id) { return 0U; } - // Check object state - if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueGetCapacity(mq, 0U); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return 0U; - } - EvrRtxMessageQueueGetCapacity(mq, mq->mp_info.max_blocks); return mq->mp_info.max_blocks; @@ -617,13 +572,6 @@ static uint32_t svcRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id) { return 0U; } - // Check object state - if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueGetMsgSize(mq, 0U); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return 0U; - } - EvrRtxMessageQueueGetMsgSize(mq, mq->msg_size); return mq->msg_size; @@ -641,13 +589,6 @@ static uint32_t svcRtxMessageQueueGetCount (osMessageQueueId_t mq_id) { return 0U; } - // Check object state - if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueGetCount(mq, 0U); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return 0U; - } - EvrRtxMessageQueueGetCount(mq, mq->msg_count); return mq->msg_count; @@ -665,13 +606,6 @@ static uint32_t svcRtxMessageQueueGetSpace (osMessageQueueId_t mq_id) { return 0U; } - // Check object state - if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueGetSpace(mq, 0U); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return 0U; - } - EvrRtxMessageQueueGetSpace(mq, mq->mp_info.max_blocks - mq->msg_count); return (mq->mp_info.max_blocks - mq->msg_count); @@ -693,13 +627,6 @@ static osStatus_t svcRtxMessageQueueReset (osMessageQueueId_t mq_id) { return osErrorParameter; } - // Check object state - if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueError(mq, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - // Remove Messages from Queue for (;;) { // Get Message from Queue @@ -710,7 +637,7 @@ static osStatus_t svcRtxMessageQueueReset (osMessageQueueId_t mq_id) { MessageQueueRemove(mq, msg); EvrRtxMessageQueueRetrieved(mq, NULL); // Free memory - msg->state = osRtxObjectInactive; + msg->id = osRtxIdInvalid; (void)osRtxMemoryPoolFree(&mq->mp_info, msg); } @@ -731,7 +658,6 @@ static osStatus_t svcRtxMessageQueueReset (osMessageQueueId_t mq_id) { memcpy(&msg[1], ptr, mq->msg_size); // Store Message into Queue msg->id = osRtxIdMessage; - msg->state = osRtxObjectActive; msg->flags = 0U; msg->priority = (uint8_t)reg[3]; MessageQueuePut(mq, msg); @@ -759,16 +685,6 @@ static osStatus_t svcRtxMessageQueueDelete (osMessageQueueId_t mq_id) { return osErrorParameter; } - // Check object state - if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueError(mq, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - - // Mark object as inactive - mq->state = osRtxObjectInactive; - // Unblock waiting threads if (mq->thread_list != NULL) { do { @@ -778,6 +694,9 @@ static osStatus_t svcRtxMessageQueueDelete (osMessageQueueId_t mq_id) { osRtxThreadDispatch(NULL); } + // Mark object as invalid + mq->id = osRtxIdInvalid; + // Free data memory if ((mq->flags & osRtxFlagSystemMemory) != 0U) { (void)osRtxMemoryFree(osRtxInfo.mem.mq_data, mq->mp_info.block_base); @@ -832,13 +751,6 @@ osStatus_t isrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, return osErrorParameter; } - // Check object state - if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueError(mq, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - // Try to allocate memory //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] msg = osRtxMemoryPoolAlloc(&mq->mp_info); @@ -846,7 +758,6 @@ osStatus_t isrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, // Copy Message memcpy(&msg[1], msg_ptr, mq->msg_size); msg->id = osRtxIdMessage; - msg->state = osRtxObjectActive; msg->flags = 0U; msg->priority = msg_prio; // Register post ISR processing @@ -881,13 +792,6 @@ osStatus_t isrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8 return osErrorParameter; } - // Check object state - if (mq->state == osRtxObjectInactive) { - EvrRtxMessageQueueError(mq, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - // Get Message from Queue msg = MessageQueueGet(mq); if (msg != NULL) { diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mutex.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mutex.c index 609d4f42b66..43a7b7ce3ae 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mutex.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mutex.c @@ -134,7 +134,6 @@ static osMutexId_t svcRtxMutexNew (const osMutexAttr_t *attr) { if (mutex != NULL) { // Initialize control block mutex->id = osRtxIdMutex; - mutex->state = osRtxObjectActive; mutex->flags = flags; mutex->attr = (uint8_t)attr_bits; mutex->name = name; @@ -164,13 +163,6 @@ static const char *svcRtxMutexGetName (osMutexId_t mutex_id) { return NULL; } - // Check object state - if (mutex->state == osRtxObjectInactive) { - EvrRtxMutexGetName(mutex, NULL); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return NULL; - } - EvrRtxMutexGetName(mutex, mutex->name); return mutex->name; @@ -198,13 +190,6 @@ static osStatus_t svcRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { return osErrorParameter; } - // Check object state - if (mutex->state == osRtxObjectInactive) { - EvrRtxMutexError(mutex, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - // Check if Mutex is not locked if (mutex->lock == 0U) { // Acquire Mutex @@ -283,9 +268,9 @@ static osStatus_t svcRtxMutexRelease (osMutexId_t mutex_id) { return osErrorParameter; } - // Check object state - if (mutex->state == osRtxObjectInactive) { - EvrRtxMutexError(mutex, (int32_t)osErrorResource); + // Check if Mutex is not locked + if (mutex->lock == 0U) { + EvrRtxMutexError(mutex, osRtxErrorMutexNotLocked); //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; } @@ -297,13 +282,6 @@ static osStatus_t svcRtxMutexRelease (osMutexId_t mutex_id) { return osErrorResource; } - // Check if Mutex is not locked - if (mutex->lock == 0U) { - EvrRtxMutexError(mutex, osRtxErrorMutexNotLocked); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - // Decrement Lock counter mutex->lock--; EvrRtxMutexReleased(mutex, mutex->lock); @@ -368,13 +346,6 @@ static osThreadId_t svcRtxMutexGetOwner (osMutexId_t mutex_id) { return NULL; } - // Check object state - if (mutex->state == osRtxObjectInactive) { - EvrRtxMutexGetOwner(mutex, NULL); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return NULL; - } - // Check if Mutex is not locked if (mutex->lock == 0U) { EvrRtxMutexGetOwner(mutex, NULL); @@ -402,16 +373,6 @@ static osStatus_t svcRtxMutexDelete (osMutexId_t mutex_id) { return osErrorParameter; } - // Check object state - if (mutex->state == osRtxObjectInactive) { - EvrRtxMutexError(mutex, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - - // Mark object as inactive - mutex->state = osRtxObjectInactive; - // Check if Mutex is locked if (mutex->lock != 0U) { @@ -456,6 +417,9 @@ static osStatus_t svcRtxMutexDelete (osMutexId_t mutex_id) { osRtxThreadDispatch(NULL); } + // Mark object as invalid + mutex->id = osRtxIdInvalid; + // Free object memory if ((mutex->flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.mutex != NULL) { diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_semaphore.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_semaphore.c index a1f8d4c9a4b..ebca85543c0 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_semaphore.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_semaphore.c @@ -110,11 +110,6 @@ static uint32_t SemaphoreTokenIncrement (os_semaphore_t *semaphore) { static void osRtxSemaphorePostProcess (os_semaphore_t *semaphore) { os_thread_t *thread; - if (semaphore->state == osRtxObjectInactive) { - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return; - } - // Check if Thread is waiting for a token if (semaphore->thread_list != NULL) { // Try to acquire token @@ -122,7 +117,7 @@ static void osRtxSemaphorePostProcess (os_semaphore_t *semaphore) { // Wakeup waiting Thread with highest Priority thread = osRtxThreadListGet(osRtxObject(semaphore)); osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE); - EvrRtxSemaphoreAcquired(semaphore); + EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens); } } } @@ -195,7 +190,6 @@ static osSemaphoreId_t svcRtxSemaphoreNew (uint32_t max_count, uint32_t initial_ if (semaphore != NULL) { // Initialize control block semaphore->id = osRtxIdSemaphore; - semaphore->state = osRtxObjectActive; semaphore->flags = flags; semaphore->name = name; semaphore->thread_list = NULL; @@ -225,13 +219,6 @@ static const char *svcRtxSemaphoreGetName (osSemaphoreId_t semaphore_id) { return NULL; } - // Check object state - if (semaphore->state == osRtxObjectInactive) { - EvrRtxSemaphoreGetName(semaphore, NULL); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return NULL; - } - EvrRtxSemaphoreGetName(semaphore, semaphore->name); return semaphore->name; @@ -250,16 +237,9 @@ static osStatus_t svcRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t return osErrorParameter; } - // Check object state - if (semaphore->state == osRtxObjectInactive) { - EvrRtxSemaphoreError(semaphore, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - // Try to acquire token if (SemaphoreTokenDecrement(semaphore) != 0U) { - EvrRtxSemaphoreAcquired(semaphore); + EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens); status = osOK; } else { // No token available @@ -295,25 +275,18 @@ static osStatus_t svcRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) { return osErrorParameter; } - // Check object state - if (semaphore->state == osRtxObjectInactive) { - EvrRtxSemaphoreError(semaphore, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - // Check if Thread is waiting for a token if (semaphore->thread_list != NULL) { - EvrRtxSemaphoreReleased(semaphore); + EvrRtxSemaphoreReleased(semaphore, semaphore->tokens); // Wakeup waiting Thread with highest Priority thread = osRtxThreadListGet(osRtxObject(semaphore)); osRtxThreadWaitExit(thread, (uint32_t)osOK, TRUE); - EvrRtxSemaphoreAcquired(semaphore); + EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens); status = osOK; } else { // Try to release token if (SemaphoreTokenIncrement(semaphore) != 0U) { - EvrRtxSemaphoreReleased(semaphore); + EvrRtxSemaphoreReleased(semaphore, semaphore->tokens); status = osOK; } else { EvrRtxSemaphoreError(semaphore, osRtxErrorSemaphoreCountLimit); @@ -336,13 +309,6 @@ static uint32_t svcRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id) { return 0U; } - // Check object state - if (semaphore->state == osRtxObjectInactive) { - EvrRtxSemaphoreGetCount(semaphore, 0U); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return 0U; - } - EvrRtxSemaphoreGetCount(semaphore, semaphore->tokens); return semaphore->tokens; @@ -361,16 +327,6 @@ static osStatus_t svcRtxSemaphoreDelete (osSemaphoreId_t semaphore_id) { return osErrorParameter; } - // Check object state - if (semaphore->state == osRtxObjectInactive) { - EvrRtxSemaphoreError(semaphore, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - - // Mark object as inactive - semaphore->state = osRtxObjectInactive; - // Unblock waiting threads if (semaphore->thread_list != NULL) { do { @@ -380,6 +336,9 @@ static osStatus_t svcRtxSemaphoreDelete (osSemaphoreId_t semaphore_id) { osRtxThreadDispatch(NULL); } + // Mark object as invalid + semaphore->id = osRtxIdInvalid; + // Free object memory if ((semaphore->flags & osRtxFlagSystemObject) != 0U) { if (osRtxInfo.mpi.semaphore != NULL) { @@ -424,16 +383,9 @@ osStatus_t isrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeou return osErrorParameter; } - // Check object state - if (semaphore->state == osRtxObjectInactive) { - EvrRtxSemaphoreError(semaphore, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - // Try to acquire token if (SemaphoreTokenDecrement(semaphore) != 0U) { - EvrRtxSemaphoreAcquired(semaphore); + EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens); status = osOK; } else { // No token available @@ -458,18 +410,11 @@ osStatus_t isrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) { return osErrorParameter; } - // Check object state - if (semaphore->state == osRtxObjectInactive) { - EvrRtxSemaphoreError(semaphore, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - // Try to release token if (SemaphoreTokenIncrement(semaphore) != 0U) { // Register post ISR processing osRtxPostProcess(osRtxObject(semaphore)); - EvrRtxSemaphoreReleased(semaphore); + EvrRtxSemaphoreReleased(semaphore, semaphore->tokens); status = osOK; } else { EvrRtxSemaphoreError(semaphore, osRtxErrorSemaphoreCountLimit); diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_thread.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_thread.c index 56b0b8637a4..a82bfc5c263 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_thread.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_thread.c @@ -24,7 +24,7 @@ */ #include "rtx_lib.h" -#include "rt_OsEventObserver.h" + // OS Runtime Object Memory Usage #if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) @@ -151,7 +151,7 @@ void osRtxThreadListPut (os_object_t *object, os_thread_t *thread) { priority = thread->priority; prev = osRtxThreadObject(object); - next = object->thread_list; + next = prev->thread_next; while ((next != NULL) && (next->priority >= priority)) { prev = next; next = next->thread_next; @@ -166,7 +166,7 @@ void osRtxThreadListPut (os_object_t *object, os_thread_t *thread) { /// Get a Thread with Highest Priority from specified Object list and remove it. /// \param[in] object generic object. -/// \return thread object. +/// \return thread object. os_thread_t *osRtxThreadListGet (os_object_t *object) { os_thread_t *thread; @@ -182,9 +182,16 @@ os_thread_t *osRtxThreadListGet (os_object_t *object) { return thread; } +#if (!defined(EVR_RTX_DISABLE) && \ + (((OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_TIMEOUT_DISABLE)) || \ + ((OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_TIMEOUT_DISABLE)) || \ + ((OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_TIMEOUT_DISABLE)) || \ + ((OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_TIMEOUT_DISABLE)) || \ + ((OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_TIMEOUT_DISABLE)) || \ + ((OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_TIMEOUT_DISABLE)))) + /// Retrieve Thread list root. /// \param[in] thread thread object. -#ifndef EVR_RTX_DISABLE static void *osRtxThreadListRoot (os_thread_t *thread) { os_thread_t *thread0; @@ -194,6 +201,7 @@ static void *osRtxThreadListRoot (os_thread_t *thread) { } return thread0; } + #endif /// Re-sort a Thread in linked Object list by Priority (Highest at Head). @@ -426,17 +434,6 @@ void osRtxThreadSwitch (os_thread_t *thread) { osRtxInfo.thread.run.next = thread; osRtxThreadStackCheck(); EvrRtxThreadSwitched(thread); - - if (osEventObs && osEventObs->thread_switch) { - osEventObs->thread_switch(thread->context); - } -} - -/// Notify the OS event observer of an imminent thread switch. -void thread_switch_helper(void) { - if (osEventObs && osEventObs->thread_switch) { - osEventObs->thread_switch(osRtxInfo.thread.run.next->context); - } } /// Dispatch specified Thread or Ready Thread with Highest Priority. @@ -546,6 +543,24 @@ __WEAK void osRtxThreadStackCheck (void) { } } +#ifdef RTX_TF_M_EXTENSION +/// Get TrustZone Module Identifier of running Thread. +/// \return TrustZone Module Identifier. +uint32_t osRtxTzGetModuleId (void) { + os_thread_t *thread; + uint32_t tz_module; + + thread = osRtxThreadGetRunning(); + if (thread != NULL) { + tz_module = thread->tz_module; + } else { + tz_module = 0U; + } + + return tz_module; +} +#endif + // ==== Post ISR processing ==== @@ -554,13 +569,6 @@ __WEAK void osRtxThreadStackCheck (void) { static void osRtxThreadPostProcess (os_thread_t *thread) { uint32_t thread_flags; - // Check thread state - if ((thread->state == osRtxThreadInactive) || - (thread->state == osRtxThreadTerminated)) { - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return; - } - // Check if Thread is waiting for Thread Flags if (thread->state == osRtxThreadWaitingThreadFlags) { thread_flags = ThreadFlagsCheck(thread, thread->wait_flags, thread->flags_options); @@ -575,8 +583,8 @@ static void osRtxThreadPostProcess (os_thread_t *thread) { // ==== Service Calls ==== /// Create a thread and add it to Active Threads. -/// \note API identical to osThreadContextNew -osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr, void *context) { +/// \note API identical to osThreadNew +static osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { os_thread_t *thread; uint32_t attr_bits; void *stack_mem; @@ -778,6 +786,9 @@ osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThrea thread->thread_addr = (uint32_t)func; #if (DOMAIN_NS == 1) thread->tz_memory = tz_memory; + #ifdef RTX_TF_M_EXTENSION + thread->tz_module = tz_module; + #endif #endif // Initialize stack @@ -805,18 +816,11 @@ osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThrea // Register post ISR processing function osRtxInfo.post_process.thread = osRtxThreadPostProcess; - EvrRtxThreadCreated(thread, thread->thread_addr); + EvrRtxThreadCreated(thread, thread->thread_addr, thread->name); } else { EvrRtxThreadError(NULL, (int32_t)osErrorNoMemory); } - - /* Notify the OS event observer of a new thread. */ - if (osEventObs && osEventObs->thread_create) { - thread->context = osEventObs->thread_create((int)thread, context); - } else { - thread->context = context; - } - + if (thread != NULL) { osRtxThreadDispatch(thread); } @@ -836,13 +840,6 @@ static const char *svcRtxThreadGetName (osThreadId_t thread_id) { return NULL; } - // Check object state - if (thread->state == osRtxObjectInactive) { - EvrRtxThreadGetName(thread, NULL); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return NULL; - } - EvrRtxThreadGetName(thread, thread->name); return thread->name; @@ -890,13 +887,6 @@ static uint32_t svcRtxThreadGetStackSize (osThreadId_t thread_id) { return 0U; } - // Check object state - if (thread->state == osRtxObjectInactive) { - EvrRtxThreadGetStackSize(thread, 0U); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return 0U; - } - EvrRtxThreadGetStackSize(thread, thread->stack_size); return thread->stack_size; @@ -916,13 +906,6 @@ static uint32_t svcRtxThreadGetStackSpace (osThreadId_t thread_id) { return 0U; } - // Check object state - if (thread->state == osRtxObjectInactive) { - EvrRtxThreadGetStackSpace(thread, 0U); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return 0U; - } - // Check if stack watermark is not enabled if ((osRtxConfig.flags & osRtxConfigStackWatermark) == 0U) { EvrRtxThreadGetStackSpace(thread, 0U); @@ -961,8 +944,7 @@ static osStatus_t svcRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t } // Check object state - if ((thread->state == osRtxThreadInactive) || - (thread->state == osRtxThreadTerminated)) { + if (thread->state == osRtxThreadTerminated) { EvrRtxThreadError(thread, (int32_t)osErrorResource); //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; @@ -992,8 +974,7 @@ static osPriority_t svcRtxThreadGetPriority (osThreadId_t thread_id) { } // Check object state - if ((thread->state == osRtxThreadInactive) || - (thread->state == osRtxThreadTerminated)) { + if (thread->state == osRtxThreadTerminated) { EvrRtxThreadGetPriority(thread, osPriorityError); //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osPriorityError; @@ -1119,8 +1100,9 @@ static osStatus_t svcRtxThreadResume (osThreadId_t thread_id) { /// \param[in] thread thread object. static void osRtxThreadFree (os_thread_t *thread) { - // Mark object as inactive + // Mark object as inactive and invalid thread->state = osRtxThreadInactive; + thread->id = osRtxIdInvalid; #if (DOMAIN_NS == 1) // Free secure process stack @@ -1170,13 +1152,6 @@ static osStatus_t svcRtxThreadDetach (osThreadId_t thread_id) { return osErrorResource; } - // Check object state - if (thread->state == osRtxThreadInactive) { - EvrRtxThreadError(thread, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } - if (thread->state == osRtxThreadTerminated) { osRtxThreadListUnlink(&osRtxInfo.thread.terminate_list, thread); osRtxThreadFree(thread); @@ -1210,8 +1185,7 @@ static osStatus_t svcRtxThreadJoin (osThreadId_t thread_id) { } // Check object state - if ((thread->state == osRtxThreadInactive) || - (thread->state == osRtxThreadRunning)) { + if (thread->state == osRtxThreadRunning) { EvrRtxThreadError(thread, (int32_t)osErrorResource); //lint -e{904} "Return statement before end of function" [MISRA Note 1] return osErrorResource; @@ -1326,10 +1300,6 @@ static osStatus_t svcRtxThreadTerminate (osThreadId_t thread_id) { break; } - if (osEventObs && osEventObs->thread_destroy) { - osEventObs->thread_destroy(thread->context); - } - if (status == osOK) { // Release owned Mutexes osRtxMutexOwnerRelease(thread->mutex_list); @@ -1463,8 +1433,7 @@ static uint32_t svcRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { } // Check object state - if ((thread->state == osRtxThreadInactive) || - (thread->state == osRtxThreadTerminated)) { + if (thread->state == osRtxThreadTerminated) { EvrRtxThreadError(thread, (int32_t)osErrorResource); //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorResource); @@ -1513,14 +1482,6 @@ static uint32_t svcRtxThreadFlagsClear (uint32_t flags) { return ((uint32_t)osErrorParameter); } - // Check object state - if ((thread->state == osRtxThreadInactive) || - (thread->state == osRtxThreadTerminated)) { - EvrRtxThreadError(thread, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return ((uint32_t)osErrorResource); - } - // Clear Thread Flags thread_flags = ThreadFlagsClear(thread, flags); @@ -1542,14 +1503,6 @@ static uint32_t svcRtxThreadFlagsGet (void) { return 0U; } - // Check object state - if ((thread->state == osRtxThreadInactive) || - (thread->state == osRtxThreadTerminated)) { - EvrRtxThreadFlagsGet(0U); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return 0U; - } - EvrRtxThreadFlagsGet(thread->thread_flags); return thread->thread_flags; @@ -1602,7 +1555,7 @@ static uint32_t svcRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_ // Service Calls definitions //lint ++flb "Library Begin" [MISRA Note 11] -SVC0_4 (ThreadNew, osThreadId_t, osThreadFunc_t, void *, const osThreadAttr_t *, void *) +SVC0_3 (ThreadNew, osThreadId_t, osThreadFunc_t, void *, const osThreadAttr_t *) SVC0_1 (ThreadGetName, const char *, osThreadId_t) SVC0_0 (ThreadGetId, osThreadId_t) SVC0_1 (ThreadGetState, osThreadState_t, osThreadId_t) @@ -1644,8 +1597,7 @@ uint32_t isrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { } // Check object state - if ((thread->state == osRtxThreadInactive) || - (thread->state == osRtxThreadTerminated)) { + if (thread->state == osRtxThreadTerminated) { EvrRtxThreadError(thread, (int32_t)osErrorResource); //lint -e{904} "Return statement before end of function" [MISRA Note 1] return ((uint32_t)osErrorResource); @@ -1673,7 +1625,7 @@ bool_t osRtxThreadStartup (void) { // Create Idle Thread if (osRtxInfo.thread.idle == NULL) { osRtxInfo.thread.idle = osRtxThreadId( - svcRtxThreadNew(osRtxIdleThread, NULL, osRtxConfig.idle_thread_attr, NULL) + svcRtxThreadNew(osRtxIdleThread, NULL, osRtxConfig.idle_thread_attr) ); if (osRtxInfo.thread.idle == NULL) { ret = FALSE; @@ -1684,7 +1636,7 @@ bool_t osRtxThreadStartup (void) { if (osRtxConfig.timer_mq_mcnt != 0U) { if (osRtxInfo.timer.thread == NULL) { osRtxInfo.timer.thread = osRtxThreadId( - svcRtxThreadNew(osRtxTimerThread, NULL, osRtxConfig.timer_thread_attr, NULL) + svcRtxThreadNew(osRtxTimerThread, NULL, osRtxConfig.timer_thread_attr) ); if (osRtxInfo.timer.thread == NULL) { ret = FALSE; @@ -1700,17 +1652,14 @@ bool_t osRtxThreadStartup (void) { /// Create a thread and add it to Active Threads. osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { - return osThreadContextNew(func, argument, attr, NULL); -} - -osThreadId_t osThreadContextNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr, void *context) { osThreadId_t thread_id; + EvrRtxThreadNew(func, argument, attr); if (IsIrqMode() || IsIrqMasked()) { EvrRtxThreadError(NULL, (int32_t)osErrorISR); thread_id = NULL; } else { - thread_id = __svcThreadNew(func, argument, attr, context); + thread_id = __svcThreadNew(func, argument, attr); } return thread_id; } @@ -1733,10 +1682,9 @@ osThreadId_t osThreadGetId (void) { osThreadId_t thread_id; if (IsIrqMode() || IsIrqMasked()) { - EvrRtxThreadGetId(NULL); - thread_id = NULL; + thread_id = svcRtxThreadGetId(); } else { - thread_id = __svcThreadGetId(); + thread_id = __svcThreadGetId(); } return thread_id; } diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_timer.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_timer.c index 450123fedc0..d7932a85120 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_timer.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_timer.c @@ -240,13 +240,6 @@ static const char *svcRtxTimerGetName (osTimerId_t timer_id) { return NULL; } - // Check object state - if (timer->state == osRtxObjectInactive) { - EvrRtxTimerGetName(timer, NULL); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return NULL; - } - EvrRtxTimerGetName(timer, timer->name); return timer->name; @@ -264,12 +257,6 @@ static osStatus_t svcRtxTimerStart (osTimerId_t timer_id, uint32_t ticks) { return osErrorParameter; } - // Check object state - if (timer->state == osRtxTimerInactive) { - EvrRtxTimerError(timer, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } if (timer->state == osRtxTimerRunning) { TimerRemove(timer); } else { @@ -331,7 +318,6 @@ static uint32_t svcRtxTimerIsRunning (osTimerId_t timer_id) { return 0U; } - // Check object state if (timer->state == osRtxTimerRunning) { EvrRtxTimerIsRunning(timer, 1U); is_running = 1U; @@ -355,18 +341,13 @@ static osStatus_t svcRtxTimerDelete (osTimerId_t timer_id) { return osErrorParameter; } - // Check object state - if (timer->state == osRtxTimerInactive) { - EvrRtxTimerError(timer, (int32_t)osErrorResource); - //lint -e{904} "Return statement before end of function" [MISRA Note 1] - return osErrorResource; - } if (timer->state == osRtxTimerRunning) { TimerRemove(timer); } - // Mark object as inactive + // Mark object as inactive and invalid timer->state = osRtxTimerInactive; + timer->id = osRtxIdInvalid; // Free object memory if ((timer->flags & osRtxFlagSystemObject) != 0U) { diff --git a/rtos/TARGET_CORTEX/rtx5/Source/os_tick_ptim.c b/rtos/TARGET_CORTEX/rtx5/Source/os_tick_ptim.c index ae216ebd4ad..e75ac3a3b00 100644 --- a/rtos/TARGET_CORTEX/rtx5/Source/os_tick_ptim.c +++ b/rtos/TARGET_CORTEX/rtx5/Source/os_tick_ptim.c @@ -1,11 +1,11 @@ /**************************************************************************//** * @file os_tick_ptim.c * @brief CMSIS OS Tick implementation for Private Timer - * @version V1.0.1 - * @date 24. November 2017 + * @version V1.0.2 + * @date 02. March 2018 ******************************************************************************/ /* - * Copyright (c) 2017 ARM Limited. All rights reserved. + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.c index f5c0031c2f3..88c242710fa 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.c @@ -67,30 +67,30 @@ #define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) #define MCG_S_IREFST_VAL ((MCG->S & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT) #define MCG_S_PLLST_VAL ((MCG->S & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT) -#define MCG_C1_FRDIV_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C1) & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT) -#define MCG_C2_LP_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT) -#define MCG_C2_RANGE_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT) -#define MCG_SC_FCRDIV_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT) +#define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT) +#define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT) +#define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT) +#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT) #define MCG_S2_PLLCST_VAL ((MCG->S2 & MCG_S2_PLLCST_MASK) >> MCG_S2_PLLCST_SHIFT) -#define MCG_C7_OSCSEL_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C7) & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT) +#define MCG_C7_OSCSEL_VAL ((MCG->C7 & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT) #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT) #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT) -#define MCG_C7_PLL32KREFSEL_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C7) & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT) -#define MCG_C5_PLLREFSEL0_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C5) & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) +#define MCG_C7_PLL32KREFSEL_VAL ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT) +#define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) #define MCG_C11_PRDIV1_VAL ((MCG->C11 & MCG_C11_PRDIV1_MASK) >> MCG_C11_PRDIV1_SHIFT) #define MCG_C12_VDIV1_VAL ((MCG->C12 & MCG_C12_VDIV1_MASK) >> MCG_C12_VDIV1_SHIFT) -#define MCG_C5_PRDIV0_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C5) & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT) -#define MCG_C6_VDIV0_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C6) & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT) +#define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT) +#define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT) #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK) -#define SIM_CLKDIV1_OUTDIV1_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) -#define SIM_CLKDIV1_OUTDIV2_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) -#define SIM_CLKDIV1_OUTDIV3_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT) -#define SIM_CLKDIV1_OUTDIV4_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) -#define SIM_SOPT1_OSC32KSEL_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->SOPT1) & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT) -#define SIM_SOPT2_PLLFLLSEL_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->SOPT2) & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT) +#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) +#define SIM_CLKDIV1_OUTDIV2_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) +#define SIM_CLKDIV1_OUTDIV3_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT) +#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) +#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT) +#define SIM_SOPT2_PLLFLLSEL_VAL ((SIM->SOPT2 & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT) /* MCG_S_CLKST definition. */ enum _mcg_clkout_stat @@ -491,8 +491,7 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) void CLOCK_SetSimConfig(sim_clock_config_t const *config) { - __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV1, config->clkdiv1); - + SIM->CLKDIV1 = config->clkdiv1; CLOCK_SetPllFllSelClock(config->pllFllSel); CLOCK_SetEr32kClock(config->er32kSrc); } @@ -505,30 +504,30 @@ bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) if (kCLOCK_UsbSrcExt == src) { - __FSL_CLOCK_SECURE_BITS_CLEAR(&SIM->SOPT2, SIM_SOPT2_USBSRC_MASK); + SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; } else { switch (freq) { case 120000000U: - __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1)); + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1); break; case 96000000U: - __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0)); + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0); break; case 72000000U: - __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1)); + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1); break; case 48000000U: - __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0)); + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0); break; default: ret = false; break; } - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK, (uint32_t)src); + SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src); } CLOCK_EnableClock(kCLOCK_Usbfs0); @@ -575,7 +574,7 @@ uint32_t CLOCK_GetFllFreq(void) uint32_t freq; /* If FLL is not enabled currently, then return 0U. */ - if ((__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) + if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) { return 0U; } @@ -596,7 +595,7 @@ uint32_t CLOCK_GetFllFreq(void) uint32_t CLOCK_GetInternalRefClkFreq(void) { /* If MCGIRCLK is gated. */ - if (!(__FSL_CLOCK_SECURE_READ(&MCG->C1) & MCG_C1_IRCLKEN_MASK)) + if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK)) { return 0U; } @@ -666,10 +665,10 @@ status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel) needDelay = false; } - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C7, MCG_C7_OSCSEL_MASK, MCG_C7_OSCSEL(oscsel)); + MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel); if (kMCG_OscselOsc == oscsel) { - if (__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_EREFS_MASK) + if (MCG->C2 & MCG_C2_EREFS_MASK) { while (!(MCG->S & MCG_S_OSCINIT0_MASK)) { @@ -712,20 +711,20 @@ status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, if (fcrdiv != curFcrdiv) { /* If fast IRC is in use currently, change to slow IRC. */ - if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (__FSL_CLOCK_SECURE_READ(&MCG->C1) & MCG_C1_IRCLKEN_MASK))) + if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCLKEN_MASK))) { - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C2, MCG_C2_IRCS_MASK, MCG_C2_IRCS(kMCG_IrcSlow)); + MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); while (MCG_S_IRCST_VAL != kMCG_IrcSlow) { } } /* Update FCRDIV. */ - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->SC, MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK, MCG_SC_FCRDIV(fcrdiv)); + MCG->SC = (MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv); } /* Set internal reference clock selection. */ - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C2, MCG_C2_IRCS_MASK, MCG_C2_IRCS(ircs)); - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK, (uint8_t)enableMode); + MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); + MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode; /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */ if ((mcgOutClkState == kMCG_ClkOutStatInt) || (enableMode & kMCG_IrclkEnable)) @@ -842,12 +841,12 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config) uint8_t mcg_c5 = 0U; mcg_c5 |= MCG_C5_PRDIV0(config->prdiv); - __FSL_CLOCK_SECURE_WRITE(&MCG->C5, mcg_c5); /* Disable the PLL first. */ + MCG->C5 = mcg_c5; /* Disable the PLL first. */ - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C6, MCG_C6_VDIV0_MASK, MCG_C6_VDIV0(config->vdiv)); + MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv); /* Set enable mode. */ - __FSL_CLOCK_SECURE_BITS_SET(&MCG->C5, ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode)); + MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); /* Wait for PLL lock. */ while (!(MCG->S & MCG_S_LOCK0_MASK)) @@ -862,25 +861,25 @@ void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode) if (kMCG_MonitorNone == mode) { - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_CME0_MASK); + MCG->C6 &= ~MCG_C6_CME0_MASK; } else { if (kMCG_MonitorInt == mode) { - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LOCRE0_MASK); + MCG->C2 &= ~MCG_C2_LOCRE0_MASK; } else { - __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LOCRE0_MASK); + MCG->C2 |= MCG_C2_LOCRE0_MASK; } - __FSL_CLOCK_SECURE_BITS_SET(&MCG->C6, MCG_C6_CME0_MASK); + MCG->C6 |= MCG_C6_CME0_MASK; } } void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode) { - uint8_t mcg_c8 = __FSL_CLOCK_SECURE_READ(&MCG->C8); + uint8_t mcg_c8 = MCG->C8; mcg_c8 &= ~(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK); @@ -892,7 +891,7 @@ void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode) } mcg_c8 |= MCG_C8_CME1_MASK; } - __FSL_CLOCK_SECURE_WRITE(&MCG->C8, mcg_c8); + MCG->C8 = mcg_c8; } void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) @@ -904,11 +903,11 @@ void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) if (kMCG_MonitorNone == mode) { - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_LOLIE0_MASK); + MCG->C6 &= ~MCG_C6_LOLIE0_MASK; } else { - mcg_c8 = __FSL_CLOCK_SECURE_READ(&MCG->C8); + mcg_c8 = MCG->C8; mcg_c8 &= ~MCG_C8_LOCS1_MASK; @@ -920,8 +919,8 @@ void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) { mcg_c8 |= MCG_C8_LOLRE_MASK; } - __FSL_CLOCK_SECURE_WRITE(&MCG->C8, mcg_c8); - __FSL_CLOCK_SECURE_BITS_SET(&MCG->C6, MCG_C6_LOLIE0_MASK); + MCG->C8 = mcg_c8; + MCG->C6 |= MCG_C6_LOLIE0_MASK; } } @@ -930,7 +929,7 @@ uint32_t CLOCK_GetStatusFlags(void) uint32_t ret = 0U; uint8_t mcg_s = MCG->S; - if (__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_LOCS0_MASK) + if (MCG->SC & MCG_SC_LOCS0_MASK) { ret |= kMCG_Osc0LostFlag; } @@ -938,7 +937,7 @@ uint32_t CLOCK_GetStatusFlags(void) { ret |= kMCG_Osc0InitFlag; } - if (__FSL_CLOCK_SECURE_READ(&MCG->C8) & MCG_C8_LOCS1_MASK) + if (MCG->C8 & MCG_C8_LOCS1_MASK) { ret |= kMCG_RtcOscLostFlag; } @@ -963,8 +962,8 @@ void CLOCK_ClearStatusFlags(uint32_t mask) } if (mask & kMCG_RtcOscLostFlag) { - reg = __FSL_CLOCK_SECURE_READ(&MCG->C8); - __FSL_CLOCK_SECURE_WRITE(&MCG->C8, reg); + reg = MCG->C8; + MCG->C8 = reg; } if (mask & kMCG_Pll0LostFlag) { @@ -979,7 +978,7 @@ void CLOCK_InitOsc0(osc_config_t const *config) OSC_SetCapLoad(OSC0, config->capLoad); OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig); - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C2, OSC_MODE_MASK, MCG_C2_RANGE(range) | (uint8_t)config->workMode); + MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK)) { @@ -993,7 +992,7 @@ void CLOCK_InitOsc0(osc_config_t const *config) void CLOCK_DeinitOsc0(void) { OSC0->CR = 0U; - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, OSC_MODE_MASK); + MCG->C2 &= ~OSC_MODE_MASK; } status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms) @@ -1040,21 +1039,21 @@ status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_ MCG->ATCVL = (uint8_t)actv; MCG->ATCVH = (uint8_t)(actv >> 8U); - mcg_sc = __FSL_CLOCK_SECURE_READ(&MCG->SC); + mcg_sc = MCG->SC; mcg_sc &= ~(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK); mcg_sc |= (MCG_SC_ATMF_MASK | MCG_SC_ATMS(atms)); - __FSL_CLOCK_SECURE_WRITE(&MCG->SC, (mcg_sc | MCG_SC_ATME_MASK)); + MCG->SC = (mcg_sc | MCG_SC_ATME_MASK); /* Wait for finished. */ - while (__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_ATME_MASK) + while (MCG->SC & MCG_SC_ATME_MASK) { } /* Error occurs? */ - if (__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_ATMF_MASK) + if (MCG->SC & MCG_SC_ATMF_MASK) { /* Clear the failed flag. */ - __FSL_CLOCK_SECURE_WRITE(&MCG->SC, mcg_sc); + MCG->SC = mcg_sc; return kStatus_MCG_AtmHardwareFail; } @@ -1201,7 +1200,7 @@ status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela /* Set CLKS and IREFS. */ MCG->C1 = - ((__FSL_CLOCK_SECURE_READ(&MCG->C1) & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ + ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ | MCG_C1_IREFS(kMCG_FllSrcInternal)); /* IREFS = 1 */ /* Wait and check status. */ @@ -1260,7 +1259,7 @@ status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void } /* Set CLKS and IREFS. */ - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK, + MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ | MCG_C1_FRDIV(frdiv) /* FRDIV */ | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ @@ -1317,7 +1316,7 @@ status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela mcg_c4 = MCG->C4; - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); /* Disable lowpower. */ + MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ /* Errata: ERR007993 @@ -1333,8 +1332,8 @@ status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDela } /* Set CLKS and IREFS. */ - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK, - (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */ + MCG->C1 = + ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */ | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ /* Wait and check status. */ @@ -1378,13 +1377,13 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void #endif /* Change to FLL mode. */ - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_PLLS_MASK); + MCG->C6 &= ~MCG_C6_PLLS_MASK; while (MCG->S & MCG_S_PLLST_MASK) { } /* Set LP bit to enable the FLL */ - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); + MCG->C2 &= ~MCG_C2_LP_MASK; mcg_c4 = MCG->C4; @@ -1402,7 +1401,7 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void } /* Set CLKS and IREFS. */ - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK, + MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ | MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */ | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ @@ -1445,7 +1444,7 @@ status_t CLOCK_SetBlpiMode(void) #endif /* MCG_CONFIG_CHECK_PARAM */ /* Set LP. */ - __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK); + MCG->C2 |= MCG_C2_LP_MASK; return kStatus_Success; } @@ -1460,7 +1459,7 @@ status_t CLOCK_SetBlpeMode(void) #endif /* Set LP bit to enter BLPE mode. */ - __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK); + MCG->C2 |= MCG_C2_LP_MASK; return kStatus_Success; } @@ -1473,10 +1472,10 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co This function is designed to change MCG to PBE mode from PEE/BLPE/FBE, but with this workflow, the source mode could be all modes except PEI/PBI. */ - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); /* Disable lowpower. */ + MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ /* Change to use external clock first. */ - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); /* Wait for CLKST clock status bits to show clock source is ext ref clk */ while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != @@ -1485,7 +1484,7 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co } /* Disable PLL first, then configure PLL. */ - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_PLLS_MASK); + MCG->C6 &= ~MCG_C6_PLLS_MASK; while (MCG->S & MCG_S_PLLST_MASK) { } @@ -1496,7 +1495,7 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co } /* Change to PLL mode. */ - __FSL_CLOCK_SECURE_BITS_SET(&MCG->C6, MCG_C6_PLLS_MASK); + MCG->C6 |= MCG_C6_PLLS_MASK; /* Wait for PLL mode changed. */ while (!(MCG->S & MCG_S_PLLST_MASK)) @@ -1517,7 +1516,7 @@ status_t CLOCK_SetPeeMode(void) #endif /* Change to use PLL/FLL output clock first. */ - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcOut)); + MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); /* Wait for clock status bits to update */ while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll) @@ -1537,15 +1536,15 @@ status_t CLOCK_ExternalModeToFbeModeQuick(void) #endif /* MCG_CONFIG_CHECK_PARAM */ /* Disable low power */ - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); + MCG->C2 &= ~MCG_C2_LP_MASK; - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) { } /* Disable PLL. */ - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_PLLS_MASK); + MCG->C6 &= ~MCG_C6_PLLS_MASK; while (MCG->S & MCG_S_PLLST_MASK) { } @@ -1563,9 +1562,9 @@ status_t CLOCK_InternalModeToFbiModeQuick(void) #endif /* Disable low power */ - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); + MCG->C2 &= ~MCG_C2_LP_MASK; - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); + MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) { } @@ -1592,13 +1591,13 @@ status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEn CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv); /* If reset mode is not BLPI, first enter FBI mode. */ - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); + MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal); while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) { } /* Enter BLPI mode. */ - __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK); + MCG->C2 |= MCG_C2_LP_MASK; return kStatus_Success; } @@ -1608,8 +1607,8 @@ status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) CLOCK_SetExternalRefClkConfig(oscsel); /* Set to FBE mode. */ - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK, - (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ + MCG->C1 = + ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */ @@ -1619,7 +1618,7 @@ status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) } /* In FBE now, start to enter BLPE. */ - __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK); + MCG->C2 |= MCG_C2_LP_MASK; return kStatus_Success; } @@ -1633,7 +1632,7 @@ status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mc CLOCK_SetPbeMode(pllcs, config); /* Change to use PLL output clock. */ - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcOut)); + MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll) { } @@ -1693,7 +1692,7 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config) /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */ if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt) { - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); /* Disable lowpower. */ + MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ { CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay); @@ -1739,7 +1738,7 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config) } else { - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) { } @@ -1763,7 +1762,7 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config) } else { - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C5, (uint32_t)kMCG_PllEnableIndependent); + MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent; } return kStatus_Success; } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.h index ae7d6a435fa..b20629add16 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.h +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.h @@ -31,27 +31,8 @@ #ifndef _FSL_CLOCK_H_ #define _FSL_CLOCK_H_ -#include "core_cmSecureAccess.h" #include "fsl_common.h" - -/* Fallback implementation. */ -#define __FSL_CLOCK_SECURE_WRITE(addr, val) \ - SECURE_WRITE(addr, val) - -#define __FSL_CLOCK_SECURE_READ(addr) \ - SECURE_READ(addr) - -#define __FSL_CLOCK_SECURE_BITS_SET(addr, mask) \ - SECURE_BITS_SET(addr, mask) - -#define __FSL_CLOCK_SECURE_BITS_CLEAR(addr, mask) \ - SECURE_BITS_CLEAR(addr, mask) - -#define __FSL_CLOCK_SECURE_BITS_SET_VALUE(addr, mask, val) \ - SECURE_BITS_SET_VALUE(addr, mask, val) - - /*! @addtogroup clock */ /*! @{ */ @@ -684,7 +665,7 @@ extern "C" { static inline void CLOCK_EnableClock(clock_ip_name_t name) { uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); - __FSL_CLOCK_SECURE_BITS_SET((volatile uint32_t *) regAddr, (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name))); + (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); } /*! @@ -695,7 +676,7 @@ static inline void CLOCK_EnableClock(clock_ip_name_t name) static inline void CLOCK_DisableClock(clock_ip_name_t name) { uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); - __FSL_CLOCK_SECURE_BITS_CLEAR((volatile uint32_t *) regAddr, (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name))); + (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); } /*! @@ -705,7 +686,7 @@ static inline void CLOCK_DisableClock(clock_ip_name_t name) */ static inline void CLOCK_SetEr32kClock(uint32_t src) { - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT1, SIM_SOPT1_OSC32KSEL_MASK, SIM_SOPT1_OSC32KSEL(src)); + SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src)); } /*! @@ -715,7 +696,7 @@ static inline void CLOCK_SetEr32kClock(uint32_t src) */ static inline void CLOCK_SetSdhc0Clock(uint32_t src) { - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_SDHCSRC_MASK, SIM_SOPT2_SDHCSRC(src)); + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src)); } /*! @@ -725,7 +706,7 @@ static inline void CLOCK_SetSdhc0Clock(uint32_t src) */ static inline void CLOCK_SetEnetTime0Clock(uint32_t src) { - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_TIMESRC_MASK, SIM_SOPT2_TIMESRC(src)); + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TIMESRC_MASK) | SIM_SOPT2_TIMESRC(src)); } /*! @@ -735,7 +716,7 @@ static inline void CLOCK_SetEnetTime0Clock(uint32_t src) */ static inline void CLOCK_SetRmii0Clock(uint32_t src) { - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_RMIISRC_MASK, SIM_SOPT2_RMIISRC(src)); + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RMIISRC_MASK) | SIM_SOPT2_RMIISRC(src)); } /*! @@ -745,7 +726,7 @@ static inline void CLOCK_SetRmii0Clock(uint32_t src) */ static inline void CLOCK_SetTraceClock(uint32_t src) { - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_TRACECLKSEL_MASK, SIM_SOPT2_TRACECLKSEL(src)); + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src)); } /*! @@ -755,7 +736,7 @@ static inline void CLOCK_SetTraceClock(uint32_t src) */ static inline void CLOCK_SetPllFllSelClock(uint32_t src) { - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_PLLFLLSEL_MASK, SIM_SOPT2_PLLFLLSEL(src)); + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src)); } /*! @@ -765,7 +746,7 @@ static inline void CLOCK_SetPllFllSelClock(uint32_t src) */ static inline void CLOCK_SetClkOutClock(uint32_t src) { - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_CLKOUTSEL_MASK, SIM_SOPT2_CLKOUTSEL(src)); + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src)); } /*! @@ -775,7 +756,7 @@ static inline void CLOCK_SetClkOutClock(uint32_t src) */ static inline void CLOCK_SetRtcClkOutClock(uint32_t src) { - __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_RTCCLKOUTSEL_MASK, SIM_SOPT2_RTCCLKOUTSEL(src)); + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src)); } /*! @brief Enable USB FS clock. @@ -811,11 +792,8 @@ static inline void CLOCK_DisableUsbfs0Clock(void) */ static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4) { - __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV1, - SIM_CLKDIV1_OUTDIV1(outdiv1) | - SIM_CLKDIV1_OUTDIV2(outdiv2) | - SIM_CLKDIV1_OUTDIV3(outdiv3) | - SIM_CLKDIV1_OUTDIV4(outdiv4)); + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) | + SIM_CLKDIV1_OUTDIV4(outdiv4); } /*! @@ -908,7 +886,7 @@ void CLOCK_SetSimConfig(sim_clock_config_t const *config); */ static inline void CLOCK_SetSimSafeDivs(void) { - __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV1, 0x01240000UL); + SIM->CLKDIV1 = 0x01240000U; } /*! @name MCG frequency functions. */ @@ -984,11 +962,11 @@ static inline void CLOCK_SetLowPowerEnable(bool enable) { if (enable) { - __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK); + MCG->C2 |= MCG_C2_LP_MASK; } else { - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); + MCG->C2 &= ~MCG_C2_LP_MASK; } } @@ -1057,7 +1035,7 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config); */ static inline void CLOCK_DisablePll0(void) { - __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C5, MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); + MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); } /*! diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c index cef44c106e6..a79c6a8bf8a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c @@ -33,7 +33,6 @@ #include "em_system.h" #include "em_assert.h" #include -#include "core_cmSecureAccess.h" /***************************************************************************//** * @addtogroup emlib @@ -62,24 +61,19 @@ void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev) EFM_ASSERT(rev); - uint32_t pid0 = SECURE_READ(&(ROMTABLE->PID0)); - uint32_t pid1 = SECURE_READ(&(ROMTABLE->PID1)); - uint32_t pid2 = SECURE_READ(&(ROMTABLE->PID2)); - uint32_t pid3 = SECURE_READ(&(ROMTABLE->PID3)); - /* CHIP FAMILY bit [5:2] */ - tmp = (((pid1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); + tmp = (((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); /* CHIP FAMILY bit [1:0] */ - tmp |= ((pid0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); + tmp |= ((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); rev->family = tmp; /* CHIP MAJOR bit [3:0] */ - rev->major = (pid0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT; + rev->major = (ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT; /* CHIP MINOR bit [7:4] */ - tmp = (((pid2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); + tmp = (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); /* CHIP MINOR bit [3:0] */ - tmp |= ((pid3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); + tmp |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); rev->minor = tmp; } diff --git a/tools/importer/README.md b/tools/importer/README.md index 1ef476ee219..e5d2ca1cce6 100644 --- a/tools/importer/README.md +++ b/tools/importer/README.md @@ -48,3 +48,8 @@ Note: You must resolve any conflicts that arise during this cherry-pick process. ### Input to importer.py 1. Repository: -r ( Example: CMSIS / Mbed-tls) 2. `repo`_importer.json: -c (Example: cmsis_importer.json) + +For example the command below can be used to update CMSIS: +`python tools\importer\importer.py -c tools\importer\cmsis_importer.json -r ` + +Note: This script must be run from the mbed-os directory to work correctly. diff --git a/tools/importer/cmsis_importer.json b/tools/importer/cmsis_importer.json index d1a3b9fe347..1882f0069af 100644 --- a/tools/importer/cmsis_importer.json +++ b/tools/importer/cmsis_importer.json @@ -99,6 +99,10 @@ { "src_file" : "CMSIS/RTOS2/RTX/Source/IAR/irq_ca.S", "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Library/cmsis_os1.c", + "dest_file" : "rtos/TARGET_CORTEX/rtx4/cmsis_os1.c" } ], "folders" : [ @@ -140,19 +144,12 @@ } ], "commit_sha" : [ - "466b74e518eb9a4f2389dee1fc58ec1617be35d7", - "a06759d76e286994e457ba5aa6a8f6bb028828ce", - "0f0f21fdfeb25f0b350bbaba560270537f873e7a", - "3f7a235c6cc118b0bf634f330185718ef95477d9", - "0774ee3c8515ba447230433f44aab94a2cea02d2", - "5611950394fda1308087520ef3381c95244df201", - "b108cc8a8ad3d5e9c51b4ef95139aacf690d4223", - "adb6e821cc448f005e63ba9c7e2ce335abd54082", - "acd8ab1ff0588410f0fc5463fa12094250a371fb", - "1a511c456143bd31606f6a47807f506da1b51b90", - "474d2e3c9944d2866a0643795aafdfee743488eb", - "7b3a3a441ab6451462bd476721d6e8cb6ddd6c9d", - "d30da821a19fb6776e15eea33c5b45052a264dfd" + "4360b7bbf815c4d812005938c9c27af199803a97", + "cc2e0517e1c6440abf88f2815b8e1501a55cdd4d", + "b88254809eb626689c8aeb41304a308bf4e34a04", + "287121ffdc4c9c19f9ce8872e4edd941862daca1", + "1752803626865147dca92f30a39cef8d04581736", + "6a6e3ac0ebab1a6b6aa08d0928702c79562acee9" ] }