From 63a63198ff54161f2e2aef38242826af23d4d860 Mon Sep 17 00:00:00 2001 From: Peter Conheeney Date: Thu, 25 Feb 2016 09:06:57 +0000 Subject: [PATCH 1/3] update to repo --- .../TARGET_MPS2_BEID/CMSDK_BEID.h | 769 ------------------ .../TARGET_MPS2_BEID/SMM_MPS2.h | 616 -------------- .../TOOLCHAIN_ARM_STD/MPS2.sct | 15 - .../TOOLCHAIN_ARM_STD/startup_MPS2.s | 291 ------- .../TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h | 14 - .../TARGET_MPS2_BEID/cmsis_nvic.c | 30 - .../TARGET_MPS2_BEID/cmsis_nvic.h | 26 - .../TARGET_MPS2_BEID/peripherallink.h | 34 - .../TARGET_MPS2_BEID/system_CMSDK_BEID.c | 95 --- .../TARGET_MPS2_BEID/system_CMSDK_BEID.h | 75 -- .../TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h | 135 ++- .../TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h | 119 +-- .../TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct | 50 +- .../TOOLCHAIN_ARM_STD/startup_MPS2.s | 157 ++-- .../TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h | 46 +- .../TARGET_MPS2_M0/cmsis_nvic.c | 52 +- .../TARGET_MPS2_M0/cmsis_nvic.h | 48 +- .../TARGET_MPS2_M0/peripherallink.h | 46 +- .../TARGET_MPS2_M0/system_CMSDK_CM0.c | 50 +- .../TARGET_MPS2_M0/system_CMSDK_CM0.h | 50 +- .../TARGET_MPS2_M0P/CMSDK_CM0plus.h | 141 ++-- .../TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h | 119 +-- .../TOOLCHAIN_ARM_STD/MPS2.sct | 50 +- .../TOOLCHAIN_ARM_STD/startup_MPS2.s | 163 ++-- .../TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h | 46 +- .../TARGET_MPS2_M0P/cmsis_nvic.c | 52 +- .../TARGET_MPS2_M0P/cmsis_nvic.h | 48 +- .../TARGET_MPS2_M0P/peripherallink.h | 46 +- .../TARGET_MPS2_M0P/system_CMSDK_CM0plus.c | 51 +- .../TARGET_MPS2_M0P/system_CMSDK_CM0plus.h | 50 +- .../TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h | 121 ++- .../TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h | 119 +-- .../TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct | 50 +- .../TOOLCHAIN_ARM_STD/startup_MPS2.s | 157 ++-- .../TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h | 46 +- .../TARGET_MPS2_M3/cmsis_nvic.c | 46 +- .../TARGET_MPS2_M3/cmsis_nvic.h | 48 +- .../TARGET_MPS2_M3/peripherallink.h | 46 +- .../TARGET_MPS2_M3/system_CMSDK_CM3.c | 50 +- .../TARGET_MPS2_M3/system_CMSDK_CM3.h | 50 +- .../TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h | 283 +++---- .../TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h | 119 +-- .../TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct | 50 +- .../TOOLCHAIN_ARM_STD/startup_MPS2.s | 129 ++- .../TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h | 46 +- .../TARGET_MPS2_M4/cmsis_nvic.c | 46 +- .../TARGET_MPS2_M4/cmsis_nvic.h | 48 +- .../TARGET_MPS2_M4/peripherallink.h | 46 +- .../TARGET_MPS2_M4/system_CMSDK_CM4.c | 51 +- .../TARGET_MPS2_M4/system_CMSDK_CM4.h | 51 +- .../TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h | 67 +- .../TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h | 27 +- .../TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/MPS2.sct | 6 +- .../TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s | 85 +- .../TOOLCHAIN_GCC_ARM/gcc_arm.ld | 195 ----- .../TOOLCHAIN_GCC_ARM/startup_ARMCM7.s | 314 ------- .../TARGET_MPS2_M7/cmsis_nvic.h | 2 +- .../TARGET_MPS2_M7/system_CMSDK_CM7.c | 9 +- .../TARGET_MPS2_M7/system_CMSDK_CM7.h | 6 +- .../TARGET_MPS2/PeripheralNames.h | 28 +- .../hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h | 79 +- .../TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c | 15 +- .../TARGET_MPS2/SDK/mps2_ethernet_api.c | 39 + .../hal/TARGET_ARM_SSG/TARGET_MPS2/device.h | 2 +- .../hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c | 16 + .../TARGET_ARM_SSG/TARGET_MPS2/gpio_object.h | 4 +- .../hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c | 571 ++++++++----- .../hal/TARGET_ARM_SSG/TARGET_MPS2/objects.h | 8 + .../TARGET_ARM_SSG/TARGET_MPS2/serial_api.c | 229 +++++- .../hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c | 65 +- .../TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c | 4 +- .../host_tests_plugins/module_copy_mps2.py | 6 +- 72 files changed, 2442 insertions(+), 4421 deletions(-) delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/SMM_MPS2.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/peripherallink.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/gcc_arm.ld delete mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/startup_ARMCM7.s diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h deleted file mode 100644 index 6c1b55ec69c..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h +++ /dev/null @@ -1,769 +0,0 @@ -/**************************************************************************//** - * @file CMSDK_BEID.h - * @brief CMSIS Core Peripheral Access Layer Header File for - * CMSDK_BEID Device - * @version V3.02 - * @date 15. November 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef CMSDK_BEID_H -#define CMSDK_BEID_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ---------------------- CMSDK_BEID Specific Interrupt Numbers ------------------ */ - UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ - UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ - UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ - UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */ - UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */ - UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */ - UARTRX3_IRQn = 6, /* Was PORT0_ALL_IRQn Port 1 combined Interrupt */ - UARTTX3_IRQn = 7, /* Was PORT1_ALL_IRQn Port 1 combined Interrupt */ - TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ - TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ - DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ - SPI_IRQn = 11, /* SPI Interrupt */ - UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ - ETHERNET_IRQn = 13, /* Ethernet Interrupt */ - I2S_IRQn = 14, /* I2S Interrupt */ - TSC_IRQn = 15, /* Touch Screen Interrupt */ -// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */ - PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */ - PORT0_1_IRQn = 17, /* There are 16 pins in total */ - PORT0_2_IRQn = 18, - PORT0_3_IRQn = 19, - PORT0_4_IRQn = 20, - PORT0_5_IRQn = 21, - PORT0_6_IRQn = 22, - PORT0_7_IRQn = 23, - PORT0_8_IRQn = 24, - PORT0_9_IRQn = 25, - PORT0_10_IRQn = 26, - PORT0_11_IRQn = 27, - PORT0_12_IRQn = 28, - PORT0_13_IRQn = 29, - PORT0_14_IRQn = 30, - PORT0_15_IRQn = 31, -} IRQn_Type; - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */ -#define __CM3_REV 0x0201 /* Core revision r2p1 */ -#define __MPU_PRESENT 1 /* MPU present or not */ -#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ - -#include /* Processor and core peripherals */ -#include "system_CMSDK_BEID.h" /* System Header */ - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined ( __CC_ARM ) - #pragma push -#pragma anon_unions -#elif defined(__ICCARM__) - #pragma language=extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - -/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -typedef struct -{ - __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ - __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ - __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ - }; - __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ - -} CMSDK_UART_TypeDef; - -/* CMSDK_UART DATA Register Definitions */ - -#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ -#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ - -#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ -#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ - -#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ -#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ - -#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ -#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ - -#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ -#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ - -#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ -#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ - -#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ -#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ - -#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ -#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ - -#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ -#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ - -#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ -#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ - -#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ -#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ - -#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ -#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ - -#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ -#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ - -#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ -#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ - -#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ -#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ - -#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ -#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ - -#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ -#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ - - -/*----------------------------- Timer (TIMER) -------------------------------*/ -typedef struct -{ - __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ - __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ - __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ - }; - -} CMSDK_TIMER_TypeDef; - -/* CMSDK_TIMER CTRL Register Definitions */ - -#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ -#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ - -#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ -#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ - -#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ -#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ - -#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ -#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ - -#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ -#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ - -#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ -#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ - -#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ -#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ - -#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ -#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ - - -/*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ - __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ - __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ - __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ - __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ - __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ - __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ - uint32_t RESERVED0; - __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ - __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ - __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ - __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ - __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ - __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ - __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ - uint32_t RESERVED1[945]; - __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ - __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ -} CMSDK_DUALTIMER_BOTH_TypeDef; - -#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ -#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ - -#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ -#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ - -#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ -#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ - -#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ -#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ - -#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ -#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ - -#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ -#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ - -#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ -#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ - -#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ -#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ - -#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ -#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ - -#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ -#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ - -#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ -#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ - -#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ -#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ - -#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ -#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ - -#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ -#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ - -#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ -#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ - -#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ -#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ - -#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ -#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ - -#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ -#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ - -#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ -#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ - -#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ -#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ - -#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ -#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ - -#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ -#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ - -#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ -#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ - -#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ -#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ - - -typedef struct -{ - __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ - __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ - __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ - __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ - __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ - __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ - __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ -} CMSDK_DUALTIMER_SINGLE_TypeDef; - -#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ -#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ - -#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ -#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ - -#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ -#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ - -#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ -#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ - -#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ -#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ - -#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ -#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ - -#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ -#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ - -#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ -#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ - -#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ -#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ - -#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ -#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ - -#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ -#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ - -#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ -#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ - - -/*-------------------- General Purpose Input Output (GPIO) -------------------*/ -typedef struct -{ - __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ - __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ - uint32_t RESERVED0[2]; - __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ - __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ - __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ - __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ - __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ - __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ - __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ - __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ - __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ - __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ - union { - __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ - __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ - }; - uint32_t RESERVED1[241]; - __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ - __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ -} CMSDK_GPIO_TypeDef; - -#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ -#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ - -#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ -#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ - -#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ -#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ - -#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ -#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ - -#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ -#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ - -#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ -#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ - -#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ -#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ - -#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ -#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ - -#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ -#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ - -#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ -#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ - -#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ -#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ - -#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ -#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ - -#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ -#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ - -#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ -#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ - -#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ -#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ - -#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ -#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ - - -/*------------- System Control (SYSCON) --------------------------------------*/ -typedef struct -{ - __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ - __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ - __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ - __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ - __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ - uint32_t RESERVED0[3]; - __IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */ - __IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */ - uint32_t RESERVED1[2]; - __IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */ - __IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */ - uint32_t RESERVED2[2]; - __IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */ - __IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */ - __IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */ - __IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */ - __IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */ - __IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */ - uint32_t RESERVED3[10]; - __IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */ - __IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */ - __IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */ - __IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */ - __IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */ - __IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */ - uint32_t RESERVED4[2]; - __IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */ - __IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */ - __IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */ - __IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */ - __IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */ - __IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */ - uint32_t RESERVED5[2]; - __IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */ - __IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */ - __IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */ - __IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */ - __IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */ - __IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */ - __IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */ - __IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */ - __O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */ - __IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */ - uint32_t RESERVED6[2]; - __IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */ - __IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */ - __I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */ - uint32_t RESERVED7[1]; - __IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */ - __IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */ - __IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */ -} CMSDK_SYSCON_TypeDef; - -#define CMSDK_SYSCON_REMAP_Pos 0 -#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ - -#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 -#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ - -#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 -#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ - -#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 -#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ - -#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 -#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ - -#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 -#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ - -#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 -#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ - -#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 -#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ - -#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 -#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ - -#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 -#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ - - -/*------------- PL230 uDMA (PL230) --------------------------------------*/ -typedef struct -{ - __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ - __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ - __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ - __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ - __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ - __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ - __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ - __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ - __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ - __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ - __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ - __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ - __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ - __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ - __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ - __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ - uint32_t RESERVED0[3]; - __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ - -} CMSDK_PL230_TypeDef; - -#define PL230_DMA_CHNL_BITS 0 - -#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */ -#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */ - -#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */ -#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */ - -#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */ -#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */ - -#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */ -#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */ - -#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */ -#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */ - -#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */ -#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */ - -#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */ -#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */ - -#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */ -#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */ - -#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */ -#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */ - -#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */ -#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */ - -#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */ -#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */ - -#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */ -#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */ - -#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */ -#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */ - -#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */ -#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */ - -#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */ -#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */ - -#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */ -#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */ - -#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */ -#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */ - -#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */ -#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */ - -#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */ -#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */ - -#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */ -#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */ - -#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */ -#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */ - -#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */ -#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */ - -#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */ -#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */ - - -/*------------------- Watchdog ----------------------------------------------*/ -typedef struct -{ - - __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ - __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ - __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ - __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ - __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ - __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ - uint32_t RESERVED0[762]; - __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ - uint32_t RESERVED1[191]; - __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ - __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ -}CMSDK_WATCHDOG_TypeDef; - -#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ -#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ - -#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ -#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */ - -#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ -#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ - -#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ -#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ - -#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ -#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ - -#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ -#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ - -#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ -#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ - -#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ -#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */ - -#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ -#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ - -#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ -#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ - - - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined ( __CC_ARM ) - #pragma pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif - - - - -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -/* Peripheral and SRAM base address */ -#define CMSDK_FLASH_BASE (0x00000000UL) -#define CMSDK_SRAM_BASE (0x20000000UL) -#define CMSDK_PERIPH_BASE (0x40000000UL) - -#define CMSDK_RAM_BASE (0x20000000UL) -#define CMSDK_APB_BASE (0x40000000UL) -#define CMSDK_AHB_BASE (0x40010000UL) - -/* APB peripherals */ -#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) -#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) -#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) -#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) -#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) -#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x5000UL) -#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x4000UL) -#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) -#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) -#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) -#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) - -/* AHB peripherals */ -#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) -#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) -#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) -#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) -#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) - - -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) -#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) -#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) -#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) -#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) -#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) -#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) -#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) -#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) -#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) -#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE ) -#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) -#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) -#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) -#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) -#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) - - -#ifdef __cplusplus -} -#endif - -#endif /* CMSDK_BEID_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/SMM_MPS2.h deleted file mode 100644 index a0c31990809..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/SMM_MPS2.h +++ /dev/null @@ -1,616 +0,0 @@ -/* - * Copyright: - * ---------------------------------------------------------------- - * This confidential and proprietary software may be used only as - * authorised by a licensing agreement from ARM Limited - * (C) COPYRIGHT 2014 ARM Limited - * ALL RIGHTS RESERVED - * The entire notice above must be reproduced on all authorised - * copies and copies may only be made to the extent permitted - * by a licensing agreement from ARM Limited. - * ---------------------------------------------------------------- - * File: smm_mps2.h - * Release: Version 1.0 - * ---------------------------------------------------------------- - */ - -#ifndef __SMM_MPS2_H -#define __SMM_MPS2_H - -#include "peripherallink.h" /* device specific header file */ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/******************************************************************************/ -/* FPGA System Register declaration */ -/******************************************************************************/ - -typedef struct -{ - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - uint32_t RESERVED3[1]; - __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[9]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS -} MPS2_FPGAIO_TypeDef; - -// MISC register bit definitions - -#define CLCD_CS_Pos 0 -#define CLCD_CS_Msk (1UL< CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error - }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT -} MPS2_I2S_TypeDef; - -#define I2S_CONTROL_TXEN_Pos 0 -#define I2S_CONTROL_TXEN_Msk (1UL<> (lsb)) -#define INSERT_BITS(arg, msb, lsb, value) \ - ((arg) = ((arg) & ~CREATE_MASK(msb, lsb)) | (((value) << (lsb)) & CREATE_MASK(msb, lsb))) - -#define MASK_FIELD(arg, field) MASK_BITS(arg, field##_MSB, field##_LSB) -#define EXTRACT_FIELD(arg, field) EXTRACT_BITS(arg, field##_MSB, field##_LSB) -#define INSERT_FIELD(arg, field, value) INSERT_BITS(arg, field##_MSB, field##_LSB, value) - -#define SET_BIT(arg, bit) ((arg) |= (1 << (bit))) -#define CLEAR_BIT(arg, bit) ((arg) &= ~(1 << (bit))) -#define TEST_BIT(arg, bit) ((arg) & (1 << (bit))) - -#ifndef NoOfElements -#define NoOfElements(array) (sizeof(array) / sizeof(array[0])) -#endif - -#endif /* __SMM_MPS2_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct deleted file mode 100644 index 2afd726abec..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File *** -; ************************************************************* - - LR_IROM1 0x00000000 0x00400000 { ; load region size_region - ER_IROM1 +0 { ; load address = execution address - *.o (RESET, +FIRST) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 +0 { ; RW data - .ANY (+RW +ZI) - } - } - diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s deleted file mode 100644 index e67bee5a75e..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s +++ /dev/null @@ -1,291 +0,0 @@ -;/**************************************************************************//** -; * @file startup_CMSDK_CM3.s -; * @brief CMSIS Core Device Startup File for -; * CMSDK_CM3 Device -; * @version V3.02 -; * @date 15. November 2013 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; ******************************************************************************/ -;/* Copyright (c) 2011 - 2013 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UARTRX0_Handler ; UART 0 RX Handler - DCD UARTTX0_Handler ; UART 0 TX Handler - DCD UARTRX1_Handler ; UART 1 RX Handler - DCD UARTTX1_Handler ; UART 1 TX Handler - DCD UARTRX2_Handler ; UART 2 RX Handler - DCD UARTTX2_Handler ; UART 2 TX Handler - DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; TIMER 0 handler - DCD TIMER1_Handler ; TIMER 1 handler - DCD DUALTIMER_HANDLER ; Dual timer handler - DCD SPI_Handler ; SPI exceptions Handler - DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler - DCD ETHERNET_Handler ; Ethernet Overflow Handler - DCD I2S_Handler ; I2S Handler - DCD TSC_Handler ; Touch Screen handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler - DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler - DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler - DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler - DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler - DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler - DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler - DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler - DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT UARTRX0_Handler [WEAK] - EXPORT UARTTX0_Handler [WEAK] - EXPORT UARTRX1_Handler [WEAK] - EXPORT UARTTX1_Handler [WEAK] - EXPORT UARTRX2_Handler [WEAK] - EXPORT UARTTX2_Handler [WEAK] - EXPORT PORT0_COMB_Handler [WEAK] - EXPORT PORT1_COMB_Handler [WEAK] - EXPORT TIMER0_Handler [WEAK] - EXPORT TIMER1_Handler [WEAK] - EXPORT DUALTIMER_HANDLER [WEAK] - EXPORT SPI_Handler [WEAK] - EXPORT UARTOVF_Handler [WEAK] - EXPORT ETHERNET_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - EXPORT TSC_Handler [WEAK] - EXPORT PORT0_0_Handler [WEAK] - EXPORT PORT0_1_Handler [WEAK] - EXPORT PORT0_2_Handler [WEAK] - EXPORT PORT0_3_Handler [WEAK] - EXPORT PORT0_4_Handler [WEAK] - EXPORT PORT0_5_Handler [WEAK] - EXPORT PORT0_6_Handler [WEAK] - EXPORT PORT0_7_Handler [WEAK] - EXPORT PORT0_8_Handler [WEAK] - EXPORT PORT0_9_Handler [WEAK] - EXPORT PORT0_10_Handler [WEAK] - EXPORT PORT0_11_Handler [WEAK] - EXPORT PORT0_12_Handler [WEAK] - EXPORT PORT0_13_Handler [WEAK] - EXPORT PORT0_14_Handler [WEAK] - EXPORT PORT0_15_Handler [WEAK] - -UARTRX0_Handler -UARTTX0_Handler -UARTRX1_Handler -UARTTX1_Handler -UARTRX2_Handler -UARTTX2_Handler -PORT0_COMB_Handler -PORT1_COMB_Handler -TIMER0_Handler -TIMER1_Handler -DUALTIMER_HANDLER -SPI_Handler -UARTOVF_Handler -ETHERNET_Handler -I2S_Handler -TSC_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler -PORT0_8_Handler -PORT0_9_Handler -PORT0_10_Handler -PORT0_11_Handler -PORT0_12_Handler -PORT0_13_Handler -PORT0_14_Handler -PORT0_15_Handler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h deleted file mode 100644 index f34873c2698..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h +++ /dev/null @@ -1,14 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC1768 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "CMSDK_BEID.h" -#include "SMM_MPS2.h" -#include "cmsis_nvic.h" - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.c deleted file mode 100644 index 6b8c4a27d55..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.c +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic for LCP1768 - * Copyright (c) 2009-2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ -#include "cmsis_nvic.h" - -#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM -#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - uint32_t i; - - // Copy and switch to dynamic vectors if the first time called - if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { - uint32_t *old_vectors = vectors; - vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; - for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; - } - vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; -} diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h deleted file mode 100644 index 600de99554d..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h +++ /dev/null @@ -1,26 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic - * Copyright (c) 2009-2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#include "cmsis.h" - -#define NVIC_NUM_VECTORS (16 + 32) -#define NVIC_USER_IRQ_OFFSET 16 - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/peripherallink.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/peripherallink.h deleted file mode 100644 index 6f031cd4aef..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/peripherallink.h +++ /dev/null @@ -1,34 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: Device.h - * Purpose: Include the correct device header file - *----------------------------------------------------------------------------- - * This file is part of the uVision/ARM development tools. - * This software may only be used under the terms of a valid, current, - * end user licence from KEIL for a compatible version of KEIL software - * development tools. Nothing else gives you the right to use this software. - * - * This software is supplied "AS IS" without warranties of any kind. - * - * Copyright (c) 2013 KEIL - An ARM Company. All rights reserved. - *----------------------------------------------------------------------------*/ - -#ifndef __DEVICE_H -#define __DEVICE_H - -#if defined CMSDK_CM0 - #include "CMSDK_CM0.h" /* device specific header file */ -#elif defined CMSDK_CM0plus - #include "CMSDK_CM0plus.h" /* device specific header file */ -#elif defined CMSDK_CM3 - #include "CMSDK_CM3.h" /* device specific header file */ -#elif defined CMSDK_CM4 - #include "CMSDK_CM4.h" /* device specific header file */ -#elif defined CMSDK_CM7 - #include "CMSDK_CM7.h" /* device specific header file */ -#elif defined CMSDK_BEID - #include "CMSDK_BEID.h" /* device specific header file */ -#else - #warning "no appropriate header file found!" -#endif - -#endif /* __DEVICE_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.c deleted file mode 100644 index 02946c0cfe3..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************//** - * @file system_CMSDK_BEID.c - * @brief CMSIS Device System Source File for - * CMSDK_M3 Device - * @version V3.02 - * @date 15. November 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#include "CMSDK_BEID.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define __XTAL (50000000UL) /* Oscillator frequency */ - -#define __SYSTEM_CLOCK (__XTAL / 2) - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate (void) -{ - - SystemCoreClock = __SYSTEM_CLOCK; - -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = __SYSTEM_CLOCK; - - // Enable AHB and APB clock - CMSDK_SYSCON->AHBCLKCFG0SET = 0xF; // GPIO - CMSDK_SYSCON->APBCLKCFG0SET = 0x37; // UART0, UART1, TIMER0, TIMER1, DUAL TIMER -} diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h deleted file mode 100644 index c61fc631f59..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************//** - * @file system_CMSDK_BEID.h - * @brief CMSIS Device Peripheral Access Layer Header File for - * CMSDK_BEID Device - * @version V3.02 - * @date 15. March 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef SYSTEM_CMSDK_BEID_H -#define SYSTEM_CMSDK_BEID_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_CMSDK_BEID_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h index b07dfc6a6bd..6b547b020cd 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h @@ -1,41 +1,37 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * @file CMSDK_CM0.h * @brief CMSIS Core Peripheral Access Layer Header File for * CMSDK_CM0 Device -* @version V3.02 -* @date 15. November 2013 -* -* @note configured for CM7 without FPU * *******************************************************************************/ @@ -52,51 +48,48 @@ typedef enum IRQn { -/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - - - - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ +/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ /* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */ - UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ - UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ - UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ - UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */ - UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */ - UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */ - PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */ - PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */ - TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ - TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ - DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ - SPI_IRQn = 11, /* SPI Interrupt */ - UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ - ETHERNET_IRQn = 13, /* Ethernet Interrupt */ - I2S_IRQn = 14, /* I2S Interrupt */ - TSC_IRQn = 15, /* Touch Screen Interrupt */ -// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */ - PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */ - PORT0_1_IRQn = 17, /* There are 16 pins in total */ - PORT0_2_IRQn = 18, - PORT0_3_IRQn = 19, - PORT0_4_IRQn = 20, - PORT0_5_IRQn = 21, - PORT0_6_IRQn = 22, - PORT0_7_IRQn = 23, - PORT0_8_IRQn = 24, - PORT0_9_IRQn = 25, - PORT0_10_IRQn = 26, - PORT0_11_IRQn = 27, - PORT0_12_IRQn = 28, - PORT0_13_IRQn = 29, - PORT0_14_IRQn = 30, - PORT0_15_IRQn = 31, + UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ + SPI_IRQn = 11, /*!< SPI Interrupt */ + UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ + I2S_IRQn = 14, /*!< I2S Interrupt */ + TSC_IRQn = 15, /*!< Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ } IRQn_Type; @@ -686,7 +679,9 @@ typedef struct #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) +#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL) #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) /* AHB peripherals */ @@ -704,6 +699,8 @@ typedef struct #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) +#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) +#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE ) #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h index 910d5abd977..f0d07a3c30d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h @@ -1,36 +1,36 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * File: smm_mps2.h -* Release: Version 1.0 +* Release: Version 1.1 *******************************************************************************/ #ifndef __SMM_MPS2_H @@ -46,7 +46,7 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct +typedef struct { __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections // [31:2] : Reserved @@ -65,11 +65,14 @@ typedef struct // Bit[31:0] : reload value for prescale counter __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. uint32_t RESERVED4[9]; __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:7] : Reserved + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS // [6] : CLCD_BL_CTRL // [5] : CLCD_RD // [4] : CLCD_RS @@ -93,12 +96,18 @@ typedef struct #define CLCD_RD_Msk (1UL< Undefined! // <5=> Undefined! // <6=> Undefined! - // <7=> Undefined! + // <7=> Undefined! // RX Buffer Water Level // <0=> Undefined! // <1=> / IRQ triggers when less than 1 space available @@ -355,7 +364,7 @@ typedef struct // <4=> / IRQ triggers when less than 4 space available // <5=> Undefined! // <6=> Undefined! - // <7=> Undefined! + // <7=> Undefined! // FIFO reset // <0=> Normal operation // <1=> FIFO reset @@ -363,12 +372,12 @@ typedef struct // <0=> Normal operation // <1=> Assert audio Codec reset /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS + __I uint32_t STATUS; // STATUS // TX Buffer alert // <0=> TX buffer don't need service yet // <1=> TX buffer need service // RX Buffer alert - // <0=> RX buffer don't need service yet + // <0=> RX buffer don't need service yet // <1=> RX buffer need service // TX Buffer Empty // <0=> TX buffer have data @@ -383,33 +392,33 @@ typedef struct // <0=> RX buffer not full // <1=> RX buffer full union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR // TX error // <0=> Okay // <1=> TX overrun/underrun // RX error - // <0=> Okay + // <0=> Okay // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR // TX error // <0=> Okay // <1=> Clear TX error // RX error - // <0=> Okay + // <0=> Okay // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel + __O uint32_t TXBUF; // Transmit buffer + // Right channel // Left channel /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel + __I uint32_t RXBUF; // Receive buffer + // Right channel // Left channel uint32_t RESERVED1[186]; __IO uint32_t ITCR; // Integration Test Control Register @@ -556,7 +565,12 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */ #define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */ #define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */ +#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */ +#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */ +#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */ #define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */ +#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */ +#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */ #define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */ #ifdef CORTEX_M7 @@ -565,8 +579,8 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */ #endif -#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */ #define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */ +#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */ /******************************************************************************/ /* Peripheral declaration */ @@ -575,11 +589,16 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE ) #define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE ) #define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE ) +#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE ) +#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE ) #define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE ) #define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE ) #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct index 24f887bcd99..625a92a2db6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct @@ -1,33 +1,33 @@ ;* MPS2 CMSIS Library ;* -;* Copyright (c) 2006-2015 ARM Limited +;* Copyright (c) 2006-2016 ARM Limited ;* All rights reserved. -;* -;* Redistribution and use in source and binary forms, with or without +;* +;* Redistribution and use in source and binary forms, with or without ;* modification, are permitted provided that the following conditions are met: -;* -;* 1. Redistributions of source code must retain the above copyright notice, +;* +;* 1. Redistributions of source code must retain the above copyright notice, ;* this list of conditions and the following disclaimer. -;* -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation +;* +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation ;* and/or other materials provided with the distribution. -;* -;* 3. Neither the name of the copyright holder nor the names of its contributors -;* may be used to endorse or promote products derived from this software without +;* +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software without ;* specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -;* POSSIBILITY OF SUCH DAMAGE. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +;* POSSIBILITY OF SUCH DAMAGE. ;* ; ************************************************************* ; *** Scatter-Loading Description File *** @@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM - RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data + ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM + RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data .ANY (+RW +ZI) } } diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/startup_MPS2.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/startup_MPS2.s index 49c71305a75..71dff7dabf1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/startup_MPS2.s +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/startup_MPS2.s @@ -1,43 +1,42 @@ -;/**************************************************************************//** -; * @file startup_CMSDK_CM0.s -; * @brief CMSIS Core Device Startup File for -; * CMSDK_CM0 Device -; * @version V3.02 -; * @date 04. February 2015 -; * -; * @note -; * Copyright (C) 2015 ARM Limited. All rights reserved. -; * -; ******************************************************************************/ -;/* Copyright (c) 2011 - 2015 ARM LIMITED +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM0.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM0 Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ ; Stack Configuration @@ -108,22 +107,22 @@ __Vectors DCD __initial_sp ; Top of Stack DCD ETHERNET_Handler ; Ethernet Overflow Handler DCD I2S_Handler ; I2S Handler DCD TSC_Handler ; Touch Screen handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler - DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler - DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler - DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler - DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler - DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler - DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler - DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler - DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors @@ -185,6 +184,14 @@ Default_Handler PROC EXPORT ETHERNET_Handler [WEAK] EXPORT I2S_Handler [WEAK] EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] EXPORT PORT0_0_Handler [WEAK] EXPORT PORT0_1_Handler [WEAK] EXPORT PORT0_2_Handler [WEAK] @@ -193,14 +200,6 @@ Default_Handler PROC EXPORT PORT0_5_Handler [WEAK] EXPORT PORT0_6_Handler [WEAK] EXPORT PORT0_7_Handler [WEAK] - EXPORT PORT0_8_Handler [WEAK] - EXPORT PORT0_9_Handler [WEAK] - EXPORT PORT0_10_Handler [WEAK] - EXPORT PORT0_11_Handler [WEAK] - EXPORT PORT0_12_Handler [WEAK] - EXPORT PORT0_13_Handler [WEAK] - EXPORT PORT0_14_Handler [WEAK] - EXPORT PORT0_15_Handler [WEAK] UARTRX0_Handler UARTTX0_Handler @@ -218,22 +217,22 @@ UARTOVF_Handler ETHERNET_Handler I2S_Handler TSC_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler -PORT0_8_Handler -PORT0_9_Handler -PORT0_10_Handler -PORT0_11_Handler -PORT0_12_Handler -PORT0_13_Handler -PORT0_14_Handler -PORT0_15_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler B . ENDP diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h index 14cc79d7b57..843f1e4811e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * A generic CMSIS include header, pulling in MPS2 specifics *******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c index 837273baf7b..159fce69aeb 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * CMSIS-style functionality to support dynamic vectors *******************************************************************************/ @@ -41,13 +41,13 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { // Space for dynamic vectors, initialised to allocate in R/W static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; - // Set the vector - vectors[IRQn + 16] = vector; + // Set the vector + vectors[IRQn + 16] = vector; } uint32_t NVIC_GetVector(IRQn_Type IRQn) { // We can always read vectors at 0x0, as the addresses are remapped - uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; + uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; // Return the vector return vectors[IRQn + 16]; diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h index 3d3a3e2fd99..8ad5fdcd634 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * CMSIS-style functionality to support dynamic vectors *******************************************************************************/ @@ -37,7 +37,7 @@ #include "cmsis.h" -#define NVIC_NUM_VECTORS (16 + 32) +#define NVIC_NUM_VECTORS (16 + 48) #define NVIC_USER_IRQ_OFFSET 16 #ifdef __cplusplus diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h index 94c315ae03f..80541d90d31 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * Name: Device.h * Purpose: Include the correct device header file diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c index f1c17e2f626..4adf1e4a115 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c @@ -1,41 +1,37 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * @file system_CMSDK_CM0.c * @brief CMSIS Device System Source File for * CMSDK_M0 Device -* @version V3.02 -* @date 15. November 2013 -* -* @note * *******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h index e6bd21b0c86..cdbd1322422 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h @@ -1,42 +1,38 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. * ******************************************************************************* * @file system_CMSDK_CM0.h * @brief CMSIS Device Peripheral Access Layer Header File for * CMSDK_CM0 Device -* @version V3.02 -* @date 15. March 2013 -* -* @note * ******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h index 4689f196954..3c062956e46 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h @@ -1,41 +1,37 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * @file CMSDK_CM0plus.h * @brief CMSIS Core Peripheral Access Layer Header File for * CMSDK_CM0plus Device -* @version V3.02 -* @date 15. November 2013 -* -* @note configured for CM7 without FPU * *******************************************************************************/ @@ -52,51 +48,48 @@ typedef enum IRQn { -/* ------------------- Cortex-M0+ Processor Exceptions Numbers ------------------ */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - - - - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - -/* ---------------------- CMSDK_CM0plus Specific Interrupt Numbers -------------- */ - UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ - UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ - UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ - UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */ - UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */ - UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */ - PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */ - PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */ - TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ - TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ - DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ - SPI_IRQn = 11, /* SPI Interrupt */ - UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ - ETHERNET_IRQn = 13, /* Ethernet Interrupt */ - I2S_IRQn = 14, /* I2S Interrupt */ - TSC_IRQn = 15, /* Touch Screen Interrupt */ -// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */ - PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */ - PORT0_1_IRQn = 17, /* There are 16 pins in total */ - PORT0_2_IRQn = 18, - PORT0_3_IRQn = 19, - PORT0_4_IRQn = 20, - PORT0_5_IRQn = 21, - PORT0_6_IRQn = 22, - PORT0_7_IRQn = 23, - PORT0_8_IRQn = 24, - PORT0_9_IRQn = 25, - PORT0_10_IRQn = 26, - PORT0_11_IRQn = 27, - PORT0_12_IRQn = 28, - PORT0_13_IRQn = 29, - PORT0_14_IRQn = 30, - PORT0_15_IRQn = 31, +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + +/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */ + UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ + SPI_IRQn = 11, /*!< SPI Interrupt */ + UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ + I2S_IRQn = 14, /*!< I2S Interrupt */ + TSC_IRQn = 15, /*!< Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ } IRQn_Type; @@ -687,7 +680,9 @@ typedef struct #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) +#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL) #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) /* AHB peripherals */ @@ -705,6 +700,8 @@ typedef struct #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) +#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) +#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE ) #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h index 910d5abd977..34f1a94dd9e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h @@ -1,36 +1,36 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * File: smm_mps2.h -* Release: Version 1.0 +* Release: Version 1.1 *******************************************************************************/ #ifndef __SMM_MPS2_H @@ -46,7 +46,7 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct +typedef struct { __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections // [31:2] : Reserved @@ -65,11 +65,14 @@ typedef struct // Bit[31:0] : reload value for prescale counter __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. uint32_t RESERVED4[9]; __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:7] : Reserved + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS // [6] : CLCD_BL_CTRL // [5] : CLCD_RD // [4] : CLCD_RS @@ -93,12 +96,18 @@ typedef struct #define CLCD_RD_Msk (1UL< Undefined! // <5=> Undefined! // <6=> Undefined! - // <7=> Undefined! + // <7=> Undefined! // RX Buffer Water Level // <0=> Undefined! // <1=> / IRQ triggers when less than 1 space available @@ -355,7 +364,7 @@ typedef struct // <4=> / IRQ triggers when less than 4 space available // <5=> Undefined! // <6=> Undefined! - // <7=> Undefined! + // <7=> Undefined! // FIFO reset // <0=> Normal operation // <1=> FIFO reset @@ -363,12 +372,12 @@ typedef struct // <0=> Normal operation // <1=> Assert audio Codec reset /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS + __I uint32_t STATUS; // STATUS // TX Buffer alert // <0=> TX buffer don't need service yet // <1=> TX buffer need service // RX Buffer alert - // <0=> RX buffer don't need service yet + // <0=> RX buffer don't need service yet // <1=> RX buffer need service // TX Buffer Empty // <0=> TX buffer have data @@ -383,33 +392,33 @@ typedef struct // <0=> RX buffer not full // <1=> RX buffer full union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR // TX error // <0=> Okay // <1=> TX overrun/underrun // RX error - // <0=> Okay + // <0=> Okay // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR // TX error // <0=> Okay // <1=> Clear TX error // RX error - // <0=> Okay + // <0=> Okay // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel + __O uint32_t TXBUF; // Transmit buffer + // Right channel // Left channel /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel + __I uint32_t RXBUF; // Receive buffer + // Right channel // Left channel uint32_t RESERVED1[186]; __IO uint32_t ITCR; // Integration Test Control Register @@ -556,7 +565,12 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */ #define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */ #define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */ +#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */ +#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */ +#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */ #define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */ +#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */ +#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */ #define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */ #ifdef CORTEX_M7 @@ -565,8 +579,8 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */ #endif -#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */ #define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */ +#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */ /******************************************************************************/ /* Peripheral declaration */ @@ -575,11 +589,16 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE ) #define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE ) #define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE ) +#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE ) +#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE ) #define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE ) #define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE ) #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/MPS2.sct b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/MPS2.sct index 24f887bcd99..625a92a2db6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/MPS2.sct +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/MPS2.sct @@ -1,33 +1,33 @@ ;* MPS2 CMSIS Library ;* -;* Copyright (c) 2006-2015 ARM Limited +;* Copyright (c) 2006-2016 ARM Limited ;* All rights reserved. -;* -;* Redistribution and use in source and binary forms, with or without +;* +;* Redistribution and use in source and binary forms, with or without ;* modification, are permitted provided that the following conditions are met: -;* -;* 1. Redistributions of source code must retain the above copyright notice, +;* +;* 1. Redistributions of source code must retain the above copyright notice, ;* this list of conditions and the following disclaimer. -;* -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation +;* +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation ;* and/or other materials provided with the distribution. -;* -;* 3. Neither the name of the copyright holder nor the names of its contributors -;* may be used to endorse or promote products derived from this software without +;* +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software without ;* specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -;* POSSIBILITY OF SUCH DAMAGE. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +;* POSSIBILITY OF SUCH DAMAGE. ;* ; ************************************************************* ; *** Scatter-Loading Description File *** @@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM - RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data + ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM + RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data .ANY (+RW +ZI) } } diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/startup_MPS2.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/startup_MPS2.s index 005952b80e2..df56e011ee8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/startup_MPS2.s +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/startup_MPS2.s @@ -1,43 +1,42 @@ -;/**************************************************************************//** -; * @file startup_CMSDK_CM0.s -; * @brief CMSIS Core Device Startup File for -; * CMSDK_CM0 Device -; * @version V3.02 -; * @date 15. November 2013 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; ******************************************************************************/ -;/* Copyright (c) 2011 - 2013 ARM LIMITED +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM0P.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM0P Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ ; Stack Configuration @@ -108,22 +107,22 @@ __Vectors DCD __initial_sp ; Top of Stack DCD ETHERNET_Handler ; Ethernet Overflow Handler DCD I2S_Handler ; I2S Handler DCD TSC_Handler ; Touch Screen handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler - DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler - DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler - DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler - DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler - DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler - DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler - DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler - DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors @@ -164,9 +163,9 @@ PendSV_Handler PROC B . ENDP SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP + EXPORT SysTick_Handler [WEAK] + B . + ENDP Default_Handler PROC EXPORT UARTRX0_Handler [WEAK] @@ -185,6 +184,14 @@ Default_Handler PROC EXPORT ETHERNET_Handler [WEAK] EXPORT I2S_Handler [WEAK] EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] EXPORT PORT0_0_Handler [WEAK] EXPORT PORT0_1_Handler [WEAK] EXPORT PORT0_2_Handler [WEAK] @@ -193,14 +200,6 @@ Default_Handler PROC EXPORT PORT0_5_Handler [WEAK] EXPORT PORT0_6_Handler [WEAK] EXPORT PORT0_7_Handler [WEAK] - EXPORT PORT0_8_Handler [WEAK] - EXPORT PORT0_9_Handler [WEAK] - EXPORT PORT0_10_Handler [WEAK] - EXPORT PORT0_11_Handler [WEAK] - EXPORT PORT0_12_Handler [WEAK] - EXPORT PORT0_13_Handler [WEAK] - EXPORT PORT0_14_Handler [WEAK] - EXPORT PORT0_15_Handler [WEAK] UARTRX0_Handler UARTTX0_Handler @@ -218,22 +217,22 @@ UARTOVF_Handler ETHERNET_Handler I2S_Handler TSC_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler -PORT0_8_Handler -PORT0_9_Handler -PORT0_10_Handler -PORT0_11_Handler -PORT0_12_Handler -PORT0_13_Handler -PORT0_14_Handler -PORT0_15_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler B . ENDP diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h index 4ecd6c9f5fc..42a187b43e2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * A generic CMSIS include header, pulling in MPS2 specifics *******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.c index 837273baf7b..159fce69aeb 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.c @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * CMSIS-style functionality to support dynamic vectors *******************************************************************************/ @@ -41,13 +41,13 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { // Space for dynamic vectors, initialised to allocate in R/W static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; - // Set the vector - vectors[IRQn + 16] = vector; + // Set the vector + vectors[IRQn + 16] = vector; } uint32_t NVIC_GetVector(IRQn_Type IRQn) { // We can always read vectors at 0x0, as the addresses are remapped - uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; + uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; // Return the vector return vectors[IRQn + 16]; diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.h index 3d3a3e2fd99..8ad5fdcd634 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.h @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * CMSIS-style functionality to support dynamic vectors *******************************************************************************/ @@ -37,7 +37,7 @@ #include "cmsis.h" -#define NVIC_NUM_VECTORS (16 + 32) +#define NVIC_NUM_VECTORS (16 + 48) #define NVIC_USER_IRQ_OFFSET 16 #ifdef __cplusplus diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/peripherallink.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/peripherallink.h index 94c315ae03f..80541d90d31 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/peripherallink.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/peripherallink.h @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * Name: Device.h * Purpose: Include the correct device header file diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.c index 8f05cb753dd..2150db57afc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.c +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.c @@ -1,46 +1,41 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * @file system_CMSDK_CM0plus.c * @brief CMSIS Device System Source File for * CMSDK_M0 Device -* @version V3.02 -* @date 15. November 2013 -* -* @note * *******************************************************************************/ - #include "CMSDK_CM0plus.h" /*---------------------------------------------------------------------------- diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.h index 4010c8cca53..8dce0ba0a57 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.h @@ -1,42 +1,38 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. * ******************************************************************************* * @file system_CMSDK_CM0plus.h * @brief CMSIS Device Peripheral Access Layer Header File for * CMSDK_CM0plus Device -* @version V3.02 -* @date 15. March 2013 -* -* @note * ******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h index e4c64b96285..c9db03f9414 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h @@ -1,41 +1,37 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * @file CMSDK_CM3.h * @brief CMSIS Core Peripheral Access Layer Header File for * CMSDK_CM3 Device -* @version V3.02 -* @date 15. November 2013 -* -* @note configured for CM7 without FPU * *******************************************************************************/ @@ -63,40 +59,39 @@ typedef enum IRQn PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ SysTick_IRQn = -1, /* 15 System Tick Interrupt */ -/* ---------------------- CMSDK_CM3 Specific Interrupt Numbers ------------------ */ - UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ - UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ - UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ - UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */ - UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */ - UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */ - PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */ - PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */ - TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ - TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ - DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ - SPI_IRQn = 11, /* SPI Interrupt */ - UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ - ETHERNET_IRQn = 13, /* Ethernet Interrupt */ - I2S_IRQn = 14, /* I2S Interrupt */ - TSC_IRQn = 15, /* Touch Screen Interrupt */ -// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */ - PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */ - PORT0_1_IRQn = 17, /* There are 16 pins in total */ - PORT0_2_IRQn = 18, - PORT0_3_IRQn = 19, - PORT0_4_IRQn = 20, - PORT0_5_IRQn = 21, - PORT0_6_IRQn = 22, - PORT0_7_IRQn = 23, - PORT0_8_IRQn = 24, - PORT0_9_IRQn = 25, - PORT0_10_IRQn = 26, - PORT0_11_IRQn = 27, - PORT0_12_IRQn = 28, - PORT0_13_IRQn = 29, - PORT0_14_IRQn = 30, - PORT0_15_IRQn = 31, +/****** CMSDK Specific Interrupt Numbers *********************************************************/ + UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ + SPI_IRQn = 11, /*!< SPI Interrupt */ + UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ + I2S_IRQn = 14, /*!< I2S Interrupt */ + TSC_IRQn = 15, /*!< Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ } IRQn_Type; @@ -686,7 +681,9 @@ typedef struct #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) +#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL) #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) /* AHB peripherals */ @@ -704,6 +701,8 @@ typedef struct #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) +#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) +#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE ) #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h index 910d5abd977..f0d07a3c30d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h @@ -1,36 +1,36 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * File: smm_mps2.h -* Release: Version 1.0 +* Release: Version 1.1 *******************************************************************************/ #ifndef __SMM_MPS2_H @@ -46,7 +46,7 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct +typedef struct { __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections // [31:2] : Reserved @@ -65,11 +65,14 @@ typedef struct // Bit[31:0] : reload value for prescale counter __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. uint32_t RESERVED4[9]; __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:7] : Reserved + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS // [6] : CLCD_BL_CTRL // [5] : CLCD_RD // [4] : CLCD_RS @@ -93,12 +96,18 @@ typedef struct #define CLCD_RD_Msk (1UL< Undefined! // <5=> Undefined! // <6=> Undefined! - // <7=> Undefined! + // <7=> Undefined! // RX Buffer Water Level // <0=> Undefined! // <1=> / IRQ triggers when less than 1 space available @@ -355,7 +364,7 @@ typedef struct // <4=> / IRQ triggers when less than 4 space available // <5=> Undefined! // <6=> Undefined! - // <7=> Undefined! + // <7=> Undefined! // FIFO reset // <0=> Normal operation // <1=> FIFO reset @@ -363,12 +372,12 @@ typedef struct // <0=> Normal operation // <1=> Assert audio Codec reset /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS + __I uint32_t STATUS; // STATUS // TX Buffer alert // <0=> TX buffer don't need service yet // <1=> TX buffer need service // RX Buffer alert - // <0=> RX buffer don't need service yet + // <0=> RX buffer don't need service yet // <1=> RX buffer need service // TX Buffer Empty // <0=> TX buffer have data @@ -383,33 +392,33 @@ typedef struct // <0=> RX buffer not full // <1=> RX buffer full union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR // TX error // <0=> Okay // <1=> TX overrun/underrun // RX error - // <0=> Okay + // <0=> Okay // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR // TX error // <0=> Okay // <1=> Clear TX error // RX error - // <0=> Okay + // <0=> Okay // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel + __O uint32_t TXBUF; // Transmit buffer + // Right channel // Left channel /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel + __I uint32_t RXBUF; // Receive buffer + // Right channel // Left channel uint32_t RESERVED1[186]; __IO uint32_t ITCR; // Integration Test Control Register @@ -556,7 +565,12 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */ #define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */ #define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */ +#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */ +#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */ +#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */ #define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */ +#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */ +#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */ #define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */ #ifdef CORTEX_M7 @@ -565,8 +579,8 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */ #endif -#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */ #define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */ +#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */ /******************************************************************************/ /* Peripheral declaration */ @@ -575,11 +589,16 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE ) #define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE ) #define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE ) +#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE ) +#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE ) #define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE ) #define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE ) #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct index 24f887bcd99..625a92a2db6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct @@ -1,33 +1,33 @@ ;* MPS2 CMSIS Library ;* -;* Copyright (c) 2006-2015 ARM Limited +;* Copyright (c) 2006-2016 ARM Limited ;* All rights reserved. -;* -;* Redistribution and use in source and binary forms, with or without +;* +;* Redistribution and use in source and binary forms, with or without ;* modification, are permitted provided that the following conditions are met: -;* -;* 1. Redistributions of source code must retain the above copyright notice, +;* +;* 1. Redistributions of source code must retain the above copyright notice, ;* this list of conditions and the following disclaimer. -;* -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation +;* +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation ;* and/or other materials provided with the distribution. -;* -;* 3. Neither the name of the copyright holder nor the names of its contributors -;* may be used to endorse or promote products derived from this software without +;* +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software without ;* specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -;* POSSIBILITY OF SUCH DAMAGE. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +;* POSSIBILITY OF SUCH DAMAGE. ;* ; ************************************************************* ; *** Scatter-Loading Description File *** @@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM - RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data + ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM + RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data .ANY (+RW +ZI) } } diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/startup_MPS2.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/startup_MPS2.s index e67bee5a75e..282a0820574 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/startup_MPS2.s +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/startup_MPS2.s @@ -1,43 +1,42 @@ -;/**************************************************************************//** -; * @file startup_CMSDK_CM3.s -; * @brief CMSIS Core Device Startup File for -; * CMSDK_CM3 Device -; * @version V3.02 -; * @date 15. November 2013 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; ******************************************************************************/ -;/* Copyright (c) 2011 - 2013 ARM LIMITED +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM3.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM3 Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ ; Stack Configuration @@ -108,22 +107,22 @@ __Vectors DCD __initial_sp ; Top of Stack DCD ETHERNET_Handler ; Ethernet Overflow Handler DCD I2S_Handler ; I2S Handler DCD TSC_Handler ; Touch Screen handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler - DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler - DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler - DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler - DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler - DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler - DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler - DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler - DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors @@ -205,6 +204,14 @@ Default_Handler PROC EXPORT ETHERNET_Handler [WEAK] EXPORT I2S_Handler [WEAK] EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] EXPORT PORT0_0_Handler [WEAK] EXPORT PORT0_1_Handler [WEAK] EXPORT PORT0_2_Handler [WEAK] @@ -213,14 +220,6 @@ Default_Handler PROC EXPORT PORT0_5_Handler [WEAK] EXPORT PORT0_6_Handler [WEAK] EXPORT PORT0_7_Handler [WEAK] - EXPORT PORT0_8_Handler [WEAK] - EXPORT PORT0_9_Handler [WEAK] - EXPORT PORT0_10_Handler [WEAK] - EXPORT PORT0_11_Handler [WEAK] - EXPORT PORT0_12_Handler [WEAK] - EXPORT PORT0_13_Handler [WEAK] - EXPORT PORT0_14_Handler [WEAK] - EXPORT PORT0_15_Handler [WEAK] UARTRX0_Handler UARTTX0_Handler @@ -238,22 +237,22 @@ UARTOVF_Handler ETHERNET_Handler I2S_Handler TSC_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler -PORT0_8_Handler -PORT0_9_Handler -PORT0_10_Handler -PORT0_11_Handler -PORT0_12_Handler -PORT0_13_Handler -PORT0_14_Handler -PORT0_15_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler B . ENDP diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h index fa013eff79c..9f5e1923768 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * A generic CMSIS include header, pulling in MPS2 specifics *******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.c index f42fb77ad22..9ac558cceb3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.c @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * CMSIS-style functionality to support dynamic vectors *******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.h index 3d3a3e2fd99..8ad5fdcd634 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.h @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * CMSIS-style functionality to support dynamic vectors *******************************************************************************/ @@ -37,7 +37,7 @@ #include "cmsis.h" -#define NVIC_NUM_VECTORS (16 + 32) +#define NVIC_NUM_VECTORS (16 + 48) #define NVIC_USER_IRQ_OFFSET 16 #ifdef __cplusplus diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/peripherallink.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/peripherallink.h index 94c315ae03f..80541d90d31 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/peripherallink.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/peripherallink.h @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * Name: Device.h * Purpose: Include the correct device header file diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.c index cef3beecb76..06ee46c7104 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.c +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.c @@ -1,41 +1,37 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * @file system_CMSDK_CM3.c * @brief CMSIS Device System Source File for * CMSDK_M3 Device -* @version V3.02 -* @date 15. November 2013 -* -* @note * *******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.h index 7581fd5b639..15b2192f35b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.h @@ -1,42 +1,38 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. * ******************************************************************************* * @file system_CMSDK_CM3.h * @brief CMSIS Device Peripheral Access Layer Header File for * CMSDK_CM3 Device -* @version V3.02 -* @date 15. March 2013 -* -* @note * ******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h index 6e2c0a5f6ee..ca7b64a7ac2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h @@ -1,41 +1,37 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * @file CMSDK_CM4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for * Device CMSDK_CM4 -* @version V3.01 -* @date 06. March 2012 -* -* @note configured for CM7 without FPU * *******************************************************************************/ @@ -45,80 +41,57 @@ #ifdef __cplusplus extern "C" { -#endif - -/** @addtogroup CMSDK_CM4_Definitions CMSDK_CM4 Definitions - This file defines all structures and symbols for CMSDK_CM4: - - registers and bitfields - - peripheral base address - - peripheral ID - - Peripheral definitions - @{ -*/ +#endif -/******************************************************************************/ -/* Processor and Core Peripherals */ -/******************************************************************************/ -/** @addtogroup CMSDK_CM4_CMSIS Device CMSIS Definitions - Configuration of the Cortex-M4 Processor and Core Peripherals - @{ -*/ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ +/* ------------------------- Interrupt Number Definition ------------------------ */ typedef enum IRQn { -/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ - -/****** CMSDK Specific Interrupt Numbers *******************************************************/ - UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ - UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ - UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ - UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ - UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ - UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ -// UARTRX3_IRQn = 6, /*!< UART 2 RX Interrupt //only used in extended version */ -// UARTTX3_IRQn = 7, /*!< UART 2 TX Interrupt //only used in extended version */ - PORT0_ALL_IRQn = 6, /*!< Port 1 combined Interrupt */ - PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ - TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ - TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ - DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ - SPI_IRQn = 11, /*!< SPI Interrupt */ - UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ - ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ - I2S_IRQn = 14, /*!< I2S Interrupt */ - TSC_IRQn = 15, /* Touch Screen Interrupt */ -// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */ - PORT0_0_IRQn = 16, /*!< All P0 I/O pins can be used as interrupt source. */ - PORT0_1_IRQn = 17, /*!< There are 16 pins in total */ - PORT0_2_IRQn = 18, - PORT0_3_IRQn = 19, - PORT0_4_IRQn = 20, - PORT0_5_IRQn = 21, - PORT0_6_IRQn = 22, - PORT0_7_IRQn = 23, - PORT0_8_IRQn = 24, - PORT0_9_IRQn = 25, - PORT0_10_IRQn = 26, - PORT0_11_IRQn = 27, - PORT0_12_IRQn = 28, - PORT0_13_IRQn = 29, - PORT0_14_IRQn = 30, - PORT0_15_IRQn = 31, +/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/****** CMSDK Specific Interrupt Numbers *********************************************************/ + UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */ + SPI_IRQn = 11, /*!< SPI Interrupt */ + UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */ + I2S_IRQn = 14, /*!< I2S Interrupt */ + TSC_IRQn = 15, /*!< Touch Screen Interrupt */ + PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */ } IRQn_Type; @@ -285,23 +258,23 @@ typedef struct __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ - // TimerEn: Timer Enable - // TimerMode: Timer Mode - // <0=> Freerunning-mode - // <1=> Periodic mode - // IntEnable: Interrupt Enable - // TimerPre: Timer Prescale - // <0=> / 1 - // <1=> / 16 - // <2=> / 256 - // <3=> Undefined! - // TimerSize: Timer Size - // <0=> 16-bit counter - // <1=> 32-bit counter - // OneShot: One-shoot mode - // <0=> Wrapping mode - // <1=> One-shot mode - // + /* TimerEn: Timer Enable */ + /* TimerMode: Timer Mode */ + /* <0=> Freerunning-mode */ + /* <1=> Periodic mode */ + /* IntEnable: Interrupt Enable */ + /* TimerPre: Timer Prescale */ + /* <0=> / 1 */ + /* <1=> / 16 */ + /* <2=> / 256 */ + /* <3=> Undefined! */ + /* TimerSize: Timer Size */ + /* <0=> 16-bit counter */ + /* <1=> 32-bit counter */ + /* OneShot: One-shoot mode */ + /* <0=> Wrapping mode */ + /* <1=> One-shot mode */ + /* */ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ @@ -310,23 +283,23 @@ typedef struct __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ - // TimerEn: Timer Enable - // TimerMode: Timer Mode - // <0=> Freerunning-mode - // <1=> Periodic mode - // IntEnable: Interrupt Enable - // TimerPre: Timer Prescale - // <0=> / 1 - // <1=> / 16 - // <2=> / 256 - // <3=> Undefined! - // TimerSize: Timer Size - // <0=> 16-bit counter - // <1=> 32-bit counter - // OneShot: One-shoot mode - // <0=> Wrapping mode - // <1=> One-shot mode - // + /* TimerEn: Timer Enable */ + /* TimerMode: Timer Mode */ + /* <0=> Freerunning-mode */ + /* <1=> Periodic mode */ + /* IntEnable: Interrupt Enable */ + /* TimerPre: Timer Prescale */ + /* <0=> / 1 */ + /* <1=> / 16 */ + /* <2=> / 256 */ + /* <3=> Undefined! */ + /* TimerSize: Timer Size */ + /* <0=> 16-bit counter */ + /* <1=> 32-bit counter */ + /* OneShot: One-shoot mode */ + /* <0=> Wrapping mode */ + /* <1=> One-shot mode */ + /* */ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ @@ -413,23 +386,23 @@ typedef struct __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ - // TimerEn: Timer Enable - // TimerMode: Timer Mode - // <0=> Freerunning-mode - // <1=> Periodic mode - // IntEnable: Interrupt Enable - // TimerPre: Timer Prescale - // <0=> / 1 - // <1=> / 16 - // <2=> / 256 - // <3=> Undefined! - // TimerSize: Timer Size - // <0=> 16-bit counter - // <1=> 32-bit counter - // OneShot: One-shoot mode - // <0=> Wrapping mode - // <1=> One-shot mode - // + /* TimerEn: Timer Enable */ + /* TimerMode: Timer Mode */ + /* <0=> Freerunning-mode */ + /* <1=> Periodic mode */ + /* IntEnable: Interrupt Enable */ + /* TimerPre: Timer Prescale */ + /* <0=> / 1 */ + /* <1=> / 16 */ + /* <2=> / 256 */ + /* <3=> Undefined! */ + /* TimerSize: Timer Size */ + /* <0=> 16-bit counter */ + /* <1=> 32-bit counter */ + /* OneShot: One-shoot mode */ + /* <0=> Wrapping mode */ + /* <1=> One-shot mode */ + /* */ __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ @@ -1146,9 +1119,9 @@ typedef struct __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ - // RESEN: Reset enable - // INTEN: Interrupt enable - // + /* RESEN: Reset enable */ + /* INTEN: Interrupt enable */ + /* */ __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ @@ -1278,8 +1251,9 @@ __IO uint32_t MODECTRL; #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) -//#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) //only used in extended version +#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) +#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL) #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) /* AHB peripherals */ @@ -1301,9 +1275,10 @@ __IO uint32_t MODECTRL; #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) -//#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) //only used in extended version -#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) -#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) +#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) +#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE ) +#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) +#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h index 910d5abd977..3b514302355 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h @@ -1,36 +1,36 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * File: smm_mps2.h -* Release: Version 1.0 +* Release: Version 1.1 *******************************************************************************/ #ifndef __SMM_MPS2_H @@ -46,7 +46,7 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct +typedef struct { __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections // [31:2] : Reserved @@ -65,11 +65,14 @@ typedef struct // Bit[31:0] : reload value for prescale counter __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. uint32_t RESERVED4[9]; __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:7] : Reserved + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS // [6] : CLCD_BL_CTRL // [5] : CLCD_RD // [4] : CLCD_RS @@ -93,12 +96,18 @@ typedef struct #define CLCD_RD_Msk (1UL< Undefined! // <5=> Undefined! // <6=> Undefined! - // <7=> Undefined! + // <7=> Undefined! // RX Buffer Water Level // <0=> Undefined! // <1=> / IRQ triggers when less than 1 space available @@ -355,7 +364,7 @@ typedef struct // <4=> / IRQ triggers when less than 4 space available // <5=> Undefined! // <6=> Undefined! - // <7=> Undefined! + // <7=> Undefined! // FIFO reset // <0=> Normal operation // <1=> FIFO reset @@ -363,12 +372,12 @@ typedef struct // <0=> Normal operation // <1=> Assert audio Codec reset /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS + __I uint32_t STATUS; // STATUS // TX Buffer alert // <0=> TX buffer don't need service yet // <1=> TX buffer need service // RX Buffer alert - // <0=> RX buffer don't need service yet + // <0=> RX buffer don't need service yet // <1=> RX buffer need service // TX Buffer Empty // <0=> TX buffer have data @@ -383,33 +392,33 @@ typedef struct // <0=> RX buffer not full // <1=> RX buffer full union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR // TX error // <0=> Okay // <1=> TX overrun/underrun // RX error - // <0=> Okay + // <0=> Okay // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR // TX error // <0=> Okay // <1=> Clear TX error // RX error - // <0=> Okay + // <0=> Okay // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel + __O uint32_t TXBUF; // Transmit buffer + // Right channel // Left channel /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel + __I uint32_t RXBUF; // Receive buffer + // Right channel // Left channel uint32_t RESERVED1[186]; __IO uint32_t ITCR; // Integration Test Control Register @@ -556,7 +565,12 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */ #define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */ #define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */ +#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */ +#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */ +#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */ #define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */ +#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */ +#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */ #define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */ #ifdef CORTEX_M7 @@ -565,8 +579,8 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */ #endif -#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */ #define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */ +#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */ /******************************************************************************/ /* Peripheral declaration */ @@ -575,11 +589,16 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) #define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE ) #define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE ) #define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE ) +#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE ) +#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE ) #define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE ) #define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE ) #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct index 24f887bcd99..625a92a2db6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct @@ -1,33 +1,33 @@ ;* MPS2 CMSIS Library ;* -;* Copyright (c) 2006-2015 ARM Limited +;* Copyright (c) 2006-2016 ARM Limited ;* All rights reserved. -;* -;* Redistribution and use in source and binary forms, with or without +;* +;* Redistribution and use in source and binary forms, with or without ;* modification, are permitted provided that the following conditions are met: -;* -;* 1. Redistributions of source code must retain the above copyright notice, +;* +;* 1. Redistributions of source code must retain the above copyright notice, ;* this list of conditions and the following disclaimer. -;* -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation +;* +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation ;* and/or other materials provided with the distribution. -;* -;* 3. Neither the name of the copyright holder nor the names of its contributors -;* may be used to endorse or promote products derived from this software without +;* +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software without ;* specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -;* POSSIBILITY OF SUCH DAMAGE. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +;* POSSIBILITY OF SUCH DAMAGE. ;* ; ************************************************************* ; *** Scatter-Loading Description File *** @@ -39,8 +39,8 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - ; Total: 48 vectors = 192 bytes (0x0C0) to be reserved in RAM - RW_IRAM1 (0x20000000+0xC0) (0x400000-0xC0) { ; RW data + ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM + RW_IRAM1 (0x20000000+0x100) (0x400000-0x100) { ; RW data .ANY (+RW +ZI) } } diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/startup_MPS2.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/startup_MPS2.s index 53fc0f0a55f..29a1f3285f3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/startup_MPS2.s +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/startup_MPS2.s @@ -1,41 +1,38 @@ ; MPS2 CMSIS Library ; -; Copyright (c) 2006-2015 ARM Limited +; Copyright (c) 2006-2016 ARM Limited ; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without +; +; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, +; +; 1. Redistributions of source code must retain the above copyright notice, ; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation ; and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without ; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. ;****************************************************************************** ; @file startup_CMSDK_CM4.s ; @brief CMSIS Core Device Startup File for ; CMSDK_CM4 Device -; @version V3.03 -; @date 04. February 2015 ; -; @note ;****************************************************************************** ; ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ @@ -110,22 +107,22 @@ __Vectors DCD __initial_sp ; Top of Stack DCD ETHERNET_Handler ; Ethernet Overflow Handler DCD I2S_Handler ; I2S Handler DCD TSC_Handler ; Touch Screen handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler - DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler - DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler - DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler - DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler - DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler - DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler - DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler - DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors @@ -207,6 +204,14 @@ Default_Handler PROC EXPORT ETHERNET_Handler [WEAK] EXPORT I2S_Handler [WEAK] EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] EXPORT PORT0_0_Handler [WEAK] EXPORT PORT0_1_Handler [WEAK] EXPORT PORT0_2_Handler [WEAK] @@ -215,14 +220,6 @@ Default_Handler PROC EXPORT PORT0_5_Handler [WEAK] EXPORT PORT0_6_Handler [WEAK] EXPORT PORT0_7_Handler [WEAK] - EXPORT PORT0_8_Handler [WEAK] - EXPORT PORT0_9_Handler [WEAK] - EXPORT PORT0_10_Handler [WEAK] - EXPORT PORT0_11_Handler [WEAK] - EXPORT PORT0_12_Handler [WEAK] - EXPORT PORT0_13_Handler [WEAK] - EXPORT PORT0_14_Handler [WEAK] - EXPORT PORT0_15_Handler [WEAK] UARTRX0_Handler UARTTX0_Handler @@ -240,22 +237,22 @@ UARTOVF_Handler ETHERNET_Handler I2S_Handler TSC_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler -PORT0_8_Handler -PORT0_9_Handler -PORT0_10_Handler -PORT0_11_Handler -PORT0_12_Handler -PORT0_13_Handler -PORT0_14_Handler -PORT0_15_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler B . ENDP diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h index 8ac8c691a2d..562e9abd116 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * A generic CMSIS include header, pulling in MPS2 specifics *******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.c index f42fb77ad22..9ac558cceb3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.c @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * CMSIS-style functionality to support dynamic vectors *******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.h index 3d3a3e2fd99..8ad5fdcd634 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.h @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * CMSIS-style functionality to support dynamic vectors *******************************************************************************/ @@ -37,7 +37,7 @@ #include "cmsis.h" -#define NVIC_NUM_VECTORS (16 + 32) +#define NVIC_NUM_VECTORS (16 + 48) #define NVIC_USER_IRQ_OFFSET 16 #ifdef __cplusplus diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/peripherallink.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/peripherallink.h index 94c315ae03f..80541d90d31 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/peripherallink.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/peripherallink.h @@ -1,33 +1,33 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * Name: Device.h * Purpose: Include the correct device header file diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.c index a2c37a4105d..2b528a92c49 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.c +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.c @@ -1,46 +1,41 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * @file system_CMSDK_CM4.c * @brief CMSIS Device System Source File for * CMSDK_M4 Device -* @version V3.02 -* @date 15. November 2013 -* -* @note * *******************************************************************************/ - #include "CMSDK_CM4.h" /*---------------------------------------------------------------------------- diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.h index b71521e761a..c1cb7e25fcc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.h @@ -1,42 +1,38 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. * ******************************************************************************* * @file system_CMSDK_CM4.h * @brief CMSIS Device Peripheral Access Layer Header File for * CMSDK_CM4 Device -* @version V3.02 -* @date 15. March 2013 -* -* @note * ******************************************************************************/ @@ -76,5 +72,4 @@ extern void SystemCoreClockUpdate (void); #ifdef __cplusplus } #endif - #endif /* SYSTEM_CMSDK_CM4_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h index ec6cbf16ea7..bccd748bc82 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h @@ -1,6 +1,6 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,10 +32,6 @@ * @file CMSDK_CM7.h * @brief CMSIS Core Peripheral Access Layer Header File for * CMSDK_CM7 Device -* @version V1.00 -* @date 27. August 2014 -* -* @note configured for CM7 without FPU * *******************************************************************************/ @@ -52,16 +48,16 @@ extern "C" { typedef enum IRQn { -/* ------------------- CM7 Processor Exceptions Numbers --------------------- */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ -// HardFault_IRQn = -13, /* 3 HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ +/* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ /* ---------------------- CMSDK_CM7 Specific Interrupt Numbers -------------- */ UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ @@ -80,23 +76,22 @@ typedef enum IRQn ETHERNET_IRQn = 13, /* Ethernet Interrupt */ I2S_IRQn = 14, /* I2S Interrupt */ TSC_IRQn = 15, /* Touch Screen Interrupt */ -// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */ - PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */ - PORT0_1_IRQn = 17, /* There are 16 pins in total */ - PORT0_2_IRQn = 18, - PORT0_3_IRQn = 19, - PORT0_4_IRQn = 20, - PORT0_5_IRQn = 21, - PORT0_6_IRQn = 22, - PORT0_7_IRQn = 23, - PORT0_8_IRQn = 24, - PORT0_9_IRQn = 25, - PORT0_10_IRQn = 26, - PORT0_11_IRQn = 27, - PORT0_12_IRQn = 28, - PORT0_13_IRQn = 29, - PORT0_14_IRQn = 30, - PORT0_15_IRQn = 31, + PORT2_ALL_IRQn = 16, /*< Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 17, /*< Port 3 combined Interrupt */ + UARTRX3_IRQn = 18, /*< UART 3 RX Interrupt */ + UARTTX3_IRQn = 19, /*< UART 3 TX Interrupt */ + UARTRX4_IRQn = 20, /*< UART 4 RX Interrupt */ + UARTTX4_IRQn = 21, /*< UART 4 TX Interrupt */ + ADCSPI_IRQn = 22, /*< SHIELD ADC SPI Interrupt */ + SHIELDSPI_IRQn = 23, /*< SHIELD SPI Combined Interrupt */ + PORT0_0_IRQn = 24, /*< GPIO Port 0 pin 0 Interrupt */ + PORT0_1_IRQn = 25, /*< GPIO Port 0 pin 1 Interrupt */ + PORT0_2_IRQn = 26, /*< GPIO Port 0 pin 2 Interrupt */ + PORT0_3_IRQn = 27, /*< GPIO Port 0 pin 3 Interrupt */ + PORT0_4_IRQn = 28, /*< GPIO Port 0 pin 4 Interrupt */ + PORT0_5_IRQn = 29, /*< GPIO Port 0 pin 5 Interrupt */ + PORT0_6_IRQn = 30, /*< GPIO Port 0 pin 6 Interrupt */ + PORT0_7_IRQn = 31, /*< GPIO Port 0 pin 7 Interrupt */ } IRQn_Type; @@ -105,12 +100,12 @@ typedef enum IRQn /* ================================================================================ */ /* -------- Configuration of the CM7 Processor and Core Peripherals --------- */ -#define __CM4_REV 0x0000 /* Core revision r0p0 */ +#define __CM7_REV 0x0101 /* Core revision r1p1 */ #define __MPU_PRESENT 1 /* MPU present or not */ #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1 /* no FPU present */ -#define __FPU_DP 1 /* unused */ +#define __FPU_DP 1 /* unused */ #define __ICACHE_PRESENT 1 #define __DCACHE_PRESENT 1 @@ -694,7 +689,9 @@ typedef struct #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) +#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL) #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) /* AHB peripherals */ @@ -712,6 +709,8 @@ typedef struct #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) +#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) +#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE ) #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h index a7a3bc1cc62..068ae8a7094 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h @@ -1,6 +1,6 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,7 +30,7 @@ * POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * File: smm_mps2.h -* Release: Version 1.0 +* Release: Version 1.1 *******************************************************************************/ #ifndef __SMM_MPS2_H @@ -69,7 +69,10 @@ typedef struct // The pre-scaler counter is reloaded with PRESCALE after reaching 0. uint32_t RESERVED4[9]; __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:7] : Reserved + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS // [6] : CLCD_BL_CTRL // [5] : CLCD_RD // [4] : CLCD_RS @@ -93,6 +96,12 @@ typedef struct #define CLCD_RD_Msk (1UL<>> ------------------ @@ -110,22 +107,22 @@ __Vectors DCD __initial_sp ; Top of Stack DCD ETHERNET_Handler ; Ethernet Overflow Handler DCD I2S_Handler ; I2S Handler DCD TSC_Handler ; Touch Screen handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler - DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler - DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler - DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler - DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler - DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler - DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler - DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler - DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors @@ -207,6 +204,14 @@ Default_Handler PROC EXPORT ETHERNET_Handler [WEAK] EXPORT I2S_Handler [WEAK] EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] EXPORT PORT0_0_Handler [WEAK] EXPORT PORT0_1_Handler [WEAK] EXPORT PORT0_2_Handler [WEAK] @@ -215,14 +220,6 @@ Default_Handler PROC EXPORT PORT0_5_Handler [WEAK] EXPORT PORT0_6_Handler [WEAK] EXPORT PORT0_7_Handler [WEAK] - EXPORT PORT0_8_Handler [WEAK] - EXPORT PORT0_9_Handler [WEAK] - EXPORT PORT0_10_Handler [WEAK] - EXPORT PORT0_11_Handler [WEAK] - EXPORT PORT0_12_Handler [WEAK] - EXPORT PORT0_13_Handler [WEAK] - EXPORT PORT0_14_Handler [WEAK] - EXPORT PORT0_15_Handler [WEAK] UARTRX0_Handler UARTTX0_Handler @@ -240,22 +237,22 @@ UARTOVF_Handler ETHERNET_Handler I2S_Handler TSC_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler -PORT0_8_Handler -PORT0_9_Handler -PORT0_10_Handler -PORT0_11_Handler -PORT0_12_Handler -PORT0_13_Handler -PORT0_14_Handler -PORT0_15_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler B . ENDP diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/gcc_arm.ld b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/gcc_arm.ld deleted file mode 100644 index cf28eac6bc3..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/gcc_arm.ld +++ /dev/null @@ -1,195 +0,0 @@ -/* Linker script to configure memory regions. */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */ - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */ -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/startup_ARMCM7.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/startup_ARMCM7.s deleted file mode 100644 index 0d49a64b356..00000000000 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/startup_ARMCM7.s +++ /dev/null @@ -1,314 +0,0 @@ -/* File: startup_ARMCM7.S - * Purpose: startup file for Cortex-M7 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.00 - * Date: 22 August 2014 - * - */ -/* Copyright (c) 2011 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - - .syntax unified - .arch armv7-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x00000400 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x00000C00 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long WDT_IRQHandler /* 0: Watchdog Timer */ - .long RTC_IRQHandler /* 1: Real Time Clock */ - .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */ - .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */ - .long MCIA_IRQHandler /* 4: MCIa */ - .long MCIB_IRQHandler /* 5: MCIb */ - .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */ - .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */ - .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */ - .long UART4_IRQHandler /* 9: UART4 - not connected */ - .long AACI_IRQHandler /* 10: AACI / AC97 */ - .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */ - .long ENET_IRQHandler /* 12: Ethernet */ - .long USBDC_IRQHandler /* 13: USB Device */ - .long USBHC_IRQHandler /* 14: USB Host Controller */ - .long CHLCD_IRQHandler /* 15: Character LCD */ - .long FLEXRAY_IRQHandler /* 16: Flexray */ - .long CAN_IRQHandler /* 17: CAN */ - .long LIN_IRQHandler /* 18: LIN */ - .long I2C_IRQHandler /* 19: I2C ADC/DAC */ - .long 0 /* 20: Reserved */ - .long 0 /* 21: Reserved */ - .long 0 /* 22: Reserved */ - .long 0 /* 23: Reserved */ - .long 0 /* 24: Reserved */ - .long 0 /* 25: Reserved */ - .long 0 /* 26: Reserved */ - .long 0 /* 27: Reserved */ - .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */ - .long 0 /* 29: Reserved - CPU FPGA */ - .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */ - .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ - - .size __Vectors, . - __Vectors - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - -#ifndef __NO_SYSTEM_INIT - bl SystemInit -#endif - -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - def_irq_handler HardFault_Handler - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler WDT_IRQHandler - def_irq_handler RTC_IRQHandler - def_irq_handler TIM0_IRQHandler - def_irq_handler TIM2_IRQHandler - def_irq_handler MCIA_IRQHandler - def_irq_handler MCIB_IRQHandler - def_irq_handler UART0_IRQHandler - def_irq_handler UART1_IRQHandler - def_irq_handler UART2_IRQHandler - def_irq_handler UART3_IRQHandler - def_irq_handler UART4_IRQHandler - def_irq_handler AACI_IRQHandler - def_irq_handler CLCD_IRQHandler - def_irq_handler ENET_IRQHandler - def_irq_handler USBDC_IRQHandler - def_irq_handler USBHC_IRQHandler - def_irq_handler CHLCD_IRQHandler - def_irq_handler FLEXRAY_IRQHandler - def_irq_handler CAN_IRQHandler - def_irq_handler LIN_IRQHandler - def_irq_handler I2C_IRQHandler - def_irq_handler CPU_CLCD_IRQHandler - def_irq_handler SPI_IRQHandler - - .end diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis_nvic.h index 3d3a3e2fd99..04f376f4e40 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis_nvic.h @@ -37,7 +37,7 @@ #include "cmsis.h" -#define NVIC_NUM_VECTORS (16 + 32) +#define NVIC_NUM_VECTORS (16 + 48) #define NVIC_USER_IRQ_OFFSET 16 #ifdef __cplusplus diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.c index 975e536c564..0424906a538 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.c +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.c @@ -1,6 +1,6 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,10 +32,6 @@ * @file system_CMSDK_CM7.c * @brief CMSIS Device System Source File for * CMSDK_CM7 Device -* @version V1.00 -* @date 27. August 2014 -* -* @note * *******************************************************************************/ @@ -64,6 +60,9 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/* System Core Clock Frequency */ +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ /** * Update SystemCoreClock variable * diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.h index 6992de1ddf7..09301b37ed7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.h +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.h @@ -1,6 +1,6 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -33,10 +33,6 @@ * @file system_CMSDK_CM7.h * @brief CMSIS Device Peripheral Access Layer Header File for * CMSDK_CM7 Device -* @version V1.00 -* @date 27. August 2014 -* -* @note * ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PeripheralNames.h index 5664025837d..db572f47ff7 100644 --- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PeripheralNames.h @@ -24,12 +24,16 @@ extern "C" { typedef enum { UART_0 = (int)CMSDK_UART0_BASE, - UART_1 = (int)CMSDK_UART1_BASE + UART_1 = (int)CMSDK_UART1_BASE, + UART_2 = (int)CMSDK_UART3_BASE, + UART_3 = (int)CMSDK_UART4_BASE } UARTName; typedef enum { - I2C_0 = (int)MPS2_TS_I2C, - I2C_1 = (int)MPS2_AAIC_I2C + I2C_0 = (int)MPS2_TSC_I2C_BASE, + I2C_1 = (int)MPS2_AAIC_I2C_BASE, + I2C_2 = (int)MPS2_SHIELD0_I2C_BASE, + I2C_3 = (int)MPS2_SHIELD1_I2C_BASE } I2CName; @@ -41,12 +45,19 @@ typedef enum { ADC0_4, ADC0_5, ADC0_6, - ADC0_7 + ADC0_7, + ADC0_8, + ADC0_9, + ADC0_10, + ADC0_11 } ADCName; typedef enum { - SPI_0 = (int)MPS2_SSP1, - SPI_1 = (int)MPS2_SSP0 + SPI_0 = (int)MPS2_SSP1_BASE, + SPI_1 = (int)MPS2_SSP0_BASE, + SPI_2 = (int)MPS2_SSP2_BASE, + SPI_3 = (int)MPS2_SSP3_BASE, + SPI_4 = (int)MPS2_SSP4_BASE } SPIName; typedef enum { @@ -68,8 +79,9 @@ typedef enum { #define STDIO_UART UART_0 #define MBED_UART0 USBTX, USBRX -#define MBED_UART1 UART_TX1, UART_RX1 -#define MBED_UART2 UART_TX2, UART_RX2 +#define MBED_UART1 XB_TX, XB_RX +#define MBED_UART2 SH0_TX, SH0_RX +#define MBED_UART3 SH1_TX, SH1_RX #define MBED_UARTUSB USBTX, USBRX #ifdef __cplusplus diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h index 453aa53c1a8..ca27a4d4727 100644 --- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h @@ -131,20 +131,95 @@ typedef enum { CLCD_RD = 310, CLCD_BL_CTRL = 311, + //MPS2 shield 0 SPI + SHIELD_0_SPI_SCK = 320, + SHIELD_0_SPI_MOSI = 321, + SHIELD_0_SPI_MISO = 322, + SHIELD_0_SPI_nCS = 323, + + //MPS2 shield 1 SPI + SHIELD_1_SPI_SCK = 331, + SHIELD_1_SPI_MOSI = 332, + SHIELD_1_SPI_MISO = 333, + SHIELD_1_SPI_nCS = 334, + + //MPS2 shield ADC SPI + ADC_MOSI = 650, + ADC_MISO = 651, + ADC_SCLK = 652, + ADC_SSEL = 653, //MPS2 Uart USBTX = 400, USBRX = 401, - UART_TX1 = 402, - UART_RX1 = 403, + XB_TX = 402, + XB_RX = 403, UART_TX2 = 404, UART_RX2 = 405, + SH0_TX = 406, + SH0_RX = 407, + SH1_TX = 408, + SH1_RX = 409, //MPS2 I2C touchscreen and audio TSC_SDA = 500, TSC_SCL = 501, AUD_SDA = 502, AUD_SCL = 503, + + //MPS2 I2C for shield + SHIELD_0_SDA = 504, + SHIELD_0_SCL = 505, + SHIELD_1_SDA = 506, + SHIELD_1_SCL = 507, + + //MPS2 shield Analog pins + A0_0 = 600, + A0_1 = 601, + A0_2 = 602, + A0_3 = 603, + A0_4 = 604, + A0_5 = 605, + A1_0 = 606, + A1_1 = 607, + A1_2 = 608, + A1_3 = 609, + A1_4 = 610, + A1_5 = 611, + //MPS2 Shield Digital pins + D0_0 = EXP0, + D0_1 = EXP4, + D0_2 = EXP2, + D0_3 = EXP3, + D0_4 = EXP1, + D0_5 = EXP6, + D0_6 = EXP7, + D0_7 = EXP8, + D0_8 = EXP9, + D0_9 = EXP10, + D0_10 = EXP12, + D0_11 = EXP13, + D0_12 = EXP14, + D0_13 = EXP11, + D0_14 = EXP15, + D0_15 = EXP5, + + D1_0 = EXP26, + D1_1 = EXP30, + D1_2 = EXP28, + D1_3 = EXP29, + D1_4 = EXP27, + D1_5 = EXP32, + D1_6 = EXP33, + D1_7 = EXP34, + D1_8 = EXP35, + D1_9 = EXP36, + D1_10 = EXP38, + D1_11 = EXP39, + D1_12 = EXP40, + D1_13 = EXP44, + D1_14 = EXP41, + D1_15 = EXP31, // Not connected NC = (int)0xFFFFFFFF, diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c index d2d703ae513..eaa00e8d246 100644 --- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c @@ -35,9 +35,8 @@ */ #include - +#include "wait_api.h" #include "ETH_MPS2.h" -#include "fpga.h" // SMSC9220 low-level operations unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data) @@ -58,7 +57,7 @@ unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data) timedout = 50; do { val = SMSC9220->BYTE_TEST; // A no-op read. - Sleepms(1); + wait_ms(1); //Sleepms(1); timedout--; } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); @@ -92,7 +91,7 @@ unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data) timedout = 50; do { read = SMSC9220->BYTE_TEST; // A no-op read. - Sleepms(1); + wait_ms(1); //Sleepms(1); timedout--; } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); @@ -126,7 +125,7 @@ unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data) val = 0; timedout = 50; do { - Sleepms(1); + wait_ms(1); //Sleepms(1); timedout--; smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val); } while(timedout && (val & ((unsigned int)1 << 0))); @@ -166,7 +165,7 @@ unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data) do { - Sleepms(1); + wait_ms(1); //Sleepms(1); timedout--; smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd); } while(timedout && (phycmd & (1 << 0))); @@ -197,7 +196,7 @@ unsigned int smsc9220_soft_reset(void) SMSC9220->HW_CFG |= 1; do { - Sleepms(1); + wait_ms(1); //Sleepms(1); timedout--; } while(timedout && (SMSC9220->HW_CFG & 1)); @@ -224,7 +223,7 @@ unsigned int smsc9220_wait_eeprom(void) timedout = 50; do { - Sleepms(1); + wait_ms(1); //Sleepms(1); timedout--; } while(timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31))); diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.c index 44fad222c49..54028f13a2a 100644 --- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.c +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.c @@ -89,6 +89,45 @@ int smsc9220_check_macaddress(void) return error; } +void smsc9220_print_mac_registers() +{ + unsigned int read; + int i; + + i = 0; + read = 0; + + for(i = 1; i <= 0xC; i++) { + smsc9220_mac_regread(i, &read); + } + return; +} + + +void smsc9220_print_phy_registers() +{ + unsigned short read; + unsigned int i; + + i = 0; + read = 0; + for(i = 0; i <= 6; i++) { + smsc9220_phy_regread(i, &read); + } + smsc9220_phy_regread(i = 17, &read); + + smsc9220_phy_regread(i = 18, &read); + + smsc9220_phy_regread(i = 27, &read); + + smsc9220_phy_regread(i = 29, &read); + + smsc9220_phy_regread(i = 30, &read); + + smsc9220_phy_regread(i = 31, &read); + + return; +} /*---------------------------------------------------------------------------- Ethernet Device initialize diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/device.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/device.h index 32e61e943ed..52cebb2dd84 100644 --- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/device.h +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/device.h @@ -22,7 +22,7 @@ #define DEVICE_INTERRUPTIN 1 -#define DEVICE_ANALOGIN 0 +#define DEVICE_ANALOGIN 1 #define DEVICE_ANALOGOUT 0 #define DEVICE_SERIAL 1 diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c index ce17cbed2ee..cd41a9587d9 100644 --- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c @@ -57,6 +57,12 @@ void gpio_init(gpio_t *obj, PinName pin) { pin_value = pin-305; }else if (pin == 311){ pin_value = pin-305; + }else if (pin == 323){ + pin_value = pin-315; + }else if (pin == 334){ + pin_value = pin-325; + }else if (pin == 653){ + pin_value = pin-646; } obj->mask = 0x1 << pin_value; @@ -96,6 +102,16 @@ void gpio_init(gpio_t *obj, PinName pin) { obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307 }else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){ obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits + }else if (pin == 323 || pin == 334 || pin == 653){ //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653 + obj->reg_data = &MPS2_FPGAIO->MISC; //spi cs bits + } + + if (pin == 323){ + CMSDK_GPIO0->ALTFUNCSET |= 0x1000; + }else if (pin == 334){ + CMSDK_GPIO2->ALTFUNCSET |= 0x0040; + }else if (pin == 653){ + CMSDK_GPIO1->ALTFUNCSET |= 0x0001; } } } diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_object.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_object.h index 8ff7b3a770f..5bbf435fe69 100644 --- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_object.h @@ -37,9 +37,9 @@ typedef struct { } gpio_t; static inline void gpio_write(gpio_t *obj, int value) { - if (value == 1){ + if (value){ *obj->reg_data |= (obj->mask); - } else if (value == 0){ + } else { *obj->reg_data &= ~(obj->mask); } } diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c index 45b5a25c936..58c0c2bc590 100644 --- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c @@ -48,111 +48,161 @@ #define TSC_TSU 15 // Setup delay 600nS min #define AAIC_TSU 25 // Setup delay 1000nS min +#define SHIELD_TSU 25 // Setup delay 1000nS min static const PinMap PinMap_I2C_SDA[] = { {TSC_SDA, I2C_0, 0}, {AUD_SDA, I2C_1, 0}, -// {EXP_SDA, I2C_2, 0}, //only used in extended version + {SHIELD_0_SDA, I2C_2, 0}, + {SHIELD_1_SDA, I2C_3, 0}, {NC , NC , 0} }; static const PinMap PinMap_I2C_SCL[] = { {TSC_SCL, I2C_0, 0}, {AUD_SCL, I2C_1, 0}, -// {EXP_SCL, I2C_2, 0}, //only used in extended version + {SHIELD_0_SCL, I2C_2, 0}, + {SHIELD_1_SCL, I2C_3, 0}, {NC , NC, 0} }; static inline void i2c_send_byte(i2c_t *obj, unsigned char c) { int loop; - switch ((int)obj->i2c) { - case I2C_0: - obj->i2c->CONTROLC = SCL; - i2c_delay(TSC_TSU); - - for (loop = 0; loop < 8; loop++) - { - if (c & (1 << (7 - loop))) - obj->i2c->CONTROLS = SDA; - else - obj->i2c->CONTROLC = SDA; - i2c_delay(TSC_TSU); - obj->i2c->CONTROLS = SCL; - i2c_delay(TSC_TSU); + switch ((int)obj->i2c) { + case I2C_0: obj->i2c->CONTROLC = SCL; i2c_delay(TSC_TSU); - } - - obj->i2c->CONTROLS = SDA; - i2c_delay(TSC_TSU); + + for (loop = 0; loop < 8; loop++) + { + if (c & (1 << (7 - loop))) + obj->i2c->CONTROLS = SDA; + else + obj->i2c->CONTROLC = SDA; + + i2c_delay(TSC_TSU); + obj->i2c->CONTROLS = SCL; + i2c_delay(TSC_TSU); + obj->i2c->CONTROLC = SCL; + i2c_delay(TSC_TSU); + } + + obj->i2c->CONTROLS = SDA; + i2c_delay(TSC_TSU); break; - case I2C_1: - for (loop = 0; loop < 8; loop++) { - i2c_delay(AAIC_TSU); - obj->i2c->CONTROLC = SCL; - i2c_delay(AAIC_TSU); - if (c & (1 << (7 - loop))) - obj->i2c->CONTROLS = SDA; - else - obj->i2c->CONTROLC = SDA; + case I2C_1: + for (loop = 0; loop < 8; loop++) { + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SCL; + i2c_delay(AAIC_TSU); + if (c & (1 << (7 - loop))) + obj->i2c->CONTROLS = SDA; + else + obj->i2c->CONTROLC = SDA; + + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLS = SCL; + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SCL; + } + i2c_delay(AAIC_TSU); - obj->i2c->CONTROLS = SCL; + obj->i2c->CONTROLS = SDA; i2c_delay(AAIC_TSU); + break; + case I2C_2: + case I2C_3: obj->i2c->CONTROLC = SCL; - } - - i2c_delay(AAIC_TSU); - obj->i2c->CONTROLS = SDA; - i2c_delay(AAIC_TSU); - break; + i2c_delay(SHIELD_TSU); + + for (loop = 0; loop < 8; loop++) + { + if (c & (1 << (7 - loop))) + obj->i2c->CONTROLS = SDA; + else + obj->i2c->CONTROLC = SDA; + + i2c_delay(SHIELD_TSU); + obj->i2c->CONTROLS = SCL; + i2c_delay(SHIELD_TSU); + obj->i2c->CONTROLC = SCL; + i2c_delay(SHIELD_TSU); + } + + obj->i2c->CONTROLS = SDA; + i2c_delay(SHIELD_TSU); + break; } } static inline unsigned char i2c_receive_byte(i2c_t *obj) { - int data_receive_byte, loop; - switch ((int)obj->i2c) { - case I2C_0: - obj->i2c->CONTROLS = SDA; - i2c_delay(TSC_TSU); - - data_receive_byte = 0; - - for (loop = 0; loop < 8; loop++) - { - obj->i2c->CONTROLS = SCL; + int data_receive_byte, loop; + switch ((int)obj->i2c) { + case I2C_0: + obj->i2c->CONTROLS = SDA; i2c_delay(TSC_TSU); - if ((obj->i2c->CONTROL & SDA)) - data_receive_byte += (1 << (7 - loop)); - obj->i2c->CONTROLC = SCL; + + data_receive_byte = 0; + + for (loop = 0; loop < 8; loop++) + { + obj->i2c->CONTROLS = SCL; + i2c_delay(TSC_TSU); + if ((obj->i2c->CONTROL & SDA)) + data_receive_byte += (1 << (7 - loop)); + + obj->i2c->CONTROLC = SCL; + i2c_delay(TSC_TSU); + } + + obj->i2c->CONTROLC = SDA; i2c_delay(TSC_TSU); - } - - obj->i2c->CONTROLC = SDA; - i2c_delay(TSC_TSU); break; - case I2C_1: - obj->i2c->CONTROLS = SDA; - data_receive_byte = 0; - - for (loop = 0; loop < 8; loop++) { - i2c_delay(AAIC_TSU); - obj->i2c->CONTROLC = SCL; - i2c_delay(AAIC_TSU); - obj->i2c->CONTROLS = SCL | SDA; + case I2C_1: + obj->i2c->CONTROLS = SDA; + data_receive_byte = 0; + + for (loop = 0; loop < 8; loop++) { + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SCL; + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLS = SCL | SDA; + i2c_delay(AAIC_TSU); + if ((obj->i2c->CONTROL & SDA)) + data_receive_byte += (1 << (7 - loop)); + + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SCL; + } + i2c_delay(AAIC_TSU); - if ((obj->i2c->CONTROL & SDA)) - data_receive_byte += (1 << (7 - loop)); + obj->i2c->CONTROLC = SDA; i2c_delay(AAIC_TSU); - obj->i2c->CONTROLC = SCL; - } - - i2c_delay(AAIC_TSU); - obj->i2c->CONTROLC = SDA; - i2c_delay(AAIC_TSU); - break; + break; + case I2C_2: + case I2C_3: + obj->i2c->CONTROLS = SDA; + i2c_delay(SHIELD_TSU); + + data_receive_byte = 0; + + for (loop = 0; loop < 8; loop++) + { + obj->i2c->CONTROLS = SCL; + i2c_delay(SHIELD_TSU); + if ((obj->i2c->CONTROL & SDA)) + data_receive_byte += (1 << (7 - loop)); + + obj->i2c->CONTROLC = SCL; + i2c_delay(SHIELD_TSU); + } + + obj->i2c->CONTROLC = SDA; + i2c_delay(SHIELD_TSU); + break; } return data_receive_byte; } @@ -160,11 +210,13 @@ static inline unsigned char i2c_receive_byte(i2c_t *obj) static inline int i2c_receive_ack(i2c_t *obj) { int nack; - int delay_value; - switch ((int)obj->i2c) { - case I2C_0: delay_value = TSC_TSU; break; - case I2C_1: delay_value = AAIC_TSU; break; - } + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } i2c_delay(delay_value); obj->i2c->CONTROLS = SDA; @@ -186,13 +238,15 @@ static inline int i2c_receive_ack(i2c_t *obj) } -static inline void i2c_send_ack(i2c_t *obj) +static inline void i2c_send_nack(i2c_t *obj) { - int delay_value; - switch ((int)obj->i2c) { - case I2C_0: delay_value = TSC_TSU; break; - case I2C_1: delay_value = AAIC_TSU; break; - } + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } i2c_delay(delay_value); obj->i2c->CONTROLC = SCL; @@ -208,10 +262,28 @@ static inline void i2c_send_ack(i2c_t *obj) } +static inline void i2c_send_ack(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { - +} +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ // determine the SPI to use I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); @@ -223,59 +295,73 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { pinmap_pinout(sda, PinMap_I2C_SDA); pinmap_pinout(scl, PinMap_I2C_SCL); + + switch ((int)obj->i2c) { + case I2C_2: CMSDK_GPIO0->ALTFUNCSET |= 0x8020; break; + case I2C_3: CMSDK_GPIO1->ALTFUNCSET |= 0x8000; + CMSDK_GPIO2->ALTFUNCSET |= 0x0200; break; + } + + } -int i2c_start(i2c_t *obj) { - - int delay_value; - switch ((int)obj->i2c) { - case I2C_0: delay_value = TSC_TSU; break; - case I2C_1: delay_value = AAIC_TSU; break; - } - i2c_delay(delay_value); - obj->i2c->CONTROLS = SDA | SCL; - i2c_delay(delay_value); - obj->i2c->CONTROLC = SDA; - i2c_delay(delay_value); - - +int i2c_start(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + + i2c_delay(delay_value); + obj->i2c->CONTROLS = SDA | SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); return 0; } -int i2c_start_tsc(i2c_t *obj) { - - int delay_value; - switch ((int)obj->i2c) { - case I2C_0: delay_value = TSC_TSU; break; - case I2C_1: delay_value = AAIC_TSU; break; - } - i2c_delay(delay_value); - obj->i2c->CONTROLC = SDA; - i2c_delay(delay_value); - obj->i2c->CONTROLC = SCL; - i2c_delay(delay_value); +int i2c_start_tsc(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); return 0; } -int i2c_stop(i2c_t *obj) { - - int delay_value; - switch ((int)obj->i2c) { - case I2C_0: delay_value = TSC_TSU; break; - case I2C_1: delay_value = AAIC_TSU; break; - } - // Actual stop bit - i2c_delay(delay_value); - obj->i2c->CONTROLC = SDA; - i2c_delay(delay_value); - obj->i2c->CONTROLS = SCL; - i2c_delay(delay_value); - obj->i2c->CONTROLS = SDA; - i2c_delay(delay_value); - - return 0; +int i2c_stop(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + // Actual stop bit + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SDA; + i2c_delay(delay_value); + + return 0; } @@ -283,103 +369,154 @@ int i2c_stop(i2c_t *obj) { void i2c_frequency(i2c_t *obj, int hz) { } -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - unsigned int loop, rxdata; - int delay_value, sadr, ack, bytes_read; - rxdata=0; - switch ((int)obj->i2c) { - case I2C_0: - delay_value = TSC_TSU; - sadr = TSC_I2C_ADDR; - break; - case I2C_1: - delay_value = AAIC_TSU; - sadr = AAIC_I2C_ADDR; - break; - } - // Start bit - i2c_start(obj); - - // Set serial and register address - i2c_send_byte(obj,sadr); - ack += i2c_receive_ack(obj); - i2c_send_byte(obj, address); - ack += i2c_receive_ack(obj); - - // Stop bit - i2c_stop(obj); - +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + unsigned int loop, rxdata; + int sadr, ack, bytes_read; + rxdata=0; + switch ((int)obj->i2c) { + case I2C_0: + sadr = TSC_I2C_ADDR; + break; + case I2C_1: + sadr = AAIC_I2C_ADDR; + break; + case I2C_2: + case I2C_3: + sadr = address; //LM75_I2C_ADDR; or MMA7660_I2C_ADDR; + break; + } + bytes_read = 0; // Start bit - i2c_start_tsc(obj); - - // Read from serial address - i2c_send_byte(obj,sadr | 1); - ack += i2c_receive_ack(obj); - bytes_read = 0; - - switch ((int)obj->i2c) { - case I2C_0: - rxdata = (i2c_receive_byte(obj) & 0xFF); - data[((length-1)-bytes_read)] = (char)rxdata; - bytes_read++; - // Read multiple bytes - if ((length > 1) && (length < 5)) - { - for (loop = 1; loop <= (length - 1); loop++) - { - // Send ACK - i2c_delay(delay_value); - obj->i2c->CONTROLC = SDA; - i2c_delay(delay_value); - obj->i2c->CONTROLS = SCL; - i2c_delay(delay_value); - obj->i2c->CONTROLC = SCL; - i2c_delay(delay_value); - - rxdata = i2c_receive_byte(obj); - data[(length-1)-bytes_read] = (char)rxdata; - bytes_read++; - - } - } - break; - case I2C_1: - rxdata = i2c_receive_byte(obj); - data[bytes_read] = (char)rxdata; - bytes_read++; + i2c_start(obj); + + switch ((int)obj->i2c) { + case I2C_0: + // Set serial and register address + i2c_send_byte(obj,sadr); + ack += i2c_receive_ack(obj); + i2c_send_byte(obj, address); + ack += i2c_receive_ack(obj); + + // Stop bit + i2c_stop(obj); + + // Start bit + i2c_start_tsc(obj); + + // Read from I2C address + i2c_send_byte(obj,sadr | 1); + ack += i2c_receive_ack(obj); + + rxdata = (i2c_receive_byte(obj) & 0xFF); + data[((length-1)-bytes_read)] = (char)rxdata; + bytes_read++; + // Read multiple bytes + if ((length > 1) && (length < 5)) + { + for (loop = 1; loop <= (length - 1); loop++) + { + // Send ACK + i2c_send_ack(obj); + + // Next byte + //rxdata = ((rxdata << 8) & 0xFFFFFF00); + //rxdata |= (i2c_receive_byte(obj) & 0xFF); + rxdata = i2c_receive_byte(obj); + data[(length-1)-bytes_read] = (char)rxdata; + bytes_read++; + + } + } + break; + case I2C_1: + // Set serial and register address + i2c_send_byte(obj,sadr); + ack += i2c_receive_ack(obj); + i2c_send_byte(obj, address); + ack += i2c_receive_ack(obj); + + // Stop bit + i2c_stop(obj); + + // Start bit + i2c_start_tsc(obj); + // Fall through to read data + case I2C_2: + case I2C_3: + // Read from preset register address pointer + i2c_send_byte(obj,sadr | 1); + ack += i2c_receive_ack(obj); + + rxdata = i2c_receive_byte(obj); + data[bytes_read] = (char)rxdata; + bytes_read++; + // Read multiple bytes + if ((length > 1) && (length < 5)) + { + for (loop = 1; loop <= (length - 1); loop++) + { + // Send ACK + i2c_send_ack(obj); + + // Next byte + rxdata = i2c_receive_byte(obj); + data[loop] = (char)rxdata; + bytes_read++; + + } + } break; } - i2c_send_ack(obj); + i2c_send_nack(obj); - // Actual stop bit - i2c_stop(obj); + i2c_stop(obj); // Actual stop bit return bytes_read; } -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { - int ack=0; - int sadr; - switch ((int)obj->i2c) { - case I2C_0: sadr = TSC_I2C_ADDR; break; - case I2C_1: sadr = AAIC_I2C_ADDR; break; - } - for(int i = 1; i<=length; i++) - { - i2c_start(obj); - - // Set serial and register address - i2c_send_byte(obj,sadr); - ack += i2c_receive_ack(obj); - i2c_send_byte(obj, address); - ack += i2c_receive_ack(obj); - i2c_send_byte(obj, *data); - ack += i2c_receive_ack(obj); - } - - i2c_stop(obj); - if(ack==3) { return 1; } - else{ return 0; } +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int ack=0; + int sadr; + char * ptr; + char addr; + ptr = (char*)data; + switch ((int)obj->i2c) + { + case I2C_0: + sadr = TSC_I2C_ADDR; + addr = address; + break; + case I2C_1: + sadr = AAIC_I2C_ADDR; + addr = address; + break; + case I2C_2: + case I2C_3: + sadr = address; //LM75_I2C_ADDR or MMA7660_I2C_ADDR; + addr = *ptr++; + break; + } + +// printf("adr = %x, reg = %x\n",sadr, address); + i2c_start(obj); + + // Set serial and register address + i2c_send_byte(obj,sadr); + ack += i2c_receive_ack(obj); + i2c_send_byte(obj, addr); + ack += i2c_receive_ack(obj); + + for(int i = 1; iuart = (CMSDK_UART_TypeDef *)uart; //set baud rate and enable Uart in normarl mode (RX and TX enabled) - switch (uart) { - case UART_0: CMSDK_UART0->CTRL = 0; // Disable UART when changing configuration - CMSDK_UART0->CTRL = 0x3; // Normal mode - break; - case UART_1: CMSDK_UART1->CTRL = 0; // Disable UART when changing configuration - CMSDK_UART1->CTRL = 0x3; // Normal mode - break; + switch (uart) + { + case UART_0: + { + CMSDK_UART0->CTRL = 0x00; // Disable UART when changing configuration + if((int)uart_tx != NC) + { + CMSDK_UART0->CTRL |= 0x01; // TX enable + } else { + CMSDK_UART0->CTRL &= 0xFFFE; // TX disable + } + + + if((int)uart_rx != NC) + { + CMSDK_UART0->CTRL |= 0x02; // RX enable + } else { + CMSDK_UART0->CTRL &= 0xFFFD; // RX disable + } + + } + break; + case UART_1: //XBEE SOCKET UART + { + CMSDK_UART1->CTRL = 0x00; // Disable UART when changing configuration + if((int)tx != NC) + { + CMSDK_UART1->CTRL = 0x1; // TX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x0100; + } + if((int)rx != NC) + { + CMSDK_UART1->CTRL |= 0x2; // RX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x0080; + } + } + break; + case UART_2: //Sheild0 UART + { + CMSDK_UART3->CTRL = 0x00; // Disable UART when changing configuration + if((int)tx != NC) + { + CMSDK_UART3->CTRL = 0x1; // TX enable + CMSDK_GPIO0->ALTFUNCSET |= 0x0010; + } + if((int)rx != NC) + { + CMSDK_UART3->CTRL |= 0x2; // RX enable + CMSDK_GPIO0->ALTFUNCSET |= 0x0001; + } + } + break; + case UART_3: //Sheild1 UART + { + CMSDK_UART4->CTRL = 0x00; // Disable UART when changing configuration + if((int)tx != NC) + { + CMSDK_UART4->CTRL = 0x1; // TX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x4000; + } + if((int)rx != NC) + { + CMSDK_UART4->CTRL |= 0x2; // RX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x0400; + } + } + break; } // set default baud rate and format @@ -88,6 +152,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { switch (uart) { case UART_0: obj->index = 0; break; case UART_1: obj->index = 1; break; + case UART_2: obj->index = 2; break; + case UART_3: obj->index = 3; break; } uart_data[obj->index].sw_rts.pin = NC; uart_data[obj->index].sw_cts.pin = NC; @@ -102,6 +168,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { } void serial_free(serial_t *obj) { + uart_data[obj->index].serial_irq_id = 0; } // serial_baud @@ -110,24 +177,26 @@ void serial_baud(serial_t *obj, int baudrate) { // The MPS2 has a simple divider to control the baud rate. The formula is: // // Baudrate = PCLK / BAUDDIV - // - // PCLK = 25 Mhz - // so for a desired baud rate of 9600 - // 25000000 / 9600 = 2604 + // + // PCLK = 25 Mhz + // so for a desired baud rate of 9600 + // 25000000 / 9600 = 2604 // - //check to see if minimum baud value entered - int baudrate_div = 0; - baudrate_div = 25000000 / baudrate; - if(baudrate >= 16){ + //check to see if minimum baud value entered + int baudrate_div = 0; + baudrate_div = SystemCoreClock / baudrate; + if(baudrate >= 16){ switch ((int)obj->uart) { case UART_0: CMSDK_UART0->BAUDDIV = baudrate_div; break; case UART_1: CMSDK_UART1->BAUDDIV = baudrate_div; break; + case UART_2: CMSDK_UART3->BAUDDIV = baudrate_div; break; + case UART_3: CMSDK_UART4->BAUDDIV = baudrate_div; break; default: error("serial_baud"); break; } - } else { - error("serial_baud"); - } - + } else { + error("serial_baud"); + } + } void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { @@ -138,24 +207,58 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b ******************************************************************************/ static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart) { SerialIrq irq_type; - switch (intstatus) { - case 1: irq_type = TxIrq; break; - case 2: irq_type = RxIrq; break; + switch (intstatus) + { + case 1: + { + irq_type = TxIrq; + } + break; + + case 2: + { + irq_type = RxIrq; + } + break; + default: return; - } - if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) { + } /* End of Switch */ + + if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) + { gpio_write(&uart_data[index].sw_rts, 1); // Disable interrupt if it wasn't enabled by other part of the application if (!uart_data[index].rx_irq_set_api) - puart->CTRL &= ~(1 << RxIrq); + { + /* Disable Rx interrupt */ + puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk); + } } + if (uart_data[index].serial_irq_id != 0) + { if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) + { irq_handler(uart_data[index].serial_irq_id, irq_type); + } + } + + if( irq_type == TxIrq ) + { + /* Clear the TX interrupt Flag */ + puart->INTCLEAR |= 0x01; + } + else + { + /* Clear the Rx interupt Flag */ + puart->INTCLEAR |= 0x02; + } } void uart0_irq() {uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART0);} void uart1_irq() {uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART1);} +void uart2_irq() {uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART3);} +void uart3_irq() {uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART4);} void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; @@ -163,30 +266,66 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { } static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { + /* Declare a variable of type IRQn, initialise to 0 */ IRQn_Type irq_n = (IRQn_Type)0; uint32_t vector = 0; - switch ((int)obj->uart) { - case UART_0: irq_n=((irq>> 2) ? UARTRX0_IRQn : UARTTX0_IRQn); vector = (uint32_t)&uart0_irq; break; - case UART_1: irq_n=((irq>> 2) ? UARTRX1_IRQn : UARTTX1_IRQn); vector = (uint32_t)&uart1_irq; break; + switch ((int)obj->uart) + { + case UART_0: + { + irq_n = (( irq == TxIrq ) ? UARTTX0_IRQn : UARTRX0_IRQn); + vector = (uint32_t)&uart0_irq; + } + break; + + case UART_1: + { + irq_n = (( irq == TxIrq ) ? UARTTX1_IRQn : UARTRX1_IRQn); + vector = (uint32_t)&uart1_irq; + } + break; + case UART_2: + { + irq_n = (( irq == TxIrq ) ? UARTTX3_IRQn : UARTRX3_IRQn); + vector = (uint32_t)&uart2_irq; + } + break; + case UART_3: + { + irq_n = (( irq == TxIrq ) ? UARTTX4_IRQn : UARTRX4_IRQn); + vector = (uint32_t)&uart3_irq; + } + break; } - - if (enable) { - obj->uart->CTRL |= 1 << irq; + + if (enable) + { + if( irq == TxIrq ) + { + /* Transmit IRQ, set appripriate enable */ + + /* set TX interrupt enable in CTRL REG */ + obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk; + } + else + { + /* set Rx interrupt on in CTRL REG */ + obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk; + } NVIC_SetVector(irq_n, vector); NVIC_EnableIRQ(irq_n); - } else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable - int all_disabled = 0; - SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - obj->uart->CTRL &= ~(1 << irq); - all_disabled = (obj->uart->CTRL & (1 << other_irq)) == 0; - if (all_disabled) + + } + else + { /* Disable IRQ */ + + obj->uart->CTRL &= ~(1 << (irq + 2)); + NVIC_DisableIRQ(irq_n); } } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - if (RxIrq == irq) - uart_data[obj->index].rx_irq_set_api = enable; serial_irq_set_internal(obj, irq, enable); } @@ -205,11 +344,11 @@ void serial_putc(serial_t *obj, int c) { } int serial_readable(serial_t *obj) { - return obj->uart->STATE & 2; + return obj->uart->STATE & 0x2; } int serial_writable(serial_t *obj) { - return obj->uart->STATE & 1; + return obj->uart->STATE & 0x1; } void serial_clear(serial_t *obj) { diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c index 4f83ceac4c0..b52cb46eb47 100644 --- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c @@ -25,24 +25,36 @@ static const PinMap PinMap_SPI_SCLK[] = { {SCLK_SPI , SPI_0, 0}, {CLCD_SCLK , SPI_1, 0}, + {ADC_SCLK , SPI_2, 0}, + {SHIELD_0_SPI_SCK , SPI_3, 0}, + {SHIELD_1_SPI_SCK , SPI_4, 0}, {NC , NC , 0} }; static const PinMap PinMap_SPI_MOSI[] = { {MOSI_SPI, SPI_0, 0}, {CLCD_MOSI, SPI_1, 0}, + {ADC_MOSI, SPI_2, 0}, + {SHIELD_0_SPI_MOSI, SPI_3, 0}, + {SHIELD_1_SPI_MOSI, SPI_4, 0}, {NC , NC , 0} }; static const PinMap PinMap_SPI_MISO[] = { {MISO_SPI, SPI_0, 0}, {CLCD_MISO, SPI_1, 0}, + {ADC_MISO, SPI_2, 0}, + {SHIELD_0_SPI_MISO, SPI_3, 0}, + {SHIELD_1_SPI_MISO, SPI_4, 0}, {NC , NC , 0} }; static const PinMap PinMap_SPI_SSEL[] = { {SSEL_SPI, SPI_0, 0}, {CLCD_SSEL, SPI_1, 0}, + {ADC_SSEL, SPI_2, 0}, + {SHIELD_0_SPI_nCS, SPI_3, 0}, + {SHIELD_1_SPI_nCS, SPI_4, 0}, {NC , NC , 0} }; @@ -50,7 +62,9 @@ static inline int ssp_disable(spi_t *obj); static inline int ssp_enable(spi_t *obj); void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - // determine the SPI to use + + int altfunction[4]; + // determine the SPI to use SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); @@ -64,7 +78,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel // enable power and clocking switch ((int)obj->spi) { - case (int)SPI_0: + case (int)SPI_0: obj->spi->CR1 = 0; obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; obj->spi->CPSR = SSP_CPSR_DFLT; @@ -89,8 +103,53 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */ (0ul << 2) ); /* Device configured as master */ break; + case (int)SPI_2: + obj->spi->CR1 = 0; + obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; + obj->spi->DMACR = 0; + obj->spi->CR1 = SSP_CR1_SSE_Msk; + obj->spi->ICR = 0x3; + break; + case (int)SPI_3: + obj->spi->CR1 = 0; + obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; + obj->spi->DMACR = 0; + obj->spi->CR1 = SSP_CR1_SSE_Msk; + obj->spi->ICR = 0x3; + break; + case (int)SPI_4: + obj->spi->CR1 = 0; + obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; + obj->spi->DMACR = 0; + obj->spi->CR1 = SSP_CR1_SSE_Msk; + obj->spi->ICR = 0x3; + break; } + if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;} + if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;} + if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;} + if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;} + + // enable alt function + switch ((int)obj->spi) { + case (int)SPI_2: + CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[0]<<2 | altfunction[1]<<1 | altfunction[3]); + break; + case (int)SPI_3: + CMSDK_GPIO0->ALTFUNCSET |= (altfunction[1]<<14 | altfunction[0]<<13 | altfunction[3]<<12 | altfunction[2]<<11); + break; + case (int)SPI_4: + CMSDK_GPIO2->ALTFUNCSET |= (altfunction[2]<<12 | altfunction[1]<<8 | altfunction[0]<<7 | altfunction[3]<<6); + break; + } + // set default format and frequency if (ssel == NC) { spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master @@ -205,7 +264,7 @@ static inline int ssp_busy(spi_t *obj) { int spi_master_write(spi_t *obj, int value) { ssp_write(obj, value); - while (MPS2_SSP0->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */ + while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */ return (ssp_read(obj)); } diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c index 0de4335b910..514928ded8a 100644 --- a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c @@ -19,7 +19,7 @@ #define US_TICKER_TIMER1 CMSDK_DUALTIMER1 #define US_TICKER_TIMER2 CMSDK_DUALTIMER2 -#define US_TICKER_TIMER_IRQn DUALTIMER_IRQn +#define US_TICKER_TIMER_IRQn DUALTIMER_IRQn int us_ticker_inited = 0; @@ -51,7 +51,6 @@ uint32_t return_value = 0; } void us_ticker_set_interrupt(timestamp_t timestamp) { -uint32_t timer_value = 0; int delta = 0; if (!us_ticker_inited) us_ticker_init(); @@ -61,7 +60,6 @@ int delta = 0; us_ticker_irq_handler(); return; } - timer_value = (delta)*25; // enable interrupt US_TICKER_TIMER1->TimerControl = 0x0; // disable timer US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode diff --git a/workspace_tools/host_tests/host_tests_plugins/module_copy_mps2.py b/workspace_tools/host_tests/host_tests_plugins/module_copy_mps2.py index 1d99f6e9451..bcfe1d73401 100644 --- a/workspace_tools/host_tests/host_tests_plugins/module_copy_mps2.py +++ b/workspace_tools/host_tests/host_tests_plugins/module_copy_mps2.py @@ -129,16 +129,16 @@ def execute(self, capabilitity, *args, **kwargs): """ Add a delay in case there a test just finished Prevents interface firmware hiccups """ - sleep(10) + sleep(20) if capabilitity == 'mps2-copy' and self.copy_file(file, disk): - sleep(1) + sleep(3) if self.touch_file(disk + 'reboot.txt'): """ Add a delay after the board was rebooted. The actual reboot time is 20 seconds, but using 15 seconds allows us to open the COM port and save a board reset. This also prevents interface firmware hiccups. """ - sleep(16) + sleep(7) result = True return result From c381ac5f783fa99fc852c127e1498bd0eac928aa Mon Sep 17 00:00:00 2001 From: Peter Conheeney Date: Thu, 25 Feb 2016 09:08:11 +0000 Subject: [PATCH 2/3] update to repo #2 --- .../TARGET_IOTSS_BEID/CMSDK_BEID.h | 793 ++++++++++++++++++ .../TARGET_IOTSS_BEID/SMM_MPS2.h | 610 ++++++++++++++ .../TOOLCHAIN_ARM_STD/MPS2.sct | 47 ++ .../TOOLCHAIN_ARM_STD/startup_MPS2.s | 358 ++++++++ .../TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis.h | 42 + .../TARGET_IOTSS_BEID/cmsis_nvic.c | 58 ++ .../TARGET_IOTSS_BEID/cmsis_nvic.h | 54 ++ .../TARGET_IOTSS_BEID/peripherallink.h | 45 + .../TARGET_IOTSS_BEID/system_CMSDK_BEID.c | 95 +++ .../TARGET_IOTSS_BEID/system_CMSDK_BEID.h | 76 ++ .../TARGET_IOTSS/PeripheralNames.h | 91 ++ .../TARGET_ARM_SSG/TARGET_IOTSS/PinNames.h | 241 ++++++ .../TARGET_ARM_SSG/TARGET_IOTSS/PortNames.h | 31 + .../TARGET_IOTSS/SDK/ETH_MPS2.c | 450 ++++++++++ .../TARGET_IOTSS/SDK/ETH_MPS2.h | 65 ++ .../TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.c | 90 ++ .../TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.h | 34 + .../TARGET_IOTSS/SDK/mps2_ethernet_api.c | 166 ++++ .../TARGET_IOTSS/SDK/mps2_ethernet_api.h | 57 ++ .../TARGET_IOTSS/analogin_api.c | 110 +++ .../hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h | 64 ++ .../TARGET_IOTSS/ethernet_api.c | 164 ++++ .../TARGET_ARM_SSG/TARGET_IOTSS/gpio_api.c | 140 ++++ .../TARGET_IOTSS/gpio_irq_api.c | 241 ++++++ .../TARGET_ARM_SSG/TARGET_IOTSS/gpio_object.h | 55 ++ .../hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c | 542 ++++++++++++ .../hal/TARGET_ARM_SSG/TARGET_IOTSS/objects.h | 82 ++ .../hal/TARGET_ARM_SSG/TARGET_IOTSS/pinmap.c | 28 + .../TARGET_ARM_SSG/TARGET_IOTSS/port_api.c | 68 ++ .../TARGET_ARM_SSG/TARGET_IOTSS/serial_api.c | 367 ++++++++ .../hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c | 286 +++++++ .../hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_def.h | 174 ++++ .../TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c | 84 ++ .../TARGET_ARM_SSG/TARGET_MPS2/analogin_api.c | 110 +++ 34 files changed, 5918 insertions(+) create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/CMSDK_BEID.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/SMM_MPS2.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/TOOLCHAIN_ARM_STD/MPS2.sct create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/peripherallink.h create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.c create mode 100644 libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.h create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PeripheralNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PinNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PortNames.h create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.h create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.c create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.h create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/analogin_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_irq_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_object.h create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/objects.h create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/pinmap.c create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/port_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/serial_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_def.h create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c create mode 100644 libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/analogin_api.c diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/CMSDK_BEID.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/CMSDK_BEID.h new file mode 100644 index 00000000000..e4cff93f8f5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/CMSDK_BEID.h @@ -0,0 +1,793 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2016 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file CMSDK_BEID.h +* @brief CMSIS Core Peripheral Access Layer Header File for +* CMSDK_BEID Device +* +*******************************************************************************/ + + +#ifndef CMSDK_BEID_H +#define CMSDK_BEID_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ---------------------- CMSDK_CM3 Specific Interrupt Numbers ------------------ */ + UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */ + Spare_IRQn = 1, /* Undefined */ + UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */ + I2C0_IRQn = 3, /* I2C 0 Interrupt */ + I2C1_IRQn = 4, /* I2C 1 Interrupt */ + RTC_IRQn = 5, /* RTC Interrupt */ + PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ + SPI0_IRQn = 11, /* SPI 0 Interrupt */ + UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ + SPI1_IRQn = 13, /* SPI 1 Interrupt */ + RESERVED0_IRQn = 14, /* Reserved */ + TSC_IRQn = 15, /* Touch Screen Interrupt */ + PORT01_0_IRQn = 16, /* GPIO Port 0 pin 0 Handler */ + PORT01_1_IRQn = 17, /* GPIO Port 0 pin 1 Handler */ + PORT01_2_IRQn = 18, /* GPIO Port 0 pin 2 Handler */ + PORT01_3_IRQn = 19, /* GPIO Port 0 pin 3 Handler */ + PORT01_4_IRQn = 20, /* GPIO Port 0 pin 4 Handler */ + PORT01_5_IRQn = 21, /* GPIO Port 0 pin 5 Handler */ + PORT01_6_IRQn = 22, /* GPIO Port 0 pin 6 Handler */ + PORT01_7_IRQn = 23, /* GPIO Port 0 pin 7 Handler */ + PORT01_8_IRQn = 24, /* GPIO Port 0 pin 8 Handler */ + PORT01_9_IRQn = 25, /* GPIO Port 0 pin 9 Handler */ + PORT01_10_IRQn = 26, /* GPIO Port 0 pin 10 Handler */ + PORT01_11_IRQn = 27, /* GPIO Port 0 pin 11 Handler */ + PORT01_12_IRQn = 28, /* GPIO Port 0 pin 12 Handler */ + PORT01_13_IRQn = 29, /* GPIO Port 0 pin 13 Handler */ + PORT01_14_IRQn = 30, /* GPIO Port 0 pin 14 Handler */ + PORT01_15_IRQn = 31, /* GPIO Port 0 pin 15 Handler */ + SYSERROR_IRQn = 32, /* System Error Interrupt */ + EFLASH_IRQn = 33, /* Embedded Flash Interrupt */ + RESERVED1_IRQn = 34, /* Reserved */ + RESERVED2_IRQn = 35, /* Reserved */ + RESERVED3_IRQn = 36, /* Reserved */ + RESERVED4_IRQn = 37, /* Reserved */ + RESERVED5_IRQn = 38, /* Reserved */ + RESERVED6_IRQn = 39, /* Reserved */ + RESERVED7_IRQn = 40, /* Reserved */ + RESERVED8_IRQn = 41, /* Reserved */ + PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */ + TRNG_IRQn = 44, /* Random number generator Interrupt */ + UART2_IRQn = 45, /* UART 2 RX and TX Combined Interrupt */ + UART3_IRQn = 46, /* UART 3 RX and TX Combined Interrupt */ + ETHERNET_IRQn = 47, /* Ethernet interrupt t.b.a. */ + I2S_IRQn = 48, /* I2S Interrupt */ + MPS2_SPI0_IRQn = 49, /* SPI Interrupt (spi header) */ + MPS2_SPI1_IRQn = 50, /* SPI Interrupt (clcd) */ + MPS2_SPI2_IRQn = 51, /* SPI Interrupt (spi 1 ADC replacement) */ + MPS2_SPI3_IRQn = 52, /* SPI Interrupt (spi 0 shield 0 replacement) */ + MPS2_SPI4_IRQn = 53 /* SPI Interrupt (shield 1) */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */ +#define __BEID_REV 0x0201 /* Core revision r2p1 */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#include /* Processor and core peripherals */ +#include "system_CMSDK_BEID.h" /* System Header */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined ( __CC_ARM ) + #pragma push +#pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + +} CMSDK_UART_TypeDef; + +/* CMSDK_UART DATA Register Definitions */ + +#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ +#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ + +#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ +#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ + +#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ +#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ + +#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ +#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ + +#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ +#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ + +#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ +#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ + +#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ +#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ +#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ +#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ +#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ +#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ + +#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ +#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ + +#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ +#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ + +#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ +#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ + +#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ +#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ + +#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ +#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ + +#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ +#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ + + +/*----------------------------- Timer (TIMER) -------------------------------*/ +typedef struct +{ + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + +} CMSDK_TIMER_TypeDef; + +/* CMSDK_TIMER CTRL Register Definitions */ + +#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ +#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ +#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ +#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ + +#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ +#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ + +#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ +#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ + +#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ +#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ + +#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ +#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ + +#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ +#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ + + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +} CMSDK_DUALTIMER_BOTH_TypeDef; + +#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ + +#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ + + +typedef struct +{ + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +} CMSDK_DUALTIMER_SINGLE_TypeDef; + +#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ +#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ +#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ + + +/*-------------------- General Purpose Input Output (GPIO) -------------------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ + }; + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ +} CMSDK_GPIO_TypeDef; + +#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ +#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ + +#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ +#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ + +#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ +#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ + +#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ + +#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ +#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ + +#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ +#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ + + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ + uint32_t RESERVED0[3]; + __IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */ + __IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */ + uint32_t RESERVED1[2]; + __IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */ + __IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */ + uint32_t RESERVED2[2]; + __IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */ + __IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */ + __IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */ + __IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */ + __IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */ + __IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */ + uint32_t RESERVED3[10]; + __IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */ + __IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */ + __IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */ + __IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */ + __IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */ + __IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */ + uint32_t RESERVED4[2]; + __IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */ + __IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */ + __IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */ + __IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */ + __IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */ + __IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */ + uint32_t RESERVED5[2]; + __IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */ + __IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */ + __IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */ + __IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */ + __IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */ + __IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */ + __IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */ + __IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */ + __O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */ + __IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */ + uint32_t RESERVED6[2]; + __IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */ + __IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */ + __I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */ + uint32_t RESERVED7[1]; + __IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */ + __IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */ + __IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */ +} CMSDK_SYSCON_TypeDef; + +#define CMSDK_SYSCON_REMAP_Pos 0 +#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ + +#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 +#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ + +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 +#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ + +#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 +#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 +#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 +#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ + +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ + + +/*------------- PL230 uDMA (PL230) --------------------------------------*/ +typedef struct +{ + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ + +} CMSDK_PL230_TypeDef; + +#define PL230_DMA_CHNL_BITS 0 + +#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */ +#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */ +#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */ + +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */ +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */ + +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */ +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */ + +#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */ +#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */ +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */ +#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */ +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */ + +#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */ +#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */ + +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */ +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */ +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */ + +#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */ +#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */ +#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */ +#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */ +#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */ +#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */ +#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */ +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */ + +#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */ +#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */ + + +/*------------------- Watchdog ----------------------------------------------*/ +typedef struct +{ + + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +}CMSDK_WATCHDOG_TypeDef; + +#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ +#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ + +#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ +#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */ + +#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ +#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ + +#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ +#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ + +#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ +#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ + +#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ +#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */ + +#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ +#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ + +#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ + + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined ( __CC_ARM ) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +/* Peripheral and SRAM base address */ +#define CMSDK_FLASH_BASE (0x00000000UL) +#define CMSDK_SRAM_BASE (0x20000000UL) +#define CMSDK_PERIPH_BASE (0x40000000UL) + +#define CMSDK_RAM_BASE (0x20000000UL) +#define CMSDK_APB_BASE (0x40000000UL) +#define CMSDK_AHB_BASE (0x40010000UL) + +/* APB peripherals */ +#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) +#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) +#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) +#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) +#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) +#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) +#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) +#define CMSDK_UART2_BASE (0x4002C000UL) +#define CMSDK_UART3_BASE (0x4002D000UL) +#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) + +/* AHB peripherals */ +#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) +#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) +#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) +#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) +#define CMSDK_GPIO4_BASE (0x40030000UL) +#define CMSDK_GPIO5_BASE (0x40031000UL) +#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) +#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) +#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) +#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) +#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) +#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) +#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) +#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) +#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) +#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) +//#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE ) +#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) +#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) +#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) +#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) +#define CMSDK_GPIO4 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO4_BASE ) +#define CMSDK_GPIO5 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO5_BASE ) +#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) + + +#ifdef __cplusplus +} +#endif + +#endif /* CMSDK_BEID_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/SMM_MPS2.h new file mode 100644 index 00000000000..7e4d7c4c71d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/SMM_MPS2.h @@ -0,0 +1,610 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2016 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* File: smm_mps2.h +* Release: Version 1.1 +*******************************************************************************/ + +#ifndef __SMM_MPS2_H +#define __SMM_MPS2_H + +#include "peripherallink.h" /* device specific header file */ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* FPGA System Register declaration */ +/******************************************************************************/ + +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + __IO uint32_t PRESCALE; // Offset: 0x1C (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x020 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[10]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS +} MPS2_FPGAIO_TypeDef; + +// MISC register bit definitions + +#define CLCD_CS_Pos 0 +#define CLCD_CS_Msk (1UL< CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error + }; + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT +} MPS2_I2S_TypeDef; + +#define I2S_CONTROL_TXEN_Pos 0 +#define I2S_CONTROL_TXEN_Msk (1UL<>> ------------------ +; + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UART0_IRQHandler ; 0:UART 0 RX and TX Combined Interrupt + DCD Spare_IRQHandler ; 1:Undefined + DCD UART1_IRQHandler ; 2:UART 1 RX and TX Combined Interrupt + DCD I2C0_IRQHandler ; 3:I2C 0 Interrupt + DCD I2C1_IRQHandler ; 4:I2C 1 Interrupt + DCD RTC_IRQHandler ; 5:RTC Interrupt + DCD PORT0_IRQHandler ; 6:GPIO Port 0 combined Interrupt + DCD PORT1_ALL_IRQHandler ; 7:GPIO Port 1 combined Interrupt + DCD TIMER0_IRQHandler ; 8:TIMER 0 Interrupt + DCD TIMER1_IRQHandler ; 9:TIMER 1 Interrupt + DCD DUALTIMER_IRQHandler ; 10:Dual Timer Interrupt + DCD SPI0_IRQHandler ; 11:SPI 0 Interrupt + DCD UARTOVF_IRQHandler ; 12:UART 0,1,2 Overflow Interrupt + DCD SPI1_IRQHandler ; 13:SPI 1 Interrupt + DCD RESERVED0_IRQHandler ; 14:Reserved + DCD TSC_IRQHandler ; 15:Touch Screen Interrupt + DCD PORT01_0_IRQHandler ; 16:GPIO Port 0 pin 0 Handler + DCD PORT01_1_IRQHandler ; 17:GPIO Port 0 pin 1 Handler + DCD PORT01_2_IRQHandler ; 18:GPIO Port 0 pin 2 Handler + DCD PORT01_3_IRQHandler ; 19:GPIO Port 0 pin 3 Handler + DCD PORT01_4_IRQHandler ; 20:GPIO Port 0 pin 4 Handler + DCD PORT01_5_IRQHandler ; 21:GPIO Port 0 pin 5 Handler + DCD PORT01_6_IRQHandler ; 22:GPIO Port 0 pin 6 Handler + DCD PORT01_7_IRQHandler ; 23:GPIO Port 0 pin 7 Handler + DCD PORT01_8_IRQHandler ; 24:GPIO Port 0 pin 8 Handler + DCD PORT01_9_IRQHandler ; 25:GPIO Port 0 pin 9 Handler + DCD PORT01_10_IRQHandler ; 26:GPIO Port 0 pin 10 Handler + DCD PORT01_11_IRQHandler ; 27:GPIO Port 0 pin 11 Handler + DCD PORT01_12_IRQHandler ; 28:GPIO Port 0 pin 12 Handler + DCD PORT01_13_IRQHandler ; 29:GPIO Port 0 pin 13 Handler + DCD PORT01_14_IRQHandler ; 30:GPIO Port 0 pin 14 Handler + DCD PORT01_15_IRQHandler ; 31:GPIO Port 0 pin 15 Handler + DCD SYSERROR_IRQHandler ; 32:System Error Interrupt + DCD EFLASH_IRQHandler ; 33:Embedded Flash Interrupt + DCD RESERVED1_IRQHandler ; 34:Reserved + DCD RESERVED2_IRQHandler ; 35:Reserved + DCD RESERVED3_IRQHandler ; 36:Reserved + DCD RESERVED4_IRQHandler ; 37:Reserved + DCD RESERVED5_IRQHandler ; 38:Reserved + DCD RESERVED6_IRQHandler ; 39:Reserved + DCD RESERVED7_IRQHandler ; 40:Reserved + DCD RESERVED8_IRQHandler ; 41:Reserved + DCD PORT2_ALL_IRQHandler ; 42:GPIO Port 2 combined Interrupt + DCD PORT3_ALL_IRQHandler ; 43:GPIO Port 3 combined Interrupt + DCD TRNG_IRQHandler ; 44:Random number generator Interrupt + DCD UART2_IRQHandler ; 45:UART 2 RX and TX Combined Interrupt + DCD UART3_IRQHandler ; 46:UART 3 RX and TX Combined Interrupt + DCD ETHERNET_IRQHandler ; 47:Ethernet interrupt t.b.a. + DCD I2S_IRQHandler ; 48:I2S Interrupt + DCD MPS2_SPI0_IRQHandler ; 49:SPI Interrupt (spi header) + DCD MPS2_SPI1_IRQHandler ; 50:SPI Interrupt (clcd) + DCD MPS2_SPI2_IRQHandler ; 51:SPI Interrupt (spi 1 ADC replacement) + DCD MPS2_SPI3_IRQHandler ; 52:SPI Interrupt (spi 0 shield 0 replacement) + DCD MPS2_SPI4_IRQHandler ; 53:SPI Interrupt (shield 1) + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT UART0_IRQHandler [WEAK] ; 0:UART 0 RX and TX Combined Interrupt + EXPORT Spare_IRQHandler [WEAK] ; 1:Undefined + EXPORT UART1_IRQHandler [WEAK] ; 2:UART 1 RX and TX Combined Interrupt + EXPORT I2C0_IRQHandler [WEAK] ; 3:I2C 0 Interrupt + EXPORT I2C1_IRQHandler [WEAK] ; 4:I2C 1 Interrupt + EXPORT RTC_IRQHandler [WEAK] ; 5:RTC Interrupt + EXPORT PORT0_IRQHandler [WEAK] ; 6:GPIO Port 0 combined Interrupt + EXPORT PORT1_ALL_IRQHandler [WEAK] ; 7:GPIO Port 1 combined Interrupt + EXPORT TIMER0_IRQHandler [WEAK] ; 8:TIMER 0 Interrupt + EXPORT TIMER1_IRQHandler [WEAK] ; 9:TIMER 1 Interrupt + EXPORT DUALTIMER_IRQHandler [WEAK] ; 10:Dual Timer Interrupt + EXPORT SPI0_IRQHandler [WEAK] ; 11:SPI 0 Interrupt + EXPORT UARTOVF_IRQHandler [WEAK] ; 12:UART 0,1,2 Overflow Interrupt + EXPORT SPI1_IRQHandler [WEAK] ; 13:SPI 1 Interrupt + EXPORT RESERVED0_IRQHandler [WEAK] ; 14:Reserved + EXPORT TSC_IRQHandler [WEAK] ; 15:Touch Screen Interrupt + EXPORT PORT01_0_IRQHandler [WEAK] ; 16:GPIO Port 0 pin 0 Handler + EXPORT PORT01_1_IRQHandler [WEAK] ; 17:GPIO Port 0 pin 1 Handler + EXPORT PORT01_2_IRQHandler [WEAK] ; 18:GPIO Port 0 pin 2 Handler + EXPORT PORT01_3_IRQHandler [WEAK] ; 19:GPIO Port 0 pin 3 Handler + EXPORT PORT01_4_IRQHandler [WEAK] ; 20:GPIO Port 0 pin 4 Handler + EXPORT PORT01_5_IRQHandler [WEAK] ; 21:GPIO Port 0 pin 5 Handler + EXPORT PORT01_6_IRQHandler [WEAK] ; 22:GPIO Port 0 pin 6 Handler + EXPORT PORT01_7_IRQHandler [WEAK] ; 23:GPIO Port 0 pin 7 Handler + EXPORT PORT01_8_IRQHandler [WEAK] ; 24:GPIO Port 0 pin 8 Handler + EXPORT PORT01_9_IRQHandler [WEAK] ; 25:GPIO Port 0 pin 9 Handler + EXPORT PORT01_10_IRQHandler [WEAK] ; 26:GPIO Port 0 pin 10 Handler + EXPORT PORT01_11_IRQHandler [WEAK] ; 27:GPIO Port 0 pin 11 Handler + EXPORT PORT01_12_IRQHandler [WEAK] ; 28:GPIO Port 0 pin 12 Handler + EXPORT PORT01_13_IRQHandler [WEAK] ; 29:GPIO Port 0 pin 13 Handler + EXPORT PORT01_14_IRQHandler [WEAK] ; 30:GPIO Port 0 pin 14 Handler + EXPORT PORT01_15_IRQHandler [WEAK] ; 31:GPIO Port 0 pin 15 Handler + EXPORT SYSERROR_IRQHandler [WEAK] ; 32:System Error Interrupt + EXPORT EFLASH_IRQHandler [WEAK] ; 33:Embedded Flash Interrupt + EXPORT RESERVED1_IRQHandler [WEAK] ; 34:Reserved + EXPORT RESERVED2_IRQHandler [WEAK] ; 35:Reserved + EXPORT RESERVED3_IRQHandler [WEAK] ; 36:Reserved + EXPORT RESERVED4_IRQHandler [WEAK] ; 37:Reserved + EXPORT RESERVED5_IRQHandler [WEAK] ; 38:Reserved + EXPORT RESERVED6_IRQHandler [WEAK] ; 39:Reserved + EXPORT RESERVED7_IRQHandler [WEAK] ; 40:Reserved + EXPORT RESERVED8_IRQHandler [WEAK] ; 41:Reserved + EXPORT PORT2_ALL_IRQHandler [WEAK] ; 42:GPIO Port 2 combined Interrupt + EXPORT PORT3_ALL_IRQHandler [WEAK] ; 43:GPIO Port 3 combined Interrupt + EXPORT TRNG_IRQHandler [WEAK] ; 44:Random number generator Interrupt + EXPORT UART2_IRQHandler [WEAK] ; 45:UART 2 RX and TX Combined Interrupt + EXPORT UART3_IRQHandler [WEAK] ; 46:UART 3 RX and TX Combined Interrupt + EXPORT ETHERNET_IRQHandler [WEAK] ; 47:Ethernet interrupt t.b.a. + EXPORT I2S_IRQHandler [WEAK] ; 48:I2S Interrupt + EXPORT MPS2_SPI0_IRQHandler [WEAK] ; 49:SPI Interrupt (spi header) + EXPORT MPS2_SPI1_IRQHandler [WEAK] ; 50:SPI Interrupt (clcd) + EXPORT MPS2_SPI2_IRQHandler [WEAK] ; 51:SPI Interrupt (spi 1 ADC replacement) + EXPORT MPS2_SPI3_IRQHandler [WEAK] ; 52:SPI Interrupt (spi 0 shield 0 replacement) + EXPORT MPS2_SPI4_IRQHandler [WEAK] ; 53:SPI Interrupt (shield 1) + +UART0_IRQHandler +Spare_IRQHandler +UART1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +RTC_IRQHandler +PORT0_IRQHandler +PORT1_ALL_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +DUALTIMER_IRQHandler +SPI0_IRQHandler +UARTOVF_IRQHandler +SPI1_IRQHandler +RESERVED0_IRQHandler +TSC_IRQHandler +PORT01_0_IRQHandler +PORT01_1_IRQHandler +PORT01_2_IRQHandler +PORT01_3_IRQHandler +PORT01_4_IRQHandler +PORT01_5_IRQHandler +PORT01_6_IRQHandler +PORT01_7_IRQHandler +PORT01_8_IRQHandler +PORT01_9_IRQHandler +PORT01_10_IRQHandler +PORT01_11_IRQHandler +PORT01_12_IRQHandler +PORT01_13_IRQHandler +PORT01_14_IRQHandler +PORT01_15_IRQHandler +SYSERROR_IRQHandler +EFLASH_IRQHandler +RESERVED1_IRQHandler +RESERVED2_IRQHandler +RESERVED3_IRQHandler +RESERVED4_IRQHandler +RESERVED5_IRQHandler +RESERVED6_IRQHandler +RESERVED7_IRQHandler +RESERVED8_IRQHandler +PORT2_ALL_IRQHandler +PORT3_ALL_IRQHandler +TRNG_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +ETHERNET_IRQHandler +I2S_IRQHandler +MPS2_SPI0_IRQHandler +MPS2_SPI1_IRQHandler +MPS2_SPI2_IRQHandler +MPS2_SPI3_IRQHandler +MPS2_SPI4_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis.h new file mode 100644 index 00000000000..428ddfafadc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis.h @@ -0,0 +1,42 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2016 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* A generic CMSIS include header, pulling in MPS2 specifics +*******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CMSDK_BEID.h" +#include "SMM_MPS2.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.c new file mode 100644 index 00000000000..9ac558cceb3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.c @@ -0,0 +1,58 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2016 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* CMSIS-style functionality to support dynamic vectors +*******************************************************************************/ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.h new file mode 100644 index 00000000000..f8c6e871cb4 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/cmsis_nvic.h @@ -0,0 +1,54 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2016 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* CMSIS-style functionality to support dynamic vectors +*******************************************************************************/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#define NVIC_NUM_VECTORS (16 + 64) +#define NVIC_USER_IRQ_OFFSET 16 + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/peripherallink.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/peripherallink.h new file mode 100644 index 00000000000..9527c3e132a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/peripherallink.h @@ -0,0 +1,45 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2016 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* Name: Device.h +* Purpose: Include the correct device header file +*******************************************************************************/ + +#ifndef __DEVICE_H +#define __DEVICE_H + +#if defined CMSDK_BEID + #include "CMSDK_BEID.h" /* device specific header file */ +#else + #warning "no appropriate header file found!" +#endif + +#endif /* __DEVICE_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.c new file mode 100644 index 00000000000..fe1c3c7f468 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.c @@ -0,0 +1,95 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2016 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file system_CMSDK_BEID.c +* @brief CMSIS Device System Source File for +* CMSDK_BEID Device +* +*******************************************************************************/ + + +#include "CMSDK_BEID.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL (48000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (__XTAL / 2) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = __SYSTEM_CLOCK; + + // Enable AHB and APB clock + CMSDK_SYSCON->AHBCLKCFG0SET = 0xF; // GPIO + CMSDK_SYSCON->APBCLKCFG0SET = 0xF9B7; // UART0, UART1, TIMER0, TIMER1, DUAL TIMER +} diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.h new file mode 100644 index 00000000000..568afdf144c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_IOTSS_BEID/system_CMSDK_BEID.h @@ -0,0 +1,76 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2016 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************* +* @file system_CMSDK_BEID.h +* @brief CMSIS Device Peripheral Access Layer Header File for +* CMSDK_BEID Device +* +******************************************************************************/ + + +#ifndef SYSTEM_CMSDK_BEID_H +#define SYSTEM_CMSDK_BEID_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CMSDK_BEID_H */ diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PeripheralNames.h new file mode 100644 index 00000000000..0c6bf9b622e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PeripheralNames.h @@ -0,0 +1,91 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)CMSDK_UART1_BASE, + UART_1 = (int)CMSDK_UART3_BASE, + UART_2 = (int)CMSDK_UART0_BASE, + UART_3 = (int)CMSDK_UART2_BASE +} UARTName; + +typedef enum { + I2C_0 = (int)MPS2_TSC_I2C_BASE, + I2C_1 = (int)MPS2_AAIC_I2C_BASE, + I2C_2 = (int)MPS2_SHIELD0_I2C_BASE, + I2C_3 = (int)MPS2_SHIELD1_I2C_BASE + +} I2CName; + +typedef enum { + ADC0_0 = 0, + ADC0_1, + ADC0_2, + ADC0_3, + ADC0_4, + ADC0_5, + ADC0_6, + ADC0_7, + ADC0_8, + ADC0_9, + ADC0_10, + ADC0_11 +} ADCName; + +typedef enum { + SPI_0 = (int)MPS2_SSP0_BASE, + SPI_1 = (int)MPS2_SSP1_BASE, + SPI_2 = (int)MPS2_SSP2_BASE, + SPI_3 = (int)MPS2_SSP3_BASE, + SPI_4 = (int)MPS2_SSP4_BASE +} SPIName; + +typedef enum { + PWM_1 = 0, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6, + PWM_7, + PWM_8, + PWM_9, + PWM_10, + PWM_11 +} PWMName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +#define MBED_UART0 USBTX, USBRX +#define MBED_UART1 XB_TX, XB_RX +#define MBED_UART2 SH0_TX, SH0_RX +#define MBED_UART3 SH1_TX, SH1_RX +#define MBED_UARTUSB USBTX, USBRX + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PinNames.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PinNames.h new file mode 100644 index 00000000000..d24fdcb00aa --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PinNames.h @@ -0,0 +1,241 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 5 + +typedef enum { + // MPS2 EXP Pin Names + EXP0 = 0 , + EXP1 = 4 , + EXP2 = 2 , + EXP3 = 3 , + EXP4 = 1 , + EXP5 = 15, + EXP6 = 5 , + EXP7 = 6 , + EXP8 = 7 , + EXP9 = 8 , + EXP10 =9 , + EXP11 =13, + EXP12 =10, + EXP13 =11, + EXP14 =12, + EXP15 =14, + EXP16 =18, + EXP17 =19, + EXP18 =20, + EXP19 =21, + EXP20 =52, + EXP21 =53, + EXP22 =54, + EXP23 =55, + EXP24 =56, + EXP25 =57, + + EXP26 =16, + EXP27 =25, + EXP28 =24, + EXP29 =31, + EXP30 =17, + EXP31 =23, + EXP32 =27, + EXP33 =30, + EXP34 =26, + EXP35 =28, + EXP36 =29, + EXP37 =58, + EXP38 =48, + EXP39 =49, + EXP40 =50, + EXP41 =22, + EXP42 =59, + EXP43 =60, + EXP44 =51, + EXP45 =61, + EXP46 =62, + EXP47 =63, + EXP48 =64, + EXP49 =65, + EXP50 =66, + EXP51 =67, + +// Other mbed Pin Names + + //LEDs on mps2 + //user leds + USERLED1 = 100, + USERLED2 = 101, + //user switches + USERSW1 = 110, + USERSW2 = 111, + + //mcc leds + LED1 = 200, + LED2 = 201, + LED3 = 202, + LED4 = 203, + LED5 = 204, + LED6 = 205, + LED7 = 206, + LED8 = 207, + + //MCC Switches + SW1 = 210, + SW2 = 211, + SW3 = 212, + SW4 = 213, + SW5 = 214, + SW6 = 215, + SW7 = 216, + SW8 = 217, + + //MPS2 SPI header pins j21 + MOSI_SPI = 300, + MISO_SPI = 301, + SCLK_SPI = 302, + SSEL_SPI = 303, + + //MPS2 CLCD SPI + CLCD_MOSI = 304, + CLCD_MISO = 305, + CLCD_SCLK = 306, + CLCD_SSEL = 307, + CLCD_RESET = 308, + CLCD_RS = 309, + CLCD_RD = 310, + CLCD_BL_CTRL = 311, + + //MPS2 shield 0 SPI + SHIELD_0_SPI_SCK = 320, + SHIELD_0_SPI_MOSI = 321, + SHIELD_0_SPI_MISO = 322, + SHIELD_0_SPI_nCS = 323, + + //MPS2 shield 1 SPI + SHIELD_1_SPI_SCK = 331, + SHIELD_1_SPI_MOSI = 332, + SHIELD_1_SPI_MISO = 333, + SHIELD_1_SPI_nCS = 334, + + //MPS2 shield ADC SPI + ADC_MOSI = 650, + ADC_MISO = 651, + ADC_SCLK = 652, + ADC_SSEL = 653, + + //MPS2 Uart + USBTX = 400, + USBRX = 401, + XB_TX = 402, + XB_RX = 403, + SH0_TX = 404, + SH0_RX = 405, + SH1_TX = 406, + SH1_RX = 407, + + //MPS2 I2C touchscreen and audio + TSC_SDA = 500, + TSC_SCL = 501, + AUD_SDA = 502, + AUD_SCL = 503, + + //MPS2 I2C for shield + SHIELD_0_SDA = 504, + SHIELD_0_SCL = 505, + SHIELD_1_SDA = 506, + SHIELD_1_SCL = 507, + + //MPS2 shield Analog pins + A0_0 = 600, + A0_1 = 601, + A0_2 = 602, + A0_3 = 603, + A0_4 = 604, + A0_5 = 605, + A1_0 = 606, + A1_1 = 607, + A1_2 = 608, + A1_3 = 609, + A1_4 = 610, + A1_5 = 611, + //MPS2 Shield Digital pins + D0_0 = EXP0, + D0_1 = EXP4, + D0_2 = EXP2, + D0_3 = EXP3, + D0_4 = EXP1, + D0_5 = EXP6, + D0_6 = EXP7, + D0_7 = EXP8, + D0_8 = EXP9, + D0_9 = EXP10, + D0_10 = EXP12, + D0_11 = EXP13, + D0_12 = EXP14, + D0_13 = EXP11, + D0_14 = EXP15, + D0_15 = EXP5, + + D1_0 = EXP26, + D1_1 = EXP30, + D1_2 = EXP28, + D1_3 = EXP29, + D1_4 = EXP27, + D1_5 = EXP32, + D1_6 = EXP33, + D1_7 = EXP34, + D1_8 = EXP35, + D1_9 = EXP36, + D1_10 = EXP38, + D1_11 = EXP39, + D1_12 = EXP40, + D1_13 = EXP44, + D1_14 = EXP41, + D1_15 = EXP31, + + // Not connected + NC = (int)0xFFFFFFFF, +} PinName; + + +typedef enum { + PullUp = 2, + PullDown = 1, + PullNone = 0, + Repeater = 3, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PortNames.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PortNames.h new file mode 100644 index 00000000000..b8a39a01436 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/PortNames.h @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c new file mode 100644 index 00000000000..eaa00e8d246 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c @@ -0,0 +1,450 @@ +/* MPS2 Peripheral Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +*/ + +/* + * Code implementation file for the LAN Ethernet interface. + */ + +#include +#include "wait_api.h" +#include "ETH_MPS2.h" + +// SMSC9220 low-level operations +unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data) +{ + unsigned int val, maccmd; + int timedout; + int error; + + error = 0; + val = SMSC9220->MAC_CSR_CMD; + if(!(val & ((unsigned int)1 << 31))) { // Make sure there's no pending operation + maccmd = 0; + maccmd |= regoffset; + maccmd |= ((unsigned int)1 << 30); // Indicates read + maccmd |= ((unsigned int)1 << 31); // Start bit + SMSC9220->MAC_CSR_CMD = maccmd; // Start operation + + timedout = 50; + do { + val = SMSC9220->BYTE_TEST; // A no-op read. + wait_ms(1); //Sleepms(1); + timedout--; + } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); + + if(!timedout) { + error = 1; + } + else + *data = SMSC9220->MAC_CSR_DATA; + } else { + *data = 0; + } + return error; +} + +unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data) +{ + unsigned int read, maccmd; + int timedout; + int error; + + error = 0; + read = SMSC9220->MAC_CSR_CMD; + if(!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation + SMSC9220->MAC_CSR_DATA = data; // Store data. + maccmd = 0; + maccmd |= regoffset; + maccmd &= ~((unsigned int)1 << 30); // Clear indicates write + maccmd |= ((unsigned int)1 << 31); // Indicate start of operation + SMSC9220->MAC_CSR_CMD = maccmd; + + timedout = 50; + do { + read = SMSC9220->BYTE_TEST; // A no-op read. + wait_ms(1); //Sleepms(1); + timedout--; + } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31))); + + if(!timedout) { + error = 1; + } + } else { + printf("Warning: SMSC9220 MAC CSR is busy. No data written.\n"); + } + return error; +} + +unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data) +{ + unsigned int val, phycmd; int error; + int timedout; + + error = 0; + + smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); + + if(!(val & 1)) { // Not busy + phycmd = 0; + phycmd |= (1 << 11); // 1 to [15:11] + phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6] + phycmd &= ~(1 << 1); // Clear [1] indicates read. + phycmd |= (1 << 0); // Set [0] indicates operation start + + smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd); + + val = 0; + timedout = 50; + do { + wait_ms(1); //Sleepms(1); + timedout--; + smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val); + } while(timedout && (val & ((unsigned int)1 << 0))); + + if(!timedout) { + error = 1; + } + else + smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data); + + } else { + *data = 0; + } + return error; +} + +unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data) +{ + unsigned int val, phycmd; int error; + int timedout; + + error = 0; + + smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val); + + if(!(val & 1)) { // Not busy + smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF)); // Load the data + phycmd = 0; + phycmd |= (1 << 11); // 1 to [15:11] + phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6] + phycmd |= (1 << 1); // Set [1] indicates write. + phycmd |= (1 << 0); // Set [0] indicates operation start + smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd); // Start operation + + phycmd = 0; + timedout = 50; + + do { + + wait_ms(1); //Sleepms(1); + timedout--; + smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd); + } while(timedout && (phycmd & (1 << 0))); + + if(!timedout) { + error = 1; + } + + } else { + printf("Warning: SMSC9220 MAC MII is busy. No data written.\n"); + } + return error; +} + +// Returns smsc9220 id. +unsigned int smsc9220_read_id(void) +{ + return SMSC9220->ID_REV; +} + +// Initiates a soft reset, returns failure or success. +unsigned int smsc9220_soft_reset(void) +{ + int timedout; + + timedout = 10; + // Soft reset + SMSC9220->HW_CFG |= 1; + + do { + wait_ms(1); //Sleepms(1); + timedout--; + } while(timedout && (SMSC9220->HW_CFG & 1)); + + if(!timedout) + return 1; + + return 0; +} + +void smsc9220_set_txfifo(unsigned int val) +{ + // 2kb minimum, 14kb maximum + if(val < 2 || val > 14) + return; + + SMSC9220->HW_CFG = val << 16; +} + + +unsigned int smsc9220_wait_eeprom(void) +{ + int timedout; + + timedout = 50; + + do { + wait_ms(1); //Sleepms(1); + timedout--; + + } while(timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31))); + + if(!timedout) + return 1; + + return 0; +} + +/* initialise irqs */ +void smsc9220_init_irqs(void) +{ + SMSC9220->INT_EN = 0x0; + SMSC9220->INT_STS = 0xFFFFFFFF; // clear all interrupts + SMSC9220->IRQ_CFG = 0x22000100; // irq deassertion at 220 usecs and master IRQ enable. +} + +unsigned int smsc9220_check_phy(void) +{ + unsigned short phyid1, phyid2; + + smsc9220_phy_regread(SMSC9220_PHY_ID1,&phyid1); + smsc9220_phy_regread(SMSC9220_PHY_ID2,&phyid2); + return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) || + (phyid1 == 0x0 && phyid2 == 0x0)); +} + +unsigned int smsc9220_reset_phy(void) +{ + unsigned short read; + int error; + + error = 0; + if(smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) { + error = 1; + return error; + } + + read |= (1 << 15); + if(smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) { + error = 1; + return error; + } + return 0; +} + +/* Advertise all speeds and pause capabilities */ +void smsc9220_advertise_cap(void) +{ + unsigned short aneg_adv; + aneg_adv = 0; + + + smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv); + aneg_adv |= 0xDE0; + + smsc9220_phy_regwrite(SMSC9220_PHY_ANEG_ADV, aneg_adv); + smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv); + return; +} + +void smsc9220_establish_link(void) +{ + unsigned short bcr; + + smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr); + bcr |= (1 << 12) | (1 << 9); + smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, bcr); + smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr); + + { + unsigned int hw_cfg; + + hw_cfg = 0; + hw_cfg = SMSC9220->HW_CFG; + + hw_cfg &= 0xF0000; + hw_cfg |= (1 << 20); + SMSC9220->HW_CFG = hw_cfg; + } + + return; +} + +void smsc9220_enable_xmit(void) +{ + SMSC9220->TX_CFG = 0x2; // Enable trasmission + return; +} + +void smsc9220_enable_mac_xmit(void) +{ + unsigned int mac_cr; + + mac_cr = 0; + smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr); + + mac_cr |= (1 << 3); // xmit enable + mac_cr |= (1 << 28); // Heartbeat disable + + smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr); + return; +} + +void smsc9220_enable_mac_recv(void) +{ + unsigned int mac_cr; + + mac_cr = 0; + smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr); + mac_cr |= (1 << 2); // Recv enable + smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr); + + return; +} + + +unsigned int smsc9220_check_ready(void) +{ + return !(SMSC9220->PMT_CTRL & 1); +} + +/* Generate a soft irq */ +void smsc9220_set_soft_int(void) +{ + SMSC9220->INT_EN |= 0x80000000; +} + +/* clear soft irq */ +void smsc9220_clear_soft_int(void) +{ + SMSC9220->INT_STS |= 0x80000000; +} + + +unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index) +{ + unsigned int rxfifo_inf; // Tells us the status of rx payload and status fifos. + unsigned int rxfifo_stat; + + unsigned int pktsize; + unsigned int dwords_to_read; + + rxfifo_inf = SMSC9220->RX_FIFO_INF; + + if(rxfifo_inf & 0xFFFF) { // If there's data + rxfifo_stat = SMSC9220->RX_STAT_PORT; + if(rxfifo_stat != 0) { // Fetch status of this packet + pktsize = ((rxfifo_stat >> 16) & 0x3FFF); + if(rxfifo_stat & (1 << 15)) { + printf("Error occured during receiving of packets on the bus.\n"); + return 1; + } else { + /* Below formula (recommended by SMSC9220 code) + * gives 1 more than required. This is perhaps because + * a last word is needed for not word aligned packets. + */ + dwords_to_read = (pktsize + 3) >> 2; + // PIO copy of data received: + while(dwords_to_read > 0) { + recvbuf[*index] = SMSC9220->RX_DATA_PORT; + (*index)++; + dwords_to_read--; + } + } + } else { + return 1; + } + } else { + return 1; + } + + rxfifo_stat = SMSC9220->RX_STAT_PORT; + rxfifo_inf = SMSC9220->RX_FIFO_INF; + + return 0; +} + + +// Does the actual transfer of data to FIFO, note it does no +// fifo availability checking. This should be done by caller. +// Assumes the whole frame is transferred at once as a single segment +void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length) +{ + unsigned int txcmd_a, txcmd_b; + unsigned int dwords_to_write; + volatile unsigned int dwritten; + unsigned int *pktptr; + volatile unsigned int xmit_stat, xmit_stat2, xmit_inf; + int i; + + pktptr = (unsigned int *) pkt; + txcmd_a = 0; + txcmd_b = 0; + + txcmd_a |= (1 << 12) | (1 << 13); // First and last segments + txcmd_a |= length & 0x7FF; // [10:0] contains length + + txcmd_b |= ((length & 0xFFFF) << 16); // [31:16] contains length + txcmd_b |= length & 0x7FF; // [10:0] also contains length + + + SMSC9220->TX_DATA_PORT = txcmd_a; + SMSC9220->TX_DATA_PORT = txcmd_b; + dwritten = dwords_to_write = (length + 3) >> 2; + + // PIO Copy to FIFO. Could replace this with DMA. + while(dwords_to_write > 0) { + SMSC9220->TX_DATA_PORT = *pktptr; + pktptr++; + dwords_to_write--; + } + + xmit_stat = SMSC9220->TX_STAT_PORT; + xmit_stat2 = SMSC9220->TX_STAT_PORT; + xmit_inf = SMSC9220->TX_FIFO_INF; + + if(xmit_stat2 != 0 ) { + for(i = 0; i < 6; i++) { + xmit_stat2 = SMSC9220->TX_STAT_PORT; + } + } +} diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.h new file mode 100644 index 00000000000..10033b773f8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.h @@ -0,0 +1,65 @@ +/* MPS2 Peripheral Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _ETH_MPS2_H_ +#define _ETH_MPS2_H_ + +#include "SMM_MPS2.h" + +// Function declarations + +unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data); +unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data); +unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data); +unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data); + +unsigned int smsc9220_read_id(void); +unsigned int smsc9220_soft_reset(void); +void smsc9220_set_txfifo(unsigned int val); +unsigned int smsc9220_wait_eeprom(void); +void smsc9220_init_irqs(void); +unsigned int smsc9220_check_phy(void); +unsigned int smsc9220_reset_phy(void); + +void smsc9220_advertise_cap(void); +void smsc9220_establish_link(void); +void smsc9220_enable_xmit(void); +void smsc9220_enable_mac_xmit(void); +void smsc9220_enable_mac_recv(void); +unsigned int smsc9220_check_ready(void); +void smsc9220_set_soft_int(void); +void smsc9220_clear_soft_int(void); + +unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index); +void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length); + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.c new file mode 100644 index 00000000000..9f3de7e4aeb --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.c @@ -0,0 +1,90 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ---------------------------------------------------------------- + * File: fpga.c + * Release: Version 1.0 + * ---------------------------------------------------------------- + */ + +/* + * Code implementation file for the fpga functions. + */ + +#include "SMM_MPS2.h" // MPS2 common header + +// Function to delay n*ticks (25MHz = 40nS per tick) +// Used for I2C drivers +void i2c_delay(unsigned int tick) +{ + unsigned int end; + unsigned int start; + + start = MPS2_FPGAIO->COUNTER; + end = start + (tick); + + if(end >= start) + { + while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); + } + else + { + while (MPS2_FPGAIO->COUNTER >= start); + while (MPS2_FPGAIO->COUNTER < end); + } +} + +/* Sleep function to delay n*mS + * Uses FPGA counter. + */ +void Sleepms(unsigned int msec) +{ + unsigned int end; + unsigned int start; + + start = MPS2_FPGAIO->COUNTER; + end = start + (25 * msec * 1000); + + if(end >= start) + { + while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); + } + else + { + while (MPS2_FPGAIO->COUNTER >= start); + while (MPS2_FPGAIO->COUNTER < end); + } +} + +/* Sleep function to delay n*uS + */ +void Sleepus(unsigned int usec) +{ + unsigned int end; + unsigned int start; + + start = MPS2_FPGAIO->COUNTER; + end = start + (25 * usec); + + if(end >= start) + { + while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); + } + else + { + while (MPS2_FPGAIO->COUNTER >= start); + while (MPS2_FPGAIO->COUNTER < end); + } +} + diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.h new file mode 100644 index 00000000000..e4a055cfc04 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/fpga.h @@ -0,0 +1,34 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Code implementation file for the fpga functions. + */ + +#include "SMM_MPS2.h" // MPS2 common header + +// Function to delay n*ticks (25MHz = 40nS per tick) +// Used for I2C drivers +void i2c_delay(unsigned int tick); + +/* Sleep function to delay n*mS + * Uses FPGA counter. + */ +void Sleepms(unsigned int msec); + +/* Sleep function to delay n*uS + */ +void Sleepus(unsigned int usec); diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.c new file mode 100644 index 00000000000..54028f13a2a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.c @@ -0,0 +1,166 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "mps2_ethernet_api.h" +#include "cmsis.h" +#include "mbed_interface.h" +#include "toolchain.h" +#include "mbed_error.h" +#include "ETH_MPS2.h" +#include "wait_api.h" + +#define TX_PKT_SIZE 256 +#define RX_PKT_SIZE 300 + +// Types +#undef FALSE +#undef TRUE +#define FALSE 0 +#define TRUE 1 + + +int smsc9220_check_id(void) +{ + int error; + unsigned int id; + error = 0; + + id = smsc9220_read_id(); + + // If bottom and top halves of the word are the same + if(((id >> 16) & 0xFFFF) == (id & 0xFFFF)) { + error = 1; + return error; + } + switch(((id >> 16) & 0xFFFF)) { + case 0x9220: + break; + + default: + error = 1; + break; + } + + return error; +} + +int smsc9220_check_macaddress(void) +{ + int error; + const unsigned int mac_valid_high = 0xC00A; + const unsigned int mac_valid_low = 0x00F70200; + unsigned int mac_low; + unsigned int mac_high; + + error = 0; + + // Read current mac address. + smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high); + smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low); + + // Writing temporary address: + smsc9220_mac_regwrite(SMSC9220_MAC_ADDRH, mac_valid_high); + smsc9220_mac_regwrite(SMSC9220_MAC_ADDRL, mac_valid_low); + + // Verify write was correct: + smsc9220_mac_regread(SMSC9220_MAC_ADDRH, &mac_high); + smsc9220_mac_regread(SMSC9220_MAC_ADDRL, &mac_low); + + + if(mac_high != mac_valid_high || mac_low != mac_valid_low) { + error = TRUE; + return error; + } + + return error; +} + +void smsc9220_print_mac_registers() +{ + unsigned int read; + int i; + + i = 0; + read = 0; + + for(i = 1; i <= 0xC; i++) { + smsc9220_mac_regread(i, &read); + } + return; +} + + +void smsc9220_print_phy_registers() +{ + unsigned short read; + unsigned int i; + + i = 0; + read = 0; + for(i = 0; i <= 6; i++) { + smsc9220_phy_regread(i, &read); + } + smsc9220_phy_regread(i = 17, &read); + + smsc9220_phy_regread(i = 18, &read); + + smsc9220_phy_regread(i = 27, &read); + + smsc9220_phy_regread(i = 29, &read); + + smsc9220_phy_regread(i = 30, &read); + + smsc9220_phy_regread(i = 31, &read); + + return; +} + +/*---------------------------------------------------------------------------- + Ethernet Device initialize + *----------------------------------------------------------------------------*/ + +int ethernet_transmission(unsigned char * pkt, unsigned int length) +{ + smsc9220_xmit_packet(pkt, length); + return 0; +} + +int ethernet_reception(unsigned int *recvbuf, unsigned int *index) +{ + return smsc9220_recv_packet((unsigned int *)recvbuf, index); +} + +int ethernet_mac_address(char *mac) +{ + return smsc9220_check_macaddress(); +} + +unsigned int ethernet_check_ready(void) +{ + return smsc9220_check_ready(); +} + +unsigned int ethernet_intf() +{ + unsigned int txfifo_inf; + + txfifo_inf = SMSC9220->TX_FIFO_INF; + + return txfifo_inf; + +} + diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h new file mode 100644 index 00000000000..2a15b24a6cd --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h @@ -0,0 +1,57 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MPS2_ETHERNET_API_H +#define MPS2_ETHERNET_API_H + +#include "device.h" + +#if DEVICE_ETHERNET + +#ifdef __cplusplus +extern "C" { +#endif + +// Connection constants + +// send ethernet write buffer, returning the packet size sent +int ethernet_transmission(unsigned char * pkt, unsigned int length); + +// recieve from ethernet buffer, returning packet size, or 0 if no packet +int ethernet_reception(unsigned int *recvbuf, unsigned int *index); + +// get the ethernet address +int ethernet_mac_address(char *mac); + +unsigned int ethernet_check_ready(void); + +unsigned int ethernet_intf(void); + +int smsc9220_check_id(void); + +int smsc9220_check_macaddress(void); + +void smsc9220_print_mac_registers(void); +void smsc9220_print_phy_registers(void); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/analogin_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/analogin_api.c new file mode 100644 index 00000000000..63d92235c93 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/analogin_api.c @@ -0,0 +1,110 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" + +#include "cmsis.h" +#include "pinmap.h" + +#define ADC_12BIT_RANGE 0xFFF + +static const PinMap PinMap_ADC[] = { + {A0_0, ADC0_0, 0}, + {A0_1, ADC0_1, 0}, + {A0_2, ADC0_2, 0}, + {A0_3, ADC0_3, 0}, + {A0_4, ADC0_4, 0}, + {A0_5, ADC0_5, 0}, + {A1_0, ADC0_6, 0}, + {A1_1, ADC0_7, 0}, + {A1_2, ADC0_8, 0}, + {A1_3, ADC0_9, 0}, + {A1_4, ADC0_10, 0}, + {A1_5, ADC0_11, 0}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SCLK[] = { + {ADC_SCLK , SPI_3, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {ADC_MOSI, SPI_3, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {ADC_MISO, SPI_3, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {ADC_SSEL, SPI_3, 0}, + {NC , NC , 0} +}; + +#define ADC_RANGE ADC_12BIT_RANGE +int analog_spi_inited = 0; + +void analogin_init(analogin_t *obj, PinName pin) { + + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + obj->pin = pin; + obj->pin_number = pin-600; + obj->address = (0x0000 | (pin-600)); + + SPIName adc_mosi = (SPIName)pinmap_peripheral(ADC_MOSI, PinMap_SPI_MOSI); + SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO); + SPIName adc_sclk = (SPIName)pinmap_peripheral(ADC_SCLK, PinMap_SPI_SCLK); + SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL); + SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso); + SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel); + obj->adc_spi = (MPS2_SSP_TypeDef*)pinmap_merge(adc_data, adc_cntl); + + if(analog_spi_inited == 0){ + obj->adc_spi->CR1 = 0; + obj->adc_spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16; + obj->adc_spi->CPSR = SSP_CPSR_DFLT; + obj->adc_spi->IMSC = 0x8; + obj->adc_spi->DMACR = 0; + obj->adc_spi->CR1 = SSP_CR1_SSE_Msk; + obj->adc_spi->ICR = 0x3; + analog_spi_inited = 1; + } + + pinmap_pinout(ADC_MOSI, PinMap_SPI_MOSI); + pinmap_pinout(ADC_MISO, PinMap_SPI_MISO); + pinmap_pinout(ADC_SCLK, PinMap_SPI_SCLK); + pinmap_pinout(ADC_SSEL, PinMap_SPI_SSEL); + pinmap_pinout(pin, PinMap_ADC); +} + +static inline uint32_t adc_read(analogin_t *obj) { + return 0; +} + + +float analogin_read(analogin_t *obj) { + uint32_t value = adc_read(obj); + return 0; +} + +uint16_t analogin_read_u16(analogin_t *obj) { + return 0; +} + diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h new file mode 100644 index 00000000000..52cebb2dd84 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/device.h @@ -0,0 +1,64 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CLCD 1 + +#define DEVICE_TSC 1 + +#define DEVICE_AACI 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 1 + +#define DEVICE_PWMOUT 0 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 + +#define DEVICE_SLEEP 0 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c new file mode 100644 index 00000000000..b55de8a3e3e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c @@ -0,0 +1,164 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "ethernet_api.h" +#include "mps2_ethernet_api.h" +#include "cmsis.h" +#include "mbed_interface.h" +#include "toolchain.h" +#include "mbed_error.h" +#include "ETH_MPS2.h" +#include "wait_api.h" + +#define TX_PKT_SIZE 256 +#define RX_PKT_SIZE 300 + +// Types +#undef FALSE +#undef TRUE +#define FALSE 0 +#define TRUE 1 + +/*---------------------------------------------------------------------------- + Ethernet Device initialize + *----------------------------------------------------------------------------*/ +int ethernet_init() +{ + int error; + error = 0; + + if(smsc9220_check_id()) { + error = TRUE; + } + + if(smsc9220_soft_reset()) { + error = TRUE; + } + + smsc9220_set_txfifo(5); + + // Sets automatic flow control thresholds, and backpressure + // threshold to defaults specified. + SMSC9220->AFC_CFG = 0x006E3740; + + if(smsc9220_wait_eeprom()) { + error = TRUE; + } + + // Configure GPIOs as LED outputs. + SMSC9220->GPIO_CFG = 0x70070000; + + smsc9220_init_irqs(); + + /* Configure MAC addresses here if needed. */ + + if(smsc9220_check_phy()) { + error = TRUE; + } + + if(smsc9220_reset_phy()) { + error = TRUE; + return error; + } + + wait_ms(100); + // Checking whether phy reset completed successfully. + { + unsigned short phyreset; + phyreset = 0; + smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &phyreset); + if(phyreset & (1 << 15)) { + error = TRUE; + return error; + } + } + + /* Advertise capabilities */ + smsc9220_advertise_cap(); + + + /* Begin to establish link */ + smsc9220_establish_link(); // bit [12] of BCONTROL seems self-clearing. + // Although it's not so in the manual. + + /* Interrupt threshold */ + SMSC9220->FIFO_INT = 0xFF000000; + + smsc9220_enable_mac_xmit(); + + smsc9220_enable_xmit(); + + SMSC9220->RX_CFG = 0; + + smsc9220_enable_mac_recv(); + + // Rx status FIFO level irq threshold + SMSC9220->FIFO_INT &= ~(0xFF); // Clear 2 bottom nibbles + + // This sleep is compulsory otherwise txmit/receive will fail. + wait_ms(2000); + return error; + +} + +/*---------------------------------------------------------------------------- + Ethernet Device Uninitialize + *----------------------------------------------------------------------------*/ +void ethernet_free() { +} + +int ethernet_write(const char *data, int size) +{ + return 0; +} + +int ethernet_send() +{ + return 0; +} + +int ethernet_receive() +{ + return 0; +} + +// Read from an recevied ethernet packet. +// After receive returnd a number bigger than 0 it is +// possible to read bytes from this packet. +// Read will write up to size bytes into data. +// It is possible to use read multible times. +// Each time read will start reading after the last read byte before. + +int ethernet_read(char *data, int dlen) +{ + return 0; +} + +void ethernet_address(char *mac) { + mbed_mac_address(mac); +} + +int ethernet_link(void) +{ + return 0; +} + +void ethernet_set_link(int speed, int duplex) +{ + smsc9220_establish_link(); +} + diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_api.c new file mode 100644 index 00000000000..2ea0d1e54ee --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_api.c @@ -0,0 +1,140 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "pinmap.h" + +// function to enable the GPIO pin +uint32_t gpio_set(PinName pin) { + return (1); +} + +//function to initialise the gpio pin +// this links the board control bits for each pin +// with the object created for the pin +void gpio_init(gpio_t *obj, PinName pin) { + if(pin == NC){ return;} + else { + int pin_value = 0; + obj->pin = pin; + if(pin <=15){ + pin_value = pin; + }else if (pin >= 16 && pin <= 31){ + pin_value = pin-16; + }else if (pin >= 32 && pin <= 47){ + pin_value = pin-32; + }else if (pin >= 48 && pin <= 51){ + pin_value = pin-48; + }else if (pin == 100 || pin == 101){ + pin_value = pin-100; + }else if (pin == 110 || pin == 111){ + pin_value = pin-110; + }else if (pin >= 200 && pin <= 207){ + pin_value = pin-200; + }else if (pin >= 210 && pin <= 217){ + pin_value = pin-210; + }else if (pin == 303){ + pin_value = pin-302; + }else if (pin == 307){ + pin_value = pin-307; + }else if (pin == 308){ + pin_value = pin-305; + }else if (pin == 309){ + pin_value = pin-305; + }else if (pin == 310){ + pin_value = pin-305; + }else if (pin == 311){ + pin_value = pin-305; + }else if (pin == 323){ + pin_value = pin-315; + }else if (pin == 334){ + pin_value = pin-325; + }else if (pin == 653){ + pin_value = pin-646; + } + + obj->mask = 0x1 << pin_value; + obj->pin_number = pin; + if(pin <=15) { + obj->reg_data = &CMSDK_GPIO0->DATAOUT ; + obj->reg_in = &CMSDK_GPIO0->DATA ; + obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET ; + obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR ; + } else if (pin >= 16 && pin <= 31){ + obj->reg_data = &CMSDK_GPIO1->DATAOUT ; + obj->reg_in = &CMSDK_GPIO1->DATA ; + obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET ; + obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR ; + } else if (pin >= 32 && pin <= 47){ + obj->reg_data = &CMSDK_GPIO2->DATAOUT; + obj->reg_in = &CMSDK_GPIO2->DATA; + obj->reg_dir = &CMSDK_GPIO2->OUTENABLESET ; + obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR ; + } else if (pin >= 48 && pin <= 51){ + obj->reg_data = &CMSDK_GPIO3->DATAOUT; + obj->reg_in = &CMSDK_GPIO3->DATA; + obj->reg_dir = &CMSDK_GPIO3->OUTENABLESET ; + obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR ; + } else if (pin == 100 || pin == 101){ + obj->reg_data = &MPS2_FPGAIO->LED; //user leds + obj->reg_in = &MPS2_FPGAIO->LED; + } else if (pin == 110 || pin == 111){ + obj->reg_data = &MPS2_FPGAIO->BUTTON; //user switches + obj->reg_in = &MPS2_FPGAIO->BUTTON; //user switches + }else if (pin >= 200 && pin <= 207){ + obj->reg_data = &MPS2_SCC->LEDS; //mcc leds + obj->reg_in = &MPS2_SCC->LEDS; //mcc leds + }else if (pin >= 210 && pin <= 217){ + obj->reg_in = &MPS2_SCC->SWITCHES; //mcc switches + }else if (pin == 303 || pin == 307){ + obj->reg_data = &MPS2_FPGAIO->MISC; //spi chip select = 303, clcd chip select = 307 + }else if (pin == 308 || pin == 309 || pin == 310 || pin == 311){ + obj->reg_data = &MPS2_FPGAIO->MISC; //clcd control bits + }else if (pin == 323 || pin == 334 || pin == 653){ //spi 3 chip select = 323, spi 4 chip select = 334, adc chip select = 653 + obj->reg_data = &MPS2_FPGAIO->MISC; //spi cs bits + } + + if (pin == 323){ + CMSDK_GPIO0->ALTFUNCSET |= 0x0400; + }else if (pin == 334){ + CMSDK_GPIO4->ALTFUNCSET |= 0x0001; + }else if (pin == 653){ + CMSDK_GPIO1->ALTFUNCSET |= 0x0004; + } + } +} + +void gpio_mode(gpio_t *obj, PinMode mode) { + pin_mode(obj->pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) { + if(obj->pin >= 0 && obj->pin <= 51) + { + switch (direction) { + case PIN_INPUT : *obj->reg_dirclr = obj->mask; break; + case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; + } + } else {return;} +} + +int gpio_is_connected(const gpio_t *obj){ + if(obj->pin != (PinName)NC){ + return 1; + } else { + return 0; + } +} + diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_irq_api.c new file mode 100644 index 00000000000..8aa125a4b0b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_irq_api.c @@ -0,0 +1,241 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "mbed_error.h" + +#define CHANNEL_NUM 32 +#define CMSDK_GPIO_0 CMSDK_GPIO0 +#define CMSDK_GPIO_1 CMSDK_GPIO1 +#define PININT_IRQ 0 + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler irq_handler; + +static inline void handle_interrupt_in(uint32_t channel) { + uint32_t ch_bit = (1 << channel); + // Return immediately if: + // * The interrupt was already served + // * There is no user handler + // * It is a level interrupt, not an edge interrupt + if (ch_bit <16){ + if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return; + + if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_RISE); + CMSDK_GPIO_0->INTPOLSET = ch_bit; + } + if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_FALL); + } + CMSDK_GPIO_0->INTCLEAR = ch_bit; + } + + if (ch_bit>=16) { + if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return; + + if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_RISE); + CMSDK_GPIO_1->INTPOLSET = ch_bit; + } + if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_FALL); + } + CMSDK_GPIO_1->INTCLEAR = ch_bit; + } +} + +void gpio0_irq0(void) {handle_interrupt_in(0);} +void gpio0_irq1(void) {handle_interrupt_in(1);} +void gpio0_irq2(void) {handle_interrupt_in(2);} +void gpio0_irq3(void) {handle_interrupt_in(3);} +void gpio0_irq4(void) {handle_interrupt_in(4);} +void gpio0_irq5(void) {handle_interrupt_in(5);} +void gpio0_irq6(void) {handle_interrupt_in(6);} +void gpio0_irq7(void) {handle_interrupt_in(7);} +void gpio0_irq8(void) {handle_interrupt_in(8);} +void gpio0_irq9(void) {handle_interrupt_in(9);} +void gpio0_irq10(void) {handle_interrupt_in(10);} +void gpio0_irq11(void) {handle_interrupt_in(11);} +void gpio0_irq12(void) {handle_interrupt_in(12);} +void gpio0_irq13(void) {handle_interrupt_in(13);} +void gpio0_irq14(void) {handle_interrupt_in(14);} +void gpio0_irq15(void) {handle_interrupt_in(15);} +void gpio1_irq0(void) {handle_interrupt_in(16);} +void gpio1_irq1(void) {handle_interrupt_in(17);} +void gpio1_irq2(void) {handle_interrupt_in(18);} +void gpio1_irq3(void) {handle_interrupt_in(19);} +void gpio1_irq4(void) {handle_interrupt_in(20);} +void gpio1_irq5(void) {handle_interrupt_in(21);} +void gpio1_irq6(void) {handle_interrupt_in(22);} +void gpio1_irq7(void) {handle_interrupt_in(23);} +void gpio1_irq8(void) {handle_interrupt_in(24);} +void gpio1_irq9(void) {handle_interrupt_in(25);} +void gpio1_irq10(void) {handle_interrupt_in(26);} +void gpio1_irq11(void) {handle_interrupt_in(27);} +void gpio1_irq12(void) {handle_interrupt_in(28);} +void gpio1_irq13(void) {handle_interrupt_in(29);} +void gpio1_irq14(void) {handle_interrupt_in(30);} +void gpio1_irq15(void) {handle_interrupt_in(31);} + + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { + if (pin == NC) {return -1;} + else { + + irq_handler = handler; + + int found_free_channel = 0; + int i = 0; + for (i=0; ich = i; + found_free_channel = 1; + break; + } + } + if (!found_free_channel) return -1; + + + /* To select a pin for any of the eight pin interrupts, write the pin number + * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55. + * @see: mbed_capi/PinNames.h + */ + if (pin <16) + { + CMSDK_GPIO_0->INTENSET |= (0x1 << pin); + } + + if (pin >= 16) + { + CMSDK_GPIO_1->INTENSET |= (0x1 << pin); + } + + void (*channels_irq)(void) = NULL; + switch (obj->ch) { + case 0: channels_irq = &gpio0_irq0; break; + case 1: channels_irq = &gpio0_irq1; break; + case 2: channels_irq = &gpio0_irq2; break; + case 3: channels_irq = &gpio0_irq3; break; + case 4: channels_irq = &gpio0_irq4; break; + case 5: channels_irq = &gpio0_irq5; break; + case 6: channels_irq = &gpio0_irq6; break; + case 7: channels_irq = &gpio0_irq7; break; + case 8: channels_irq = &gpio0_irq8; break; + case 9: channels_irq = &gpio0_irq9; break; + case 10: channels_irq = &gpio0_irq10; break; + case 11: channels_irq = &gpio0_irq11; break; + case 12: channels_irq = &gpio0_irq12; break; + case 13: channels_irq = &gpio0_irq13; break; + case 14: channels_irq = &gpio0_irq14; break; + case 15: channels_irq = &gpio0_irq15; break; + case 16: channels_irq = &gpio1_irq0; break; + case 17: channels_irq = &gpio1_irq1; break; + case 18: channels_irq = &gpio1_irq2; break; + case 19: channels_irq = &gpio1_irq3; break; + case 20: channels_irq = &gpio1_irq4; break; + case 21: channels_irq = &gpio1_irq5; break; + case 22: channels_irq = &gpio1_irq6; break; + case 23: channels_irq = &gpio1_irq7; break; + case 24: channels_irq = &gpio1_irq8; break; + case 25: channels_irq = &gpio1_irq9; break; + case 26: channels_irq = &gpio1_irq10; break; + case 27: channels_irq = &gpio1_irq11; break; + case 28: channels_irq = &gpio1_irq12; break; + case 29: channels_irq = &gpio1_irq13; break; + case 30: channels_irq = &gpio1_irq14; break; + case 31: channels_irq = &gpio1_irq15; break; + + } + NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); + NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); + + return 0; + } +} + +void gpio_irq_free(gpio_irq_t *obj) { +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + unsigned int ch_bit = (1 << obj->ch); + + // Clear interrupt + if (obj->ch <16) + { + if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit)) + { + CMSDK_GPIO_0->INTCLEAR = ch_bit; + } + } + if (obj->ch >= 16) + { + if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit)) + { + CMSDK_GPIO_1->INTCLEAR = ch_bit; + } + } + + // Edge trigger + if (obj->ch <16) + { + CMSDK_GPIO_0->INTTYPESET &= ch_bit; + if (event == IRQ_RISE) { + CMSDK_GPIO_0->INTPOLSET |= ch_bit; + if (enable) { + CMSDK_GPIO_0->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_0->INTENCLR |= ch_bit; + } + } else { + CMSDK_GPIO_0->INTPOLCLR |= ch_bit; + if (enable) { + CMSDK_GPIO_0->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_0->INTENCLR |= ch_bit; + } + } + } + if (obj->ch >= 16) + { + CMSDK_GPIO_1->INTTYPESET &= ch_bit; + if (event == IRQ_RISE) { + CMSDK_GPIO_1->INTPOLSET |= ch_bit; + if (enable) { + CMSDK_GPIO_1->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_1->INTENCLR |= ch_bit; + } + } else { + CMSDK_GPIO_1->INTPOLCLR |= ch_bit; + if (enable) { + CMSDK_GPIO_1->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_1->INTENCLR |= ch_bit; + } + } + } +} + +void gpio_irq_enable(gpio_irq_t *obj) { + NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); +} + +void gpio_irq_disable(gpio_irq_t *obj) { + NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); +} diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_object.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_object.h new file mode 100644 index 00000000000..5bbf435fe69 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/gpio_object.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + uint32_t pin_number; + + __IO uint32_t *reg_dir; + __IO uint32_t *reg_dirclr; + __IO uint32_t *reg_data; + __I uint32_t *reg_in; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) { + if (value){ + *obj->reg_data |= (obj->mask); + } else { + *obj->reg_data &= ~(obj->mask); + } +} + +static inline int gpio_read(gpio_t *obj) { + return ((*obj->reg_in & obj->mask) ? 1 : 0); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c new file mode 100644 index 00000000000..52fac6e6c81 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/i2c_api.c @@ -0,0 +1,542 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "i2c_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "SMM_MPS2.h" +#include "wait_api.h" +#include "fpga.h" + +// Types +#undef FALSE +#undef TRUE +#define FALSE 0 +#define TRUE 1 + +// TSC I2C controller +#define TSC_I2C_ADDR 0x82 +// AACI I2C controller I2C address +#define AAIC_I2C_ADDR 0x96 +// LM75B I2C address +#define LM75_I2C_ADDR 0x90 +// MMA7660 I2C address +#define MMA7660_I2C_ADDR 0x98 + +// Timing Delays +#define TSC_TSU 15 // Setup delay 600nS min +#define AAIC_TSU 25 // Setup delay 1000nS min +#define SHIELD_TSU 25 // Setup delay 1000nS min + + +static const PinMap PinMap_I2C_SDA[] = { + {TSC_SDA, I2C_0, 0}, + {AUD_SDA, I2C_1, 0}, + {SHIELD_0_SDA, I2C_2, 0}, + {SHIELD_1_SDA, I2C_3, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {TSC_SCL, I2C_0, 0}, + {AUD_SCL, I2C_1, 0}, + {SHIELD_0_SCL, I2C_2, 0}, + {SHIELD_1_SCL, I2C_3, 0}, + {NC , NC, 0} +}; + +static inline void i2c_send_byte(i2c_t *obj, unsigned char c) +{ + int loop; + switch ((int)obj->i2c) { + case I2C_0: + obj->i2c->CONTROLC = SCL; + i2c_delay(TSC_TSU); + + for (loop = 0; loop < 8; loop++) + { + if (c & (1 << (7 - loop))) + obj->i2c->CONTROLS = SDA; + else + obj->i2c->CONTROLC = SDA; + + i2c_delay(TSC_TSU); + obj->i2c->CONTROLS = SCL; + i2c_delay(TSC_TSU); + obj->i2c->CONTROLC = SCL; + i2c_delay(TSC_TSU); + } + + obj->i2c->CONTROLS = SDA; + i2c_delay(TSC_TSU); + break; + case I2C_1: + for (loop = 0; loop < 8; loop++) { + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SCL; + i2c_delay(AAIC_TSU); + if (c & (1 << (7 - loop))) + obj->i2c->CONTROLS = SDA; + else + obj->i2c->CONTROLC = SDA; + + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLS = SCL; + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SCL; + } + + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLS = SDA; + i2c_delay(AAIC_TSU); + break; + case I2C_2: + case I2C_3: + obj->i2c->CONTROLC = SCL; + i2c_delay(SHIELD_TSU); + + for (loop = 0; loop < 8; loop++) + { + if (c & (1 << (7 - loop))) + obj->i2c->CONTROLS = SDA; + else + obj->i2c->CONTROLC = SDA; + + i2c_delay(SHIELD_TSU); + obj->i2c->CONTROLS = SCL; + i2c_delay(SHIELD_TSU); + obj->i2c->CONTROLC = SCL; + i2c_delay(SHIELD_TSU); + } + + obj->i2c->CONTROLS = SDA; + i2c_delay(SHIELD_TSU); + break; + } +} + +static inline unsigned char i2c_receive_byte(i2c_t *obj) +{ + int data_receive_byte, loop; + switch ((int)obj->i2c) { + case I2C_0: + obj->i2c->CONTROLS = SDA; + i2c_delay(TSC_TSU); + + data_receive_byte = 0; + + for (loop = 0; loop < 8; loop++) + { + obj->i2c->CONTROLS = SCL; + i2c_delay(TSC_TSU); + if ((obj->i2c->CONTROL & SDA)) + data_receive_byte += (1 << (7 - loop)); + + obj->i2c->CONTROLC = SCL; + i2c_delay(TSC_TSU); + } + + obj->i2c->CONTROLC = SDA; + i2c_delay(TSC_TSU); + break; + case I2C_1: + obj->i2c->CONTROLS = SDA; + data_receive_byte = 0; + + for (loop = 0; loop < 8; loop++) { + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SCL; + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLS = SCL | SDA; + i2c_delay(AAIC_TSU); + if ((obj->i2c->CONTROL & SDA)) + data_receive_byte += (1 << (7 - loop)); + + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SCL; + } + + i2c_delay(AAIC_TSU); + obj->i2c->CONTROLC = SDA; + i2c_delay(AAIC_TSU); + break; + case I2C_2: + case I2C_3: + obj->i2c->CONTROLS = SDA; + i2c_delay(SHIELD_TSU); + + data_receive_byte = 0; + + for (loop = 0; loop < 8; loop++) + { + obj->i2c->CONTROLS = SCL; + i2c_delay(SHIELD_TSU); + if ((obj->i2c->CONTROL & SDA)) + data_receive_byte += (1 << (7 - loop)); + + obj->i2c->CONTROLC = SCL; + i2c_delay(SHIELD_TSU); + } + + obj->i2c->CONTROLC = SDA; + i2c_delay(SHIELD_TSU); + break; + } + return data_receive_byte; +} + +static inline int i2c_receive_ack(i2c_t *obj) +{ + int nack; + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + + i2c_delay(delay_value); + obj->i2c->CONTROLS = SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SCL; + i2c_delay(delay_value); + nack = obj->i2c->CONTROL & SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SDA; + i2c_delay(delay_value); + if(nack==0) + return 1; + + return 0; +} + + +static inline void i2c_send_nack(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); + +} + +static inline void i2c_send_ack(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); + +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + // determine the SPI to use + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->i2c = (MPS2_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl); + + if ((int)obj->i2c == NC) { + error("I2C pin mapping failed"); + } + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + switch ((int)obj->i2c) { + case I2C_2: CMSDK_GPIO0->ALTFUNCSET |= 0xC000; break; + case I2C_3: CMSDK_GPIO1->ALTFUNCSET |= 0x00C0; break; + } + + +} + +int i2c_start(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + + i2c_delay(delay_value); + obj->i2c->CONTROLS = SDA | SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); + + return 0; +} + +int i2c_start_tsc(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLC = SCL; + i2c_delay(delay_value); + + return 0; +} + +int i2c_stop(i2c_t *obj) +{ + int delay_value; + switch ((int)obj->i2c) { + case I2C_0: delay_value = TSC_TSU; break; + case I2C_1: delay_value = AAIC_TSU; break; + case I2C_2: delay_value = SHIELD_TSU; break; + case I2C_3: delay_value = SHIELD_TSU; break; + } + // Actual stop bit + i2c_delay(delay_value); + obj->i2c->CONTROLC = SDA; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SCL; + i2c_delay(delay_value); + obj->i2c->CONTROLS = SDA; + i2c_delay(delay_value); + + return 0; +} + + + +void i2c_frequency(i2c_t *obj, int hz) { +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + unsigned int loop, rxdata; + int sadr, ack, bytes_read; + rxdata=0; + switch ((int)obj->i2c) { + case I2C_0: + sadr = TSC_I2C_ADDR; + break; + case I2C_1: + sadr = AAIC_I2C_ADDR; + break; + case I2C_2: + case I2C_3: + sadr = address; //LM75_I2C_ADDR; or MMA7660_I2C_ADDR; + break; + } + bytes_read = 0; + // Start bit + i2c_start(obj); + + switch ((int)obj->i2c) { + case I2C_0: + // Set serial and register address + i2c_send_byte(obj,sadr); + ack += i2c_receive_ack(obj); + i2c_send_byte(obj, address); + ack += i2c_receive_ack(obj); + + // Stop bit + i2c_stop(obj); + + // Start bit + i2c_start_tsc(obj); + + // Read from I2C address + i2c_send_byte(obj,sadr | 1); + ack += i2c_receive_ack(obj); + + rxdata = (i2c_receive_byte(obj) & 0xFF); + data[((length-1)-bytes_read)] = (char)rxdata; + bytes_read++; + // Read multiple bytes + if ((length > 1) && (length < 5)) + { + for (loop = 1; loop <= (length - 1); loop++) + { + // Send ACK + i2c_send_ack(obj); + + // Next byte + //rxdata = ((rxdata << 8) & 0xFFFFFF00); + //rxdata |= (i2c_receive_byte(obj) & 0xFF); + rxdata = i2c_receive_byte(obj); + data[(length-1)-bytes_read] = (char)rxdata; + bytes_read++; + + } + } + break; + case I2C_1: + // Set serial and register address + i2c_send_byte(obj,sadr); + ack += i2c_receive_ack(obj); + i2c_send_byte(obj, address); + ack += i2c_receive_ack(obj); + + // Stop bit + i2c_stop(obj); + + // Start bit + i2c_start_tsc(obj); + // Fall through to read data + case I2C_2: + case I2C_3: + // Read from preset register address pointer + i2c_send_byte(obj,sadr | 1); + ack += i2c_receive_ack(obj); + + rxdata = i2c_receive_byte(obj); + data[bytes_read] = (char)rxdata; + bytes_read++; + // Read multiple bytes + if ((length > 1) && (length < 5)) + { + for (loop = 1; loop <= (length - 1); loop++) + { + // Send ACK + i2c_send_ack(obj); + + // Next byte + rxdata = i2c_receive_byte(obj); + data[loop] = (char)rxdata; + bytes_read++; + + } + } + break; + } + i2c_send_nack(obj); + + i2c_stop(obj); // Actual stop bit + + return bytes_read; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int ack=0; + int sadr; + char * ptr; + char addr; + ptr = (char*)data; + switch ((int)obj->i2c) + { + case I2C_0: + sadr = TSC_I2C_ADDR; + addr = address; + break; + case I2C_1: + sadr = AAIC_I2C_ADDR; + addr = address; + break; + case I2C_2: + case I2C_3: + sadr = address; //LM75_I2C_ADDR or MMA7660_I2C_ADDR; + addr = *ptr++; + break; + } + +// printf("adr = %x, reg = %x\n",sadr, address); + i2c_start(obj); + + // Set serial and register address + i2c_send_byte(obj,sadr); + ack += i2c_receive_ack(obj); + i2c_send_byte(obj, addr); + ack += i2c_receive_ack(obj); + + for(int i = 1; iport = port; + obj->mask = mask; + + CMSDK_GPIO_TypeDef *port_reg = (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO0_BASE + ((int)port * 0x10)); + + obj->reg_in = &port_reg->DATAOUT; + obj->reg_dir = &port_reg->OUTENABLESET; + obj->reg_dirclr = &port_reg->OUTENABLECLR; + + uint32_t i; + // The function is set per pin: reuse gpio logic + for (i=0; i<16; i++) { + if (obj->mask & (1<port, i)); + } + } + + port_dir(obj, dir); +} + +void port_mode(port_t *obj, PinMode mode) { + uint32_t i; + // The mode is set per pin: reuse pinmap logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) { + switch (dir) { + case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; + case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; + } +} + +void port_write(port_t *obj, int value) { + *obj->reg_in = value; +} + +int port_read(port_t *obj) { + return (*obj->reg_in); +} diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/serial_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/serial_api.c new file mode 100644 index 00000000000..4341abcfaf5 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/serial_api.c @@ -0,0 +1,367 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// math.h required for floating point operations for baud rate calculation +#include +#include +#include +#include + +#include "serial_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "gpio_api.h" + +/****************************************************************************** + * INITIALIZATION + ******************************************************************************/ + +static const PinMap PinMap_UART_TX[] = { + {USBTX , UART_0, 0}, + {XB_TX , UART_1, 0}, + {SH0_TX , UART_2, 0}, + {SH1_TX , UART_3, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {USBRX , UART_0, 0}, + {XB_RX , UART_1, 0}, + {SH0_RX , UART_2, 0}, + {SH1_RX , UART_3, 0}, + {NC , NC , 0} +}; + +#define UART_NUM 4 + +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +struct serial_global_data_s { + uint32_t serial_irq_id; + gpio_t sw_rts, sw_cts; + uint8_t count, rx_irq_set_flow, rx_irq_set_api; +}; + +static struct serial_global_data_s uart_data[UART_NUM]; + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + int is_stdio_uart = 0; + + // determine the UART to use + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + if ((int)uart == NC) { + error("Serial pinout mapping failed"); + } + + obj->uart = (CMSDK_UART_TypeDef *)uart; + //set baud rate and enable Uart in normarl mode (RX and TX enabled) + switch (uart) + { + case UART_0: //UART HEADER + { + CMSDK_UART1->CTRL = 0x0; // Disable UART when changing configuration + if((int)tx != NC) + { + CMSDK_UART1->CTRL |= 0x01; // TX enable + } else { + CMSDK_UART1->CTRL &= 0xFFFE; // TX disable + } + if((int)rx != NC) + { + CMSDK_UART1->CTRL |= 0x02; // RX enable + } else { + CMSDK_UART1->CTRL &= 0xFFFD; // RX disable + } + } + break; + case UART_1: //XBEE SOCKET UART + { + CMSDK_UART3->CTRL = 0x00; // Disable UART when changing configuration + if((int)tx != NC) + { + CMSDK_UART3->CTRL = 0x1; // TX enable + CMSDK_GPIO4->ALTFUNCSET |= 0x0100; + } + if((int)rx != NC) + { + CMSDK_UART3->CTRL |= 0x2; // RX enable + CMSDK_GPIO4->ALTFUNCSET |= 0x0080; + } + } + break; + case UART_2: //Sheild0 UART + { + CMSDK_UART0->CTRL = 0x00; // Disable UART when changing configuration + if((int)uart_tx != NC) + { + CMSDK_UART0->CTRL |= 0x01; // TX enable + CMSDK_GPIO0->ALTFUNCSET |= 0x0002; + } + + if((int)uart_rx != NC) + { + CMSDK_UART0->CTRL |= 0x02; // RX enable + CMSDK_GPIO0->ALTFUNCSET |= 0x0001; + } + } + break; + case UART_3: //Sheild1 UART + { + CMSDK_UART2->CTRL = 0x00; // Disable UART when changing configuration + if((int)tx != NC) + { + CMSDK_UART2->CTRL = 0x1; // TX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x0002; + } + if((int)rx != NC) + { + CMSDK_UART2->CTRL |= 0x2; // RX enable + CMSDK_GPIO1->ALTFUNCSET |= 0x0001; + } + } + break; + } + + // set default baud rate and format + serial_baud (obj, 9600); + + // pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + switch (uart) { + case UART_0: obj->index = 0; break; + case UART_1: obj->index = 1; break; + case UART_2: obj->index = 2; break; + case UART_3: obj->index = 3; break; + } + uart_data[obj->index].sw_rts.pin = NC; + uart_data[obj->index].sw_cts.pin = NC; + serial_set_flow_control(obj, FlowControlNone, NC, NC); + + is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + uart_data[obj->index].serial_irq_id = 0; +} + +// serial_baud +// set the baud rate, taking in to account the current SystemFrequency +void serial_baud(serial_t *obj, int baudrate) { + // The MPS2 has a simple divider to control the baud rate. The formula is: + // + // Baudrate = PCLK / BAUDDIV + // + // PCLK = 24 Mhz + // so for a desired baud rate of 9600 + // 24000000 / 9600 = 2500 + // + //check to see if minimum baud value entered + int baudrate_div = 0; + baudrate_div = SystemCoreClock / baudrate; + if(baudrate >= 16){ + switch ((int)obj->uart) { + case UART_0: CMSDK_UART1->BAUDDIV = baudrate_div; break; + case UART_1: CMSDK_UART3->BAUDDIV = baudrate_div; break; + case UART_2: CMSDK_UART0->BAUDDIV = baudrate_div; break; + case UART_3: CMSDK_UART2->BAUDDIV = baudrate_div; break; + default: error("serial_baud"); break; + } + } else { + error("serial_baud"); + } + +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeDef *puart) { + SerialIrq irq_type; + switch (intstatus) + { + case 1: + { + irq_type = TxIrq; + } + break; + + case 2: + { + irq_type = RxIrq; + } + break; + + default: return; + } /* End of Switch */ + + if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) + { + gpio_write(&uart_data[index].sw_rts, 1); + // Disable interrupt if it wasn't enabled by other part of the application + if (!uart_data[index].rx_irq_set_api) + { + /* Disable Rx interrupt */ + puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk); + } + } + + if (uart_data[index].serial_irq_id != 0) + { + if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) + { + irq_handler(uart_data[index].serial_irq_id, irq_type); + } + } + + if( irq_type == TxIrq ) + { + /* Clear the TX interrupt Flag */ + puart->INTCLEAR |= 0x01; + } + else + { + /* Clear the Rx interupt Flag */ + puart->INTCLEAR |= 0x02; + } +} + +void uart0_irq() {uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART1);} +void uart1_irq() {uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART3);} +void uart2_irq() {uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART0);} +void uart3_irq() {uart_irq(CMSDK_UART2->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART2);} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + uart_data[obj->index].serial_irq_id = id; +} + +static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + switch ((int)obj->uart) + { + case UART_0: + irq_n = UART0_IRQn; + vector = (uint32_t)&uart0_irq; + break; + case UART_1: + irq_n = UART1_IRQn; + vector = (uint32_t)&uart1_irq; + break; + case UART_2: + { + irq_n = UART2_IRQn; + vector = (uint32_t)&uart2_irq; + } + break; + case UART_3: + { + irq_n = UART3_IRQn; + vector = (uint32_t)&uart3_irq; + } + break; + } + + if (enable) + { + if (irq == TxIrq) + { + /* set TX interrupt enable in CTRL REG */ + obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk; + } + else + { + /* set Rx interrupt on in CTRL REG */ + obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk; + } + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + } + else if ((irq == TxIrq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) + { /* Disable IRQ */ + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + + obj->uart->CTRL &= ~(1 << (irq + 2)); + + all_disabled = (obj->uart->CTRL & (1 << (other_irq + 2))) == 0; + + if (all_disabled) + { + NVIC_DisableIRQ(irq_n); + } + } +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + if (RxIrq == irq) + uart_data[obj->index].rx_irq_set_api = enable; + serial_irq_set_internal(obj, irq, enable); +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ +int serial_getc(serial_t *obj) { + while (serial_readable(obj) == 0); + int data = obj->uart->DATA; + return data; +} + +void serial_putc(serial_t *obj, int c) { + while (serial_writable(obj)); + obj->uart->DATA = c; +} + +int serial_readable(serial_t *obj) { + return obj->uart->STATE & 0x2; +} + +int serial_writable(serial_t *obj) { + return obj->uart->STATE & 0x1; +} + +void serial_clear(serial_t *obj) { + obj->uart->DATA = 0x00; +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { +} + +void serial_break_clear(serial_t *obj) { +} +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { +} + diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c new file mode 100644 index 00000000000..1239f2d6fea --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c @@ -0,0 +1,286 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "spi_api.h" +#include "spi_def.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "wait_api.h" + +static const PinMap PinMap_SPI_SCLK[] = { + {SCLK_SPI , SPI_0, 0}, + {CLCD_SCLK , SPI_1, 0}, + {ADC_SCLK , SPI_2, 0}, + {SHIELD_0_SPI_SCK , SPI_3, 0}, + {SHIELD_1_SPI_SCK , SPI_4, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {MOSI_SPI, SPI_0, 0}, + {CLCD_MOSI, SPI_1, 0}, + {ADC_MOSI, SPI_2, 0}, + {SHIELD_0_SPI_MOSI, SPI_3, 0}, + {SHIELD_1_SPI_MOSI, SPI_4, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {MISO_SPI, SPI_0, 0}, + {CLCD_MISO, SPI_1, 0}, + {ADC_MISO, SPI_2, 0}, + {SHIELD_0_SPI_MISO, SPI_3, 0}, + {SHIELD_1_SPI_MISO, SPI_4, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {SSEL_SPI, SPI_0, 0}, + {CLCD_SSEL, SPI_1, 0}, + {ADC_SSEL, SPI_2, 0}, + {SHIELD_0_SPI_nCS, SPI_3, 0}, + {SHIELD_1_SPI_nCS, SPI_4, 0}, + {NC , NC , 0} +}; + +static inline int ssp_disable(spi_t *obj); +static inline int ssp_enable(spi_t *obj); + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + + int altfunction[4]; + // determine the SPI to use + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); + if ((int)obj->spi == NC) { + error("SPI pinout mapping failed"); + } + + // enable power and clocking + switch ((int)obj->spi) { + case (int)SPI_0: + obj->spi->CR1 = 0; + obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; + obj->spi->DMACR = 0; + obj->spi->CR1 = SSP_CR1_SSE_Msk; + obj->spi->ICR = 0x3; + break; + case (int)SPI_1: + /* Configure SSP used for LCD */ + obj->spi->CR1 = 0; /* Synchronous serial port disable */ + obj->spi->DMACR = 0; /* Disable FIFO DMA */ + obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */ + obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */ + (1ul << 1) ); /* Clear SSPRTINTR interrupt */ + obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */ + (0ul << 4) | /* Motorola frame format */ + (0ul << 6) | /* CPOL = 0 */ + (0ul << 7) | /* CPHA = 0 */ + (1ul << 8) ); /* Set serial clock rate */ + obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */ + obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */ + (0ul << 2) ); /* Device configured as master */ + break; + case (int)SPI_2: + obj->spi->CR1 = 0; + obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; + obj->spi->DMACR = 0; + obj->spi->CR1 = SSP_CR1_SSE_Msk; + obj->spi->ICR = 0x3; + break; + case (int)SPI_3: + obj->spi->CR1 = 0; + obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; + obj->spi->DMACR = 0; + obj->spi->CR1 = SSP_CR1_SSE_Msk; + obj->spi->ICR = 0x3; + break; + case (int)SPI_4: + obj->spi->CR1 = 0; + obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; + obj->spi->CPSR = SSP_CPSR_DFLT; + obj->spi->IMSC = 0x8; + obj->spi->DMACR = 0; + obj->spi->CR1 = SSP_CR1_SSE_Msk; + obj->spi->ICR = 0x3; + break; + } + + if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;} + if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;} + if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;} + if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;} + + // enable alt function + switch ((int)obj->spi) { + case (int)SPI_2: + CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<5 | altfunction[0]<<4 | altfunction[1]<<3 | altfunction[3]<<2); + break; + case (int)SPI_3: + CMSDK_GPIO0->ALTFUNCSET |= (altfunction[2]<<13 | altfunction[1]<<12 | altfunction[0]<<11 | altfunction[3]<<10); + break; + case (int)SPI_4: + CMSDK_GPIO4->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[1]<<2 | altfunction[0]<<1 | altfunction[3]); + break; + } + + // set default format and frequency + if (ssel == NC) { + spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master + } else { + spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave + } + spi_frequency(obj, 1000000); + + // enable the ssp channel + ssp_enable(obj); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) {} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + ssp_disable(obj); + if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) { + error("SPI format error"); + } + + int polarity = (mode & 0x2) ? 1 : 0; + int phase = (mode & 0x1) ? 1 : 0; + + // set it up + int DSS = bits - 1; // DSS (data select size) + int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity + int SPH = (phase) ? 1 : 0; // SPH - clock out phase + + int FRF = 0; // FRF (frame format) = SPI + uint32_t tmp = obj->spi->CR0; + tmp &= ~(0xFFFF); + tmp |= DSS << 0 + | FRF << 4 + | SPO << 6 + | SPH << 7; + obj->spi->CR0 = tmp; + + tmp = obj->spi->CR1; + tmp &= ~(0xD); + tmp |= 0 << 0 // LBM - loop back mode - off + | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave + | 0 << 3; // SOD - slave output disable - na + obj->spi->CR1 = tmp; + + ssp_enable(obj); +} + +void spi_frequency(spi_t *obj, int hz) { + ssp_disable(obj); + + uint32_t PCLK = SystemCoreClock; + + int prescaler; + + for (prescaler = 2; prescaler <= 254; prescaler += 2) { + int prescale_hz = PCLK / prescaler; + + // calculate the divider + int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); + + // check we can support the divider + if (divider < 256) { + // prescaler + obj->spi->CPSR = prescaler; + + // divider + obj->spi->CR0 &= ~(0xFFFF << 8); + obj->spi->CR0 |= (divider - 1) << 8; + ssp_enable(obj); + return; + } + } + error("Couldn't setup requested SPI frequency"); +} + +static inline int ssp_disable(spi_t *obj) { + return obj->spi->CR1 &= ~(1 << 1); +} + +static inline int ssp_enable(spi_t *obj) { + return obj->spi->CR1 |= SSP_CR1_SSE_Msk; +} + +static inline int ssp_readable(spi_t *obj) { + return obj->spi->SR & (1 << 2); +} + +static inline int ssp_writeable(spi_t *obj) { + return obj->spi->SR & SSP_SR_BSY_Msk; +} + +static inline void ssp_write(spi_t *obj, int value) { + obj->spi->DR = value; + while (ssp_writeable(obj)); +} +static inline int ssp_read(spi_t *obj) { + int read_DR = obj->spi->DR; + return read_DR; +} + +static inline int ssp_busy(spi_t *obj) { + return (obj->spi->SR & (1 << 4)) ? (1) : (0); +} + +int spi_master_write(spi_t *obj, int value) { + ssp_write(obj, value); + while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */ + return (ssp_read(obj)); +} + +int spi_slave_receive(spi_t *obj) { + return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); +} + +int spi_slave_read(spi_t *obj) { + return obj->spi->DR; +} + +void spi_slave_write(spi_t *obj, int value) { + while (ssp_writeable(obj) == 0) ; + obj->spi->DR = value; +} + +int spi_busy(spi_t *obj) { + return ssp_busy(obj); +} diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_def.h b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_def.h new file mode 100644 index 00000000000..c6d61b84808 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/spi_def.h @@ -0,0 +1,174 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ---------------------------------------------------------------- + * File: apspi.h + * Release: Version 2.0 + * ---------------------------------------------------------------- + * + * SSP interface Support + * ===================== + */ + +#define SSPCS_BASE (0x4002804C) // SSP chip select register +#define SSP_BASE (0x40020000) // SSP Prime Cell + +#define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00)) +#define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04)) +#define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08)) +#define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C)) +#define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10)) +#define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14)) +#define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18)) +#define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C)) +#define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20)) +#define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24)) +#define SSPCS ((volatile unsigned int *)(SSPCS_BASE)) + +// SSPCR0 Control register 0 +#define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3 +#define SSPCR0_SPH 0x0080 // SSPCLKOUT phase +#define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity +#define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola +#define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits +#define SSPCR0_DSS_16 0x000F // Data packet size, 16bits + +// SSPCR1 Control register 1 +#define SSPCR1_SOD 0x0008 // Slave Output mode Disable +#define SSPCR1_MS 0x0004 // Master or Slave mode +#define SSPCR1_SSE 0x0002 // Serial port enable +#define SSPCR1_LBM 0x0001 // Loop Back Mode + +// SSPSR Status register +#define SSPSR_BSY 0x0010 // Busy +#define SSPSR_RFF 0x0008 // Receive FIFO full +#define SSPSR_RNE 0x0004 // Receive FIFO not empty +#define SSPSR_TNF 0x0002 // Transmit FIFO not full +#define SSPSR_TFE 0x0001 // Transmit FIFO empty + +// SSPCPSR Clock prescale register +#define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8 + +// SSPIMSC Interrupt mask set and clear register +#define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked +#define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked +#define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked +#define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked + +// SSPRIS Raw interrupt status register +#define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag +#define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag +#define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag +#define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag + +// SSPMIS Masked interrupt status register +#define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag +#define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag +#define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag +#define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag + +// SSPICR Interrupt clear register +#define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag +#define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag + +// SSPDMACR DMA control register +#define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA +#define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA + +// SPICS register (0=Chip Select low) +#define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS) + +// SPI defaults +#define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS) + +// EEPROM instruction set +#define EEWRSR 0x0001 // Write status +#define EEWRITE 0x0002 // Write data +#define EEREAD 0x0003 // Read data +#define EEWDI 0x0004 // Write disable +#define EEWREN 0x0006 // Write enable +#define EERDSR 0x0005 // Read status + +// EEPROM status register flags +#define EERDSR_WIP 0x0001 // Write in process +#define EERDSR_WEL 0x0002 // Write enable latch +#define EERDSR_BP0 0x0004 // Block protect 0 +#define EERDSR_BP1 0x0008 // Block protect 1 +#define EERDSR_WPEN 0x0080 // Write protect enable + + /* ---------------------------------------------------------------- + * + * Color LCD Support + * ================= + */ + +// Color LCD Controller Internal Register addresses +#define LSSPCS_BASE (0x4002804C) // LSSP chip select register +#define LSSP_BASE (0x40021000) // LSSP Prime Cell + +#define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00)) +#define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04)) +#define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08)) +#define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C)) +#define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10)) +#define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14)) +#define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18)) +#define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C)) +#define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20)) +#define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24)) +#define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE)) + +// LSSPCR0 Control register 0 +#define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR)) +#define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase +#define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity +#define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola +#define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits +#define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits + +// LSSPCR1 Control register 1 +#define LSSPCR1_SOD 0x0008 // Slave Output mode Disable +#define LSSPCR1_MS 0x0004 // Master or Slave mode +#define LSSPCR1_SSE 0x0002 // Serial port enable +#define LSSPCR1_LBM 0x0001 // Loop Back Mode + +// LSSPSR Status register +#define LSSPSR_BSY 0x0010 // Busy +#define LSSPSR_RFF 0x0008 // Receive FIFO full +#define LSSPSR_RNE 0x0004 // Receive FIFO not empty +#define LSSPSR_TNF 0x0002 // Transmit FIFO not full +#define LSSPSR_TFE 0x0001 // Transmit FIFO empty + +// LSSPCPSR Clock prescale register +#define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR) + +// SPICS register +#define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS) +#define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS) +#define LCD_RESET 0x0008 // RESET (CLCD_RESET) +#define LCD_RS 0x0010 // RS (CLCD_RS) +#define LCD_RD 0x0020 // RD (CLCD_RD) +#define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL) + +// SPI defaults +#define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS) +#define LSPI_START (0x70) // Start byte for SPI transfer +#define LSPI_RD (0x01) // WR bit 1 within start +#define LSPI_WR (0x00) // WR bit 0 within start +#define LSPI_DATA (0x02) // RS bit 1 within start byte +#define LSPI_INDEX (0x00) // RS bit 0 within start byte + +// Screen size +#define LCD_WIDTH 320 // Screen Width (in pixels) +#define LCD_HEIGHT 240 // Screen Height (in pixels) diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c new file mode 100644 index 00000000000..bbf150abcef --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c @@ -0,0 +1,84 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "us_ticker_api.h" +#include "PeripheralNames.h" + +#define US_TICKER_TIMER1 CMSDK_DUALTIMER1 +#define US_TICKER_TIMER2 CMSDK_DUALTIMER2 +#define US_TICKER_TIMER_IRQn DUALTIMER_IRQn + +int us_ticker_inited = 0; + +void us_ticker_init(void) { + if (us_ticker_inited) return; + us_ticker_inited = 1; + + US_TICKER_TIMER1->TimerControl = 0x0; // disable timer + US_TICKER_TIMER2->TimerControl = 0x00; // disable timer + US_TICKER_TIMER1->TimerLoad = 0xFFFFFFFF; + US_TICKER_TIMER2->TimerLoad = 0xFFFFFFFF; + + US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode + US_TICKER_TIMER2->TimerControl = 0x42; // enable interrupt and set to 32 bit counter + + US_TICKER_TIMER1->TimerControl |= 0x80; // enable counter + US_TICKER_TIMER2->TimerControl |= 0x80; // enable counter + + NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); +} + +uint32_t us_ticker_read() { + uint32_t return_value = 0; + + if (!us_ticker_inited) + us_ticker_init(); + return_value = ((~US_TICKER_TIMER2->TimerValue)/24); + return return_value; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) { + int delta = 0; + + if (!us_ticker_inited) + us_ticker_init(); + delta = (int)(timestamp - us_ticker_read()); + if (delta <= 0) { + // This event was in the past: + us_ticker_irq_handler(); + return; + } + // enable interrupt + US_TICKER_TIMER1->TimerControl = 0x0; // disable timer + US_TICKER_TIMER1->TimerControl = 0x62; // enable interrupt and set to 32 bit counter and set to periodic mode + US_TICKER_TIMER1->TimerLoad = (delta)*24; //initialise the timer value + US_TICKER_TIMER1->TimerControl |= 0x80; //enable timer +} + +void us_ticker_disable_interrupt(void) { + + US_TICKER_TIMER1->TimerControl &= 0xDF; + US_TICKER_TIMER2->TimerControl &= 0xDF; + +} + +void us_ticker_clear_interrupt(void) { + + US_TICKER_TIMER1->TimerIntClr = 0x1; + US_TICKER_TIMER2->TimerIntClr = 0x1; + +} diff --git a/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/analogin_api.c b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/analogin_api.c new file mode 100644 index 00000000000..63d92235c93 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_ARM_SSG/TARGET_MPS2/analogin_api.c @@ -0,0 +1,110 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" + +#include "cmsis.h" +#include "pinmap.h" + +#define ADC_12BIT_RANGE 0xFFF + +static const PinMap PinMap_ADC[] = { + {A0_0, ADC0_0, 0}, + {A0_1, ADC0_1, 0}, + {A0_2, ADC0_2, 0}, + {A0_3, ADC0_3, 0}, + {A0_4, ADC0_4, 0}, + {A0_5, ADC0_5, 0}, + {A1_0, ADC0_6, 0}, + {A1_1, ADC0_7, 0}, + {A1_2, ADC0_8, 0}, + {A1_3, ADC0_9, 0}, + {A1_4, ADC0_10, 0}, + {A1_5, ADC0_11, 0}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SCLK[] = { + {ADC_SCLK , SPI_3, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {ADC_MOSI, SPI_3, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {ADC_MISO, SPI_3, 0}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {ADC_SSEL, SPI_3, 0}, + {NC , NC , 0} +}; + +#define ADC_RANGE ADC_12BIT_RANGE +int analog_spi_inited = 0; + +void analogin_init(analogin_t *obj, PinName pin) { + + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + obj->pin = pin; + obj->pin_number = pin-600; + obj->address = (0x0000 | (pin-600)); + + SPIName adc_mosi = (SPIName)pinmap_peripheral(ADC_MOSI, PinMap_SPI_MOSI); + SPIName adc_miso = (SPIName)pinmap_peripheral(ADC_MISO, PinMap_SPI_MISO); + SPIName adc_sclk = (SPIName)pinmap_peripheral(ADC_SCLK, PinMap_SPI_SCLK); + SPIName adc_ssel = (SPIName)pinmap_peripheral(ADC_SSEL, PinMap_SPI_SSEL); + SPIName adc_data = (SPIName)pinmap_merge(adc_mosi, adc_miso); + SPIName adc_cntl = (SPIName)pinmap_merge(adc_sclk, adc_ssel); + obj->adc_spi = (MPS2_SSP_TypeDef*)pinmap_merge(adc_data, adc_cntl); + + if(analog_spi_inited == 0){ + obj->adc_spi->CR1 = 0; + obj->adc_spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_16; + obj->adc_spi->CPSR = SSP_CPSR_DFLT; + obj->adc_spi->IMSC = 0x8; + obj->adc_spi->DMACR = 0; + obj->adc_spi->CR1 = SSP_CR1_SSE_Msk; + obj->adc_spi->ICR = 0x3; + analog_spi_inited = 1; + } + + pinmap_pinout(ADC_MOSI, PinMap_SPI_MOSI); + pinmap_pinout(ADC_MISO, PinMap_SPI_MISO); + pinmap_pinout(ADC_SCLK, PinMap_SPI_SCLK); + pinmap_pinout(ADC_SSEL, PinMap_SPI_SSEL); + pinmap_pinout(pin, PinMap_ADC); +} + +static inline uint32_t adc_read(analogin_t *obj) { + return 0; +} + + +float analogin_read(analogin_t *obj) { + uint32_t value = adc_read(obj); + return 0; +} + +uint16_t analogin_read_u16(analogin_t *obj) { + return 0; +} + From b7e2f73aac404d683df4df3e79d71ed5d00db173 Mon Sep 17 00:00:00 2001 From: Peter Conheeney Date: Thu, 25 Feb 2016 09:56:37 +0000 Subject: [PATCH 3/3] latest changes 250216 --- workspace_tools/export/uvision4.py | 6 + .../export/uvision4_arm_iotss_beid.uvopt.tmpl | 190 ++++++++ .../uvision4_arm_iotss_beid.uvproj.tmpl | 428 ++++++++++++++++++ .../export/uvision4_arm_mps2_m0.uvopt.tmpl | 190 ++++++++ .../export/uvision4_arm_mps2_m0.uvproj.tmpl | 428 ++++++++++++++++++ .../export/uvision4_arm_mps2_m0p.uvopt.tmpl | 190 ++++++++ .../export/uvision4_arm_mps2_m0p.uvproj.tmpl | 428 ++++++++++++++++++ .../export/uvision4_arm_mps2_m3.uvopt.tmpl | 190 ++++++++ .../export/uvision4_arm_mps2_m3.uvproj.tmpl | 428 ++++++++++++++++++ .../export/uvision4_arm_mps2_m4.uvopt.tmpl | 190 ++++++++ .../export/uvision4_arm_mps2_m4.uvproj.tmpl | 428 ++++++++++++++++++ .../export/uvision4_arm_mps2_m7.uvopt.tmpl | 190 ++++++++ .../export/uvision4_arm_mps2_m7.uvproj.tmpl | 428 ++++++++++++++++++ workspace_tools/targets.py | 18 +- 14 files changed, 3723 insertions(+), 9 deletions(-) create mode 100644 workspace_tools/export/uvision4_arm_iotss_beid.uvopt.tmpl create mode 100644 workspace_tools/export/uvision4_arm_iotss_beid.uvproj.tmpl create mode 100644 workspace_tools/export/uvision4_arm_mps2_m0.uvopt.tmpl create mode 100644 workspace_tools/export/uvision4_arm_mps2_m0.uvproj.tmpl create mode 100644 workspace_tools/export/uvision4_arm_mps2_m0p.uvopt.tmpl create mode 100644 workspace_tools/export/uvision4_arm_mps2_m0p.uvproj.tmpl create mode 100644 workspace_tools/export/uvision4_arm_mps2_m3.uvopt.tmpl create mode 100644 workspace_tools/export/uvision4_arm_mps2_m3.uvproj.tmpl create mode 100644 workspace_tools/export/uvision4_arm_mps2_m4.uvopt.tmpl create mode 100644 workspace_tools/export/uvision4_arm_mps2_m4.uvproj.tmpl create mode 100644 workspace_tools/export/uvision4_arm_mps2_m7.uvopt.tmpl create mode 100644 workspace_tools/export/uvision4_arm_mps2_m7.uvproj.tmpl diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py index 031a5cbc658..34daac1b658 100644 --- a/workspace_tools/export/uvision4.py +++ b/workspace_tools/export/uvision4.py @@ -147,6 +147,12 @@ class Uvision4(Exporter): 'SAMD21J18A', 'SAMD21G18A', 'SAML21J18A', + 'ARM_IOTSS_BEID', + 'ARM_MPS2_M0', + 'ARM_MPS2_M0P', + 'ARM_MPS2_M3', + 'ARM_MPS2_M4', + 'ARM_MPS2_M7', ] FILE_TYPES = { diff --git a/workspace_tools/export/uvision4_arm_iotss_beid.uvopt.tmpl b/workspace_tools/export/uvision4_arm_iotss_beid.uvopt.tmpl new file mode 100644 index 00000000000..a42d20f13ad --- /dev/null +++ b/workspace_tools/export/uvision4_arm_iotss_beid.uvopt.tmpl @@ -0,0 +1,190 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + ARM MPS2 BEID + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 0 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + + + + + + + + src + 1 + 0 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + main.cpp + main.cpp + 0 + 0 + + + + diff --git a/workspace_tools/export/uvision4_arm_iotss_beid.uvproj.tmpl b/workspace_tools/export/uvision4_arm_iotss_beid.uvproj.tmpl new file mode 100644 index 00000000000..e5642db4112 --- /dev/null +++ b/workspace_tools/export/uvision4_arm_iotss_beid.uvproj.tmpl @@ -0,0 +1,428 @@ + + + + 1.1 + +
###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
+ + + + ARM MPS2 BEID + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + IROM(0x00000000,0x400000) IRAM(0x20000000,0x400000) CPUTYPE("Cortex-M3") CLOCK(25000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 5125 + CMSDK_BEID.h + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 1 + + + + + + + + + + + + + + BIN\UL2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x400000 + + + 1 + 0x0 + 0x400000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x400000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x400000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + --entry=Reset_Handler + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + + diff --git a/workspace_tools/export/uvision4_arm_mps2_m0.uvopt.tmpl b/workspace_tools/export/uvision4_arm_mps2_m0.uvopt.tmpl new file mode 100644 index 00000000000..deee8301898 --- /dev/null +++ b/workspace_tools/export/uvision4_arm_mps2_m0.uvopt.tmpl @@ -0,0 +1,190 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + ARM MPS2 M0P + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 0 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM0P + SARMCM3.DLL + -MPU + TCM.DLL + -pCM0P + + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + + + + + + + + src + 1 + 0 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + main.cpp + main.cpp + 0 + 0 + + + + diff --git a/workspace_tools/export/uvision4_arm_mps2_m0p.uvproj.tmpl b/workspace_tools/export/uvision4_arm_mps2_m0p.uvproj.tmpl new file mode 100644 index 00000000000..f6e934b05fb --- /dev/null +++ b/workspace_tools/export/uvision4_arm_mps2_m0p.uvproj.tmpl @@ -0,0 +1,428 @@ + + + + 1.1 + +
###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
+ + + + ARM MPS2 M0P + 0x4 + ARM-ADS + + + Cortex-M0P + ARM + IROM(0x00000000,0x400000) IRAM(0x20000000,0x400000) CPUTYPE("Cortex-M0P") CLOCK(25000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 5125 + CMSDK_CM0P.h + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM0P + SARMCM3.DLL + -MPU + TCM.DLL + -pCM0P + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 1 + + + + + + + + + + + + + + BIN\UL2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0P" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x400000 + + + 1 + 0x0 + 0x400000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x400000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x400000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + --entry=Reset_Handler + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + + diff --git a/workspace_tools/export/uvision4_arm_mps2_m3.uvopt.tmpl b/workspace_tools/export/uvision4_arm_mps2_m3.uvopt.tmpl new file mode 100644 index 00000000000..b5a0fe5dbbd --- /dev/null +++ b/workspace_tools/export/uvision4_arm_mps2_m3.uvopt.tmpl @@ -0,0 +1,190 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
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### uVision Project, (C) Keil Software
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###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
+ + + + ARM MPS2 M4 + 0x4 + ARM-ADS + + + Cortex-M4 + ARM + IROM(0x00000000,0x400000) IRAM(0x20000000,0x400000) CPUTYPE("Cortex-M4") CLOCK(25000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 5125 + CMSDK_CM4.h + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 1 + + + + + + + + + + + + + + BIN\UL2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x400000 + + + 1 + 0x0 + 0x400000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x400000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x400000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + --entry=Reset_Handler + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + + diff --git a/workspace_tools/export/uvision4_arm_mps2_m7.uvopt.tmpl b/workspace_tools/export/uvision4_arm_mps2_m7.uvopt.tmpl new file mode 100644 index 00000000000..6504d2f4032 --- /dev/null +++ b/workspace_tools/export/uvision4_arm_mps2_m7.uvopt.tmpl @@ -0,0 +1,190 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + ARM MPS2 M7 + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 0 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + + + + + + + + src + 1 + 0 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + main.cpp + main.cpp + 0 + 0 + + + + diff --git a/workspace_tools/export/uvision4_arm_mps2_m7.uvproj.tmpl b/workspace_tools/export/uvision4_arm_mps2_m7.uvproj.tmpl new file mode 100644 index 00000000000..cfb747e235e --- /dev/null +++ b/workspace_tools/export/uvision4_arm_mps2_m7.uvproj.tmpl @@ -0,0 +1,428 @@ + + + + 1.1 + +
###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
+ + + + ARM MPS2 M7 + 0x4 + ARM-ADS + + + Cortex-M7 + ARM + IROM(0x00000000,0x400000) IRAM(0x20000000,0x400000) CPUTYPE("Cortex-M7") CLOCK(25000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 5125 + CMSDK_CM7.h + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 1 + + + + + + + + + + + + + + BIN\UL2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x400000 + + + 1 + 0x0 + 0x400000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x400000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x400000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + --entry=Reset_Handler + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + + diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index e27c8446e24..d2df59da967 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -1604,24 +1604,24 @@ def __init__(self): class ARM_MPS2_M7(ARM_MPS2_Target): def __init__(self): ARM_MPS2_Target.__init__(self) - self.core = "Cortex-M4F" + self.core = "Cortex-M7" self.extra_labels = ['ARM_SSG', 'MPS2', 'MPS2_M7'] self.macros = ['CMSDK_CM7'] self.supported_toolchains = ["ARM"] self.default_toolchain = "ARM" -class ARM_MPS2_BEID(ARM_MPS2_Target): +class ARM_IOTSS_Target(Target): def __init__(self): - ARM_MPS2_Target.__init__(self) + Target.__init__(self) +class ARM_IOTSS_BEID(ARM_IOTSS_Target): + def __init__(self): + ARM_IOTSS_Target.__init__(self) self.core = "Cortex-M3" - self.extra_labels = ['ARM_SSG', 'MPS2', 'MPS2_BEID'] + self.extra_labels = ['ARM_SSG', 'IOTSS', 'IOTSS_BEID'] self.macros = ['CMSDK_BEID'] self.supported_toolchains = ["ARM"] self.default_toolchain = "ARM" -class ARM_MPS2(ARM_MPS2_M4): - pass - ### Renesas ### @@ -1936,8 +1936,8 @@ def __init__(self): ARM_MPS2_M3(), ARM_MPS2_M4(), ARM_MPS2_M7(), - ARM_MPS2_BEID(), - ARM_MPS2(), + + ARM_IOTSS_BEID(), ### Renesas ### RZ_A1H(),