From fb1d9c28785bd1529d523752b464ce897ea4800f Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Thu, 27 Oct 2022 13:45:14 +0300 Subject: [PATCH] Replace MAX32660, MAX32670 I2C driver with final one in MSDK - apply clang-format - Fix i2c repeated start issue Signed-off-by: Sadik.Ozer --- .../PeriphDrivers/Source/I2C/i2c_me11.c | 253 ++-- .../PeriphDrivers/Source/I2C/i2c_reva.c | 1102 +++++++++-------- .../PeriphDrivers/Source/I2C/i2c_reva.h | 163 +-- .../PeriphDrivers/Source/I2C/i2c_reva_regs.h | 431 +++---- .../PeriphDrivers/Source/I2C/i2c_me15.c | 255 ++-- .../PeriphDrivers/Source/I2C/i2c_reva.c | 1100 ++++++++-------- .../PeriphDrivers/Source/I2C/i2c_reva.h | 161 +-- .../PeriphDrivers/Source/I2C/i2c_reva_regs.h | 429 +++---- 8 files changed, 2065 insertions(+), 1829 deletions(-) diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c index bf20b140a18..042207ec484 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c @@ -1,5 +1,5 @@ /* **************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files(the "Software"), @@ -31,7 +31,6 @@ * *************************************************************************** */ - #include #include #include @@ -46,7 +45,6 @@ #include "mxc_i2c.h" #include "i2c_reva.h" - /* **** Definitions **** */ #define MXC_I2C_FASTPLUS_SPEED 1000000 @@ -58,334 +56,335 @@ uint32_t interruptCheck = MXC_F_I2C_INTFL0_AMI | MXC_F_I2C_INTFL0_DNRERI; /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_I2C_Init(mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr) +int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr) { - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } MXC_I2C_Shutdown(i2c); // Clear everything out - - if(i2c == MXC_I2C0) { + + if (i2c == MXC_I2C0) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0); MXC_GPIO_Config(&gpio_cfg_i2c0); - } - else if(i2c == MXC_I2C1) { + } else if (i2c == MXC_I2C1) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1); MXC_GPIO_Config(&gpio_cfg_i2c1); - } - else { + } else { return E_NO_DEVICE; } - - return MXC_I2C_RevA_Init((mxc_i2c_reva_regs_t*) i2c, masterMode, slaveAddr); + + return MXC_I2C_RevA_Init((mxc_i2c_reva_regs_t *)i2c, masterMode, slaveAddr); } -int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx) +int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t *i2c, unsigned int slaveAddr, int idx) { - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } - if(idx != 0) { + if (idx != 0) { // Multiple slaves are not supported yet return E_NOT_SUPPORTED; } - - if(slaveAddr > MXC_F_I2C_SLADDR_SLA) { + + if (slaveAddr > MXC_F_I2C_SLADDR_SLA) { // Only support addresses up to 10 bits return E_BAD_PARAM; } - + i2c->sladdr = 0; - - if(slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { + + if (slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { // Set for 10bit addressing mode i2c->sladdr = MXC_F_I2C_SLADDR_EA; } - + i2c->sladdr |= slaveAddr; - + return E_NO_ERROR; } -int MXC_I2C_Shutdown(mxc_i2c_regs_t* i2c) +int MXC_I2C_Shutdown(mxc_i2c_regs_t *i2c) { // Configure GPIO for I2C - if(i2c == MXC_I2C0) { + if (i2c == MXC_I2C0) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0); - } - else if(i2c == MXC_I2C1) { + } else if (i2c == MXC_I2C1) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); - } - else { + } else { return E_NO_DEVICE; } - - + int i2cNum = MXC_I2C_GET_IDX(i2c); - + // Reconcile this with MXC_SYS_I2C_Init when we figure out what to do abotu system level things - switch(i2cNum) { + switch (i2cNum) { case 0: MXC_GCR->rst0 |= MXC_F_GCR_RST0_I2C0; break; - + case 1: MXC_GCR->rst1 |= MXC_F_GCR_RST1_I2C1; break; - + default: return E_BAD_PARAM; } - + return E_NO_ERROR; } -int MXC_I2C_SetFrequency(mxc_i2c_regs_t* i2c, unsigned int hz) +int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz) { - // ME13 doesn't support high speed more - if(hz > MXC_I2C_FASTPLUS_SPEED) { + if (hz > MXC_I2C_FASTPLUS_SPEED) { return E_NOT_SUPPORTED; } - - return MXC_I2C_RevA_SetFrequency((mxc_i2c_reva_regs_t*) i2c, hz); + + return MXC_I2C_RevA_SetFrequency((mxc_i2c_reva_regs_t *)i2c, hz); } -unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetFrequency((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetFrequency((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t* i2c) +int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_ReadyForSleep((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_ReadyForSleep((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_SetClockStretching(mxc_i2c_regs_t* i2c, int enable) +int MXC_I2C_SetClockStretching(mxc_i2c_regs_t *i2c, int enable) { - return MXC_I2C_RevA_SetClockStretching((mxc_i2c_reva_regs_t*) i2c, enable); + return MXC_I2C_RevA_SetClockStretching((mxc_i2c_reva_regs_t *)i2c, enable); } -int MXC_I2C_GetClockStretching(mxc_i2c_regs_t* i2c) +int MXC_I2C_GetClockStretching(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetClockStretching((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetClockStretching((mxc_i2c_reva_regs_t *)i2c); } /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ -int MXC_I2C_Start(mxc_i2c_regs_t* i2c) +int MXC_I2C_Start(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_Start((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_Start((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_Stop(mxc_i2c_regs_t* i2c) +int MXC_I2C_Stop(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_Stop((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_Stop((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_WriteByte(mxc_i2c_regs_t* i2c, unsigned char byte) +int MXC_I2C_WriteByte(mxc_i2c_regs_t *i2c, unsigned char byte) { - return MXC_I2C_RevA_WriteByte((mxc_i2c_reva_regs_t*) i2c, byte); + return MXC_I2C_RevA_WriteByte((mxc_i2c_reva_regs_t *)i2c, byte); } -int MXC_I2C_ReadByte(mxc_i2c_regs_t* i2c, unsigned char* byte, int ack) +int MXC_I2C_ReadByte(mxc_i2c_regs_t *i2c, unsigned char *byte, int ack) { - return MXC_I2C_RevA_ReadByte((mxc_i2c_reva_regs_t*) i2c, byte, ack); + return MXC_I2C_RevA_ReadByte((mxc_i2c_reva_regs_t *)i2c, byte, ack); } -int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t* i2c, unsigned char* byte, mxc_i2c_getAck_t getAck) +int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck) { - return MXC_I2C_RevA_ReadByteInteractive((mxc_i2c_reva_regs_t*) i2c, byte, (mxc_i2c_reva_getAck_t) getAck); + return MXC_I2C_RevA_ReadByteInteractive((mxc_i2c_reva_regs_t *)i2c, byte, + (mxc_i2c_reva_getAck_t)getAck); } -int MXC_I2C_Write(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len) +int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len) { - return MXC_I2C_RevA_Write((mxc_i2c_reva_regs_t*) i2c, bytes, len); + return MXC_I2C_RevA_Write((mxc_i2c_reva_regs_t *)i2c, bytes, len); } -int MXC_I2C_Read(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack) +int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack) { - return MXC_I2C_RevA_Read((mxc_i2c_reva_regs_t*) i2c, bytes, len, ack); + return MXC_I2C_RevA_Read((mxc_i2c_reva_regs_t *)i2c, bytes, len, ack); } -int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len) { - return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t*) i2c, bytes, len); + return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); } -int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) +int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback) { uint8_t i2cNum; mxc_dma_config_t config; i2cNum = MXC_I2C_GET_IDX(i2c); - - switch(i2cNum) { + + switch (i2cNum) { case 0: config.reqsel = MXC_DMA_REQUEST_I2C0RX; break; - + case 1: config.reqsel = MXC_DMA_REQUEST_I2C1RX; break; } - return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t*) i2c, bytes, len, (mxc_i2c_reva_dma_complete_cb_t) callback, config, MXC_DMA); + return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, + (mxc_i2c_reva_dma_complete_cb_t)callback, config, MXC_DMA); } -int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t* i2c) +int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetRXFIFOAvailable((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetRXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len) { - return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t*) i2c, bytes, len); + return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); } -int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) +int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback) { uint8_t i2cNum; mxc_dma_config_t config; i2cNum = MXC_I2C_GET_IDX(i2c); - - switch(i2cNum) { + + switch (i2cNum) { case 0: config.reqsel = MXC_DMA_REQUEST_I2C0TX; break; - + case 1: config.reqsel = MXC_DMA_REQUEST_I2C1TX; break; } - return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t*) i2c, bytes, len, (mxc_i2c_reva_dma_complete_cb_t) callback, config, MXC_DMA); + return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, + (mxc_i2c_reva_dma_complete_cb_t)callback, config, MXC_DMA); } -int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t* i2c) +int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetTXFIFOAvailable((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetTXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t* i2c) +void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_ClearRXFIFO((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_ClearRXFIFO((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t* i2c) +void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_ClearTXFIFO((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_ClearTXFIFO((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_GetFlags(mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *flags1) +int MXC_I2C_GetFlags(mxc_i2c_regs_t *i2c, unsigned int *flags0, unsigned int *flags1) { - return MXC_I2C_RevA_GetFlags((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + return MXC_I2C_RevA_GetFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_ClearFlags(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_ClearFlags(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) { - MXC_I2C_RevA_ClearFlags((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + MXC_I2C_RevA_ClearFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_EnableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_EnableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) { - MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_DisableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_DisableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) { - MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c) +void MXC_I2C_EnablePreload(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c) +void MXC_I2C_DisablePreload(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c) +void MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_EnableGeneralCall ((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_EnableGeneralCall((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c) +void MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_DisableGeneralCall ((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_DisableGeneralCall((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout) +void MXC_I2C_SetTimeout(mxc_i2c_regs_t *i2c, unsigned int timeout) { - MXC_I2C_RevA_SetTimeout ((mxc_i2c_reva_regs_t*) i2c, timeout); + MXC_I2C_RevA_SetTimeout((mxc_i2c_reva_regs_t *)i2c, timeout); } -unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetTimeout(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetTimeout ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetTimeout((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_Recover(mxc_i2c_regs_t* i2c, unsigned int retries) +int MXC_I2C_Recover(mxc_i2c_regs_t *i2c, unsigned int retries) { - return MXC_I2C_RevA_Recover((mxc_i2c_reva_regs_t*) i2c, retries); + return MXC_I2C_RevA_Recover((mxc_i2c_reva_regs_t *)i2c, retries); } /* ************************************************************************* */ /* Transaction level functions */ /* ************************************************************************* */ -int MXC_I2C_MasterTransaction(mxc_i2c_req_t* req) +int MXC_I2C_MasterTransaction(mxc_i2c_req_t *req) { - return MXC_I2C_RevA_MasterTransaction((mxc_i2c_reva_req_t*) req); + return MXC_I2C_RevA_MasterTransaction((mxc_i2c_reva_req_t *)req); } -int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t* req) +int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t *req) { - return MXC_I2C_RevA_MasterTransactionAsync((mxc_i2c_reva_req_t*) req); + return MXC_I2C_RevA_MasterTransactionAsync((mxc_i2c_reva_req_t *)req); } -int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t* req) +int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t *req) { - return MXC_I2C_RevA_MasterTransactionDMA((mxc_i2c_reva_req_t*) req, MXC_DMA); + return MXC_I2C_RevA_MasterTransactionDMA((mxc_i2c_reva_req_t *)req, MXC_DMA); } -int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback) +int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) { - return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); + return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t *)i2c, + (mxc_i2c_reva_slave_handler_t)callback, interruptCheck); } -int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback) +int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) { - return MXC_I2C_RevA_SlaveTransactionAsync((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); + return MXC_I2C_RevA_SlaveTransactionAsync( + (mxc_i2c_reva_regs_t *)i2c, (mxc_i2c_reva_slave_handler_t)callback, interruptCheck); } -int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) { - return MXC_I2C_RevA_SetRXThreshold((mxc_i2c_reva_regs_t*) i2c, numBytes); + return MXC_I2C_RevA_SetRXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes); } -unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetRXThreshold((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetRXThreshold((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) { - return MXC_I2C_RevA_SetTXThreshold((mxc_i2c_reva_regs_t*) i2c, numBytes); + return MXC_I2C_RevA_SetTXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes); } -unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_AsyncHandler(mxc_i2c_regs_t* i2c) +void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t*) i2c, interruptCheck); + MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t *)i2c, interruptCheck); } void MXC_I2C_DMACallback(int ch, int error) diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c index 56d335f4d43..572ca6f0cb2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c @@ -1,5 +1,5 @@ /* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -47,99 +47,100 @@ /* **** Variable Declaration **** */ typedef struct { mxc_i2c_reva_req_t *req; - int master; // 1 for Master, 0 for slave - int channelTx; // DMA channel for TX transaction - int channelRx; // DMA channel for RX transaction - int writeDone; // Write done flag - int readDone; // Flag done flag + int master; // 1 for Master, 0 for slave + int channelTx; // DMA channel for TX transaction + int channelRx; // DMA channel for RX transaction + volatile int writeDone; // Write done flag + volatile int readDone; // Flag done flag } mxc_i2c_reva_req_state_t; static mxc_i2c_reva_req_state_t states[MXC_I2C_INSTANCES]; -void* AsyncRequests[MXC_I2C_INSTANCES]; -unsigned int AsyncWritten[MXC_I2C_INSTANCES]; -unsigned int AsyncRead[MXC_I2C_INSTANCES]; +void *AsyncRequests[MXC_I2C_INSTANCES]; +unsigned int AsyncWritten[MXC_I2C_INSTANCES]; +unsigned int AsyncRead[MXC_I2C_INSTANCES]; /* **** Function Prototypes **** */ -void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal); -void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_MasterAsyncHandler (int i2cNum); -int MXC_I2C_RevA_DMAHandler (mxc_i2c_reva_req_t* req); -unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); +void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal); +void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); +int MXC_I2C_RevA_DMAHandler(mxc_i2c_reva_req_t *req); +unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + unsigned int interruptEnables, int *retVal); /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int slaveAddr) -{ +int MXC_I2C_RevA_Init(mxc_i2c_reva_regs_t *i2c, int masterMode, unsigned int slaveAddr) +{ int err; - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } - if ((err = MXC_I2C_Recover ((mxc_i2c_regs_t*) i2c, 16)) != E_NO_ERROR) { + if ((err = MXC_I2C_Recover((mxc_i2c_regs_t *)i2c, 16)) != E_NO_ERROR) { return err; } - + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_EN; - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); // Set the thresholds here and allow the user to change them as needed - MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 2); // set TX threshold to 2 bytes - MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 6); // set RX threshold to 6 bytes - + MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 2); // set TX threshold to 2 bytes + MXC_I2C_SetRXThreshold((mxc_i2c_regs_t *)i2c, 6); // set RX threshold to 6 bytes + if (!masterMode) { - MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t*) i2c, slaveAddr, 0); - states[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)].master = 0; - } - else { + MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t *)i2c, slaveAddr, 0); + states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 0; + } else { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_MST_MODE; - states[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)].master = 1; + states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 1; } return E_NO_ERROR; } -int MXC_I2C_RevA_SetSlaveAddr (mxc_i2c_reva_regs_t* i2c, unsigned int slaveAddr, int idx) +int MXC_I2C_RevA_SetSlaveAddr(mxc_i2c_reva_regs_t *i2c, unsigned int slaveAddr, int idx) { if (i2c == NULL) { return E_NULL_PTR; } - + if (idx != 0) { // Multiple slaves are not supported yet return E_NOT_SUPPORTED; } - + if (slaveAddr > MXC_F_I2C_REVA_SLAVE_ADDR) { // Only support addresses up to 10 bits return E_BAD_PARAM; } - + i2c->slave = 0; - + if (slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { // Set for 10bit addressing mode i2c->slave = MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN; } - + i2c->slave |= slaveAddr; - + return E_NO_ERROR; } -int MXC_I2C_RevA_Shutdown (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_Shutdown(mxc_i2c_reva_regs_t *i2c) { return E_NOT_SUPPORTED; } -int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz) +int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz) { unsigned int ticksTotal, hiClks, lowClks; - + if (i2c == NULL) { return E_NULL_PTR; } @@ -147,161 +148,159 @@ int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz) if (hz > MXC_I2C_REVA_FASTPLUS_SPEED) { // We're going to enable high speed int hsLowClks, hsHiClks; - + // Calculate the period of SCL and set up 33% duty cycle ticksTotal = PeripheralClock / hz; hsLowClks = (ticksTotal * 2) / 3 - 1; hsHiClks = ticksTotal / 3 - 1; - + // For rounding errors, adjust by 1 clock tick if (ticksTotal % 1) { hsHiClks++; } - + // If we're too slow for high speed, bail out if ((hsHiClks > 0xF) || (hsLowClks > 0xF)) { return E_BAD_PARAM; } - + hz = MXC_I2C_REVA_FAST_SPEED; // High speed preambles will be sent at 400kHz } - + // Calculate the period of SCL, 50% duty cycle ticksTotal = PeripheralClock / hz; hiClks = (ticksTotal >> 1) - 1; lowClks = (ticksTotal >> 1) - 1; - + // Adjust for rounding errors if (ticksTotal % 1) { hiClks++; } - + // Check for maximum/minimum supported speeds - if ( (hiClks > MXC_F_I2C_REVA_CLKHI_HI) || (lowClks == 0)) { + if ((hiClks > MXC_F_I2C_REVA_CLKHI_HI) || (lowClks == 0)) { return E_BAD_PARAM; } - + i2c->clklo = lowClks & MXC_F_I2C_REVA_CLKLO_LO; i2c->clkhi = hiClks & MXC_F_I2C_REVA_CLKHI_HI; - + // Return the actual speed set, since it won't be exactly what's requested - return MXC_I2C_GetFrequency ((mxc_i2c_regs_t*) i2c); + return MXC_I2C_GetFrequency((mxc_i2c_regs_t *)i2c); } -unsigned int MXC_I2C_RevA_GetFrequency (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetFrequency(mxc_i2c_reva_regs_t *i2c) { unsigned int sclCycles = 0; - + // Calculate the speed based on what we've written into registers sclCycles = (i2c->clklo & MXC_F_I2C_REVA_CLKLO_LO) + (i2c->clkhi & MXC_F_I2C_REVA_CLKHI_HI); - + return PeripheralClock / sclCycles; } -int MXC_I2C_RevA_ReadyForSleep (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_ReadyForSleep(mxc_i2c_reva_regs_t *i2c) { - if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } - - if (AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] != NULL) { + + if (AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] != NULL) { return E_BUSY; } - + return E_NO_ERROR; } -int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable) +int MXC_I2C_RevA_SetClockStretching(mxc_i2c_reva_regs_t *i2c, int enable) { if (i2c == NULL) { return E_NULL_PTR; } - + if (enable) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; - } - else { + } else { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; } - + return E_NO_ERROR; } -int MXC_I2C_RevA_GetClockStretching (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_GetClockStretching(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } - return ! ( (i2c->ctrl & MXC_F_I2C_REVA_CTRL_CLKSTR_DIS) >> MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS); + return !((i2c->ctrl & MXC_F_I2C_REVA_CTRL_CLKSTR_DIS) >> MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS); } /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_Start(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } - + // If we have an incomplete transfer, we need to do a restart if (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_START) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; // No check for start generation } - + return E_NO_ERROR; } -int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_Stop(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; - - while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP); - + + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP) {} + return E_NO_ERROR; } -int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte) +int MXC_I2C_RevA_WriteByte(mxc_i2c_reva_regs_t *i2c, unsigned char byte) { if (i2c == NULL) { return E_NULL_PTR; } - + if (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)) { return E_OVERFLOW; } - + // I'm depending on an interrupt flag here // This might cause issues with the transaction level functions to come - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); i2c->fifo = byte; - - while (! (i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)); - + + while (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)) {} + return i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DATA_ERR; } -int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ack) +int MXC_I2C_RevA_ReadByte(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, int ack) { if ((i2c == NULL) || (byte == NULL)) { return E_NULL_PTR; } - if (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { + if (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM) { return E_UNDERFLOW; } - - *byte = (uint8_t) (i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); - if(ack) { + *byte = (uint8_t)(i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); + + if (ack) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK; } else { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_IRXM_ACK; @@ -310,290 +309,293 @@ int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ac return E_NO_ERROR; } -int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck) +int MXC_I2C_RevA_ReadByteInteractive(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, + mxc_i2c_reva_getAck_t getAck) { if ((i2c == NULL) || (byte == NULL)) { return E_NULL_PTR; } - if (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { + if (!(i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { return E_UNDERFLOW; } - - *byte = (uint8_t) (i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); - + + *byte = (uint8_t)(i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); + if (getAck == NULL) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; + } else { + i2c->ctrl |= (!!getAck((mxc_i2c_reva_regs_t *)i2c, *byte)) + << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; } - else { - i2c->ctrl |= (!!getAck ((mxc_i2c_reva_regs_t*) i2c, *byte)) << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; - } - + return E_NO_ERROR; } -int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len) +int MXC_I2C_RevA_Write(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len) { int notAcked = 0; unsigned written = 0; - + if (i2c == NULL) { return E_NULL_PTR; } - + if ((bytes == NULL) || (len == NULL)) { return E_NULL_PTR; } - + for (; written < *len; written++) { - int retVal = MXC_I2C_WriteByte ((mxc_i2c_regs_t*) i2c, bytes[written]); - + int retVal = MXC_I2C_WriteByte((mxc_i2c_regs_t *)i2c, bytes[written]); + if (retVal >= 0) { notAcked += retVal; - } - else { + } else { *len = written; return retVal; } } - + *len = written; notAcked = (notAcked > 0) ? 1 : 0; return notAcked; } -int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack) +int MXC_I2C_RevA_Read(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack) { unsigned read = 0; - + if (i2c == NULL) { return E_NULL_PTR; } - + if ((bytes == NULL) || (len == NULL)) { return E_NULL_PTR; } - for (; read < *len-1; read++) { - int retVal = MXC_I2C_ReadByte ((mxc_i2c_regs_t*) i2c, & (bytes[read]), 1); - + for (; read < *len - 1; read++) { + int retVal = MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), 1); + if (retVal != E_NO_ERROR) { *len = read; return retVal; } } - + read++; *len = read; - return MXC_I2C_ReadByte ((mxc_i2c_regs_t*) i2c, & (bytes[read]), ack); + return MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), ack); } -int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_RevA_ReadRXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len) { unsigned read = 0; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - - while ( (len > read) && (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM))) { + + while ((len > read) && (!(i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM))) { bytes[read++] = i2c->fifo; } - + return read; } -int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ - mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) +int MXC_I2C_RevA_ReadRXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma) { uint8_t i2cNum; uint8_t channel; mxc_dma_srcdst_t srcdst; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); - - #if TARGET_NUM == 32665 + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + +#if TARGET_NUM == 32665 channel = MXC_DMA_AcquireChannel(dma); - #else +#else channel = MXC_DMA_AcquireChannel(); - #endif - +#endif + config.ch = channel; - + config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - + config.srcinc_en = 0; config.dstinc_en = 1; - + srcdst.ch = channel; srcdst.dest = bytes; srcdst.len = len; - + states[i2cNum].channelRx = channel; MXC_DMA_ConfigChannel(config, srcdst); - + if (states[i2cNum].master) { MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); - } - - else { + } else { MXC_DMA_SetCallback(channel, NULL); } - - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); + + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].cfg |= MXC_F_DMA_CFG_CTZIEN; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); i2c->dma |= MXC_F_I2C_REVA_DMA_RX_EN; - + return E_NO_ERROR; } -int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c) -{ - if(i2c == NULL) { +int MXC_I2C_RevA_GetRXFIFOAvailable(mxc_i2c_reva_regs_t *i2c) +{ + if (i2c == NULL) { return E_NULL_PTR; } - + return (i2c->rxctrl1 & MXC_F_I2C_REVA_RXCTRL1_LVL) >> MXC_F_I2C_REVA_RXCTRL1_LVL_POS; } -int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_RevA_WriteTXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len) { unsigned written = 0; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - while ( (len > written) && (! (i2c->status & MXC_F_I2C_REVA_STATUS_TX_FULL))) { + while ((len > written) && (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_FULL))) { i2c->fifo = bytes[written++]; } - + return written; } -int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ - mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) +int MXC_I2C_RevA_WriteTXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma) { uint8_t i2cNum; uint8_t channel; mxc_dma_srcdst_t srcdst; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*)i2c); - + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; - - #if TARGET_NUM == 32665 + +#if TARGET_NUM == 32665 channel = MXC_DMA_AcquireChannel(dma); - #else +#else channel = MXC_DMA_AcquireChannel(); - #endif - +#endif + config.ch = channel; - + config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - + config.srcinc_en = 1; config.dstinc_en = 0; - + srcdst.ch = channel; srcdst.source = bytes; srcdst.len = len; - + states[i2cNum].channelTx = channel; MXC_DMA_ConfigChannel(config, srcdst); - + if (states[i2cNum].master) { MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); - } - else { + } else { MXC_DMA_SetCallback(channel, NULL); } - - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); + + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); // MXC_DMA->ch[channel].cfg |= MXC_F_DMA_CFG_CTZIEN; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); i2c->dma |= MXC_F_I2C_REVA_DMA_TX_EN; - + return E_NO_ERROR; } -int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_GetTXFIFOAvailable(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } - - int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; - return txFIFOlen - ( (i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS); + + int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> + MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; + return txFIFOlen - + ((i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS); } -void MXC_I2C_RevA_ClearRXFIFO (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c) { i2c->rxctrl0 |= MXC_F_I2C_REVA_RXCTRL0_FLUSH; - - while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH); + + while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH) {} } -void MXC_I2C_RevA_ClearTXFIFO (mxc_i2c_reva_regs_t* i2c) -{ +void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c) +{ i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_FLUSH; - - while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH); + + while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH) {} } -int MXC_I2C_RevA_GetFlags (mxc_i2c_reva_regs_t* i2c, unsigned int *flags0, unsigned int *flags1) +int MXC_I2C_RevA_GetFlags(mxc_i2c_reva_regs_t *i2c, unsigned int *flags0, unsigned int *flags1) { if (i2c == NULL) { return E_NULL_PTR; } - + if ((flags0 == NULL) || (flags1 == NULL)) { return E_BAD_PARAM; } - + *flags0 = i2c->intfl0; *flags1 = i2c->intfl1; - + return E_NO_ERROR; } -void MXC_I2C_RevA_ClearFlags (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_RevA_ClearFlags(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1) { i2c->intfl0 = flags0; i2c->intfl1 = flags1; } -void MXC_I2C_RevA_EnableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_RevA_EnableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1) { i2c->inten0 |= flags0; i2c->inten1 |= flags1; } -void MXC_I2C_RevA_DisableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_RevA_DisableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1) { i2c->inten0 &= ~flags0; i2c->inten1 &= ~flags1; } -int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries) +int MXC_I2C_RevA_Recover(mxc_i2c_reva_regs_t *i2c, unsigned int retries) { int err; unsigned int i; - - if(i2c == NULL) { + + if (i2c == NULL) { return E_NULL_PTR; } @@ -602,91 +604,91 @@ int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries) i2c->ctrl |= MXC_F_I2C_REVA_CTRL_EN; int swBit = i2c->ctrl & MXC_F_I2C_REVA_CTRL_BB_MODE; - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } i2c->ctrl |= MXC_F_I2C_REVA_CTRL_BB_MODE; - + // Follow the procedure detailed in the header file // Delay 10uS between each step to give the line/slaves time to react for (i = 0; i < retries; i++) { - MXC_Delay (10); + MXC_Delay(10); i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SCL_OUT; - + MXC_Delay(10); - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SCL) { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; continue; // Give up and try again } - - MXC_Delay (10); + + MXC_Delay(10); i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SDA_OUT; - + MXC_Delay(10); - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA) { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; continue; // Give up and try again } - - MXC_Delay (10); + + MXC_Delay(10); i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SDA_OUT; - + MXC_Delay(10); - - if (! (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA)) { + + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA)) { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; continue; // Give up and try again } - - MXC_Delay (10); + + MXC_Delay(10); i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT; - + MXC_Delay(10); - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SCL) { err = E_NO_ERROR; // We have control break; } } - + if (swBit == 0) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_BB_MODE; } i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_EN; - + return err; } -void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t *i2c) { i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE; } -void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t *i2c) { i2c->txctrl0 &= ~MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE; } -void MXC_I2C_RevA_EnableGeneralCall (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_EnableGeneralCall(mxc_i2c_reva_regs_t *i2c) { - i2c->txctrl0 &= ~MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_GC_ADDR_EN; } -void MXC_I2C_RevA_DisableGeneralCall (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_DisableGeneralCall(mxc_i2c_reva_regs_t *i2c) { - i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_GC_ADDR_EN; } -void MXC_I2C_RevA_SetTimeout (mxc_i2c_reva_regs_t* i2c, unsigned int timeout) +void MXC_I2C_RevA_SetTimeout(mxc_i2c_reva_regs_t *i2c, unsigned int timeout) { i2c->timeout |= (timeout & 0xFFFF); } -unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetTimeout(mxc_i2c_reva_regs_t *i2c) { return (i2c->timeout & 0xFFFF); } @@ -695,24 +697,24 @@ unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c) /* Transaction level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req) +int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req) { - mxc_i2c_reva_regs_t* i2c = req->i2c; // Save off pointer for faster access + mxc_i2c_reva_regs_t *i2c = req->i2c; // Save off pointer for faster access unsigned int written = 0; unsigned int read = 0; - + if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { return E_NOT_SUPPORTED; } - - if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } - + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { return E_BAD_STATE; } - + // if(!read | write) // Start // send addr w/ write bit @@ -728,288 +730,309 @@ int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req) // read rx_len bytes acking all // stop or restart // return good or error - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); i2c->inten0 = 0; i2c->inten1 = 0; - + if ((req->rx_len == 0) || (req->tx_len != 0)) { // Load the slave address with write bit set i2c->fifo = (req->addr << 1) & ~0x1; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; } - + while (req->tx_len > written) { if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { - written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); + written += MXC_I2C_WriteTXFIFO((mxc_i2c_regs_t *)i2c, &req->tx_buf[written], + req->tx_len - written); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; } - + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { req->tx_len = written; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); + MXC_I2C_Stop((mxc_i2c_regs_t *)i2c); return E_COMM_ERR; } } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0); - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, + MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0); + if (req->rx_len != 0) { if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; - } - else { + } else { i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read } - - MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed - - while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); - - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + + MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed + + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART) {} + + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. } - + while (req->rx_len > read) { if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { - read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); + read += + MXC_I2C_ReadRXFIFO((mxc_i2c_regs_t *)i2c, &req->rx_buf[read], req->rx_len - read); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; } - + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { req->rx_len = read; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); + MXC_I2C_Stop((mxc_i2c_regs_t *)i2c); return E_COMM_ERR; } - - if ( (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { - if ( (req->rx_len-read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + + if ((i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { + if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; - } - else { + } else { i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read } - + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. } } - + if (req->restart) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; + + while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)) {} + // Wait for Transaction to finish } - - while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)); // Wait for Transaction to finish - while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)); // Wait for Transaction to finish - + + while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)) {} + // Wait for Transaction to finish + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_STOP; - + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { return E_COMM_ERR; } - + return E_NO_ERROR; } -int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req) +int MXC_I2C_RevA_MasterTransactionAsync(mxc_i2c_reva_req_t *req) { - int i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*)(req->i2c)); - mxc_i2c_reva_regs_t* i2c = req->i2c; - + int i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)(req->i2c)); + mxc_i2c_reva_regs_t *i2c = req->i2c; + if (i2cNum < 0) { return E_BAD_PARAM; } - + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { return E_BAD_STATE; } - + if (AsyncRequests[i2cNum] == NULL) { if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { return E_NOT_SUPPORTED; } - - AsyncRequests[i2cNum] = (void*) req; + + AsyncRequests[i2cNum] = (void *)req; AsyncWritten[i2cNum] = 0; AsyncRead[i2cNum] = 0; - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - - if ((req->rx_len == 0) || (req->tx_len != 0)) { - i2c->fifo = (req->addr << 1) & ~0x1; // Load the slave address with write bit set - i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + + i2c->inten0 = MXC_I2C_REVA_ERROR; + + if (req->tx_len) { + i2c->fifo = (req->addr << 1) & ~0x1; // Load the slave address with write bit set + } else if (req->rx_len) { + i2c->fifo = (req->addr << 1) | 0x1; // Load the slave address with read bit set + + /* Set the number of bytes to read */ + if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + i2c->rxctrl1 = 0; + } else { + i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read + } + + /* Enable RX Threshold interrupt for when the FIFO is full */ + i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); + } else { + /* Must have tx_len and/or rx_len */ + return E_BAD_PARAM; } - - i2c->inten0 = MXC_I2C_REVA_ERROR | MXC_F_I2C_REVA_INTEN0_TX_THD; + + MXC_I2C_Start((mxc_i2c_regs_t *)i2c); + + /* Fill the FIFO as nessary */ + MXC_I2C_RevA_MasterAsyncHandler(i2cNum); + return E_NO_ERROR; - } - else { + } else { return E_BUSY; } } -int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t* dma) +int MXC_I2C_RevA_MasterTransactionDMA(mxc_i2c_reva_req_t *req, mxc_dma_regs_t *dma) { int i2cNum; - - mxc_i2c_reva_regs_t* i2c = req->i2c; // Save off pointer for faster access - i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); + + mxc_i2c_reva_regs_t *i2c = req->i2c; // Save off pointer for faster access + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { return E_NOT_SUPPORTED; } - + if (i2cNum < 0) { return E_BAD_PARAM; } - + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { return E_BAD_STATE; } - + if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { return E_BAD_PARAM; } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - - MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 2); - MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 1); - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + + MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 2); + MXC_I2C_SetRXThreshold((mxc_i2c_regs_t *)i2c, 1); + states[i2cNum].req = req; - + states[i2cNum].channelTx = 0xFF; states[i2cNum].channelRx = 0xFF; - - #if TARGET_NUM == 32665 + +#if TARGET_NUM == 32665 MXC_DMA_Init(dma); - #else +#else MXC_DMA_Init(); - #endif - +#endif + //tx if ((req->tx_buf != NULL) && !(states[i2cNum].writeDone)) { - i2c->fifo = ((req->addr) << 1) & ~0x1; // Load the slave address with write bit set - - #if TARGET_NUM == 32665 - MXC_I2C_WriteTXFIFODMA ((mxc_i2c_regs_t*) i2c, req->tx_buf, req->tx_len, NULL, dma); - #else - MXC_I2C_WriteTXFIFODMA ((mxc_i2c_regs_t*) i2c, req->tx_buf, req->tx_len, NULL); - #endif - } - else { + i2c->fifo = ((req->addr) << 1) & ~0x1; // Load the slave address with write bit set + +#if TARGET_NUM == 32665 + MXC_I2C_WriteTXFIFODMA((mxc_i2c_regs_t *)i2c, req->tx_buf, req->tx_len, NULL, dma); +#else + MXC_I2C_WriteTXFIFODMA((mxc_i2c_regs_t *)i2c, req->tx_buf, req->tx_len, NULL); +#endif + } else { states[i2cNum].writeDone = 1; } - + if (req->rx_buf != NULL) { - while(states[i2cNum].writeDone != 1); //Ensure DMA transmit has finished before attempting to receive + while (states[i2cNum].writeDone != 1) {} + //Ensure DMA transmit has finished before attempting to receive - if ( (states[i2cNum].writeDone) && (!states[i2cNum].readDone)) { + if ((states[i2cNum].writeDone) && (!states[i2cNum].readDone)) { if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; - } - else { + } else { i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read } - MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed - - while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); - - i2c->fifo = ((req->addr) << 1) | 0x1; // Load the slave address with write bit set - - #if TARGET_NUM == 32665 - MXC_I2C_ReadRXFIFODMA ((mxc_i2c_regs_t*) i2c, req->rx_buf, req->rx_len, NULL, dma); - #else - MXC_I2C_ReadRXFIFODMA ((mxc_i2c_regs_t*) i2c, req->rx_buf, req->rx_len, NULL); - #endif + MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed + + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART) {} + + i2c->fifo = ((req->addr) << 1) | 0x1; // Load the slave address with write bit set + +#if TARGET_NUM == 32665 + MXC_I2C_ReadRXFIFODMA((mxc_i2c_regs_t *)i2c, req->rx_buf, req->rx_len, NULL, dma); +#else + MXC_I2C_ReadRXFIFODMA((mxc_i2c_regs_t *)i2c, req->rx_buf, req->rx_len, NULL); +#endif } - } - else { + } else { states[i2cNum].readDone = 1; } - + return E_NO_ERROR; } void MXC_I2C_RevA_DMACallback(int ch, int error) { mxc_i2c_reva_req_t *temp_req; - - for (int i = 0; i < MXC_I2C_INSTANCES; i ++) { + + for (int i = 0; i < MXC_I2C_INSTANCES; i++) { if (states[i].channelTx == ch) { //save the request temp_req = states[i].req; states[i].writeDone = 1; - + if (states[i].readDone) { if (temp_req->restart) { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; } - + MXC_DMA_ReleaseChannel(states[i].channelRx); MXC_DMA_ReleaseChannel(states[i].channelTx); - + // Callback if not NULL if (temp_req->callback != NULL) { temp_req->callback(temp_req, E_NO_ERROR); } } - } - - else if (states[i].channelRx == ch) { + } else if (states[i].channelRx == ch) { //save the request states[i].readDone = 1; temp_req = states[i].req; - + if (states[i].writeDone) { if (temp_req->restart) { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; } - + MXC_DMA_ReleaseChannel(states[i].channelRx); MXC_DMA_ReleaseChannel(states[i].channelTx); - + // Callback if not NULL if (temp_req->callback != NULL) { temp_req->callback(temp_req, E_NO_ERROR); - } + } } } } } -int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) +int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck) { unsigned int interruptEnables = interruptCheck; int retVal = E_NO_ERROR; - - if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { return E_BAD_STATE; } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + // Callback called on // Slave Address Match (distinguish read/write) // RX Threshold @@ -1026,98 +1049,110 @@ int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_ // I2C_EVT_TRANS_COMP // I2C_EVT_UNDERFLOW // I2C_EVT_OVERFLOW - + while (interruptEnables > 0) { interruptEnables = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, interruptEnables, &retVal); } - + return retVal; } -int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) +int MXC_I2C_RevA_SlaveTransactionAsync(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck) { - int i2cnum = MXC_I2C_GET_IDX((mxc_i2c_regs_t*) i2c); - + int i2cnum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + if (i2cnum < 0) { return E_BAD_PARAM; } - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { return E_BAD_STATE; } - + if (AsyncRequests[i2cnum] != NULL) { return E_BUSY; } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 1); // set TX threshold to 2 bytes - MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 1); // set RX threshold to 6 bytes - AsyncRequests[i2cnum] = (void *) callback; - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 1); // set TX threshold to 2 bytes + MXC_I2C_SetRXThreshold((mxc_i2c_regs_t *)i2c, 1); // set RX threshold to 6 bytes + AsyncRequests[i2cnum] = (void *)callback; + i2c->inten0 = interruptCheck; - + return E_NO_ERROR; } -int MXC_I2C_RevA_SetRXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes) { - unsigned int rxFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS; - + unsigned int rxFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH) >> + MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS; + if (numBytes > rxFIFOlen) { return E_BAD_PARAM; } - - i2c->rxctrl0 = (i2c->rxctrl0 & ~MXC_F_I2C_REVA_RXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS); + + i2c->rxctrl0 = (i2c->rxctrl0 & ~MXC_F_I2C_REVA_RXCTRL0_THD_LVL) | + (numBytes << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS); return E_NO_ERROR; } -unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetRXThreshold(mxc_i2c_reva_regs_t *i2c) { return (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_THD_LVL) >> MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS; } -int MXC_I2C_RevA_SetTXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes) { - unsigned int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; - + unsigned int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> + MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; + if (numBytes > txFIFOlen) { return E_BAD_PARAM; } - - i2c->txctrl0 = (i2c->txctrl0 & ~MXC_F_I2C_REVA_TXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS); + + i2c->txctrl0 = (i2c->txctrl0 & ~MXC_F_I2C_REVA_TXCTRL0_THD_LVL) | + (numBytes << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS); return E_NO_ERROR; } -unsigned int MXC_I2C_RevA_GetTXThreshold (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetTXThreshold(mxc_i2c_reva_regs_t *i2c) { return (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_THD_LVL) >> MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS; } -void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal) +void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal) { // Don't need to check for return value as this function is not accessible to user // i2c is already cheked for NULL from where this function is being called - mxc_i2c_reva_req_t* req = (mxc_i2c_reva_req_t*) AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)]; - + mxc_i2c_reva_req_t *req = + (mxc_i2c_reva_req_t *)AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)]; + if (req->callback != NULL) { req->callback(req, retVal); } } -void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c) { + /* Disable and clear interrupts */ i2c->inten0 = 0; i2c->inten1 = 0; - + + i2c->intfl0 = i2c->intfl0; + i2c->intfl1 = i2c->intfl1; + // Don't need to check for return value as this function is not accessible to user // i2c is already cheked for NULL from where this function is being called - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } -void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c) { // Don't need to check for return value as this function is not accessible to user // i2c is already cheked for NULL from where this function is being called @@ -1129,95 +1164,119 @@ void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum) { unsigned int written = AsyncWritten[i2cNum]; unsigned int read = AsyncRead[i2cNum]; - mxc_i2c_reva_regs_t* i2c = (mxc_i2c_reva_regs_t*) MXC_I2C_GET_BASE (i2cNum); - mxc_i2c_reva_req_t* req = (mxc_i2c_reva_req_t*) AsyncRequests[i2cNum]; - + mxc_i2c_reva_regs_t *i2c = (mxc_i2c_reva_regs_t *)MXC_I2C_GET_BASE(i2cNum); + mxc_i2c_reva_req_t *req = (mxc_i2c_reva_req_t *)AsyncRequests[i2cNum]; + + /* Check for errors */ + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { + /* Clear and disable interrupts */ + i2c->intfl0 = i2c->intfl0; + i2c->intfl1 = i2c->intfl1; + i2c->inten0 = 0; + i2c->inten1 = 0; + + MXC_I2C_Stop((mxc_i2c_regs_t *)i2c); + MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR); + MXC_I2C_RevA_AsyncStop(i2c); + + return; + } + + /* Write data to the TX FIFO */ if (req->tx_len > written) { if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { - written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); + written += MXC_I2C_WriteTXFIFO((mxc_i2c_regs_t *)i2c, &req->tx_buf[written], + req->tx_len - written); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; } - - if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { - req->tx_len = written; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); - MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); - MXC_I2C_RevA_AsyncStop (i2c); + + /* Enable the TX Threshold interrupt if we still need to write to the TX FIFO */ + if (written < req->tx_len) { + i2c->inten0 |= MXC_F_I2C_REVA_INTEN0_TX_THD; + } else { + i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_TX_THD); + } + + /* Send a restart if we're reading after writing */ + if ((req->tx_len == written) && (req->rx_len)) { + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; + i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_DONE); } } - + + /* Read data in the RX FIFO */ if (req->rx_len > read) { if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { - read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); + read += + MXC_I2C_ReadRXFIFO((mxc_i2c_regs_t *)i2c, &req->rx_buf[read], req->rx_len - read); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; } - - if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { - req->rx_len = read; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); - MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); - MXC_I2C_RevA_AsyncStop (i2c); - } - - if ( (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { - if ( (req->rx_len-read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { - i2c->rxctrl1 = 0; - } - else { - i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read - } - - i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. - } } - - if ( (req->tx_len == written) && (read == 0)) { - i2c->inten0 &= ~MXC_F_I2C_REVA_INTEN0_TX_THD; - i2c->inten0 |= MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE; - - if ( (req->rx_len) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + + /* Done writing, still reading */ + if ((req->tx_len == written) && (req->rx_len - read) && + (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)) { + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; + + /* First done interrupt after completing writes to the TX FIFO */ + if (read == 0) { + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + } + + /* Set the number of bytes to read */ + if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; + } else { + i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read } - else { - i2c->rxctrl1 = (req->rx_len); // 0 for 256, otherwise number of bytes to read + + /* Enable RX Threshold interrupt for when the FIFO is full */ + if (read < req->rx_len) { + i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); + } else { + i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); } - - MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed - - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. } - - if ( (req->tx_len == written) && (req->rx_len == read)) { - i2c->inten0 &= ~ (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); - + + /* Done reading and writing */ + if ((req->tx_len == written) && (req->rx_len == read)) { + /* Disable and clear interrupts */ + i2c->inten0 = 0; + i2c->inten1 = 0; + i2c->intfl0 = i2c->intfl0; + i2c->intfl1 = i2c->intfl1; + + /* Send a restart or stop at the end of the transaction */ if (req->restart) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; } - + + /* Call the callback */ if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { - MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); - } - else { + MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR); + } else { MXC_I2C_RevA_AsyncCallback(i2c, E_NO_ERROR); } - + + /* Clear the async state */ MXC_I2C_RevA_AsyncStop(i2c); + + } else { + AsyncWritten[i2cNum] = written; + AsyncRead[i2cNum] = read; } - - AsyncWritten[i2cNum] = written; - AsyncRead[i2cNum] = read; } -unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal) +unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + unsigned int interruptEnables, int *retVal) { uint32_t tFlags = i2c->intfl0; *retVal = E_NO_ERROR; - + uint32_t readFlag = i2c->ctrl & MXC_F_I2C_REVA_CTRL_READ; // Callback called on // Slave Address Match (distinguish read/write) @@ -1235,114 +1294,161 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_r // I2C_EVT_TRANS_COMP // I2C_EVT_UNDERFLOW // I2C_EVT_OVERFLOW - if (!(interruptEnables & (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH| MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { + if (!(interruptEnables & + (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH | + MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { // The STOPERR/STARTERR interrupt that's enabled here could fire before we are addressed // (fires anytime a stop/start is detected out of sequence). if (tFlags & MXC_I2C_REVA_ERROR) { *retVal = E_COMM_ERR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } - + if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV)) { if (tFlags & MXC_F_I2C_REVA_INTFL0_RX_THD) { - callback (i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; } - + if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_RX_OV) { - callback (i2c, MXC_I2C_REVA_EVT_OVERFLOW, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_OVERFLOW, NULL); + } + i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_RX_OV; } } - - if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) { + + if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | + MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) { if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_THD) { - callback (i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; } - + if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_TX_UN) { - callback (i2c, MXC_I2C_REVA_EVT_UNDERFLOW, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_UNDERFLOW, NULL); + } + i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_TX_UN; } - + if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT) { *retVal = E_NO_ERROR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT; interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } } - + if (tFlags & MXC_F_I2C_REVA_INTFL0_STOP) { *retVal = E_NO_ERROR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_STOP; interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } } if (tFlags & MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH) { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; + interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | + MXC_I2C_REVA_ERROR; } - + if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | + MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; } - if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH){ + if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH) { if (readFlag & MXC_F_I2C_REVA_CTRL_READ) { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; - } - else { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | + MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + } else { + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; + interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | + MXC_I2C_REVA_ERROR; } } else if (tFlags & MXC_I2C_REVA_ERROR) { *retVal = E_COMM_ERR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); - MXC_I2C_RevA_ClearFlags(i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + + MXC_I2C_RevA_ClearFlags(i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts MXC_I2C_RevA_ClearTXFIFO(i2c); MXC_I2C_RevA_ClearRXFIFO(i2c); interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } - + return interruptEnables; } -void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptCheck) +void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck) { - int i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); + int i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); int slaveRetVal; - + if (i2cNum < 0) { return; } - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { - MXC_I2C_RevA_MasterAsyncHandler (i2cNum); - } - else { - mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t) AsyncRequests[i2cNum]; - i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler (i2c, callback, i2c->inten0, &slaveRetVal); + MXC_I2C_RevA_MasterAsyncHandler(i2cNum); + } else { + mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t)AsyncRequests[i2cNum]; + i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, i2c->inten0, &slaveRetVal); } } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h index c32f66eb711..aa41e2c5761 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h @@ -1,5 +1,5 @@ /* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -31,8 +31,8 @@ * *************************************************************************** */ -#ifndef _I2C_REVA_H_ -#define _I2C_REVA_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ #include #include @@ -46,33 +46,34 @@ #include "i2c_reva_regs.h" #include "dma.h" - /* **** Definitions **** */ -#define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F -#define MXC_I2C_REVA_STD_MODE 100000 -#define MXC_I2C_REVA_FAST_SPEED 400000 -#define MXC_I2C_REVA_FASTPLUS_SPEED 1000000 -#define MXC_I2C_REVA_HS_MODE 3400000 +#define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F +#define MXC_I2C_REVA_STD_MODE 100000 +#define MXC_I2C_REVA_FAST_SPEED 400000 +#define MXC_I2C_REVA_FASTPLUS_SPEED 1000000 +#define MXC_I2C_REVA_HS_MODE 3400000 -#define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF -#define MXC_I2C_REVA_INTFL1_MASK 0x00000007 +#define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF +#define MXC_I2C_REVA_INTFL1_MASK 0x00000007 -#define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256 +#define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256 -#define MXC_I2C_REVA_ERROR (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | \ - MXC_F_I2C_REVA_INTFL0_DATA_ERR | MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \ - MXC_F_I2C_REVA_INTFL0_STOP_ERR) +#define MXC_I2C_REVA_ERROR \ + (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | \ + MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | MXC_F_I2C_REVA_INTFL0_DATA_ERR | \ + MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \ + MXC_F_I2C_REVA_INTFL0_STOP_ERR) typedef struct _i2c_reva_req_t mxc_i2c_reva_req_t; -typedef int (*mxc_i2c_reva_getAck_t) (mxc_i2c_reva_regs_t* i2c, unsigned char byte); -typedef void (*mxc_i2c_reva_complete_cb_t) (mxc_i2c_reva_req_t* req, int result); -typedef void (*mxc_i2c_reva_dma_complete_cb_t) (int len, int result); +typedef int (*mxc_i2c_reva_getAck_t)(mxc_i2c_reva_regs_t *i2c, unsigned char byte); +typedef void (*mxc_i2c_reva_complete_cb_t)(mxc_i2c_reva_req_t *req, int result); +typedef void (*mxc_i2c_reva_dma_complete_cb_t)(int len, int result); struct _i2c_reva_req_t { - mxc_i2c_reva_regs_t* i2c; + mxc_i2c_reva_regs_t *i2c; unsigned int addr; - unsigned char* tx_buf; + unsigned char *tx_buf; unsigned int tx_len; - unsigned char* rx_buf; + unsigned char *rx_buf; unsigned int rx_len; int restart; mxc_i2c_reva_complete_cb_t callback; @@ -86,72 +87,86 @@ typedef enum { MXC_I2C_REVA_EVT_UNDERFLOW, MXC_I2C_REVA_EVT_OVERFLOW, } mxc_i2c_reva_slave_event_t; -typedef int (*mxc_i2c_reva_slave_handler_t) (mxc_i2c_reva_regs_t* i2c, - mxc_i2c_reva_slave_event_t event, void* data); +typedef int (*mxc_i2c_reva_slave_handler_t)(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_event_t event, void *data); /* **** Variable Declaration **** */ +extern void *AsyncRequests[MXC_I2C_INSTANCES]; + /* **** Function Prototypes **** */ /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int slaveAddr); -int MXC_I2C_RevA_SetSlaveAddr (mxc_i2c_reva_regs_t* i2c, unsigned int slaveAddr, int idx); -int MXC_I2C_RevA_Shutdown (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz); -unsigned int MXC_I2C_RevA_GetFrequency (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_ReadyForSleep (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable); -int MXC_I2C_RevA_GetClockStretching (mxc_i2c_reva_regs_t* i2c); +int MXC_I2C_RevA_Init(mxc_i2c_reva_regs_t *i2c, int masterMode, unsigned int slaveAddr); +int MXC_I2C_RevA_SetSlaveAddr(mxc_i2c_reva_regs_t *i2c, unsigned int slaveAddr, int idx); +int MXC_I2C_RevA_Shutdown(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz); +unsigned int MXC_I2C_RevA_GetFrequency(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_ReadyForSleep(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_SetClockStretching(mxc_i2c_reva_regs_t *i2c, int enable); +int MXC_I2C_RevA_GetClockStretching(mxc_i2c_reva_regs_t *i2c); /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte); -int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ack); -int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck); -int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len); -int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack); -int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); -int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); -int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); -int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); -int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_ClearRXFIFO (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_ClearTXFIFO (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_GetFlags (mxc_i2c_reva_regs_t* i2c, unsigned int *flags0, unsigned int *flags1); -void MXC_I2C_RevA_ClearFlags (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); -void MXC_I2C_RevA_EnableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); -void MXC_I2C_RevA_DisableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); -void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_EnableGeneralCall (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_DisableGeneralCall (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_SetTimeout (mxc_i2c_reva_regs_t* i2c, unsigned int timeout); -unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries); +int MXC_I2C_RevA_Start(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_Stop(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_WriteByte(mxc_i2c_reva_regs_t *i2c, unsigned char byte); +int MXC_I2C_RevA_ReadByte(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, int ack); +int MXC_I2C_RevA_ReadByteInteractive(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, + mxc_i2c_reva_getAck_t getAck); +int MXC_I2C_RevA_Write(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len); +int MXC_I2C_RevA_Read(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack); +int MXC_I2C_RevA_ReadRXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len); +int MXC_I2C_RevA_ReadRXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma); +int MXC_I2C_RevA_GetRXFIFOAvailable(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_WriteTXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len); +int MXC_I2C_RevA_WriteTXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma); +int MXC_I2C_RevA_GetTXFIFOAvailable(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_GetFlags(mxc_i2c_reva_regs_t *i2c, unsigned int *flags0, unsigned int *flags1); +void MXC_I2C_RevA_ClearFlags(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_EnableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_DisableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_EnableGeneralCall(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_DisableGeneralCall(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_SetTimeout(mxc_i2c_reva_regs_t *i2c, unsigned int timeout); +unsigned int MXC_I2C_RevA_GetTimeout(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_Recover(mxc_i2c_reva_regs_t *i2c, unsigned int retries); /* ************************************************************************* */ /* Transaction level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req); -int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req); -int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t* dma); -int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); -int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); -int MXC_I2C_RevA_SetRXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes); -unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_SetTXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes); -unsigned int MXC_I2C_RevA_GetTXThreshold (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal); -void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_MasterAsyncHandler (int i2cNum); -unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); -void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptCheck); -void MXC_I2C_RevA_DMACallback (int ch, int error); +int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req); +int MXC_I2C_RevA_MasterTransactionAsync(mxc_i2c_reva_req_t *req); +int MXC_I2C_RevA_MasterTransactionDMA(mxc_i2c_reva_req_t *req, mxc_dma_regs_t *dma); +int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck); +int MXC_I2C_RevA_SlaveTransactionAsync(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck); +int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes); +unsigned int MXC_I2C_RevA_GetRXThreshold(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes); +unsigned int MXC_I2C_RevA_GetTXThreshold(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal); +void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); +unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + unsigned int interruptEnables, int *retVal); +void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck); +void MXC_I2C_RevA_DMACallback(int ch, int error); -#endif /* _I2C_REVA_H_ */ \ No newline at end of file +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h index d4a3ee29813..49a434116ff 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h @@ -4,7 +4,7 @@ */ /* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -37,8 +37,8 @@ * *************************************************************************** */ -#ifndef _I2C_REVA_REGS_H_ -#define _I2C_REVA_REGS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -115,25 +115,25 @@ typedef struct { * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. * @{ */ - #define MXC_R_I2C_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ - #define MXC_R_I2C_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ - #define MXC_R_I2C_REVA_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ - #define MXC_R_I2C_REVA_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ - #define MXC_R_I2C_REVA_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ - #define MXC_R_I2C_REVA_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ - #define MXC_R_I2C_REVA_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ - #define MXC_R_I2C_REVA_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ - #define MXC_R_I2C_REVA_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ - #define MXC_R_I2C_REVA_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ - #define MXC_R_I2C_REVA_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ - #define MXC_R_I2C_REVA_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ - #define MXC_R_I2C_REVA_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ - #define MXC_R_I2C_REVA_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ - #define MXC_R_I2C_REVA_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ - #define MXC_R_I2C_REVA_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ - #define MXC_R_I2C_REVA_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ - #define MXC_R_I2C_REVA_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ - #define MXC_R_I2C_REVA_SLAVE ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: 0x004C */ +#define MXC_R_I2C_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ +#define MXC_R_I2C_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ +#define MXC_R_I2C_REVA_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ +#define MXC_R_I2C_REVA_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ +#define MXC_R_I2C_REVA_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ +#define MXC_R_I2C_REVA_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ +#define MXC_R_I2C_REVA_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ +#define MXC_R_I2C_REVA_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ +#define MXC_R_I2C_REVA_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ +#define MXC_R_I2C_REVA_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ +#define MXC_R_I2C_REVA_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ +#define MXC_R_I2C_REVA_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ +#define MXC_R_I2C_REVA_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ +#define MXC_R_I2C_REVA_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ +#define MXC_R_I2C_REVA_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ +#define MXC_R_I2C_REVA_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ +#define MXC_R_I2C_REVA_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ +#define MXC_R_I2C_REVA_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ +#define MXC_R_I2C_REVA_SLAVE ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: 0x004C */ /**@} end of group i2c_registers */ /** @@ -142,47 +142,47 @@ typedef struct { * @brief Control Register0. * @{ */ - #define MXC_F_I2C_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ - #define MXC_F_I2C_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_I2C_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ - #define MXC_F_I2C_REVA_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ - #define MXC_F_I2C_REVA_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ +#define MXC_F_I2C_REVA_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ +#define MXC_F_I2C_REVA_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ - #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ - #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ +#define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ - #define MXC_F_I2C_REVA_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ - #define MXC_F_I2C_REVA_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ +#define MXC_F_I2C_REVA_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ - #define MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ - #define MXC_F_I2C_REVA_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ +#define MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ +#define MXC_F_I2C_REVA_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ - #define MXC_F_I2C_REVA_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ - #define MXC_F_I2C_REVA_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ +#define MXC_F_I2C_REVA_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ +#define MXC_F_I2C_REVA_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ - #define MXC_F_I2C_REVA_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ - #define MXC_F_I2C_REVA_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ +#define MXC_F_I2C_REVA_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ +#define MXC_F_I2C_REVA_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ - #define MXC_F_I2C_REVA_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ - #define MXC_F_I2C_REVA_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ +#define MXC_F_I2C_REVA_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ +#define MXC_F_I2C_REVA_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ - #define MXC_F_I2C_REVA_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ - #define MXC_F_I2C_REVA_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ +#define MXC_F_I2C_REVA_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ +#define MXC_F_I2C_REVA_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ - #define MXC_F_I2C_REVA_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ - #define MXC_F_I2C_REVA_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ +#define MXC_F_I2C_REVA_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ +#define MXC_F_I2C_REVA_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ - #define MXC_F_I2C_REVA_CTRL_READ_POS 11 /**< CTRL_READ Position */ - #define MXC_F_I2C_REVA_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_READ_POS)) /**< CTRL_READ Mask */ +#define MXC_F_I2C_REVA_CTRL_READ_POS 11 /**< CTRL_READ Position */ +#define MXC_F_I2C_REVA_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_READ_POS)) /**< CTRL_READ Mask */ - #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ - #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ +#define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ +#define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ - #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ - #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ +#define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ +#define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ - #define MXC_F_I2C_REVA_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ - #define MXC_F_I2C_REVA_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ +#define MXC_F_I2C_REVA_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ /**@} end of group I2C_CTRL_Register */ @@ -192,23 +192,23 @@ typedef struct { * @brief Status Register. * @{ */ - #define MXC_F_I2C_REVA_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ - #define MXC_F_I2C_REVA_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ +#define MXC_F_I2C_REVA_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ +#define MXC_F_I2C_REVA_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ - #define MXC_F_I2C_REVA_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ - #define MXC_F_I2C_REVA_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ +#define MXC_F_I2C_REVA_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ +#define MXC_F_I2C_REVA_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ - #define MXC_F_I2C_REVA_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ - #define MXC_F_I2C_REVA_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ +#define MXC_F_I2C_REVA_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ +#define MXC_F_I2C_REVA_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ - #define MXC_F_I2C_REVA_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ - #define MXC_F_I2C_REVA_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ +#define MXC_F_I2C_REVA_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ +#define MXC_F_I2C_REVA_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ - #define MXC_F_I2C_REVA_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ - #define MXC_F_I2C_REVA_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ +#define MXC_F_I2C_REVA_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ +#define MXC_F_I2C_REVA_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ - #define MXC_F_I2C_REVA_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ - #define MXC_F_I2C_REVA_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ +#define MXC_F_I2C_REVA_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ +#define MXC_F_I2C_REVA_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ /**@} end of group I2C_STATUS_Register */ @@ -218,62 +218,62 @@ typedef struct { * @brief Interrupt Status Register. * @{ */ - #define MXC_F_I2C_REVA_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ - #define MXC_F_I2C_REVA_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ +#define MXC_F_I2C_REVA_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ +#define MXC_F_I2C_REVA_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ - #define MXC_F_I2C_REVA_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ - #define MXC_F_I2C_REVA_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ +#define MXC_F_I2C_REVA_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ +#define MXC_F_I2C_REVA_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ - #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ - #define MXC_F_I2C_REVA_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ +#define MXC_F_I2C_REVA_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ +#define MXC_F_I2C_REVA_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ - #define MXC_F_I2C_REVA_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ - #define MXC_F_I2C_REVA_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ +#define MXC_F_I2C_REVA_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ +#define MXC_F_I2C_REVA_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ - #define MXC_F_I2C_REVA_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ - #define MXC_F_I2C_REVA_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ +#define MXC_F_I2C_REVA_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ +#define MXC_F_I2C_REVA_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ - #define MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ - #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ +#define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ +#define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ - #define MXC_F_I2C_REVA_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ - #define MXC_F_I2C_REVA_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ +#define MXC_F_I2C_REVA_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ +#define MXC_F_I2C_REVA_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ - #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ /**@} end of group I2C_INTFL0_Register */ @@ -283,62 +283,62 @@ typedef struct { * @brief Interrupt Enable Register. * @{ */ - #define MXC_F_I2C_REVA_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ - #define MXC_F_I2C_REVA_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ +#define MXC_F_I2C_REVA_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ +#define MXC_F_I2C_REVA_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ - #define MXC_F_I2C_REVA_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ - #define MXC_F_I2C_REVA_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ +#define MXC_F_I2C_REVA_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ +#define MXC_F_I2C_REVA_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ - #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ - #define MXC_F_I2C_REVA_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ +#define MXC_F_I2C_REVA_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ +#define MXC_F_I2C_REVA_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ - #define MXC_F_I2C_REVA_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ - #define MXC_F_I2C_REVA_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ +#define MXC_F_I2C_REVA_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ +#define MXC_F_I2C_REVA_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ - #define MXC_F_I2C_REVA_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ - #define MXC_F_I2C_REVA_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ +#define MXC_F_I2C_REVA_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ +#define MXC_F_I2C_REVA_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ - #define MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ - #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ +#define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ +#define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ - #define MXC_F_I2C_REVA_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ - #define MXC_F_I2C_REVA_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ +#define MXC_F_I2C_REVA_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ +#define MXC_F_I2C_REVA_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ - #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ /**@} end of group I2C_INTEN0_Register */ @@ -348,14 +348,14 @@ typedef struct { * @brief Interrupt Status Register 1. * @{ */ - #define MXC_F_I2C_REVA_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ - #define MXC_F_I2C_REVA_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ +#define MXC_F_I2C_REVA_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ +#define MXC_F_I2C_REVA_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ - #define MXC_F_I2C_REVA_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ - #define MXC_F_I2C_REVA_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ +#define MXC_F_I2C_REVA_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ +#define MXC_F_I2C_REVA_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ - #define MXC_F_I2C_REVA_INTFL1_START_POS 2 /**< INTFL1_START Position */ - #define MXC_F_I2C_REVA_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_START_POS)) /**< INTFL1_START Mask */ +#define MXC_F_I2C_REVA_INTFL1_START_POS 2 /**< INTFL1_START Position */ +#define MXC_F_I2C_REVA_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_START_POS)) /**< INTFL1_START Mask */ /**@} end of group I2C_INTFL1_Register */ @@ -365,14 +365,14 @@ typedef struct { * @brief Interrupt Staus Register 1. * @{ */ - #define MXC_F_I2C_REVA_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ - #define MXC_F_I2C_REVA_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ +#define MXC_F_I2C_REVA_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ +#define MXC_F_I2C_REVA_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ - #define MXC_F_I2C_REVA_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ - #define MXC_F_I2C_REVA_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ +#define MXC_F_I2C_REVA_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ +#define MXC_F_I2C_REVA_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ - #define MXC_F_I2C_REVA_INTEN1_START_POS 2 /**< INTEN1_START Position */ - #define MXC_F_I2C_REVA_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_START_POS)) /**< INTEN1_START Mask */ +#define MXC_F_I2C_REVA_INTEN1_START_POS 2 /**< INTEN1_START Position */ +#define MXC_F_I2C_REVA_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_START_POS)) /**< INTEN1_START Mask */ /**@} end of group I2C_INTEN1_Register */ @@ -382,11 +382,11 @@ typedef struct { * @brief FIFO Configuration Register. * @{ */ - #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ - #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ +#define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ +#define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ - #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ - #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ +#define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ +#define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ /**@} end of group I2C_FIFOLEN_Register */ @@ -396,14 +396,14 @@ typedef struct { * @brief Receive Control Register 0. * @{ */ - #define MXC_F_I2C_REVA_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ - #define MXC_F_I2C_REVA_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ +#define MXC_F_I2C_REVA_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ +#define MXC_F_I2C_REVA_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ - #define MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ - #define MXC_F_I2C_REVA_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ +#define MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ +#define MXC_F_I2C_REVA_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ - #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ - #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ +#define MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ +#define MXC_F_I2C_REVA_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ /**@} end of group I2C_RXCTRL0_Register */ @@ -413,11 +413,11 @@ typedef struct { * @brief Receive Control Register 1. * @{ */ - #define MXC_F_I2C_REVA_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ - #define MXC_F_I2C_REVA_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ +#define MXC_F_I2C_REVA_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ +#define MXC_F_I2C_REVA_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ - #define MXC_F_I2C_REVA_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ - #define MXC_F_I2C_REVA_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ +#define MXC_F_I2C_REVA_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ +#define MXC_F_I2C_REVA_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ /**@} end of group I2C_RXCTRL1_Register */ @@ -427,29 +427,29 @@ typedef struct { * @brief Transmit Control Register 0. * @{ */ - #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ - #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ +#define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ - #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ +#define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ - #define MXC_F_I2C_REVA_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ +#define MXC_F_I2C_REVA_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS 8 /**< TXCTRL0_THD_LVL Position */ - #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS)) /**< TXCTRL0_THD_LVL Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS 8 /**< TXCTRL0_THD_LVL Position */ +#define MXC_F_I2C_REVA_TXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS)) /**< TXCTRL0_THD_LVL Mask */ /**@} end of group I2C_TXCTRL0_Register */ @@ -459,11 +459,11 @@ typedef struct { * @brief Transmit Control Register 1. * @{ */ - #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ - #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ +#define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ +#define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ - #define MXC_F_I2C_REVA_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ - #define MXC_F_I2C_REVA_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ +#define MXC_F_I2C_REVA_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ +#define MXC_F_I2C_REVA_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ /**@} end of group I2C_TXCTRL1_Register */ @@ -473,8 +473,8 @@ typedef struct { * @brief Data Register. * @{ */ - #define MXC_F_I2C_REVA_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ - #define MXC_F_I2C_REVA_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ +#define MXC_F_I2C_REVA_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_I2C_REVA_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ /**@} end of group I2C_FIFO_Register */ @@ -484,17 +484,17 @@ typedef struct { * @brief Master Control Register. * @{ */ - #define MXC_F_I2C_REVA_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ - #define MXC_F_I2C_REVA_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ +#define MXC_F_I2C_REVA_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ - #define MXC_F_I2C_REVA_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ - #define MXC_F_I2C_REVA_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ +#define MXC_F_I2C_REVA_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ - #define MXC_F_I2C_REVA_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ - #define MXC_F_I2C_REVA_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ +#define MXC_F_I2C_REVA_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ - #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ - #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ +#define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ /**@} end of group I2C_MSTCTRL_Register */ @@ -504,8 +504,8 @@ typedef struct { * @brief Clock Low Register. * @{ */ - #define MXC_F_I2C_REVA_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ - #define MXC_F_I2C_REVA_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ +#define MXC_F_I2C_REVA_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ +#define MXC_F_I2C_REVA_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ /**@} end of group I2C_CLKLO_Register */ @@ -515,8 +515,8 @@ typedef struct { * @brief Clock high Register. * @{ */ - #define MXC_F_I2C_REVA_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ - #define MXC_F_I2C_REVA_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ +#define MXC_F_I2C_REVA_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ +#define MXC_F_I2C_REVA_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ /**@} end of group I2C_CLKHI_Register */ @@ -526,11 +526,11 @@ typedef struct { * @brief Clock high Register. * @{ */ - #define MXC_F_I2C_REVA_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ - #define MXC_F_I2C_REVA_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ +#define MXC_F_I2C_REVA_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ +#define MXC_F_I2C_REVA_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ - #define MXC_F_I2C_REVA_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ - #define MXC_F_I2C_REVA_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ +#define MXC_F_I2C_REVA_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ +#define MXC_F_I2C_REVA_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ /**@} end of group I2C_HSCLK_Register */ @@ -540,8 +540,8 @@ typedef struct { * @brief Timeout Register * @{ */ - #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ - #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ +#define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ +#define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ /**@} end of group I2C_TIMEOUT_Register */ @@ -551,11 +551,11 @@ typedef struct { * @brief DMA Register. * @{ */ - #define MXC_F_I2C_REVA_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ - #define MXC_F_I2C_REVA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ +#define MXC_F_I2C_REVA_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ +#define MXC_F_I2C_REVA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ - #define MXC_F_I2C_REVA_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ - #define MXC_F_I2C_REVA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ +#define MXC_F_I2C_REVA_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ +#define MXC_F_I2C_REVA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ /**@} end of group I2C_DMA_Register */ @@ -565,11 +565,11 @@ typedef struct { * @brief Slave Address Register. * @{ */ - #define MXC_F_I2C_REVA_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */ - #define MXC_F_I2C_REVA_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_REVA_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */ +#define MXC_F_I2C_REVA_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */ +#define MXC_F_I2C_REVA_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_REVA_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */ - #define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */ - #define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */ +#define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */ +#define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */ /**@} end of group I2C_SLAVE_Register */ @@ -577,4 +577,5 @@ typedef struct { } #endif -#endif /* _I2C_REGS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c index d98a03eaea9..8d6fd6a7de1 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c @@ -31,7 +31,6 @@ * *************************************************************************** */ - #include #include #include @@ -46,7 +45,6 @@ #include "mxc_i2c.h" #include "i2c_reva.h" - /* **** Definitions **** */ #define MXC_I2C_FASTPLUS_SPEED 1000000 @@ -58,54 +56,51 @@ uint32_t interruptCheck = MXC_F_I2C_INTFL0_ADDR_MATCH | MXC_F_I2C_INTFL0_DNR_ERR /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_I2C_Init(mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr) +int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr) { if (i2c == NULL) { return E_NULL_PTR; } - - MXC_I2C_Shutdown(i2c); // Clear everything out - + + MXC_I2C_Shutdown(i2c); // Clear everything out + if (i2c == MXC_I2C0) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0); MXC_GPIO_Config(&gpio_cfg_i2c0); - } - #if TARGET_NUM != 32675 - else if (i2c == MXC_I2C1) { +#if TARGET_NUM != 32675 + } else if (i2c == MXC_I2C1) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1); MXC_GPIO_Config(&gpio_cfg_i2c1); - } - #endif - else if (i2c == MXC_I2C2) { +#endif + } else if (i2c == MXC_I2C2) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C2); MXC_GPIO_Config(&gpio_cfg_i2c2); - } - else { + } else { return E_NO_DEVICE; } - - return MXC_I2C_RevA_Init ((mxc_i2c_reva_regs_t*) i2c, masterMode, slaveAddr); + + return MXC_I2C_RevA_Init((mxc_i2c_reva_regs_t *)i2c, masterMode, slaveAddr); } -int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx) +int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t *i2c, unsigned int slaveAddr, int idx) { - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } - if(idx != 0) { + if (idx != 0) { // Multiple slaves are not supported yet return E_NOT_SUPPORTED; } - if(slaveAddr > MXC_F_I2C_SLAVE_ADDR) { + if (slaveAddr > MXC_F_I2C_SLAVE_ADDR) { // Only support addresses up to 10 bits return E_BAD_PARAM; } i2c->slave = 0; - if(slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { + if (slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { // Set for 10bit addressing mode i2c->slave = MXC_F_I2C_SLAVE_EXT_ADDR_EN; } @@ -115,295 +110,295 @@ int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx) return E_NO_ERROR; } -int MXC_I2C_Shutdown(mxc_i2c_regs_t* i2c) +int MXC_I2C_Shutdown(mxc_i2c_regs_t *i2c) { // Configure GPIO for I2C if (i2c == MXC_I2C0) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0); MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0); - } - else if (i2c == MXC_I2C1) { + } else if (i2c == MXC_I2C1) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1); - } - else if (i2c == MXC_I2C2) { + } else if (i2c == MXC_I2C2) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C2); MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2); - } - else { + } else { return E_NO_DEVICE; } - + return E_NO_ERROR; } -int MXC_I2C_Reset (mxc_i2c_regs_t* i2c) +int MXC_I2C_Reset(mxc_i2c_regs_t *i2c) { // Configure GPIO for I2C - if(i2c == MXC_I2C0) { + if (i2c == MXC_I2C0) { MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0); - } - else if(i2c == MXC_I2C1) { + } else if (i2c == MXC_I2C1) { MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1); - } - else if(i2c == MXC_I2C2) { + } else if (i2c == MXC_I2C2) { MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2); - } - else { + } else { return E_NO_DEVICE; } - - return E_NO_ERROR; + + return E_NO_ERROR; } -int MXC_I2C_SetFrequency(mxc_i2c_regs_t* i2c, unsigned int hz) +int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz) { // ME13 doesn't support high speed more if (hz > MXC_I2C_FASTPLUS_SPEED) { return E_NOT_SUPPORTED; } - - return MXC_I2C_RevA_SetFrequency ((mxc_i2c_reva_regs_t*) i2c, hz); + + return MXC_I2C_RevA_SetFrequency((mxc_i2c_reva_regs_t *)i2c, hz); } -unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetFrequency ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetFrequency((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t* i2c) +int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_ReadyForSleep ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_ReadyForSleep((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_SetClockStretching(mxc_i2c_regs_t* i2c, int enable) +int MXC_I2C_SetClockStretching(mxc_i2c_regs_t *i2c, int enable) { - return MXC_I2C_RevA_SetClockStretching ((mxc_i2c_reva_regs_t*) i2c, enable); + return MXC_I2C_RevA_SetClockStretching((mxc_i2c_reva_regs_t *)i2c, enable); } -int MXC_I2C_GetClockStretching(mxc_i2c_regs_t* i2c) +int MXC_I2C_GetClockStretching(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetClockStretching ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetClockStretching((mxc_i2c_reva_regs_t *)i2c); } /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ -int MXC_I2C_Start(mxc_i2c_regs_t* i2c) +int MXC_I2C_Start(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_Start ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_Start((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_Stop(mxc_i2c_regs_t* i2c) +int MXC_I2C_Stop(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_Stop ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_Stop((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_WriteByte(mxc_i2c_regs_t* i2c, unsigned char byte) +int MXC_I2C_WriteByte(mxc_i2c_regs_t *i2c, unsigned char byte) { - return MXC_I2C_RevA_WriteByte ((mxc_i2c_reva_regs_t*) i2c, byte); + return MXC_I2C_RevA_WriteByte((mxc_i2c_reva_regs_t *)i2c, byte); } -int MXC_I2C_ReadByte(mxc_i2c_regs_t* i2c, unsigned char* byte, int ack) +int MXC_I2C_ReadByte(mxc_i2c_regs_t *i2c, unsigned char *byte, int ack) { - return MXC_I2C_RevA_ReadByte ((mxc_i2c_reva_regs_t*) i2c, byte, ack); + return MXC_I2C_RevA_ReadByte((mxc_i2c_reva_regs_t *)i2c, byte, ack); } - // return MXC_I2C_RevA_ReadByteInteractive ((mxc_i2c_reva_regs_t*) i2c, byte, (mxc_i2c_reva_getAck_t) getAck); +// return MXC_I2C_RevA_ReadByteInteractive ((mxc_i2c_reva_regs_t*) i2c, byte, (mxc_i2c_reva_getAck_t) getAck); // } -int MXC_I2C_Write(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len) +int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len) { - return MXC_I2C_RevA_Write ((mxc_i2c_reva_regs_t*) i2c, bytes, len); + return MXC_I2C_RevA_Write((mxc_i2c_reva_regs_t *)i2c, bytes, len); } -int MXC_I2C_Read(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack) +int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack) { - return MXC_I2C_RevA_Read ((mxc_i2c_reva_regs_t*) i2c, bytes, len, ack); + return MXC_I2C_RevA_Read((mxc_i2c_reva_regs_t *)i2c, bytes, len, ack); } -int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len) { - return MXC_I2C_RevA_ReadRXFIFO ((mxc_i2c_reva_regs_t*) i2c, bytes, len); + return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); } -int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) +int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback) { uint8_t i2cNum; mxc_dma_config_t config; - + i2cNum = MXC_I2C_GET_IDX(i2c); - + switch (i2cNum) { case 0: config.reqsel = MXC_DMA_REQUEST_I2C0RX; break; - + case 1: config.reqsel = MXC_DMA_REQUEST_I2C1RX; break; - + default: return E_BAD_PARAM; } - - return MXC_I2C_RevA_ReadRXFIFODMA ((mxc_i2c_reva_regs_t*) i2c, bytes, len, callback, config, MXC_DMA); + + return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, callback, config, + MXC_DMA); } -int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t* i2c) +int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetRXFIFOAvailable ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetRXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len) { - return MXC_I2C_RevA_WriteTXFIFO ((mxc_i2c_reva_regs_t*) i2c, bytes, len); + return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); } -int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) +int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback) { uint8_t i2cNum; mxc_dma_config_t config; - + i2cNum = MXC_I2C_GET_IDX(i2c); - + switch (i2cNum) { case 0: config.reqsel = MXC_DMA_REQUEST_I2C0TX; break; - + case 1: config.reqsel = MXC_DMA_REQUEST_I2C1TX; break; - + default: return E_BAD_PARAM; } - return MXC_I2C_RevA_WriteTXFIFODMA ((mxc_i2c_reva_regs_t*) i2c, bytes, len, callback, config, MXC_DMA); + return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, callback, config, + MXC_DMA); } -int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t* i2c) +int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetTXFIFOAvailable ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetTXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t* i2c) +void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_ClearRXFIFO ((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_ClearRXFIFO((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t* i2c) +void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_ClearTXFIFO ((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_ClearTXFIFO((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_GetFlags(mxc_i2c_regs_t* i2c, unsigned int* flags0, unsigned int* flags1) +int MXC_I2C_GetFlags(mxc_i2c_regs_t *i2c, unsigned int *flags0, unsigned int *flags1) { - return MXC_I2C_RevA_GetFlags ((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + return MXC_I2C_RevA_GetFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_ClearFlags(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_ClearFlags(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) { - MXC_I2C_RevA_ClearFlags ((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + MXC_I2C_RevA_ClearFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_EnableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_EnableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) { - MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_DisableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_DisableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) { - MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c) +void MXC_I2C_EnablePreload(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c) +void MXC_I2C_DisablePreload(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c) +void MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_EnableGeneralCall ((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_EnableGeneralCall((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c) +void MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_DisableGeneralCall ((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_DisableGeneralCall((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout) +void MXC_I2C_SetTimeout(mxc_i2c_regs_t *i2c, unsigned int timeout) { - MXC_I2C_RevA_SetTimeout ((mxc_i2c_reva_regs_t*) i2c, timeout); + MXC_I2C_RevA_SetTimeout((mxc_i2c_reva_regs_t *)i2c, timeout); } -unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetTimeout(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetTimeout ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetTimeout((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_Recover(mxc_i2c_regs_t* i2c, unsigned int retries) +int MXC_I2C_Recover(mxc_i2c_regs_t *i2c, unsigned int retries) { - return MXC_I2C_RevA_Recover ((mxc_i2c_reva_regs_t*) i2c, retries); + return MXC_I2C_RevA_Recover((mxc_i2c_reva_regs_t *)i2c, retries); } /* ************************************************************************* */ /* Transaction level functions */ /* ************************************************************************* */ -int MXC_I2C_MasterTransaction(mxc_i2c_req_t* req) +int MXC_I2C_MasterTransaction(mxc_i2c_req_t *req) { - return MXC_I2C_RevA_MasterTransaction ((mxc_i2c_reva_req_t*) req); + return MXC_I2C_RevA_MasterTransaction((mxc_i2c_reva_req_t *)req); } -int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t* req) +int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t *req) { - return MXC_I2C_RevA_MasterTransactionAsync ((mxc_i2c_reva_req_t*) req); + return MXC_I2C_RevA_MasterTransactionAsync((mxc_i2c_reva_req_t *)req); } -int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t* req) +int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t *req) { - return MXC_I2C_RevA_MasterTransactionDMA ((mxc_i2c_reva_req_t*) req, MXC_DMA); + return MXC_I2C_RevA_MasterTransactionDMA((mxc_i2c_reva_req_t *)req, MXC_DMA); } -int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback) +int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) { - return MXC_I2C_RevA_SlaveTransaction ((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); + return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t *)i2c, + (mxc_i2c_reva_slave_handler_t)callback, interruptCheck); } -int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback) +int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) { - return MXC_I2C_RevA_SlaveTransactionAsync ((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); + return MXC_I2C_RevA_SlaveTransactionAsync( + (mxc_i2c_reva_regs_t *)i2c, (mxc_i2c_reva_slave_handler_t)callback, interruptCheck); } -int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) { - return MXC_I2C_RevA_SetRXThreshold ((mxc_i2c_reva_regs_t*) i2c, numBytes); + return MXC_I2C_RevA_SetRXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes); } -unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetRXThreshold ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetRXThreshold((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) { - return MXC_I2C_RevA_SetTXThreshold ((mxc_i2c_reva_regs_t*) i2c, numBytes); + return MXC_I2C_RevA_SetTXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes); } -unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetTXThreshold ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_AsyncHandler(mxc_i2c_regs_t* i2c) +void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_AsyncHandler ((mxc_i2c_reva_regs_t*) i2c, interruptCheck); + MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t *)i2c, interruptCheck); } void MXC_I2C_DMACallback(int ch, int error) diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c index 287027ba31e..572ca6f0cb2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c @@ -47,99 +47,100 @@ /* **** Variable Declaration **** */ typedef struct { mxc_i2c_reva_req_t *req; - int master; // 1 for Master, 0 for slave - int channelTx; // DMA channel for TX transaction - int channelRx; // DMA channel for RX transaction - volatile int writeDone; // Write done flag - volatile int readDone; // Flag done flag + int master; // 1 for Master, 0 for slave + int channelTx; // DMA channel for TX transaction + int channelRx; // DMA channel for RX transaction + volatile int writeDone; // Write done flag + volatile int readDone; // Flag done flag } mxc_i2c_reva_req_state_t; static mxc_i2c_reva_req_state_t states[MXC_I2C_INSTANCES]; -void* AsyncRequests[MXC_I2C_INSTANCES]; -unsigned int AsyncWritten[MXC_I2C_INSTANCES]; -unsigned int AsyncRead[MXC_I2C_INSTANCES]; +void *AsyncRequests[MXC_I2C_INSTANCES]; +unsigned int AsyncWritten[MXC_I2C_INSTANCES]; +unsigned int AsyncRead[MXC_I2C_INSTANCES]; /* **** Function Prototypes **** */ -void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal); -void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_MasterAsyncHandler (int i2cNum); -int MXC_I2C_RevA_DMAHandler (mxc_i2c_reva_req_t* req); -unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); +void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal); +void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); +int MXC_I2C_RevA_DMAHandler(mxc_i2c_reva_req_t *req); +unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + unsigned int interruptEnables, int *retVal); /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int slaveAddr) -{ +int MXC_I2C_RevA_Init(mxc_i2c_reva_regs_t *i2c, int masterMode, unsigned int slaveAddr) +{ int err; - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } - if ((err = MXC_I2C_Recover ((mxc_i2c_regs_t*) i2c, 16)) != E_NO_ERROR) { + if ((err = MXC_I2C_Recover((mxc_i2c_regs_t *)i2c, 16)) != E_NO_ERROR) { return err; } - + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_EN; - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); // Set the thresholds here and allow the user to change them as needed - MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 2); // set TX threshold to 2 bytes - MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 6); // set RX threshold to 6 bytes - + MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 2); // set TX threshold to 2 bytes + MXC_I2C_SetRXThreshold((mxc_i2c_regs_t *)i2c, 6); // set RX threshold to 6 bytes + if (!masterMode) { - MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t*) i2c, slaveAddr, 0); - states[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)].master = 0; - } - else { + MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t *)i2c, slaveAddr, 0); + states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 0; + } else { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_MST_MODE; - states[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)].master = 1; + states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 1; } return E_NO_ERROR; } -int MXC_I2C_RevA_SetSlaveAddr (mxc_i2c_reva_regs_t* i2c, unsigned int slaveAddr, int idx) +int MXC_I2C_RevA_SetSlaveAddr(mxc_i2c_reva_regs_t *i2c, unsigned int slaveAddr, int idx) { if (i2c == NULL) { return E_NULL_PTR; } - + if (idx != 0) { // Multiple slaves are not supported yet return E_NOT_SUPPORTED; } - + if (slaveAddr > MXC_F_I2C_REVA_SLAVE_ADDR) { // Only support addresses up to 10 bits return E_BAD_PARAM; } - + i2c->slave = 0; - + if (slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { // Set for 10bit addressing mode i2c->slave = MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN; } - + i2c->slave |= slaveAddr; - + return E_NO_ERROR; } -int MXC_I2C_RevA_Shutdown (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_Shutdown(mxc_i2c_reva_regs_t *i2c) { return E_NOT_SUPPORTED; } -int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz) +int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz) { unsigned int ticksTotal, hiClks, lowClks; - + if (i2c == NULL) { return E_NULL_PTR; } @@ -147,161 +148,159 @@ int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz) if (hz > MXC_I2C_REVA_FASTPLUS_SPEED) { // We're going to enable high speed int hsLowClks, hsHiClks; - + // Calculate the period of SCL and set up 33% duty cycle ticksTotal = PeripheralClock / hz; hsLowClks = (ticksTotal * 2) / 3 - 1; hsHiClks = ticksTotal / 3 - 1; - + // For rounding errors, adjust by 1 clock tick if (ticksTotal % 1) { hsHiClks++; } - + // If we're too slow for high speed, bail out if ((hsHiClks > 0xF) || (hsLowClks > 0xF)) { return E_BAD_PARAM; } - + hz = MXC_I2C_REVA_FAST_SPEED; // High speed preambles will be sent at 400kHz } - + // Calculate the period of SCL, 50% duty cycle ticksTotal = PeripheralClock / hz; hiClks = (ticksTotal >> 1) - 1; lowClks = (ticksTotal >> 1) - 1; - + // Adjust for rounding errors if (ticksTotal % 1) { hiClks++; } - + // Check for maximum/minimum supported speeds - if ( (hiClks > MXC_F_I2C_REVA_CLKHI_HI) || (lowClks == 0)) { + if ((hiClks > MXC_F_I2C_REVA_CLKHI_HI) || (lowClks == 0)) { return E_BAD_PARAM; } - + i2c->clklo = lowClks & MXC_F_I2C_REVA_CLKLO_LO; i2c->clkhi = hiClks & MXC_F_I2C_REVA_CLKHI_HI; - + // Return the actual speed set, since it won't be exactly what's requested - return MXC_I2C_GetFrequency ((mxc_i2c_regs_t*) i2c); + return MXC_I2C_GetFrequency((mxc_i2c_regs_t *)i2c); } -unsigned int MXC_I2C_RevA_GetFrequency (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetFrequency(mxc_i2c_reva_regs_t *i2c) { unsigned int sclCycles = 0; - + // Calculate the speed based on what we've written into registers sclCycles = (i2c->clklo & MXC_F_I2C_REVA_CLKLO_LO) + (i2c->clkhi & MXC_F_I2C_REVA_CLKHI_HI); - + return PeripheralClock / sclCycles; } -int MXC_I2C_RevA_ReadyForSleep (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_ReadyForSleep(mxc_i2c_reva_regs_t *i2c) { - if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } - - if (AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] != NULL) { + + if (AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] != NULL) { return E_BUSY; } - + return E_NO_ERROR; } -int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable) +int MXC_I2C_RevA_SetClockStretching(mxc_i2c_reva_regs_t *i2c, int enable) { if (i2c == NULL) { return E_NULL_PTR; } - + if (enable) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; - } - else { + } else { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; } - + return E_NO_ERROR; } -int MXC_I2C_RevA_GetClockStretching (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_GetClockStretching(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } - return ! ( (i2c->ctrl & MXC_F_I2C_REVA_CTRL_CLKSTR_DIS) >> MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS); + return !((i2c->ctrl & MXC_F_I2C_REVA_CTRL_CLKSTR_DIS) >> MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS); } /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_Start(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } - + // If we have an incomplete transfer, we need to do a restart if (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_START) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; // No check for start generation } - + return E_NO_ERROR; } -int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_Stop(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; - - while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP); - + + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP) {} + return E_NO_ERROR; } -int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte) +int MXC_I2C_RevA_WriteByte(mxc_i2c_reva_regs_t *i2c, unsigned char byte) { if (i2c == NULL) { return E_NULL_PTR; } - + if (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)) { return E_OVERFLOW; } - + // I'm depending on an interrupt flag here // This might cause issues with the transaction level functions to come - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); i2c->fifo = byte; - - while (! (i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)); - + + while (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)) {} + return i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DATA_ERR; } -int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ack) +int MXC_I2C_RevA_ReadByte(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, int ack) { if ((i2c == NULL) || (byte == NULL)) { return E_NULL_PTR; } - if (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { + if (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM) { return E_UNDERFLOW; } - - *byte = (uint8_t) (i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); - if(ack) { + *byte = (uint8_t)(i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); + + if (ack) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK; } else { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_IRXM_ACK; @@ -310,290 +309,293 @@ int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ac return E_NO_ERROR; } -int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck) +int MXC_I2C_RevA_ReadByteInteractive(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, + mxc_i2c_reva_getAck_t getAck) { if ((i2c == NULL) || (byte == NULL)) { return E_NULL_PTR; } - if (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { + if (!(i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { return E_UNDERFLOW; } - - *byte = (uint8_t) (i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); - + + *byte = (uint8_t)(i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); + if (getAck == NULL) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; + } else { + i2c->ctrl |= (!!getAck((mxc_i2c_reva_regs_t *)i2c, *byte)) + << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; } - else { - i2c->ctrl |= (!!getAck ((mxc_i2c_reva_regs_t*) i2c, *byte)) << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; - } - + return E_NO_ERROR; } -int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len) +int MXC_I2C_RevA_Write(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len) { int notAcked = 0; unsigned written = 0; - + if (i2c == NULL) { return E_NULL_PTR; } - + if ((bytes == NULL) || (len == NULL)) { return E_NULL_PTR; } - + for (; written < *len; written++) { - int retVal = MXC_I2C_WriteByte ((mxc_i2c_regs_t*) i2c, bytes[written]); - + int retVal = MXC_I2C_WriteByte((mxc_i2c_regs_t *)i2c, bytes[written]); + if (retVal >= 0) { notAcked += retVal; - } - else { + } else { *len = written; return retVal; } } - + *len = written; notAcked = (notAcked > 0) ? 1 : 0; return notAcked; } -int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack) +int MXC_I2C_RevA_Read(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack) { unsigned read = 0; - + if (i2c == NULL) { return E_NULL_PTR; } - + if ((bytes == NULL) || (len == NULL)) { return E_NULL_PTR; } - for (; read < *len-1; read++) { - int retVal = MXC_I2C_ReadByte ((mxc_i2c_regs_t*) i2c, & (bytes[read]), 1); - + for (; read < *len - 1; read++) { + int retVal = MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), 1); + if (retVal != E_NO_ERROR) { *len = read; return retVal; } } - + read++; *len = read; - return MXC_I2C_ReadByte ((mxc_i2c_regs_t*) i2c, & (bytes[read]), ack); + return MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), ack); } -int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_RevA_ReadRXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len) { unsigned read = 0; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - - while ( (len > read) && (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM))) { + + while ((len > read) && (!(i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM))) { bytes[read++] = i2c->fifo; } - + return read; } -int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ - mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) +int MXC_I2C_RevA_ReadRXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma) { uint8_t i2cNum; uint8_t channel; mxc_dma_srcdst_t srcdst; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); - - #if TARGET_NUM == 32665 + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + +#if TARGET_NUM == 32665 channel = MXC_DMA_AcquireChannel(dma); - #else +#else channel = MXC_DMA_AcquireChannel(); - #endif - +#endif + config.ch = channel; - + config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - + config.srcinc_en = 0; config.dstinc_en = 1; - + srcdst.ch = channel; srcdst.dest = bytes; srcdst.len = len; - + states[i2cNum].channelRx = channel; MXC_DMA_ConfigChannel(config, srcdst); - + if (states[i2cNum].master) { MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); - } - - else { + } else { MXC_DMA_SetCallback(channel, NULL); } - - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); + + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].cfg |= MXC_F_DMA_CFG_CTZIEN; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); i2c->dma |= MXC_F_I2C_REVA_DMA_RX_EN; - + return E_NO_ERROR; } -int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c) -{ - if(i2c == NULL) { +int MXC_I2C_RevA_GetRXFIFOAvailable(mxc_i2c_reva_regs_t *i2c) +{ + if (i2c == NULL) { return E_NULL_PTR; } - + return (i2c->rxctrl1 & MXC_F_I2C_REVA_RXCTRL1_LVL) >> MXC_F_I2C_REVA_RXCTRL1_LVL_POS; } -int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_RevA_WriteTXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len) { unsigned written = 0; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - while ( (len > written) && (! (i2c->status & MXC_F_I2C_REVA_STATUS_TX_FULL))) { + while ((len > written) && (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_FULL))) { i2c->fifo = bytes[written++]; } - + return written; } -int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ - mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) +int MXC_I2C_RevA_WriteTXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma) { uint8_t i2cNum; uint8_t channel; mxc_dma_srcdst_t srcdst; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*)i2c); - + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; - - #if TARGET_NUM == 32665 + +#if TARGET_NUM == 32665 channel = MXC_DMA_AcquireChannel(dma); - #else +#else channel = MXC_DMA_AcquireChannel(); - #endif - +#endif + config.ch = channel; - + config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - + config.srcinc_en = 1; config.dstinc_en = 0; - + srcdst.ch = channel; srcdst.source = bytes; srcdst.len = len; - + states[i2cNum].channelTx = channel; MXC_DMA_ConfigChannel(config, srcdst); - + if (states[i2cNum].master) { MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); - } - else { + } else { MXC_DMA_SetCallback(channel, NULL); } - - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); + + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); // MXC_DMA->ch[channel].cfg |= MXC_F_DMA_CFG_CTZIEN; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); i2c->dma |= MXC_F_I2C_REVA_DMA_TX_EN; - + return E_NO_ERROR; } -int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_GetTXFIFOAvailable(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } - - int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; - return txFIFOlen - ( (i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS); + + int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> + MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; + return txFIFOlen - + ((i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS); } -void MXC_I2C_RevA_ClearRXFIFO (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c) { i2c->rxctrl0 |= MXC_F_I2C_REVA_RXCTRL0_FLUSH; - - while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH); + + while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH) {} } -void MXC_I2C_RevA_ClearTXFIFO (mxc_i2c_reva_regs_t* i2c) -{ +void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c) +{ i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_FLUSH; - - while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH); + + while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH) {} } -int MXC_I2C_RevA_GetFlags (mxc_i2c_reva_regs_t* i2c, unsigned int *flags0, unsigned int *flags1) +int MXC_I2C_RevA_GetFlags(mxc_i2c_reva_regs_t *i2c, unsigned int *flags0, unsigned int *flags1) { if (i2c == NULL) { return E_NULL_PTR; } - + if ((flags0 == NULL) || (flags1 == NULL)) { return E_BAD_PARAM; } - + *flags0 = i2c->intfl0; *flags1 = i2c->intfl1; - + return E_NO_ERROR; } -void MXC_I2C_RevA_ClearFlags (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_RevA_ClearFlags(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1) { i2c->intfl0 = flags0; i2c->intfl1 = flags1; } -void MXC_I2C_RevA_EnableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_RevA_EnableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1) { i2c->inten0 |= flags0; i2c->inten1 |= flags1; } -void MXC_I2C_RevA_DisableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_RevA_DisableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1) { i2c->inten0 &= ~flags0; i2c->inten1 &= ~flags1; } -int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries) +int MXC_I2C_RevA_Recover(mxc_i2c_reva_regs_t *i2c, unsigned int retries) { int err; unsigned int i; - - if(i2c == NULL) { + + if (i2c == NULL) { return E_NULL_PTR; } @@ -602,91 +604,91 @@ int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries) i2c->ctrl |= MXC_F_I2C_REVA_CTRL_EN; int swBit = i2c->ctrl & MXC_F_I2C_REVA_CTRL_BB_MODE; - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } i2c->ctrl |= MXC_F_I2C_REVA_CTRL_BB_MODE; - + // Follow the procedure detailed in the header file // Delay 10uS between each step to give the line/slaves time to react for (i = 0; i < retries; i++) { - MXC_Delay (10); + MXC_Delay(10); i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SCL_OUT; - + MXC_Delay(10); - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SCL) { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; continue; // Give up and try again } - - MXC_Delay (10); + + MXC_Delay(10); i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SDA_OUT; - + MXC_Delay(10); - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA) { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; continue; // Give up and try again } - - MXC_Delay (10); + + MXC_Delay(10); i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SDA_OUT; - + MXC_Delay(10); - - if (! (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA)) { + + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA)) { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; continue; // Give up and try again } - - MXC_Delay (10); + + MXC_Delay(10); i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT; - + MXC_Delay(10); - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SCL) { err = E_NO_ERROR; // We have control break; } } - + if (swBit == 0) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_BB_MODE; } i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_EN; - + return err; } -void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t *i2c) { i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE; } -void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t *i2c) { i2c->txctrl0 &= ~MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE; } -void MXC_I2C_RevA_EnableGeneralCall (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_EnableGeneralCall(mxc_i2c_reva_regs_t *i2c) { - i2c->txctrl0 &= ~MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_GC_ADDR_EN; } -void MXC_I2C_RevA_DisableGeneralCall (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_DisableGeneralCall(mxc_i2c_reva_regs_t *i2c) { - i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_GC_ADDR_EN; } -void MXC_I2C_RevA_SetTimeout (mxc_i2c_reva_regs_t* i2c, unsigned int timeout) +void MXC_I2C_RevA_SetTimeout(mxc_i2c_reva_regs_t *i2c, unsigned int timeout) { i2c->timeout |= (timeout & 0xFFFF); } -unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetTimeout(mxc_i2c_reva_regs_t *i2c) { return (i2c->timeout & 0xFFFF); } @@ -695,24 +697,24 @@ unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c) /* Transaction level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req) +int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req) { - mxc_i2c_reva_regs_t* i2c = req->i2c; // Save off pointer for faster access + mxc_i2c_reva_regs_t *i2c = req->i2c; // Save off pointer for faster access unsigned int written = 0; unsigned int read = 0; - + if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { return E_NOT_SUPPORTED; } - - if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } - + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { return E_BAD_STATE; } - + // if(!read | write) // Start // send addr w/ write bit @@ -728,288 +730,309 @@ int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req) // read rx_len bytes acking all // stop or restart // return good or error - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); i2c->inten0 = 0; i2c->inten1 = 0; - + if ((req->rx_len == 0) || (req->tx_len != 0)) { // Load the slave address with write bit set i2c->fifo = (req->addr << 1) & ~0x1; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; } - + while (req->tx_len > written) { if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { - written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); + written += MXC_I2C_WriteTXFIFO((mxc_i2c_regs_t *)i2c, &req->tx_buf[written], + req->tx_len - written); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; } - + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { req->tx_len = written; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); + MXC_I2C_Stop((mxc_i2c_regs_t *)i2c); return E_COMM_ERR; } } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0); - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, + MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0); + if (req->rx_len != 0) { if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; - } - else { + } else { i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read } - - MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed - - while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); - - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + + MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed + + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART) {} + + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. } - + while (req->rx_len > read) { if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { - read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); + read += + MXC_I2C_ReadRXFIFO((mxc_i2c_regs_t *)i2c, &req->rx_buf[read], req->rx_len - read); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; } - + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { req->rx_len = read; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); + MXC_I2C_Stop((mxc_i2c_regs_t *)i2c); return E_COMM_ERR; } - - if ( (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { - if ( (req->rx_len-read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + + if ((i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { + if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; - } - else { + } else { i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read } - + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. } } - + if (req->restart) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; + + while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)) {} + // Wait for Transaction to finish } - - while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)); // Wait for Transaction to finish - while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)); // Wait for Transaction to finish - + + while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)) {} + // Wait for Transaction to finish + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_STOP; - + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { return E_COMM_ERR; } - + return E_NO_ERROR; } -int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req) +int MXC_I2C_RevA_MasterTransactionAsync(mxc_i2c_reva_req_t *req) { - int i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*)(req->i2c)); - mxc_i2c_reva_regs_t* i2c = req->i2c; - + int i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)(req->i2c)); + mxc_i2c_reva_regs_t *i2c = req->i2c; + if (i2cNum < 0) { return E_BAD_PARAM; } - + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { return E_BAD_STATE; } - + if (AsyncRequests[i2cNum] == NULL) { if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { return E_NOT_SUPPORTED; } - - AsyncRequests[i2cNum] = (void*) req; + + AsyncRequests[i2cNum] = (void *)req; AsyncWritten[i2cNum] = 0; AsyncRead[i2cNum] = 0; - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - - if ((req->rx_len == 0) || (req->tx_len != 0)) { - i2c->fifo = (req->addr << 1) & ~0x1; // Load the slave address with write bit set - i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + + i2c->inten0 = MXC_I2C_REVA_ERROR; + + if (req->tx_len) { + i2c->fifo = (req->addr << 1) & ~0x1; // Load the slave address with write bit set + } else if (req->rx_len) { + i2c->fifo = (req->addr << 1) | 0x1; // Load the slave address with read bit set + + /* Set the number of bytes to read */ + if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + i2c->rxctrl1 = 0; + } else { + i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read + } + + /* Enable RX Threshold interrupt for when the FIFO is full */ + i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); + } else { + /* Must have tx_len and/or rx_len */ + return E_BAD_PARAM; } - - i2c->inten0 = MXC_I2C_REVA_ERROR | MXC_F_I2C_REVA_INTEN0_TX_THD; + + MXC_I2C_Start((mxc_i2c_regs_t *)i2c); + + /* Fill the FIFO as nessary */ + MXC_I2C_RevA_MasterAsyncHandler(i2cNum); + return E_NO_ERROR; - } - else { + } else { return E_BUSY; } } -int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t* dma) +int MXC_I2C_RevA_MasterTransactionDMA(mxc_i2c_reva_req_t *req, mxc_dma_regs_t *dma) { int i2cNum; - - mxc_i2c_reva_regs_t* i2c = req->i2c; // Save off pointer for faster access - i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); + + mxc_i2c_reva_regs_t *i2c = req->i2c; // Save off pointer for faster access + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { return E_NOT_SUPPORTED; } - + if (i2cNum < 0) { return E_BAD_PARAM; } - + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { return E_BAD_STATE; } - + if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { return E_BAD_PARAM; } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - - MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 2); - MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 1); - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + + MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 2); + MXC_I2C_SetRXThreshold((mxc_i2c_regs_t *)i2c, 1); + states[i2cNum].req = req; - + states[i2cNum].channelTx = 0xFF; states[i2cNum].channelRx = 0xFF; - - #if TARGET_NUM == 32665 + +#if TARGET_NUM == 32665 MXC_DMA_Init(dma); - #else +#else MXC_DMA_Init(); - #endif - +#endif + //tx if ((req->tx_buf != NULL) && !(states[i2cNum].writeDone)) { - i2c->fifo = ((req->addr) << 1) & ~0x1; // Load the slave address with write bit set - - #if TARGET_NUM == 32665 - MXC_I2C_WriteTXFIFODMA ((mxc_i2c_regs_t*) i2c, req->tx_buf, req->tx_len, NULL, dma); - #else - MXC_I2C_WriteTXFIFODMA ((mxc_i2c_regs_t*) i2c, req->tx_buf, req->tx_len, NULL); - #endif - } - else { + i2c->fifo = ((req->addr) << 1) & ~0x1; // Load the slave address with write bit set + +#if TARGET_NUM == 32665 + MXC_I2C_WriteTXFIFODMA((mxc_i2c_regs_t *)i2c, req->tx_buf, req->tx_len, NULL, dma); +#else + MXC_I2C_WriteTXFIFODMA((mxc_i2c_regs_t *)i2c, req->tx_buf, req->tx_len, NULL); +#endif + } else { states[i2cNum].writeDone = 1; } - + if (req->rx_buf != NULL) { - while(states[i2cNum].writeDone != 1); //Ensure DMA transmit has finished before attempting to receive + while (states[i2cNum].writeDone != 1) {} + //Ensure DMA transmit has finished before attempting to receive - if ( (states[i2cNum].writeDone) && (!states[i2cNum].readDone)) { + if ((states[i2cNum].writeDone) && (!states[i2cNum].readDone)) { if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; - } - else { + } else { i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read } - MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed - - while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); - - i2c->fifo = ((req->addr) << 1) | 0x1; // Load the slave address with write bit set - - #if TARGET_NUM == 32665 - MXC_I2C_ReadRXFIFODMA ((mxc_i2c_regs_t*) i2c, req->rx_buf, req->rx_len, NULL, dma); - #else - MXC_I2C_ReadRXFIFODMA ((mxc_i2c_regs_t*) i2c, req->rx_buf, req->rx_len, NULL); - #endif + MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed + + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART) {} + + i2c->fifo = ((req->addr) << 1) | 0x1; // Load the slave address with write bit set + +#if TARGET_NUM == 32665 + MXC_I2C_ReadRXFIFODMA((mxc_i2c_regs_t *)i2c, req->rx_buf, req->rx_len, NULL, dma); +#else + MXC_I2C_ReadRXFIFODMA((mxc_i2c_regs_t *)i2c, req->rx_buf, req->rx_len, NULL); +#endif } - } - else { + } else { states[i2cNum].readDone = 1; } - + return E_NO_ERROR; } void MXC_I2C_RevA_DMACallback(int ch, int error) { mxc_i2c_reva_req_t *temp_req; - - for (int i = 0; i < MXC_I2C_INSTANCES; i ++) { + + for (int i = 0; i < MXC_I2C_INSTANCES; i++) { if (states[i].channelTx == ch) { //save the request temp_req = states[i].req; states[i].writeDone = 1; - + if (states[i].readDone) { if (temp_req->restart) { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; } - + MXC_DMA_ReleaseChannel(states[i].channelRx); MXC_DMA_ReleaseChannel(states[i].channelTx); - + // Callback if not NULL if (temp_req->callback != NULL) { temp_req->callback(temp_req, E_NO_ERROR); } } - } - - else if (states[i].channelRx == ch) { + } else if (states[i].channelRx == ch) { //save the request states[i].readDone = 1; temp_req = states[i].req; - + if (states[i].writeDone) { if (temp_req->restart) { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; } - + MXC_DMA_ReleaseChannel(states[i].channelRx); MXC_DMA_ReleaseChannel(states[i].channelTx); - + // Callback if not NULL if (temp_req->callback != NULL) { temp_req->callback(temp_req, E_NO_ERROR); - } + } } } } } -int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) +int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck) { unsigned int interruptEnables = interruptCheck; int retVal = E_NO_ERROR; - - if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { return E_BAD_STATE; } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + // Callback called on // Slave Address Match (distinguish read/write) // RX Threshold @@ -1026,98 +1049,110 @@ int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_ // I2C_EVT_TRANS_COMP // I2C_EVT_UNDERFLOW // I2C_EVT_OVERFLOW - + while (interruptEnables > 0) { interruptEnables = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, interruptEnables, &retVal); } - + return retVal; } -int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) +int MXC_I2C_RevA_SlaveTransactionAsync(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck) { - int i2cnum = MXC_I2C_GET_IDX((mxc_i2c_regs_t*) i2c); - + int i2cnum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + if (i2cnum < 0) { return E_BAD_PARAM; } - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { return E_BAD_STATE; } - + if (AsyncRequests[i2cnum] != NULL) { return E_BUSY; } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 1); // set TX threshold to 2 bytes - MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 1); // set RX threshold to 6 bytes - AsyncRequests[i2cnum] = (void *) callback; - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 1); // set TX threshold to 2 bytes + MXC_I2C_SetRXThreshold((mxc_i2c_regs_t *)i2c, 1); // set RX threshold to 6 bytes + AsyncRequests[i2cnum] = (void *)callback; + i2c->inten0 = interruptCheck; - + return E_NO_ERROR; } -int MXC_I2C_RevA_SetRXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes) { - unsigned int rxFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS; - + unsigned int rxFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH) >> + MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS; + if (numBytes > rxFIFOlen) { return E_BAD_PARAM; } - - i2c->rxctrl0 = (i2c->rxctrl0 & ~MXC_F_I2C_REVA_RXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS); + + i2c->rxctrl0 = (i2c->rxctrl0 & ~MXC_F_I2C_REVA_RXCTRL0_THD_LVL) | + (numBytes << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS); return E_NO_ERROR; } -unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetRXThreshold(mxc_i2c_reva_regs_t *i2c) { return (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_THD_LVL) >> MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS; } -int MXC_I2C_RevA_SetTXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes) { - unsigned int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; - + unsigned int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> + MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; + if (numBytes > txFIFOlen) { return E_BAD_PARAM; } - - i2c->txctrl0 = (i2c->txctrl0 & ~MXC_F_I2C_REVA_TXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS); + + i2c->txctrl0 = (i2c->txctrl0 & ~MXC_F_I2C_REVA_TXCTRL0_THD_LVL) | + (numBytes << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS); return E_NO_ERROR; } -unsigned int MXC_I2C_RevA_GetTXThreshold (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetTXThreshold(mxc_i2c_reva_regs_t *i2c) { return (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_THD_LVL) >> MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS; } -void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal) +void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal) { // Don't need to check for return value as this function is not accessible to user // i2c is already cheked for NULL from where this function is being called - mxc_i2c_reva_req_t* req = (mxc_i2c_reva_req_t*) AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)]; - + mxc_i2c_reva_req_t *req = + (mxc_i2c_reva_req_t *)AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)]; + if (req->callback != NULL) { req->callback(req, retVal); } } -void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c) { + /* Disable and clear interrupts */ i2c->inten0 = 0; i2c->inten1 = 0; - + + i2c->intfl0 = i2c->intfl0; + i2c->intfl1 = i2c->intfl1; + // Don't need to check for return value as this function is not accessible to user // i2c is already cheked for NULL from where this function is being called - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } -void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c) { // Don't need to check for return value as this function is not accessible to user // i2c is already cheked for NULL from where this function is being called @@ -1129,95 +1164,119 @@ void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum) { unsigned int written = AsyncWritten[i2cNum]; unsigned int read = AsyncRead[i2cNum]; - mxc_i2c_reva_regs_t* i2c = (mxc_i2c_reva_regs_t*) MXC_I2C_GET_BASE (i2cNum); - mxc_i2c_reva_req_t* req = (mxc_i2c_reva_req_t*) AsyncRequests[i2cNum]; - + mxc_i2c_reva_regs_t *i2c = (mxc_i2c_reva_regs_t *)MXC_I2C_GET_BASE(i2cNum); + mxc_i2c_reva_req_t *req = (mxc_i2c_reva_req_t *)AsyncRequests[i2cNum]; + + /* Check for errors */ + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { + /* Clear and disable interrupts */ + i2c->intfl0 = i2c->intfl0; + i2c->intfl1 = i2c->intfl1; + i2c->inten0 = 0; + i2c->inten1 = 0; + + MXC_I2C_Stop((mxc_i2c_regs_t *)i2c); + MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR); + MXC_I2C_RevA_AsyncStop(i2c); + + return; + } + + /* Write data to the TX FIFO */ if (req->tx_len > written) { if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { - written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); + written += MXC_I2C_WriteTXFIFO((mxc_i2c_regs_t *)i2c, &req->tx_buf[written], + req->tx_len - written); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; } - - if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { - req->tx_len = written; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); - MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); - MXC_I2C_RevA_AsyncStop (i2c); + + /* Enable the TX Threshold interrupt if we still need to write to the TX FIFO */ + if (written < req->tx_len) { + i2c->inten0 |= MXC_F_I2C_REVA_INTEN0_TX_THD; + } else { + i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_TX_THD); + } + + /* Send a restart if we're reading after writing */ + if ((req->tx_len == written) && (req->rx_len)) { + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; + i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_DONE); } } - + + /* Read data in the RX FIFO */ if (req->rx_len > read) { if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { - read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); + read += + MXC_I2C_ReadRXFIFO((mxc_i2c_regs_t *)i2c, &req->rx_buf[read], req->rx_len - read); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; } - - if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { - req->rx_len = read; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); - MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); - MXC_I2C_RevA_AsyncStop (i2c); - } - - if ( (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { - if ( (req->rx_len-read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { - i2c->rxctrl1 = 0; - } - else { - i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read - } - - i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. - } } - - if ( (req->tx_len == written) && (read == 0)) { - i2c->inten0 &= ~MXC_F_I2C_REVA_INTEN0_TX_THD; - i2c->inten0 |= MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE; - - if ( (req->rx_len) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + + /* Done writing, still reading */ + if ((req->tx_len == written) && (req->rx_len - read) && + (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)) { + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; + + /* First done interrupt after completing writes to the TX FIFO */ + if (read == 0) { + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + } + + /* Set the number of bytes to read */ + if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; + } else { + i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read } - else { - i2c->rxctrl1 = (req->rx_len); // 0 for 256, otherwise number of bytes to read + + /* Enable RX Threshold interrupt for when the FIFO is full */ + if (read < req->rx_len) { + i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); + } else { + i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); } - - MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed - - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. } - - if ( (req->tx_len == written) && (req->rx_len == read)) { - i2c->inten0 &= ~ (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); - + + /* Done reading and writing */ + if ((req->tx_len == written) && (req->rx_len == read)) { + /* Disable and clear interrupts */ + i2c->inten0 = 0; + i2c->inten1 = 0; + i2c->intfl0 = i2c->intfl0; + i2c->intfl1 = i2c->intfl1; + + /* Send a restart or stop at the end of the transaction */ if (req->restart) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; } - + + /* Call the callback */ if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { - MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); - } - else { + MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR); + } else { MXC_I2C_RevA_AsyncCallback(i2c, E_NO_ERROR); } - + + /* Clear the async state */ MXC_I2C_RevA_AsyncStop(i2c); + + } else { + AsyncWritten[i2cNum] = written; + AsyncRead[i2cNum] = read; } - - AsyncWritten[i2cNum] = written; - AsyncRead[i2cNum] = read; } -unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal) +unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + unsigned int interruptEnables, int *retVal) { uint32_t tFlags = i2c->intfl0; *retVal = E_NO_ERROR; - + uint32_t readFlag = i2c->ctrl & MXC_F_I2C_REVA_CTRL_READ; // Callback called on // Slave Address Match (distinguish read/write) @@ -1235,114 +1294,161 @@ unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_r // I2C_EVT_TRANS_COMP // I2C_EVT_UNDERFLOW // I2C_EVT_OVERFLOW - if (!(interruptEnables & (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH| MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { + if (!(interruptEnables & + (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH | + MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { // The STOPERR/STARTERR interrupt that's enabled here could fire before we are addressed // (fires anytime a stop/start is detected out of sequence). if (tFlags & MXC_I2C_REVA_ERROR) { *retVal = E_COMM_ERR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } - + if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV)) { if (tFlags & MXC_F_I2C_REVA_INTFL0_RX_THD) { - callback (i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; } - + if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_RX_OV) { - callback (i2c, MXC_I2C_REVA_EVT_OVERFLOW, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_OVERFLOW, NULL); + } + i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_RX_OV; } } - - if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) { + + if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | + MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) { if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_THD) { - callback (i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; } - + if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_TX_UN) { - callback (i2c, MXC_I2C_REVA_EVT_UNDERFLOW, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_UNDERFLOW, NULL); + } + i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_TX_UN; } - + if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT) { *retVal = E_NO_ERROR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT; interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } } - + if (tFlags & MXC_F_I2C_REVA_INTFL0_STOP) { *retVal = E_NO_ERROR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_STOP; interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } } if (tFlags & MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH) { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; + interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | + MXC_I2C_REVA_ERROR; } - + if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | + MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; } - if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH){ + if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH) { if (readFlag & MXC_F_I2C_REVA_CTRL_READ) { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; - } - else { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | + MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + } else { + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; + interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | + MXC_I2C_REVA_ERROR; } } else if (tFlags & MXC_I2C_REVA_ERROR) { *retVal = E_COMM_ERR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); - MXC_I2C_RevA_ClearFlags(i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + + MXC_I2C_RevA_ClearFlags(i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts MXC_I2C_RevA_ClearTXFIFO(i2c); MXC_I2C_RevA_ClearRXFIFO(i2c); interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } - + return interruptEnables; } -void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptCheck) +void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck) { - int i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); + int i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); int slaveRetVal; - + if (i2cNum < 0) { return; } - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { - MXC_I2C_RevA_MasterAsyncHandler (i2cNum); - } - else { - mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t) AsyncRequests[i2cNum]; - i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler (i2c, callback, i2c->inten0, &slaveRetVal); + MXC_I2C_RevA_MasterAsyncHandler(i2cNum); + } else { + mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t)AsyncRequests[i2cNum]; + i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, i2c->inten0, &slaveRetVal); } } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h index df0e5ba359e..aa41e2c5761 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h @@ -31,8 +31,8 @@ * *************************************************************************** */ -#ifndef _I2C_REVA_H_ -#define _I2C_REVA_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ #include #include @@ -46,33 +46,34 @@ #include "i2c_reva_regs.h" #include "dma.h" - /* **** Definitions **** */ -#define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F -#define MXC_I2C_REVA_STD_MODE 100000 -#define MXC_I2C_REVA_FAST_SPEED 400000 -#define MXC_I2C_REVA_FASTPLUS_SPEED 1000000 -#define MXC_I2C_REVA_HS_MODE 3400000 +#define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F +#define MXC_I2C_REVA_STD_MODE 100000 +#define MXC_I2C_REVA_FAST_SPEED 400000 +#define MXC_I2C_REVA_FASTPLUS_SPEED 1000000 +#define MXC_I2C_REVA_HS_MODE 3400000 -#define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF -#define MXC_I2C_REVA_INTFL1_MASK 0x00000007 +#define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF +#define MXC_I2C_REVA_INTFL1_MASK 0x00000007 -#define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256 +#define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256 -#define MXC_I2C_REVA_ERROR (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | \ - MXC_F_I2C_REVA_INTFL0_DATA_ERR | MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \ - MXC_F_I2C_REVA_INTFL0_STOP_ERR) +#define MXC_I2C_REVA_ERROR \ + (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | \ + MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | MXC_F_I2C_REVA_INTFL0_DATA_ERR | \ + MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \ + MXC_F_I2C_REVA_INTFL0_STOP_ERR) typedef struct _i2c_reva_req_t mxc_i2c_reva_req_t; -typedef int (*mxc_i2c_reva_getAck_t) (mxc_i2c_reva_regs_t* i2c, unsigned char byte); -typedef void (*mxc_i2c_reva_complete_cb_t) (mxc_i2c_reva_req_t* req, int result); -typedef void (*mxc_i2c_reva_dma_complete_cb_t) (int len, int result); +typedef int (*mxc_i2c_reva_getAck_t)(mxc_i2c_reva_regs_t *i2c, unsigned char byte); +typedef void (*mxc_i2c_reva_complete_cb_t)(mxc_i2c_reva_req_t *req, int result); +typedef void (*mxc_i2c_reva_dma_complete_cb_t)(int len, int result); struct _i2c_reva_req_t { - mxc_i2c_reva_regs_t* i2c; + mxc_i2c_reva_regs_t *i2c; unsigned int addr; - unsigned char* tx_buf; + unsigned char *tx_buf; unsigned int tx_len; - unsigned char* rx_buf; + unsigned char *rx_buf; unsigned int rx_len; int restart; mxc_i2c_reva_complete_cb_t callback; @@ -86,74 +87,86 @@ typedef enum { MXC_I2C_REVA_EVT_UNDERFLOW, MXC_I2C_REVA_EVT_OVERFLOW, } mxc_i2c_reva_slave_event_t; -typedef int (*mxc_i2c_reva_slave_handler_t) (mxc_i2c_reva_regs_t* i2c, - mxc_i2c_reva_slave_event_t event, void* data); +typedef int (*mxc_i2c_reva_slave_handler_t)(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_event_t event, void *data); /* **** Variable Declaration **** */ -extern void* AsyncRequests[MXC_I2C_INSTANCES]; +extern void *AsyncRequests[MXC_I2C_INSTANCES]; /* **** Function Prototypes **** */ /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int slaveAddr); -int MXC_I2C_RevA_SetSlaveAddr (mxc_i2c_reva_regs_t* i2c, unsigned int slaveAddr, int idx); -int MXC_I2C_RevA_Shutdown (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz); -unsigned int MXC_I2C_RevA_GetFrequency (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_ReadyForSleep (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable); -int MXC_I2C_RevA_GetClockStretching (mxc_i2c_reva_regs_t* i2c); +int MXC_I2C_RevA_Init(mxc_i2c_reva_regs_t *i2c, int masterMode, unsigned int slaveAddr); +int MXC_I2C_RevA_SetSlaveAddr(mxc_i2c_reva_regs_t *i2c, unsigned int slaveAddr, int idx); +int MXC_I2C_RevA_Shutdown(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz); +unsigned int MXC_I2C_RevA_GetFrequency(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_ReadyForSleep(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_SetClockStretching(mxc_i2c_reva_regs_t *i2c, int enable); +int MXC_I2C_RevA_GetClockStretching(mxc_i2c_reva_regs_t *i2c); /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte); -int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ack); -int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck); -int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len); -int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack); -int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); -int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); -int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); -int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); -int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_ClearRXFIFO (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_ClearTXFIFO (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_GetFlags (mxc_i2c_reva_regs_t* i2c, unsigned int *flags0, unsigned int *flags1); -void MXC_I2C_RevA_ClearFlags (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); -void MXC_I2C_RevA_EnableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); -void MXC_I2C_RevA_DisableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); -void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_EnableGeneralCall (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_DisableGeneralCall (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_SetTimeout (mxc_i2c_reva_regs_t* i2c, unsigned int timeout); -unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries); +int MXC_I2C_RevA_Start(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_Stop(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_WriteByte(mxc_i2c_reva_regs_t *i2c, unsigned char byte); +int MXC_I2C_RevA_ReadByte(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, int ack); +int MXC_I2C_RevA_ReadByteInteractive(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, + mxc_i2c_reva_getAck_t getAck); +int MXC_I2C_RevA_Write(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len); +int MXC_I2C_RevA_Read(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack); +int MXC_I2C_RevA_ReadRXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len); +int MXC_I2C_RevA_ReadRXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma); +int MXC_I2C_RevA_GetRXFIFOAvailable(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_WriteTXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len); +int MXC_I2C_RevA_WriteTXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma); +int MXC_I2C_RevA_GetTXFIFOAvailable(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_GetFlags(mxc_i2c_reva_regs_t *i2c, unsigned int *flags0, unsigned int *flags1); +void MXC_I2C_RevA_ClearFlags(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_EnableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_DisableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_EnableGeneralCall(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_DisableGeneralCall(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_SetTimeout(mxc_i2c_reva_regs_t *i2c, unsigned int timeout); +unsigned int MXC_I2C_RevA_GetTimeout(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_Recover(mxc_i2c_reva_regs_t *i2c, unsigned int retries); /* ************************************************************************* */ /* Transaction level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req); -int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req); -int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t* dma); -int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); -int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); -int MXC_I2C_RevA_SetRXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes); -unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_SetTXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes); -unsigned int MXC_I2C_RevA_GetTXThreshold (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal); -void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_MasterAsyncHandler (int i2cNum); -unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); -void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptCheck); -void MXC_I2C_RevA_DMACallback (int ch, int error); +int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req); +int MXC_I2C_RevA_MasterTransactionAsync(mxc_i2c_reva_req_t *req); +int MXC_I2C_RevA_MasterTransactionDMA(mxc_i2c_reva_req_t *req, mxc_dma_regs_t *dma); +int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck); +int MXC_I2C_RevA_SlaveTransactionAsync(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck); +int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes); +unsigned int MXC_I2C_RevA_GetRXThreshold(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes); +unsigned int MXC_I2C_RevA_GetTXThreshold(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal); +void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); +unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + unsigned int interruptEnables, int *retVal); +void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck); +void MXC_I2C_RevA_DMACallback(int ch, int error); -#endif /* _I2C_REVA_H_ */ \ No newline at end of file +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h index c15d5b4f65e..49a434116ff 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h @@ -37,8 +37,8 @@ * *************************************************************************** */ -#ifndef _I2C_REVA_REGS_H_ -#define _I2C_REVA_REGS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -115,25 +115,25 @@ typedef struct { * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. * @{ */ - #define MXC_R_I2C_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ - #define MXC_R_I2C_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ - #define MXC_R_I2C_REVA_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ - #define MXC_R_I2C_REVA_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ - #define MXC_R_I2C_REVA_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ - #define MXC_R_I2C_REVA_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ - #define MXC_R_I2C_REVA_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ - #define MXC_R_I2C_REVA_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ - #define MXC_R_I2C_REVA_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ - #define MXC_R_I2C_REVA_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ - #define MXC_R_I2C_REVA_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ - #define MXC_R_I2C_REVA_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ - #define MXC_R_I2C_REVA_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ - #define MXC_R_I2C_REVA_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ - #define MXC_R_I2C_REVA_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ - #define MXC_R_I2C_REVA_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ - #define MXC_R_I2C_REVA_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ - #define MXC_R_I2C_REVA_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ - #define MXC_R_I2C_REVA_SLAVE ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: 0x004C */ +#define MXC_R_I2C_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ +#define MXC_R_I2C_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ +#define MXC_R_I2C_REVA_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ +#define MXC_R_I2C_REVA_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ +#define MXC_R_I2C_REVA_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ +#define MXC_R_I2C_REVA_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ +#define MXC_R_I2C_REVA_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ +#define MXC_R_I2C_REVA_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ +#define MXC_R_I2C_REVA_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ +#define MXC_R_I2C_REVA_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ +#define MXC_R_I2C_REVA_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ +#define MXC_R_I2C_REVA_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ +#define MXC_R_I2C_REVA_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ +#define MXC_R_I2C_REVA_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ +#define MXC_R_I2C_REVA_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ +#define MXC_R_I2C_REVA_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ +#define MXC_R_I2C_REVA_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ +#define MXC_R_I2C_REVA_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ +#define MXC_R_I2C_REVA_SLAVE ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: 0x004C */ /**@} end of group i2c_registers */ /** @@ -142,47 +142,47 @@ typedef struct { * @brief Control Register0. * @{ */ - #define MXC_F_I2C_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ - #define MXC_F_I2C_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_I2C_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ - #define MXC_F_I2C_REVA_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ - #define MXC_F_I2C_REVA_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ +#define MXC_F_I2C_REVA_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ +#define MXC_F_I2C_REVA_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ - #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ - #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ +#define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ - #define MXC_F_I2C_REVA_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ - #define MXC_F_I2C_REVA_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ +#define MXC_F_I2C_REVA_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ - #define MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ - #define MXC_F_I2C_REVA_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ +#define MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ +#define MXC_F_I2C_REVA_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ - #define MXC_F_I2C_REVA_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ - #define MXC_F_I2C_REVA_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ +#define MXC_F_I2C_REVA_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ +#define MXC_F_I2C_REVA_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ - #define MXC_F_I2C_REVA_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ - #define MXC_F_I2C_REVA_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ +#define MXC_F_I2C_REVA_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ +#define MXC_F_I2C_REVA_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ - #define MXC_F_I2C_REVA_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ - #define MXC_F_I2C_REVA_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ +#define MXC_F_I2C_REVA_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ +#define MXC_F_I2C_REVA_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ - #define MXC_F_I2C_REVA_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ - #define MXC_F_I2C_REVA_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ +#define MXC_F_I2C_REVA_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ +#define MXC_F_I2C_REVA_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ - #define MXC_F_I2C_REVA_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ - #define MXC_F_I2C_REVA_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ +#define MXC_F_I2C_REVA_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ +#define MXC_F_I2C_REVA_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ - #define MXC_F_I2C_REVA_CTRL_READ_POS 11 /**< CTRL_READ Position */ - #define MXC_F_I2C_REVA_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_READ_POS)) /**< CTRL_READ Mask */ +#define MXC_F_I2C_REVA_CTRL_READ_POS 11 /**< CTRL_READ Position */ +#define MXC_F_I2C_REVA_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_READ_POS)) /**< CTRL_READ Mask */ - #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ - #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ +#define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ +#define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ - #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ - #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ +#define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ +#define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ - #define MXC_F_I2C_REVA_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ - #define MXC_F_I2C_REVA_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ +#define MXC_F_I2C_REVA_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ /**@} end of group I2C_CTRL_Register */ @@ -192,23 +192,23 @@ typedef struct { * @brief Status Register. * @{ */ - #define MXC_F_I2C_REVA_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ - #define MXC_F_I2C_REVA_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ +#define MXC_F_I2C_REVA_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ +#define MXC_F_I2C_REVA_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ - #define MXC_F_I2C_REVA_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ - #define MXC_F_I2C_REVA_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ +#define MXC_F_I2C_REVA_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ +#define MXC_F_I2C_REVA_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ - #define MXC_F_I2C_REVA_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ - #define MXC_F_I2C_REVA_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ +#define MXC_F_I2C_REVA_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ +#define MXC_F_I2C_REVA_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ - #define MXC_F_I2C_REVA_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ - #define MXC_F_I2C_REVA_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ +#define MXC_F_I2C_REVA_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ +#define MXC_F_I2C_REVA_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ - #define MXC_F_I2C_REVA_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ - #define MXC_F_I2C_REVA_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ +#define MXC_F_I2C_REVA_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ +#define MXC_F_I2C_REVA_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ - #define MXC_F_I2C_REVA_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ - #define MXC_F_I2C_REVA_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ +#define MXC_F_I2C_REVA_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ +#define MXC_F_I2C_REVA_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ /**@} end of group I2C_STATUS_Register */ @@ -218,62 +218,62 @@ typedef struct { * @brief Interrupt Status Register. * @{ */ - #define MXC_F_I2C_REVA_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ - #define MXC_F_I2C_REVA_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ +#define MXC_F_I2C_REVA_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ +#define MXC_F_I2C_REVA_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ - #define MXC_F_I2C_REVA_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ - #define MXC_F_I2C_REVA_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ +#define MXC_F_I2C_REVA_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ +#define MXC_F_I2C_REVA_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ - #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ - #define MXC_F_I2C_REVA_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ +#define MXC_F_I2C_REVA_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ +#define MXC_F_I2C_REVA_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ - #define MXC_F_I2C_REVA_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ - #define MXC_F_I2C_REVA_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ +#define MXC_F_I2C_REVA_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ +#define MXC_F_I2C_REVA_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ - #define MXC_F_I2C_REVA_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ - #define MXC_F_I2C_REVA_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ +#define MXC_F_I2C_REVA_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ +#define MXC_F_I2C_REVA_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ - #define MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ - #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ +#define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ +#define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ - #define MXC_F_I2C_REVA_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ - #define MXC_F_I2C_REVA_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ +#define MXC_F_I2C_REVA_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ +#define MXC_F_I2C_REVA_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ - #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ /**@} end of group I2C_INTFL0_Register */ @@ -283,62 +283,62 @@ typedef struct { * @brief Interrupt Enable Register. * @{ */ - #define MXC_F_I2C_REVA_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ - #define MXC_F_I2C_REVA_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ +#define MXC_F_I2C_REVA_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ +#define MXC_F_I2C_REVA_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ - #define MXC_F_I2C_REVA_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ - #define MXC_F_I2C_REVA_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ +#define MXC_F_I2C_REVA_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ +#define MXC_F_I2C_REVA_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ - #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ - #define MXC_F_I2C_REVA_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ +#define MXC_F_I2C_REVA_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ +#define MXC_F_I2C_REVA_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ - #define MXC_F_I2C_REVA_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ - #define MXC_F_I2C_REVA_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ +#define MXC_F_I2C_REVA_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ +#define MXC_F_I2C_REVA_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ - #define MXC_F_I2C_REVA_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ - #define MXC_F_I2C_REVA_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ +#define MXC_F_I2C_REVA_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ +#define MXC_F_I2C_REVA_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ - #define MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ - #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ +#define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ +#define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ - #define MXC_F_I2C_REVA_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ - #define MXC_F_I2C_REVA_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ +#define MXC_F_I2C_REVA_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ +#define MXC_F_I2C_REVA_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ - #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ /**@} end of group I2C_INTEN0_Register */ @@ -348,14 +348,14 @@ typedef struct { * @brief Interrupt Status Register 1. * @{ */ - #define MXC_F_I2C_REVA_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ - #define MXC_F_I2C_REVA_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ +#define MXC_F_I2C_REVA_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ +#define MXC_F_I2C_REVA_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ - #define MXC_F_I2C_REVA_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ - #define MXC_F_I2C_REVA_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ +#define MXC_F_I2C_REVA_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ +#define MXC_F_I2C_REVA_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ - #define MXC_F_I2C_REVA_INTFL1_START_POS 2 /**< INTFL1_START Position */ - #define MXC_F_I2C_REVA_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_START_POS)) /**< INTFL1_START Mask */ +#define MXC_F_I2C_REVA_INTFL1_START_POS 2 /**< INTFL1_START Position */ +#define MXC_F_I2C_REVA_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_START_POS)) /**< INTFL1_START Mask */ /**@} end of group I2C_INTFL1_Register */ @@ -365,14 +365,14 @@ typedef struct { * @brief Interrupt Staus Register 1. * @{ */ - #define MXC_F_I2C_REVA_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ - #define MXC_F_I2C_REVA_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ +#define MXC_F_I2C_REVA_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ +#define MXC_F_I2C_REVA_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ - #define MXC_F_I2C_REVA_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ - #define MXC_F_I2C_REVA_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ +#define MXC_F_I2C_REVA_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ +#define MXC_F_I2C_REVA_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ - #define MXC_F_I2C_REVA_INTEN1_START_POS 2 /**< INTEN1_START Position */ - #define MXC_F_I2C_REVA_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_START_POS)) /**< INTEN1_START Mask */ +#define MXC_F_I2C_REVA_INTEN1_START_POS 2 /**< INTEN1_START Position */ +#define MXC_F_I2C_REVA_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_START_POS)) /**< INTEN1_START Mask */ /**@} end of group I2C_INTEN1_Register */ @@ -382,11 +382,11 @@ typedef struct { * @brief FIFO Configuration Register. * @{ */ - #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ - #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ +#define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ +#define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ - #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ - #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ +#define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ +#define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ /**@} end of group I2C_FIFOLEN_Register */ @@ -396,14 +396,14 @@ typedef struct { * @brief Receive Control Register 0. * @{ */ - #define MXC_F_I2C_REVA_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ - #define MXC_F_I2C_REVA_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ +#define MXC_F_I2C_REVA_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ +#define MXC_F_I2C_REVA_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ - #define MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ - #define MXC_F_I2C_REVA_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ +#define MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ +#define MXC_F_I2C_REVA_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ - #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ - #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ +#define MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ +#define MXC_F_I2C_REVA_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ /**@} end of group I2C_RXCTRL0_Register */ @@ -413,11 +413,11 @@ typedef struct { * @brief Receive Control Register 1. * @{ */ - #define MXC_F_I2C_REVA_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ - #define MXC_F_I2C_REVA_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ +#define MXC_F_I2C_REVA_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ +#define MXC_F_I2C_REVA_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ - #define MXC_F_I2C_REVA_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ - #define MXC_F_I2C_REVA_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ +#define MXC_F_I2C_REVA_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ +#define MXC_F_I2C_REVA_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ /**@} end of group I2C_RXCTRL1_Register */ @@ -427,29 +427,29 @@ typedef struct { * @brief Transmit Control Register 0. * @{ */ - #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ - #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ +#define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ - #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ +#define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ - #define MXC_F_I2C_REVA_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ +#define MXC_F_I2C_REVA_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS 8 /**< TXCTRL0_THD_LVL Position */ - #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS)) /**< TXCTRL0_THD_LVL Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS 8 /**< TXCTRL0_THD_LVL Position */ +#define MXC_F_I2C_REVA_TXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS)) /**< TXCTRL0_THD_LVL Mask */ /**@} end of group I2C_TXCTRL0_Register */ @@ -459,11 +459,11 @@ typedef struct { * @brief Transmit Control Register 1. * @{ */ - #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ - #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ +#define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ +#define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ - #define MXC_F_I2C_REVA_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ - #define MXC_F_I2C_REVA_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ +#define MXC_F_I2C_REVA_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ +#define MXC_F_I2C_REVA_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ /**@} end of group I2C_TXCTRL1_Register */ @@ -473,8 +473,8 @@ typedef struct { * @brief Data Register. * @{ */ - #define MXC_F_I2C_REVA_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ - #define MXC_F_I2C_REVA_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ +#define MXC_F_I2C_REVA_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_I2C_REVA_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ /**@} end of group I2C_FIFO_Register */ @@ -484,17 +484,17 @@ typedef struct { * @brief Master Control Register. * @{ */ - #define MXC_F_I2C_REVA_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ - #define MXC_F_I2C_REVA_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ +#define MXC_F_I2C_REVA_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ - #define MXC_F_I2C_REVA_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ - #define MXC_F_I2C_REVA_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ +#define MXC_F_I2C_REVA_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ - #define MXC_F_I2C_REVA_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ - #define MXC_F_I2C_REVA_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ +#define MXC_F_I2C_REVA_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ - #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ - #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ +#define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ /**@} end of group I2C_MSTCTRL_Register */ @@ -504,8 +504,8 @@ typedef struct { * @brief Clock Low Register. * @{ */ - #define MXC_F_I2C_REVA_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ - #define MXC_F_I2C_REVA_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ +#define MXC_F_I2C_REVA_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ +#define MXC_F_I2C_REVA_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ /**@} end of group I2C_CLKLO_Register */ @@ -515,8 +515,8 @@ typedef struct { * @brief Clock high Register. * @{ */ - #define MXC_F_I2C_REVA_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ - #define MXC_F_I2C_REVA_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ +#define MXC_F_I2C_REVA_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ +#define MXC_F_I2C_REVA_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ /**@} end of group I2C_CLKHI_Register */ @@ -526,11 +526,11 @@ typedef struct { * @brief Clock high Register. * @{ */ - #define MXC_F_I2C_REVA_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ - #define MXC_F_I2C_REVA_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ +#define MXC_F_I2C_REVA_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ +#define MXC_F_I2C_REVA_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ - #define MXC_F_I2C_REVA_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ - #define MXC_F_I2C_REVA_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ +#define MXC_F_I2C_REVA_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ +#define MXC_F_I2C_REVA_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ /**@} end of group I2C_HSCLK_Register */ @@ -540,8 +540,8 @@ typedef struct { * @brief Timeout Register * @{ */ - #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ - #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ +#define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ +#define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ /**@} end of group I2C_TIMEOUT_Register */ @@ -551,11 +551,11 @@ typedef struct { * @brief DMA Register. * @{ */ - #define MXC_F_I2C_REVA_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ - #define MXC_F_I2C_REVA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ +#define MXC_F_I2C_REVA_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ +#define MXC_F_I2C_REVA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ - #define MXC_F_I2C_REVA_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ - #define MXC_F_I2C_REVA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ +#define MXC_F_I2C_REVA_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ +#define MXC_F_I2C_REVA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ /**@} end of group I2C_DMA_Register */ @@ -565,11 +565,11 @@ typedef struct { * @brief Slave Address Register. * @{ */ - #define MXC_F_I2C_REVA_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */ - #define MXC_F_I2C_REVA_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_REVA_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */ +#define MXC_F_I2C_REVA_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */ +#define MXC_F_I2C_REVA_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_REVA_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */ - #define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */ - #define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */ +#define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */ +#define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */ /**@} end of group I2C_SLAVE_Register */ @@ -577,4 +577,5 @@ typedef struct { } #endif -#endif /* _I2C_REGS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ +