From 375221097c719eee045908fc194cb3c6fc43393f Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Fri, 23 Aug 2019 14:31:25 -0700 Subject: [PATCH 1/4] Update CSP to latest Update HAL adapter for interface changes Misc minor fixes to HAL adapter --- .../TARGET_PSOC6/cy_analogout_api.c | 6 +- .../TARGET_Cypress/TARGET_PSOC6/cy_crc_api.c | 1 - .../TARGET_PSOC6/cy_flash_api.c | 18 +- .../TARGET_Cypress/TARGET_PSOC6/cy_gpio_api.c | 45 +- .../TARGET_PSOC6/cy_gpio_irq_api.c | 4 +- .../TARGET_Cypress/TARGET_PSOC6/cy_i2c_api.c | 33 +- .../TARGET_PSOC6/cy_lp_ticker_api.c | 14 +- .../TARGET_PSOC6/cy_pwmout_api.c | 10 +- .../TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c | 35 +- .../TARGET_PSOC6/cy_serial_api.c | 39 +- .../TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c | 27 +- .../TARGET_Cypress/TARGET_PSOC6/cy_trng_api.c | 2 +- .../TARGET_PSOC6/cy_us_ticker_api.c | 26 +- .../TARGET_PSOC6/cy_usb_phy.cpp | 6 +- .../TARGET_PSOC6/cy_watchdog_api.c | 81 + targets/TARGET_Cypress/TARGET_PSOC6/device.h | 1 + .../TARGET_Cypress/TARGET_PSOC6/gpio_object.h | 5 +- .../TARGET_Cypress/TARGET_PSOC6/mbed_rtx.h | 18 +- targets/TARGET_Cypress/TARGET_PSOC6/objects.h | 6 +- targets/TARGET_Cypress/TARGET_PSOC6/pinmap.c | 4 +- .../TARGET_PSOC6/psoc6csp/LICENSE | 165 ++ .../TARGET_PSOC6/psoc6csp/README.md | 24 + .../include/COMPONENT_RTX/cyabs_rtos_impl.h | 9 +- .../psoc6csp/abstraction/include/cyabs_rtos.h | 206 ++- .../source/COMPONENT_RTX/cyabs_rtos_rtxv5.c | 91 +- .../abstraction/source/cyabs_resource.c | 2 +- .../psoc6csp/core_lib/include/cy_result.h | 2 +- .../psoc6csp/core_lib/include/cy_utils.h | 3 + .../TARGET_PSOC6/psoc6csp/hal/include/cyhal.h | 23 +- .../psoc6csp/hal/include/cyhal_adc.h | 28 +- .../psoc6csp/hal/include/cyhal_crc.h | 11 +- .../psoc6csp/hal/include/cyhal_crc_impl.h | 24 +- .../hal/include/cyhal_crypto_common.h | 27 +- .../psoc6csp/hal/include/cyhal_dac.h | 12 +- .../psoc6csp/hal/include/cyhal_flash.h | 31 +- .../psoc6csp/hal/include/cyhal_gpio.h | 100 +- .../psoc6csp/hal/include/cyhal_hw_resources.h | 3 +- .../psoc6csp/hal/include/cyhal_hw_types.h | 295 ++-- .../psoc6csp/hal/include/cyhal_hwmgr.h | 81 +- .../psoc6csp/hal/include/cyhal_i2c.h | 117 +- .../psoc6csp/hal/include/cyhal_interconnect.h | 34 +- .../psoc6csp/hal/include/cyhal_lptimer.h | 31 +- .../psoc6csp/hal/include/cyhal_modules.h | 85 + .../psoc6csp/hal/include/cyhal_pin_package.h | 4 +- .../psoc6csp/hal/include/cyhal_pwm.h | 56 +- .../psoc6csp/hal/include/cyhal_pwm_impl.h | 69 + .../psoc6csp/hal/include/cyhal_qspi.h | 76 +- .../psoc6csp/hal/include/cyhal_rtc.h | 56 +- .../psoc6csp/hal/include/cyhal_scb_common.h | 56 +- .../psoc6csp/hal/include/cyhal_sdhc.h | 93 +- .../psoc6csp/hal/include/cyhal_sdio.h | 137 +- .../psoc6csp/hal/include/cyhal_spi.h | 55 +- .../psoc6csp/hal/include/cyhal_system.h | 36 +- .../psoc6csp/hal/include/cyhal_tcpwm_common.h | 108 ++ .../psoc6csp/hal/include/cyhal_timer.h | 72 +- .../psoc6csp/hal/include/cyhal_timer_impl.h | 69 + .../psoc6csp/hal/include/cyhal_trng.h | 7 +- .../psoc6csp/hal/include/cyhal_trng_impl.h | 1 + .../psoc6csp/hal/include/cyhal_uart.h | 75 +- .../psoc6csp/hal/include/cyhal_usb_dev.h | 102 +- .../psoc6csp/hal/include/cyhal_utils.h | 3 + .../psoc6csp/hal/include/cyhal_wdt.h | 143 ++ .../cyhal_psoc6_01_104_m_csp_ble.h | 24 +- .../cyhal_psoc6_01_104_m_csp_ble_usb.h | 22 +- .../pin_packages/cyhal_psoc6_01_116_bga_ble.h | 24 +- .../pin_packages/cyhal_psoc6_01_116_bga_usb.h | 22 +- .../pin_packages/cyhal_psoc6_01_124_bga.h | 5 +- .../pin_packages/cyhal_psoc6_01_124_bga_sip.h | 21 +- .../pin_packages/cyhal_psoc6_01_43_smt.h | 42 +- .../pin_packages/cyhal_psoc6_01_68_qfn_ble.h | 41 +- .../pin_packages/cyhal_psoc6_01_80_wlcsp.h | 25 +- .../pin_packages/cyhal_psoc6_02_100_wlcsp.h | 4 +- .../pin_packages/cyhal_psoc6_02_124_bga.h | 4 +- .../pin_packages/cyhal_psoc6_02_128_tqfp.h | 4 +- .../pin_packages/cyhal_psoc6_02_68_qfn.h | 14 +- .../pin_packages/cyhal_psoc6_03_100_tqfp.h | 8 +- .../pin_packages/cyhal_psoc6_03_49_wlcsp.h | 20 +- .../pin_packages/cyhal_psoc6_03_68_qfn.h | 10 +- .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c | 147 +- .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_crc.c | 20 +- .../psoc6csp/hal/src/cyhal_crypto_common.c | 92 +- .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c | 70 +- .../psoc6csp/hal/src/cyhal_flash.c | 40 +- .../psoc6csp/hal/src/cyhal_gpio.c | 260 +-- .../psoc6csp/hal/src/cyhal_hwmgr.c | 76 +- .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c | 637 +------ .../psoc6csp/hal/src/cyhal_interconnect.c | 96 +- .../psoc6csp/hal/src/cyhal_lptimer.c | 233 ++- .../psoc6csp/hal/src/cyhal_not_implemented.c | 191 +- .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c | 176 +- .../psoc6csp/hal/src/cyhal_qspi.c | 498 +++--- .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_rtc.c | 54 +- .../psoc6csp/hal/src/cyhal_scb_common.c | 93 +- .../psoc6csp/hal/src/cyhal_sdhc.c | 1533 ++++++++++------- .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c | 548 ++---- .../psoc6csp/hal/src/cyhal_system.c | 38 +- .../psoc6csp/hal/src/cyhal_tcpwm_common.c | 142 ++ .../psoc6csp/hal/src/cyhal_timer.c | 707 +------- .../psoc6csp/hal/src/cyhal_trng.c | 24 +- .../psoc6csp/hal/src/cyhal_uart.c | 493 +----- .../psoc6csp/hal/src/cyhal_udb_sdio.c | 104 +- .../psoc6csp/hal/src/cyhal_usb_dev.c | 311 ++-- .../psoc6csp/hal/src/cyhal_utils.c | 11 +- .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c | 225 +++ .../cyhal_psoc6_01_104_m_csp_ble.c | 102 +- .../cyhal_psoc6_01_104_m_csp_ble_usb.c | 92 +- .../pin_packages/cyhal_psoc6_01_116_bga_ble.c | 102 +- .../pin_packages/cyhal_psoc6_01_116_bga_usb.c | 92 +- .../src/pin_packages/cyhal_psoc6_01_124_bga.c | 7 +- .../pin_packages/cyhal_psoc6_01_124_bga_sip.c | 87 +- .../src/pin_packages/cyhal_psoc6_01_43_smt.c | 192 ++- .../pin_packages/cyhal_psoc6_01_68_qfn_ble.c | 187 +- .../pin_packages/cyhal_psoc6_01_80_wlcsp.c | 107 +- .../pin_packages/cyhal_psoc6_02_100_wlcsp.c | 2 +- .../src/pin_packages/cyhal_psoc6_02_124_bga.c | 2 +- .../pin_packages/cyhal_psoc6_02_128_tqfp.c | 2 +- .../src/pin_packages/cyhal_psoc6_02_68_qfn.c | 52 +- .../pin_packages/cyhal_psoc6_03_100_tqfp.c | 16 +- .../pin_packages/cyhal_psoc6_03_49_wlcsp.c | 76 +- .../src/pin_packages/cyhal_psoc6_03_68_qfn.c | 26 +- 120 files changed, 6353 insertions(+), 4903 deletions(-) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/cy_watchdog_api.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/LICENSE create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/README.md create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_tcpwm_common.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_analogout_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_analogout_api.c index 1cce07dc237..44a48e987c2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_analogout_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_analogout_api.c @@ -40,8 +40,8 @@ void analogout_free(dac_t *obj) void analogout_write(dac_t *obj, float value) { - MBED_ASSERT(value >= 0.0 && value <= 100.0f); - analogout_write_u16(obj, (uint16_t)(value * 0.01f * UINT16_MAX)); + MBED_ASSERT(value >= 0.0 && value <= 1.0f); + analogout_write_u16(obj, (uint16_t)(value * UINT16_MAX)); } void analogout_write_u16(dac_t *obj, uint16_t value) @@ -51,7 +51,7 @@ void analogout_write_u16(dac_t *obj, uint16_t value) float analogout_read(dac_t *obj) { - return 100.0f / UINT16_MAX * analogout_read_u16(obj); + return analogout_read_u16(obj) / UINT16_MAX; } uint16_t analogout_read_u16(dac_t *obj) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_crc_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_crc_api.c index 552cc1dd699..e3a98913b4f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_crc_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_crc_api.c @@ -19,7 +19,6 @@ #include "mbed_assert.h" #include "mbed_error.h" #include "cyhal_crc.h" -#include "cyhal_crc_impl.h" #if DEVICE_CRC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_flash_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_flash_api.c index f8b3d117120..fe2cb9efd63 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_flash_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_flash_api.c @@ -50,9 +50,9 @@ int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size) int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) { - MBED_ASSERT(0 == (address % obj->info.page_size)); - MBED_ASSERT(0 == (size % obj->info.page_size)); - for (uint32_t offset = 0; offset < size; offset += obj->info.page_size) { + MBED_ASSERT(0 == (address % obj->info.blocks[0].page_size)); + MBED_ASSERT(0 == (size % obj->info.blocks[0].page_size)); + for (uint32_t offset = 0; offset < size; offset += obj->info.blocks[0].page_size) { if (CY_RSLT_SUCCESS != cyhal_flash_program(&(obj->flash), address + offset, (const uint32_t *)(data + offset))) { return -1; } @@ -62,30 +62,30 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { - if (address < obj->info.start_address || address >= obj->info.start_address + obj->info.size) { + if (address < obj->info.blocks[0].start_address || address >= obj->info.blocks[0].start_address + obj->info.blocks[0].size) { return MBED_FLASH_INVALID_SIZE; } - return obj->info.sector_size; + return obj->info.blocks[0].sector_size; } uint32_t flash_get_page_size(const flash_t *obj) { - return obj->info.page_size; + return obj->info.blocks[0].page_size; } uint32_t flash_get_start_address(const flash_t *obj) { - return obj->info.start_address; + return obj->info.blocks[0].start_address; } uint32_t flash_get_size(const flash_t *obj) { - return obj->info.size; + return obj->info.blocks[0].size; } uint8_t flash_get_erase_value(const flash_t *obj) { - return obj->info.erase_value; + return obj->info.blocks[0].erase_value; } #ifdef __cplusplus diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_api.c index 7c57d780fec..c368c528ef7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_api.c @@ -29,6 +29,22 @@ extern "C" { #endif +void apply_config(gpio_t *obj) +{ + MBED_ASSERT(obj->pin != CYHAL_NC_PIN_VALUE); + + cy_rslt_t rslt; + if (CY_RSLT_SUCCESS != (rslt = cyhal_gpio_configure(obj->pin, obj->direction, obj->drive_mode))) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_GPIO, CY_RSLT_GET_CODE(rslt)), "cyhal_gpio_configure failed"); + } + + if (obj->drive_mode == PullUp) { + gpio_write(obj, 1); + } else if (obj->drive_mode == PullDown) { + gpio_write(obj, 0); + } +} + uint32_t gpio_set(PinName pin) { // unimplemented (appears to be unused) @@ -40,7 +56,9 @@ void gpio_init(gpio_t *obj, PinName pin) obj->pin = pin; if (pin != CYHAL_NC_PIN_VALUE) { cy_rslt_t rslt; - if (CY_RSLT_SUCCESS != (rslt = cyhal_gpio_init(obj->pin, CYHAL_GPIO_DIR_INPUT, CYHAL_GPIO_DRIVE_ANALOG, false))) { + obj->direction = CYHAL_GPIO_DIR_INPUT; + obj->drive_mode = CYHAL_GPIO_DRIVE_NONE; + if (CY_RSLT_SUCCESS != (rslt = cyhal_gpio_init(obj->pin, obj->direction, obj->drive_mode, false))) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_GPIO, CY_RSLT_GET_CODE(rslt)), "cyhal_gpio_init failed"); } } @@ -48,28 +66,25 @@ void gpio_init(gpio_t *obj, PinName pin) void gpio_mode(gpio_t *obj, PinMode mode) { - MBED_ASSERT(obj->pin != CYHAL_NC_PIN_VALUE); - cy_rslt_t rslt; - if (CY_RSLT_SUCCESS != (rslt = cyhal_gpio_drivemode(obj->pin, mode))) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_GPIO, CY_RSLT_GET_CODE(rslt)), "cyhal_gpio_mode failed"); - } - if (mode == PullUp) { - gpio_write(obj, 1); - } else if (mode == PullDown) { - gpio_write(obj, 0); - } + obj->drive_mode = mode; + apply_config(obj); } void gpio_dir(gpio_t *obj, PinDirection direction) { if (direction == PIN_INPUT) { - cyhal_gpio_direction(obj->pin, CYHAL_GPIO_DIR_INPUT); - gpio_mode(obj, CYHAL_GPIO_DRIVE_ANALOG); + obj->direction = CYHAL_GPIO_DIR_INPUT; + if (obj->drive_mode == CYHAL_GPIO_DRIVE_STRONG) { + obj->drive_mode = CYHAL_GPIO_DRIVE_NONE; + } } else if (direction == PIN_OUTPUT) { // mbed reads from input buffer instead of DR even for output pins so always leave input buffer enabled - cyhal_gpio_direction(obj->pin, CYHAL_GPIO_DIR_BIDIRECTIONAL); - gpio_mode(obj, CYHAL_GPIO_DRIVE_STRONG); + obj->direction = CYHAL_GPIO_DIR_BIDIRECTIONAL; + if (obj->drive_mode == CYHAL_GPIO_DRIVE_NONE || obj->drive_mode == CYHAL_GPIO_DRIVE_ANALOG) { + obj->drive_mode = CYHAL_GPIO_DRIVE_STRONG; + } } + apply_config(obj); } #ifdef __cplusplus diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_irq_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_irq_api.c index 007a90af913..1d81de5a0c8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_irq_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_irq_api.c @@ -34,7 +34,7 @@ extern "C" { void cy_gpio_irq_handler_impl(void *handler_arg, cyhal_gpio_irq_event_t event) { gpio_irq_t *obj = (gpio_irq_t *)handler_arg; - cyhal_gpio_irq_event_t masked = event & obj->mask; + cyhal_gpio_irq_event_t masked = (cyhal_gpio_irq_event_t)(event & obj->mask); void (*handler)(uint32_t, int) = (void (*)(uint32_t, int))obj->handler; if (NULL != handler && CYHAL_GPIO_IRQ_NONE != masked) { if (CYHAL_GPIO_IRQ_NONE != (masked & CYHAL_GPIO_IRQ_RISE)) { @@ -80,7 +80,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) } else { bits = CYHAL_GPIO_IRQ_NONE; } - obj->mask = enable ? (obj->mask | bits) : (obj->mask & ~bits); + obj->mask = (cyhal_gpio_irq_event_t)(enable ? (obj->mask | bits) : (obj->mask & ~bits)); cyhal_gpio_irq_enable(obj->pin, obj->mask, true); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_i2c_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_i2c_api.c index 7ef30bb7de0..95afdf7a3b1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_i2c_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_i2c_api.c @@ -45,18 +45,18 @@ static inline struct i2c_s *cy_get_i2c(i2c_t *obj) extern "C" { #endif -static uint32_t cy_i2c_convert_event(i2c_t *obj, cyhal_i2c_irq_event_t event) +static uint32_t cy_i2c_convert_event(i2c_t *obj, cyhal_i2c_event_t event) { - if (CYHAL_I2C_IRQ_NONE != (event & (CYHAL_I2C_SLAVE_ERR_EVENT | CYHAL_I2C_MASTER_ERR_EVENT))) { + if (CYHAL_I2C_EVENT_NONE != (event & (CYHAL_I2C_SLAVE_ERR_EVENT | CYHAL_I2C_MASTER_ERR_EVENT))) { event |= I2C_EVENT_ERROR; } - if (CYHAL_I2C_IRQ_NONE != (event & (CYHAL_I2C_SLAVE_RD_CMPLT_EVENT | CYHAL_I2C_SLAVE_WR_CMPLT_EVENT | CYHAL_I2C_MASTER_RD_CMPLT_EVENT | CYHAL_I2C_MASTER_WR_CMPLT_EVENT)) && !i2c_active(obj)) { + if (CYHAL_I2C_EVENT_NONE != (event & (CYHAL_I2C_SLAVE_RD_CMPLT_EVENT | CYHAL_I2C_SLAVE_WR_CMPLT_EVENT | CYHAL_I2C_MASTER_RD_CMPLT_EVENT | CYHAL_I2C_MASTER_WR_CMPLT_EVENT)) && !i2c_active(obj)) { event |= I2C_EVENT_TRANSFER_COMPLETE; } return event; } -static void cy_i2c_event_handler(void *handler_arg, cyhal_i2c_irq_event_t event) +static void cy_i2c_event_handler(void *handler_arg, cyhal_i2c_event_t event) { struct i2c_s *i2c = cy_get_i2c((i2c_t *)handler_arg); switch (event) { @@ -91,7 +91,6 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) // MBED I2C driver currently does not support free, so we will allow I2C to be reallocated. // TODO: once the the I2C driver properly supports free, this need to be fixed so that clocks and pins are no longer leaked. cyhal_hwmgr_free(&(i2c->hal_i2c.resource)); - cyhal_hwmgr_set_unconfigured(i2c->hal_i2c.resource.type, i2c->hal_i2c.resource.block_num, i2c->hal_i2c.resource.channel_num); cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(sda); cyhal_hwmgr_free(&pin_rsc); pin_rsc = cyhal_utils_get_gpio_resource(scl); @@ -105,23 +104,23 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) i2c->cfg.address = 0; i2c->cfg.frequencyhal_hz = 400000; i2c->async_handler = NULL; - cyhal_i2c_register_irq(&(i2c->hal_i2c), &cy_i2c_event_handler, obj); - cyhal_i2c_irq_enable(&(i2c->hal_i2c), (cyhal_i2c_irq_event_t)(CYHAL_I2C_SLAVE_READ_EVENT | CYHAL_I2C_SLAVE_WRITE_EVENT | CYHAL_I2C_SLAVE_ERR_EVENT | CYHAL_I2C_SLAVE_RD_CMPLT_EVENT | CYHAL_I2C_SLAVE_WR_CMPLT_EVENT | CYHAL_I2C_MASTER_ERR_EVENT | CYHAL_I2C_MASTER_RD_CMPLT_EVENT | CYHAL_I2C_MASTER_WR_CMPLT_EVENT), true); + cyhal_i2c_register_callback(&(i2c->hal_i2c), &cy_i2c_event_handler, obj); + cyhal_i2c_enable_event(&(i2c->hal_i2c), (cyhal_i2c_event_t)(CYHAL_I2C_SLAVE_READ_EVENT | CYHAL_I2C_SLAVE_WRITE_EVENT | CYHAL_I2C_SLAVE_ERR_EVENT | CYHAL_I2C_SLAVE_RD_CMPLT_EVENT | CYHAL_I2C_SLAVE_WR_CMPLT_EVENT | CYHAL_I2C_MASTER_ERR_EVENT | CYHAL_I2C_MASTER_RD_CMPLT_EVENT | CYHAL_I2C_MASTER_WR_CMPLT_EVENT), CYHAL_ISR_PRIORITY_DEFAULT, true); } void i2c_frequency(i2c_t *obj, int hz) { struct i2c_s *i2c = cy_get_i2c(obj); i2c->cfg.frequencyhal_hz = (uint32_t)hz; - if (CY_RSLT_SUCCESS != cyhal_i2c_set_config(&(i2c->hal_i2c), &(i2c->cfg))) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_i2c_set_config"); + if (CY_RSLT_SUCCESS != cyhal_i2c_configure(&(i2c->hal_i2c), &(i2c->cfg))) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_i2c_configure"); } } int i2c_start(i2c_t *obj) { - // Not supported; start/stop is generated by i2c_read/i2c_write - return -1; + // Nothing to do; start/stop is generated by i2c_read/i2c_write + return 0; } int i2c_stop(i2c_t *obj) @@ -136,7 +135,7 @@ int i2c_stop(i2c_t *obj) int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { struct i2c_s *i2c = cy_get_i2c(obj); - if (CY_RSLT_SUCCESS != cyhal_i2c_master_read(&(i2c->hal_i2c), address >> 1, (uint8_t *)data, (uint16_t)length, CY_I2C_DEFAULT_TIMEOUT)) { + if (CY_RSLT_SUCCESS != cyhal_i2c_master_read(&(i2c->hal_i2c), address >> 1, (uint8_t *)data, (uint16_t)length, CY_I2C_DEFAULT_TIMEOUT, (bool)stop)) { return (int)I2C_ERROR_NO_SLAVE; } return length; @@ -145,7 +144,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { struct i2c_s *i2c = cy_get_i2c(obj); - if (CY_RSLT_SUCCESS != cyhal_i2c_master_write(&(i2c->hal_i2c), address >> 1, (const uint8_t *)data, (uint16_t)length, CY_I2C_DEFAULT_TIMEOUT)) { + if (CY_RSLT_SUCCESS != cyhal_i2c_master_write(&(i2c->hal_i2c), address >> 1, (const uint8_t *)data, (uint16_t)length, CY_I2C_DEFAULT_TIMEOUT, (bool)stop)) { return (int)I2C_ERROR_NO_SLAVE; } // NOTE: HAL does not report how many bytes were actually sent in case of early NAK @@ -210,8 +209,8 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave) { struct i2c_s *i2c = cy_get_i2c(obj); i2c->cfg.is_slave = (0 != enable_slave); - if (CY_RSLT_SUCCESS != cyhal_i2c_set_config(&(i2c->hal_i2c), &(i2c->cfg))) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_i2c_set_config"); + if (CY_RSLT_SUCCESS != cyhal_i2c_configure(&(i2c->hal_i2c), &(i2c->cfg))) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_i2c_configure"); } } @@ -242,8 +241,8 @@ void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { struct i2c_s *i2c = cy_get_i2c(obj); i2c->cfg.address = address; - if (CY_RSLT_SUCCESS != cyhal_i2c_set_config(&(i2c->hal_i2c), &(i2c->cfg))) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_i2c_set_config"); + if (CY_RSLT_SUCCESS != cyhal_i2c_configure(&(i2c->hal_i2c), &(i2c->cfg))) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_i2c_configure"); } Cy_SCB_I2C_SlaveSetAddressMask(i2c->hal_i2c.base, (uint8_t)mask); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_lp_ticker_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_lp_ticker_api.c index 9074d5819bc..ac20ec6d165 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_lp_ticker_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_lp_ticker_api.c @@ -31,7 +31,7 @@ extern "C" { static cyhal_lptimer_t cy_lptimer0; static bool cy_lptimer_initialized = false; -static void cy_lp_ticker_handler(MBED_UNUSED void *unused1, MBED_UNUSED cyhal_lptimer_irq_event_t unused2) +static void cy_lp_ticker_handler(MBED_UNUSED void *unused1, MBED_UNUSED cyhal_lptimer_event_t unused2) { lp_ticker_irq_handler(); } @@ -46,7 +46,7 @@ void lp_ticker_init(void) cy_lptimer_initialized = true; } lp_ticker_disable_interrupt(); - cyhal_lptimer_register_irq(&cy_lptimer0, &cy_lp_ticker_handler, NULL); + cyhal_lptimer_register_callback(&cy_lptimer0, &cy_lp_ticker_handler, NULL); } void lp_ticker_free(void) @@ -62,15 +62,17 @@ uint32_t lp_ticker_read(void) void lp_ticker_set_interrupt(timestamp_t timestamp) { - if (CY_RSLT_SUCCESS != cyhal_lptimer_set_match(&cy_lptimer0, timestamp)) { + uint32_t delay; + delay = (uint32_t)timestamp - cyhal_lptimer_read(&cy_lptimer0); + + if (CY_RSLT_SUCCESS != cyhal_lptimer_set_match(&cy_lptimer0, delay)) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_lptimer_set_time"); } - cyhal_lptimer_irq_enable(&cy_lptimer0, CYHAL_LPTIMER_COMPARE_MATCH, true); } void lp_ticker_disable_interrupt(void) { - cyhal_lptimer_irq_enable(&cy_lptimer0, CYHAL_LPTIMER_COMPARE_MATCH, false); + cyhal_lptimer_enable_event(&cy_lptimer0, CYHAL_LPTIMER_COMPARE_MATCH, CYHAL_ISR_PRIORITY_DEFAULT, false); } void lp_ticker_clear_interrupt(void) @@ -87,7 +89,7 @@ const ticker_info_t *lp_ticker_get_info(void) { static const ticker_info_t info = { /* .frequency = */ CY_CFG_SYSCLK_CLKLF_FREQ_HZ, - /* .bits = */ 16 + /* .bits = */ 32 }; return &info; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_pwmout_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_pwmout_api.c index 7d57b659a6a..b0b1988eeb1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_pwmout_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_pwmout_api.c @@ -45,7 +45,7 @@ void pwmout_free(pwmout_t *obj) void pwmout_write(pwmout_t *obj, float percent) { MBED_ASSERT(percent >= 0.0f && percent <= 1.0f); - pwmout_pulsewidth_us(obj, percent * obj->period_us); + pwmout_pulsewidth_us(obj, (int)(percent * obj->period_us)); } float pwmout_read(pwmout_t *obj) @@ -66,8 +66,8 @@ void pwmout_period_ms(pwmout_t *obj, int ms) void pwmout_period_us(pwmout_t *obj, int us) { obj->period_us = (uint32_t)us; - if (CY_RSLT_SUCCESS != cyhal_pwm_period(&(obj->hal_pwm), obj->period_us, obj->width_us)) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_PWM, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_pwm_period"); + if (CY_RSLT_SUCCESS != cyhal_pwm_set_period(&(obj->hal_pwm), obj->period_us, obj->width_us)) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_PWM, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_pwm_set_period"); } if (CY_RSLT_SUCCESS != cyhal_pwm_start(&(obj->hal_pwm))) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_PWM, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_pwm_start"); @@ -87,8 +87,8 @@ void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) void pwmout_pulsewidth_us(pwmout_t *obj, int us) { obj->width_us = (uint32_t)us; - if (CY_RSLT_SUCCESS != cyhal_pwm_period(&(obj->hal_pwm), obj->period_us, obj->width_us)) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_PWM, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_pwm_period"); + if (CY_RSLT_SUCCESS != cyhal_pwm_set_period(&(obj->hal_pwm), obj->period_us, obj->width_us)) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_PWM, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_pwm_set_period"); } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c index d6c27bde730..cd28b088441 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c @@ -38,19 +38,19 @@ qspi_status_t qspi_free(qspi_t *obj) qspi_status_t qspi_frequency(qspi_t *obj, int hz) { - return CY_RSLT_SUCCESS == cyhal_qspi_frequency(&(obj->hal_qspi), (uint32_t)hz) ? QSPI_STATUS_OK : QSPI_STATUS_ERROR; + return CY_RSLT_SUCCESS == cyhal_qspi_set_frequency(&(obj->hal_qspi), (uint32_t)hz) ? QSPI_STATUS_OK : QSPI_STATUS_ERROR; } static inline cyhal_qspi_bus_width_t cyhal_qspi_convert_width(qspi_bus_width_t width) { switch (width) { case QSPI_CFG_BUS_SINGLE: - return CY_QSPI_CFG_BUS_SINGLE; + return CYHAL_QSPI_CFG_BUS_SINGLE; case QSPI_CFG_BUS_DUAL: - return CY_QSPI_CFG_BUS_DUAL; + return CYHAL_QSPI_CFG_BUS_DUAL; default: // fallthrough case QSPI_CFG_BUS_QUAD: - return CY_QSPI_CFG_BUS_QUAD; + return CYHAL_QSPI_CFG_BUS_QUAD; } } @@ -58,14 +58,14 @@ static inline cyhal_qspi_size_t cyhal_qspi_convert_addr_size(qspi_address_size_t { switch (size) { case QSPI_CFG_ADDR_SIZE_8: - return CY_QSPI_CFG_SIZE_8; + return CYHAL_QSPI_CFG_SIZE_8; case QSPI_CFG_ADDR_SIZE_16: - return CY_QSPI_CFG_SIZE_16; + return CYHAL_QSPI_CFG_SIZE_16; case QSPI_CFG_ADDR_SIZE_24: - return CY_QSPI_CFG_SIZE_24; + return CYHAL_QSPI_CFG_SIZE_24; default: // fallthrough case QSPI_CFG_ADDR_SIZE_32: - return CY_QSPI_CFG_SIZE_32; + return CYHAL_QSPI_CFG_SIZE_32; } } @@ -73,14 +73,14 @@ static inline cyhal_qspi_size_t cyhal_qspi_convert_alt_size(qspi_alt_size_t size { switch (size) { case QSPI_CFG_ALT_SIZE_8: - return CY_QSPI_CFG_SIZE_8; + return CYHAL_QSPI_CFG_SIZE_8; case QSPI_CFG_ALT_SIZE_16: - return CY_QSPI_CFG_SIZE_16; + return CYHAL_QSPI_CFG_SIZE_16; case QSPI_CFG_ALT_SIZE_24: - return CY_QSPI_CFG_SIZE_24; + return CYHAL_QSPI_CFG_SIZE_24; default: // fallthrough case QSPI_CFG_ALT_SIZE_32: - return CY_QSPI_CFG_SIZE_32; + return CYHAL_QSPI_CFG_SIZE_32; } } @@ -91,11 +91,12 @@ static void cyhal_qspi_convert_command(const qspi_command_t *from, cyhal_qspi_co to->instruction.disabled = from->instruction.disabled; to->address.bus_width = cyhal_qspi_convert_width(from->address.bus_width); to->address.size = cyhal_qspi_convert_addr_size(from->address.size); - to->address.disabled = from->address.data; - to->alt.bus_width = cyhal_qspi_convert_width(from->alt.bus_width); - to->alt.size = cyhal_qspi_convert_alt_size(from->alt.size); - to->alt.value = from->alt.value; - to->alt.disabled = from->alt.disabled; + to->address.value = from->address.value; + to->address.disabled = from->address.disabled; + to->mode_bits.bus_width = cyhal_qspi_convert_width(from->alt.bus_width); + to->mode_bits.size = cyhal_qspi_convert_alt_size(from->alt.size); + to->mode_bits.value = from->alt.value; + to->mode_bits.disabled = from->alt.disabled; to->dummy_count = from->dummy_count; to->data.bus_width = cyhal_qspi_convert_width(from->data.bus_width); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c index 3d1069b3b8c..ee9f2536cfa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c @@ -39,7 +39,7 @@ static inline struct serial_s *cy_serial_get_struct(serial_t *obj) #endif } -static void serial_handler_internal(void *handler_arg, cyhal_uart_irq_event_t event) +static void serial_handler_internal(void *handler_arg, cyhal_uart_event_t event) { serial_t *obj = (serial_t *)handler_arg; struct serial_s *ser = cy_serial_get_struct(obj); @@ -80,13 +80,13 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) if (CY_RSLT_SUCCESS != cyhal_uart_init(&(ser->hal_obj), tx, rx, NULL, NULL)) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_uart_init"); } - cyhal_uart_register_irq(&(ser->hal_obj), &serial_handler_internal, obj); + cyhal_uart_register_callback(&(ser->hal_obj), &serial_handler_internal, obj); #if DEVICE_SERIAL_ASYNCH - static const cyhal_uart_irq_event_t ENABLE_EVENTS = - CYHAL_UART_IRQ_TX_DONE | CYHAL_UART_IRQ_TX_ERROR | - CYHAL_UART_IRQ_RX_DONE | CYHAL_UART_IRQ_RX_ERROR; - cyhal_uart_irq_enable(&(ser->hal_obj), ENABLE_EVENTS, true); + static const cyhal_uart_event_t ENABLE_EVENTS = (cyhal_uart_event_t) + (CYHAL_UART_IRQ_TX_DONE | CYHAL_UART_IRQ_TX_ERROR | + CYHAL_UART_IRQ_RX_DONE | CYHAL_UART_IRQ_RX_ERROR); + cyhal_uart_enable_event(&(ser->hal_obj), ENABLE_EVENTS, CYHAL_ISR_PRIORITY_DEFAULT, true); #endif if (tx == STDIO_UART_TX) { memmove(&stdio_uart, obj, sizeof(serial_t)); @@ -103,7 +103,7 @@ void serial_free(serial_t *obj) void serial_baud(serial_t *obj, int baudrate) { struct serial_s *ser = cy_serial_get_struct(obj); - if (CY_RSLT_SUCCESS != cyhal_uart_baud(&(ser->hal_obj), baudrate, NULL)) { + if (CY_RSLT_SUCCESS != cyhal_uart_set_baud(&(ser->hal_obj), baudrate, NULL)) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_CODE_FAILED_OPERATION), "serial_baud"); } ser->baud = (uint32_t)baudrate; @@ -132,8 +132,8 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b .stop_bits = stop_bits, .parity = hal_parity, }; - if (CY_RSLT_SUCCESS != cyhal_uart_format(&(ser->hal_obj), &cfg)) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_uart_format"); + if (CY_RSLT_SUCCESS != cyhal_uart_configure(&(ser->hal_obj), &cfg)) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_uart_configure"); } } @@ -149,17 +149,18 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { struct serial_s *ser = cy_serial_get_struct(obj); if (irq == RxIrq) { - static const cyhal_uart_irq_event_t interrupt_mask = CYHAL_UART_IRQ_RX_DONE | CYHAL_UART_IRQ_RX_ERROR | CYHAL_UART_IRQ_RX_NOT_EMPTY; + static const cyhal_uart_event_t interrupt_mask = (cyhal_uart_event_t) + (CYHAL_UART_IRQ_RX_DONE | CYHAL_UART_IRQ_RX_ERROR | CYHAL_UART_IRQ_RX_NOT_EMPTY); ser->rx_event_mask = enable ? (ser->rx_event_mask | interrupt_mask) : (ser->rx_event_mask & ~interrupt_mask); - cyhal_uart_irq_enable(&(ser->hal_obj), interrupt_mask, (bool)enable); + cyhal_uart_enable_event(&(ser->hal_obj), interrupt_mask, CYHAL_ISR_PRIORITY_DEFAULT, (bool)enable); } else if (irq == TxIrq) { - static const cyhal_uart_irq_event_t interrupt_mask = CYHAL_UART_IRQ_TX_DONE | CYHAL_UART_IRQ_TX_ERROR | CYHAL_UART_IRQ_TX_EMPTY; + static const cyhal_uart_event_t interrupt_mask = CYHAL_UART_IRQ_TX_DONE | CYHAL_UART_IRQ_TX_ERROR | CYHAL_UART_IRQ_TX_EMPTY; ser->tx_event_mask = enable - ? (ser->tx_event_mask | interrupt_mask) - : (ser->tx_event_mask & ~interrupt_mask); - cyhal_uart_irq_enable(&(ser->hal_obj), interrupt_mask, (bool)enable); + ? (cyhal_uart_event_t)(ser->tx_event_mask | interrupt_mask) + : (cyhal_uart_event_t)(ser->tx_event_mask & ~interrupt_mask); + cyhal_uart_enable_event(&(ser->hal_obj), interrupt_mask, CYHAL_ISR_PRIORITY_DEFAULT, (bool)enable); } } @@ -253,7 +254,7 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, MBED_UNUSE struct serial_s *ser = cy_serial_get_struct(obj); // handler calls serial_irq_handler_async ser->async_tx_handler = (void *)handler; - if (CY_RSLT_SUCCESS != cyhal_uart_tx_async(&(ser->hal_obj), (void *)tx, tx_length)) { + if (CY_RSLT_SUCCESS != cyhal_uart_write_async(&(ser->hal_obj), (void *)tx, tx_length)) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_CODE_WRITE_FAILED), "serial_tx_asynch"); } return 0; @@ -264,7 +265,7 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, MBED_UNUSED uin struct serial_s *ser = cy_serial_get_struct(obj); // handler calls serial_irq_handler_async ser->async_rx_handler = (void *)handler; - if (CY_RSLT_SUCCESS != cyhal_uart_rx_async(&(ser->hal_obj), rx, rx_length)) { + if (CY_RSLT_SUCCESS != cyhal_uart_read_async(&(ser->hal_obj), rx, rx_length)) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_CODE_WRITE_FAILED), "serial_rx_asynch"); } } @@ -303,7 +304,7 @@ int serial_irq_handler_asynch(serial_t *obj) void serial_tx_abort_asynch(serial_t *obj) { struct serial_s *ser = cy_serial_get_struct(obj); - if (CY_RSLT_SUCCESS != cyhal_uart_tx_abort(&(ser->hal_obj))) { + if (CY_RSLT_SUCCESS != cyhal_uart_write_abort(&(ser->hal_obj))) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_FAILED_OPERATION), "serial_tx_abort_asynch"); } } @@ -311,7 +312,7 @@ void serial_tx_abort_asynch(serial_t *obj) void serial_rx_abort_asynch(serial_t *obj) { struct serial_s *ser = cy_serial_get_struct(obj); - if (CY_RSLT_SUCCESS != cyhal_uart_rx_abort(&(ser->hal_obj))) { + if (CY_RSLT_SUCCESS != cyhal_uart_read_abort(&(ser->hal_obj))) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_FAILED_OPERATION), "serial_rx_abort_asynch"); } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c index 4a6e9a51451..7f0f288d6ce 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c @@ -19,6 +19,7 @@ #include "cyhal_hwmgr.h" #include "cyhal_spi.h" #include "cyhal_scb_common.h" +#include "cyhal_utils.h" #include "cy_scb_spi.h" #include "mbed_error.h" @@ -41,13 +42,13 @@ SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName mclk) { const cyhal_resource_pin_mapping_t *map = cyhal_utils_get_resource(mclk, cyhal_pin_map_scb_spi_s_clk, sizeof(cyhal_pin_map_scb_spi_s_clk) / sizeof(*cyhal_pin_map_scb_spi_s_clk)); if (NULL != map) { - return (SPIName)CY_SCB_BASE_ADDRESSES[map->inst->block_num]; + return (SPIName)CYHAL_SCB_BASE_ADDRESSES[map->inst->block_num]; } MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "SPI not found"); return (SPIName)0; } -static void cy_spi_irq_handler_internal(void *handler_arg, cyhal_spi_irq_event_t event) +static void cy_spi_irq_handler_internal(void *handler_arg, cyhal_spi_event_t event) { struct spi_s *spi = cy_get_spi((spi_t *)handler_arg); spi->async_events = 0; @@ -78,7 +79,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel if (CY_RSLT_SUCCESS != cyhal_spi_init(&(spi->hal_spi), mosi, miso, sclk, ssel, NULL, spi->cfg.data_bits, spi->cfg.mode, spi->cfg.is_slave)) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_init"); } - cyhal_spi_register_irq(&(spi->hal_spi), &cy_spi_irq_handler_internal, obj); + cyhal_spi_register_callback(&(spi->hal_spi), &cy_spi_irq_handler_internal, obj); } void spi_free(spi_t *obj) @@ -120,8 +121,8 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) void spi_frequency(spi_t *obj, int hz) { struct spi_s *spi = cy_get_spi(obj); - if (CY_RSLT_SUCCESS != cyhal_spi_frequency(&(spi->hal_spi), hz)) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_frequency"); + if (CY_RSLT_SUCCESS != cyhal_spi_set_frequency(&(spi->hal_spi), hz)) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_set_frequency"); } spi->hz = hz; } @@ -130,11 +131,11 @@ int spi_master_write(spi_t *obj, int value) { struct spi_s *spi = cy_get_spi(obj); uint32_t received; - if (CY_RSLT_SUCCESS != cyhal_spi_write(&(spi->hal_spi), (uint32_t)value)) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_write"); + if (CY_RSLT_SUCCESS != cyhal_spi_send(&(spi->hal_spi), (uint32_t)value)) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_send"); } - if (CY_RSLT_SUCCESS != cyhal_spi_read(&(spi->hal_spi), &received)) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_read"); + if (CY_RSLT_SUCCESS != cyhal_spi_recv(&(spi->hal_spi), &received)) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_recv"); } return (int)received; } @@ -158,8 +159,8 @@ int spi_slave_read(spi_t *obj) { uint32_t value; struct spi_s *spi = cy_get_spi(obj); - if (CY_RSLT_SUCCESS != cyhal_spi_read(&(spi->hal_spi), &value)) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_read"); + if (CY_RSLT_SUCCESS != cyhal_spi_recv(&(spi->hal_spi), &value)) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_recv"); } return value; } @@ -167,8 +168,8 @@ int spi_slave_read(spi_t *obj) void spi_slave_write(spi_t *obj, int value) { struct spi_s *spi = cy_get_spi(obj); - if (CY_RSLT_SUCCESS != cyhal_spi_write(&(spi->hal_spi), value)) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_write"); + if (CY_RSLT_SUCCESS != cyhal_spi_send(&(spi->hal_spi), value)) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_spi_send"); } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_trng_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_trng_api.c index 9a3e26acfd4..4c7855c1c68 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_trng_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_trng_api.c @@ -16,7 +16,7 @@ */ #include "trng_api.h" -#include "cyhal_implementation.h" +#include "cyhal_trng.h" #include "mbed_error.h" #include diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_us_ticker_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_us_ticker_api.c index 6f27f4a4a7b..c8bad16fd84 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_us_ticker_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_us_ticker_api.c @@ -46,7 +46,7 @@ static cy_stc_syspm_callback_t cy_us_ticker_pm_data = { .callbackParams = &cy_us_ticker_pm_params, }; -static void cy_us_ticker_irq_handler(MBED_UNUSED void *arg, MBED_UNUSED cyhal_timer_irq_event_t event) +static void cy_us_ticker_irq_handler(MBED_UNUSED void *arg, MBED_UNUSED cyhal_timer_event_t event) { us_ticker_irq_handler(); } @@ -61,21 +61,21 @@ void us_ticker_init(void) MBED_ASSERT(cy_PeriClkFreqHz >= 1000000); uint32_t div_value = cy_PeriClkFreqHz / 1000000; cy_us_ticker_info.frequency = cy_PeriClkFreqHz / div_value; - cy_us_ticker_info.bits = 16; + cy_us_ticker_info.bits = CYHAL_TCPWM_DATA[cy_us_timer.resource.block_num].max_count; Cy_SysClk_PeriphSetDivider(cy_us_timer.clock.div_type, cy_us_timer.clock.div_num, div_value - 1u); - static const cyhal_timer_cfg_t cfg = { - /* .is_continuous = */ true, - /* .direction = */ CYHAL_TIMER_DIR_UP, - /* .is_compare = */ true, - /* .period = */ 0xFFFFu, - /* .compare_value = */ 0xFFFFu, - /* .value = */ 0u + const cyhal_timer_cfg_t cfg = { + .is_continuous = true, + .direction = CYHAL_TIMER_DIR_UP, + .is_compare = true, + .period = (1 << cy_us_ticker_info.bits) - 1, + .compare_value = (1 << cy_us_ticker_info.bits) - 1, + .value = 0u }; - if (CY_RSLT_SUCCESS != cyhal_timer_set_config(&cy_us_timer, &cfg)) { + if (CY_RSLT_SUCCESS != cyhal_timer_configure(&cy_us_timer, &cfg)) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_timer_set_cfg"); } Cy_TCPWM_ClearInterrupt(cy_us_timer.base, cy_us_timer.resource.channel_num, CY_TCPWM_INT_ON_CC_OR_TC); - cyhal_timer_register_irq(&cy_us_timer, CY_US_TICKER_IRQ_PRIORITY, &cy_us_ticker_irq_handler, NULL); + cyhal_timer_register_callback(&cy_us_timer, &cy_us_ticker_irq_handler, NULL); if (CY_RSLT_SUCCESS != cyhal_timer_start(&cy_us_timer)) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_timer_start"); } @@ -112,14 +112,14 @@ void us_ticker_set_interrupt(timestamp_t timestamp) Cy_TCPWM_Counter_SetCompare0(cy_us_timer.base, cy_us_timer.resource.channel_num, timestamp); if (CY_TCPWM_INT_NONE == Cy_TCPWM_GetInterruptMask(cy_us_timer.base, cy_us_timer.resource.channel_num)) { Cy_TCPWM_ClearInterrupt(cy_us_timer.base, cy_us_timer.resource.channel_num, CY_TCPWM_INT_ON_CC_OR_TC); - cyhal_timer_irq_enable(&cy_us_timer, CYHAL_TIMER_IRQ_CAPTURE_COMPARE, true); + cyhal_timer_enable_event(&cy_us_timer, CYHAL_TIMER_IRQ_CAPTURE_COMPARE, CY_US_TICKER_IRQ_PRIORITY, true); } } void us_ticker_disable_interrupt(void) { MBED_ASSERT(cy_us_ticker_initialized); - cyhal_timer_irq_enable(&cy_us_timer, CYHAL_TIMER_IRQ_CAPTURE_COMPARE, false); + cyhal_timer_enable_event(&cy_us_timer, CYHAL_TIMER_IRQ_CAPTURE_COMPARE, CY_US_TICKER_IRQ_PRIORITY, false); } void us_ticker_clear_interrupt(void) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_usb_phy.cpp b/targets/TARGET_Cypress/TARGET_PSOC6/cy_usb_phy.cpp index 1801ffca250..511c72f1abb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_usb_phy.cpp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_usb_phy.cpp @@ -94,7 +94,7 @@ void USBPhyHw::init(USBPhyEvents *events) out_event_mask = 0; // Configure interrupt and hook interrupt handler - cyhal_usb_dev_register_irq(hal_obj, (cyhal_usb_dev_irq_handler_t)&_usbisr); + cyhal_usb_dev_register_irq_callback(hal_obj, (cyhal_usb_dev_irq_callback_t)&_usbisr); cyhal_usb_dev_irq_enable(hal_obj, true); } @@ -196,12 +196,12 @@ void USBPhyHw::disconnect() void USBPhyHw::configure() { - cyhal_usb_dev_configure(&obj); + cyhal_usb_dev_set_configured(&obj); } void USBPhyHw::unconfigure() { - cyhal_usb_dev_unconfigure(&obj); + cyhal_usb_dev_set_unconfigured(&obj); } void USBPhyHw::sof_enable() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_watchdog_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_watchdog_api.c new file mode 100644 index 00000000000..523a47ccb17 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_watchdog_api.c @@ -0,0 +1,81 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_error.h" +#include "watchdog_api.h" +#include "cyhal_wdt.h" + +#if DEVICE_WATCHDOG + +#ifdef __cplusplus +extern "C" { +#endif + +static bool initialized = false; +static cyhal_wdt_t cy_wdt; + +watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) +{ + //MBED can call init multiple times so we need to free before the second init + if (initialized) { + cyhal_wdt_free(&cy_wdt); + } + + cy_rslt_t result = cyhal_wdt_init(&cy_wdt, config->timeout_ms); + + switch (result) { + case CY_RSLT_SUCCESS: + initialized = true; + return WATCHDOG_STATUS_OK; + case CY_RSLT_WDT_INVALID_TIMEOUT: + return WATCHDOG_STATUS_INVALID_ARGUMENT; + default: + return WATCHDOG_STATUS_NOT_SUPPORTED; + } +} + +void hal_watchdog_kick(void) +{ + cyhal_wdt_kick(&cy_wdt); +} + +watchdog_status_t hal_watchdog_stop(void) +{ + cyhal_wdt_stop(&cy_wdt); + return WATCHDOG_STATUS_OK; +} + +uint32_t hal_watchdog_get_reload_value(void) +{ + return cyhal_wdt_get_timeout_ms(&cy_wdt); +} + +watchdog_features_t hal_watchdog_get_platform_features(void) +{ + watchdog_features_t features = { + /* .max_timeout = */ cyhal_wdt_get_max_timeout_ms(), + /* .update_config = */ true, + /* .disable_watchdog = */ true + }; + return features; +} + +#ifdef __cplusplus +} +#endif + +#endif // DEVICE_WATCHDOG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device.h b/targets/TARGET_Cypress/TARGET_PSOC6/device.h index 1055425cdac..afb0c65696e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/device.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device.h @@ -28,6 +28,7 @@ #include "cmsis.h" #include "objects.h" +#include "cycfg.h" /* * Board clocks. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/gpio_object.h b/targets/TARGET_Cypress/TARGET_PSOC6/gpio_object.h index 2ba42671732..b4fd3be0cd7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/gpio_object.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/gpio_object.h @@ -23,7 +23,8 @@ #include "mbed_assert.h" #include "PinNamesTypes.h" #include "PinNames.h" -#include "cyhal_gpio_impl.h" +#include "PortNames.h" +#include "cyhal_gpio.h" #include "cyhal_pin_package.h" #ifdef __cplusplus @@ -32,6 +33,8 @@ extern "C" { typedef struct { cyhal_gpio_t pin; + cyhal_gpio_direction_t direction; + cyhal_gpio_drive_mode_t drive_mode; } gpio_t; struct gpio_irq_s { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_rtx.h b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_rtx.h index 21e05f308be..d8e2557da2a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_rtx.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_rtx.h @@ -21,22 +21,6 @@ #ifndef MBED_MBED_RTX_H #define MBED_MBED_RTX_H -#if defined(TARGET_CY8CKIT_062_BLE) -#ifndef INITIAL_SP -#define INITIAL_SP (0x08002000 + 0x00045800) /* Ram origin + length */ -#endif -#elif defined(TARGET_CY8CKIT_062_WIFI_BT) -#ifndef INITIAL_SP -#define INITIAL_SP (0x08002000 + 0x00045800) /* Ram origin + length */ -#endif -#elif defined(TARGET_CY8CMOD_062_4343W) -#ifndef INITIAL_SP -#define INITIAL_SP (0x08002000 + 0x000FD800) /* Ram origin + length */ -#endif -#elif defined(TARGET_CYW943012P6EVB_01) -#ifndef INITIAL_SP -#define INITIAL_SP (0x08002000 + 0x00045800) /* Ram origin + length */ -#endif -#endif +/* This file is required, but doesn't actually need to do anything. */ #endif /* MBED_MBED_RTX_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/objects.h b/targets/TARGET_Cypress/TARGET_PSOC6/objects.h index 8c988b22db8..49d72fe81ab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/objects.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/objects.h @@ -53,10 +53,10 @@ struct serial_s { uint32_t baud; void *handler; uint32_t handler_arg; - cyhal_uart_irq_event_t rx_event_mask; - cyhal_uart_irq_event_t tx_event_mask; + cyhal_uart_event_t rx_event_mask; + cyhal_uart_event_t tx_event_mask; #if DEVICE_SERIAL_ASYNCH - cyhal_uart_irq_event_t event_flags; + cyhal_uart_event_t event_flags; void *async_rx_handler; void *async_tx_handler; #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/pinmap.c b/targets/TARGET_Cypress/TARGET_PSOC6/pinmap.c index 350319acb89..30cc028a495 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/pinmap.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/pinmap.c @@ -17,10 +17,10 @@ * limitations under the License. */ -#include "mbed_assert.h" #include "pinmap.h" -#include "mbed_error.h" #include "cy_gpio.h" +#include "cyhal_gpio.h" +#include "cyhal_utils.h" void pin_function(PinName pin, int function) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/LICENSE b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/LICENSE new file mode 100644 index 00000000000..59cd3f8a320 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/LICENSE @@ -0,0 +1,165 @@ +Apache License +Version 2.0, January 2004 +http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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However, +in accepting such obligations, You may act only on Your own behalf and on Your +sole responsibility, not on behalf of any other Contributor, and only if You +agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/README.md new file mode 100644 index 00000000000..a7ac9afd74e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/README.md @@ -0,0 +1,24 @@ +# PSoC 6 CSP + +## Overview + +TBD: high-level overview + +## Features + +TBD: list of the functionality included + +## API Reference Manual + +The PSoC 6 Chip Support Package provides a set of APIs to configure, initialize and use the PSoC 6 MCU resources. + +See the [PSoC 6 CSP API Reference Manual][api] for the complete list of the provided interfaces. + +## More information +* [PSoC 6 CSP API Reference Manual][api] +* [Cypress Semiconductor](http://www.cypress.com) + +[api]: modules.html + +--- +© Cypress Semiconductor Corporation, 2019. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/COMPONENT_RTX/cyabs_rtos_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/COMPONENT_RTX/cyabs_rtos_impl.h index d454e39e757..3daa9839c8a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/COMPONENT_RTX/cyabs_rtos_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/COMPONENT_RTX/cyabs_rtos_impl.h @@ -8,13 +8,13 @@ * \copyright * Copyright 2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 -* +* * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at -* +* * http://www.apache.org/licenses/LICENSE-2.0 -* +* * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -38,7 +38,8 @@ extern "C" * Constants ******************************************************/ #define CY_RTOS_MIN_STACK_SIZE 300 /** Minimum stack size */ -#define CY_RTOS_ALIGNMENT_MASK 0x00000007UL /** Checks for 8-bit alignement */ +#define CY_RTOS_ALIGNMENT 0x00000008UL /** Minimum alignment for RTOS objects */ +#define CY_RTOS_ALIGNMENT_MASK 0x00000007UL /** Mask for checking the alignement of crated RTOS objects */ /****************************************************** diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_rtos.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_rtos.h index 2559eff1b8b..8fad10a6032 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_rtos.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_rtos.h @@ -2,10 +2,10 @@ * \file cyabs_rtos.h * * \brief -* Defines the Cypress RTOS Interface. Provides prototypes for functions that -* allow Cypress libraries to use RTOS resources such as threads, mutexes & timing -* functions in an abstract way. The APIs are implemented -* in the Port Layer RTOS interface which is specific to the RTOS in use. +* Defines the Cypress RTOS Interface. Provides prototypes for functions that +* allow Cypress libraries to use RTOS resources such as threads, mutexes & +* timing functions in an abstract way. The APIs are implemented in the Port +* Layer RTOS interface which is specific to the RTOS in use. * ******************************************************************************** * \copyright @@ -36,7 +36,7 @@ /* * Note, cyabs_rtos_impl.h above is included and is the implementation of some basic * types for the abstraction layer. The types expected to be defined are. - * + * * cy_thread_t : typedef from underlying RTOS thread type * cy_thread_arg_t : typedef from the RTOS type that is passed to the * entry function of a thread. @@ -47,15 +47,26 @@ * : to the timer callback function * cy_timer_t : typedef from the underlying RTOS timer type * cy_time_t : count of time in milliseconds - * cy_rtos_error_t : typedef from the underlying RTOS error type * + * cy_rtos_error_t : typedef from the underlying RTOS error type + * + * The enum cy_thread_priority_t needs to have the following priority values defined + * and mapped to RTOS specific values: + * CY_RTOS_PRIORITY_MIN + * CY_RTOS_PRIORITY_LOW + * CY_RTOS_PRIORITY_BELOWNORMAL + * CY_RTOS_PRIORITY_NORMAL + * CY_RTOS_PRIORITY_ABOVENORMAL + * CY_RTOS_PRIORITY_HIGH + * CY_RTOS_PRIORITY_REALTIME + * CY_RTOS_PRIORITY_MAX * - * The following #defines need to be provided for thread standard priorities: - * CY_THREAD_PRIORITY_LOW - * CY_THREAD_PRIORITY_NORMAL - * CY_THREAD_PRIORITY_HIGH - */ + * Finally, the following macros need to be defined for memory allocations: + * CY_RTOS_MIN_STACK_SIZE + * CY_RTOS_ALIGNMENT + * CY_RTOS_ALIGNMENT_MASK + */ + - /** * \addtogroup group_abstraction_rtos RTOS abstraction * \ingroup group_abstraction @@ -108,30 +119,53 @@ extern "C" /*********************************************** TYPES **********************************************/ /** -* \addtogroup group_abstraction_rtos_data_structures +* \addtogroup group_abstraction_rtos_enums * \{ */ /** - * The type of a function that is the entry point for a thread - * - * @param[in] arg the argument passed from the thread create call to the entry function + * The state a thread can be in */ -typedef void (*cy_thread_entry_fn_t)(cy_thread_arg_t arg) ; +typedef enum cy_thread_state +{ + CY_THREAD_STATE_INACTIVE, /**< thread has not started or was terminated but not yet joined */ + CY_THREAD_STATE_READY, /**< thread can run, but is not currently */ + CY_THREAD_STATE_RUNNING, /**< thread is currently running */ + CY_THREAD_STATE_BLOCKED, /**< thread is blocked waiting for something */ + CY_THREAD_STATE_TERMINATED, /**< thread has terminated but not freed */ + CY_THREAD_STATE_UNKNOWN, /**< thread is in an unknown state */ +} cy_thread_state_t; /** * The type of timer */ typedef enum cy_timer_trigger_type { - cy_timer_type_periodic = osTimerPeriodic, /**< called periodically until stopped */ - cy_timer_type_once = osTimerOnce, /**< called once only */ + CY_TIMER_TYPE_PERIODIC, /**< called periodically until stopped */ + CY_TIMER_TYPE_ONCE, /**< called once only */ + cy_timer_type_periodic = CY_TIMER_TYPE_PERIODIC, /**< \deprecated replaced by CY_TIMER_TYPE_PERIODIC */ + cy_timer_type_once = CY_TIMER_TYPE_ONCE, /**< \deprecated replaced by CY_TIMER_TYPE_ONCE */ } cy_timer_trigger_type_t ; +/** \} group_abstraction_rtos_enums */ + + +/** +* \addtogroup group_abstraction_rtos_data_structures +* \{ +*/ + +/** + * The type of a function that is the entry point for a thread + * + * @param[in] arg the argument passed from the thread create call to the entry function + */ +typedef void (*cy_thread_entry_fn_t)(cy_thread_arg_t arg) ; + /** * The callback function to be called by a timeer */ -typedef void (*cy_timer_callback_t)(cy_timer_callback_arg_t arg) ; +typedef void (*cy_timer_callback_t)(cy_timer_callback_arg_t arg); /** \} group_abstraction_rtos_data_structures */ @@ -143,7 +177,7 @@ typedef void (*cy_timer_callback_t)(cy_timer_callback_arg_t arg) ; /** * Return the last error from the RTOS. - * + * * The functions in the RTOS abstraction layer adhere to the Cypress return * results calling convention. The underlying RTOS implementations will not but rather * will have their own error code conventions. This function is provided as a service @@ -152,22 +186,23 @@ typedef void (*cy_timer_callback_t)(cy_timer_callback_arg_t arg) ; * * @return RTOS specific error code. */ -extern cy_rtos_error_t cy_rtos_last_error() ; +extern cy_rtos_error_t cy_rtos_last_error(); /*********************************************** Threads **********************************************/ -/** Create a thread with specific thread argument. +/** Create a thread with specific thread argument. * - * This function is called to startup a new thread. If the thread can exit, it must call + * This function is called to startup a new thread. If the thread can exit, it must call * cy_rtos_finish_thread() just before doing so. All created threds that can terminate, either - * by themselves or forcefully by another thread MUST be joined in order to cleanup any resources + * by themselves or forcefully by another thread MUST be joined in order to cleanup any resources * that might have been allocated for them. * * @param[out] thread Pointer to a variable which will receive the new thread handle * @param[in] entry_function Function pointer which points to the main function for the new thread * @param[in] name String thread name used for a debugger - * @param[in] stack The buffer to use for the thread stack + * @param[in] stack The buffer to use for the thread stack. This must be aligned to + CY_RTOS_ALIGNMENT with a size of at least CY_RTOS_MIN_STACK_SIZE * @param[in] stack_size The size of the thread stack in bytes * @param[in] priority The priority of the thread. Values are operating system specific, but some * common priority levels are defined: @@ -178,15 +213,15 @@ extern cy_rtos_error_t cy_rtos_last_error() ; * * @return The status of thread create request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, +extern cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg); /** Exit the current thread. * * This function is called just before a thread exits. In some cases it is sufficient - * for a thread to just return to exit, but in other cases, the RTOS must be explicitly - * signaled. In cases where a return is sufficient, this should be a null funcition. + * for a thread to just return to exit, but in other cases, the RTOS must be explicitly + * signaled. In cases where a return is sufficient, this should be a null funcition. * where the RTOS must be signaled, this function should perform that In cases operation. * In code using RTOS services, this function should be placed at any at any location * where the main thread function will return, exiting the thread. Threads that can @@ -203,7 +238,7 @@ extern cy_rslt_t cy_rtos_exit_thread(); * by it thread. This should be called both when forcibly terminating another thread * as well as any time a thread can exit on its own. For some RTOS implementations * this is not required as the thread resoruces are claimed as soon as it exits. In - * other cases, this must be called to reclaim resources. Threads that are terminated + * other cases, this must be called to reclaim resources. Threads that are terminated * must still be joined (cy_rtos_join_thread) to ensure their resources are fully * cleaned up. * @@ -215,18 +250,29 @@ extern cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread); /** Checks if the thread is running * - * This function is called to determine if a thread is running or not. + * This function is called to determine if a thread is running or not. * * @param[in] thread handle of the terminated thread to delete - * @param[out] state returns true if the thread is running, otherwise false + * @param[out] running returns true if the thread is running, otherwise false * - * @returns The status of the thread check. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR] + * @returns The status of the thread running check. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *state) ; +extern cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *running); -/** Waits for a thread to complete. +/** Gets the state the thread is currently in + * + * This function is called to determine if a thread is running or not. + * + * @param[in] thread handle of the terminated thread to delete + * @param[out] state returns the state the thread is currently in * - * This must be called on any thread that can complete to ensure that any resources that + * @returns The status of the thread state check. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR] + */ +extern cy_rslt_t cy_rtos_get_thread_state(cy_thread_t *thread, cy_thread_state_t *state); + +/** Waits for a thread to complete. + * + * This must be called on any thread that can complete to ensure that any resources that * were allocated for it are cleaned up. * * @param[in] thread Handle of the thread to wait for @@ -239,7 +285,7 @@ extern cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread); /** Create a mutex. * - * This is basically a binary mutex which can be used to synchronize between threads + * This is basically a binary mutex which can be used to synchronize between threads * and between threads and ISRs. * * @param[out] mutex Pointer to the mutex handle to be initialized @@ -250,7 +296,7 @@ extern cy_rslt_t cy_rtos_init_mutex(cy_mutex_t *mutex); /** Get a mutex. * - * If the mutex is available, it is acquired and this function returned. + * If the mutex is available, it is acquired and this function returned. * If the mutex is not available, the thread waits until the mutex is available * or until the timeout occurs. * @@ -260,11 +306,11 @@ extern cy_rslt_t cy_rtos_init_mutex(cy_mutex_t *mutex); * @param[in] timeout_ms Maximum number of milliseconds to wait while attempting to get * the mutex. Use the NEVER_TIMEOUT constant to wait forever. Must * be zero is in_isr is true - * - * @return The status of the get mutex. Returns timeout if mutex was not acquired + * + * @return The status of the get mutex. Returns timeout if mutex was not acquired * before timeout_ms period. [CY_RSLT_SUCCESS, CY_RTOS_TIMEOUT] */ -extern cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms) ; +extern cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms); /** Set a mutex. * @@ -279,7 +325,7 @@ extern cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms) ; extern cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex); /** Deletes a mutex. - * + * * This function frees the resources associated with a sempahore. * * @param[in] mutex Pointer to the mutex handle @@ -306,7 +352,7 @@ extern cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxc /** * Get/Acquire a semaphore * - * If the semaphore count is zero, waits until the semaphore count is greater than zero. + * If the semaphore count is zero, waits until the semaphore count is greater than zero. * Once the semaphore count is greater than zero, this function decrements * the count and return. It may also return if the timeout is exceeded. * @@ -317,7 +363,7 @@ extern cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxc * @param[in] in_isr true if we are trying to get the semaphore from with an ISR * @return The status of get semaphore operation [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr) ; +extern cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr); /** * Set/Release a semaphore @@ -351,23 +397,23 @@ extern cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore); * * @param[in,out] event Pointer to the event handle to be initialized * - * @return The status of the event initialization request. + * @return The status of the event initialization request. * [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_init_event(cy_event_t *event) ; +extern cy_rslt_t cy_rtos_init_event(cy_event_t *event); /** Set the event flag bits. - * + * * This is an event which can be used to signal a set of threads * with a 32 bit data element. Any threads waiting on this event are released * * @param[in] event Pointer to the event handle - * @param[in] bits The value of the 32 bit flags + * @param[in] bits The value of the 32 bit flags * @param[in] in_isr If true, this is called from an ISR, otherwise from a thread * * @return The status of the set request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; +extern cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; /** * Clear the event flag bits @@ -380,7 +426,7 @@ extern cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in * * @return The status of the clear flags request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; +extern cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; /** Get the event bits. * @@ -391,13 +437,13 @@ extern cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool * * @return The status of the get request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits) ; +extern cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits); /** Wait for the event and return bits. * * Waits for the event to be set and then returns the bits assocaited - * with the event, or waits for the given timeout period. - * @note This function returns if any bit in the set is set. + * with the event, or waits for the given timeout period. + * @note This function returns if any bit in the set is set. * * @param[in] event Pointer to the event handle * @param[in,out] bits pointer to receive the value of the event flags @@ -409,7 +455,7 @@ extern cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits) ; * * @return The status of the wait for event request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout) ; +extern cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout); /** Deinitialize a event. * @@ -419,13 +465,13 @@ extern cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool * * @return The status of the deletion request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_deinit_event(cy_event_t *event) ; +extern cy_rslt_t cy_rtos_deinit_event(cy_event_t *event); /*********************************************** Queues **********************************************/ /** Create a queue. * - * This is a queue of data where entries are placed on the back of the queue + * This is a queue of data where entries are placed on the back of the queue * and removed from the front of the queue. * * @param[out] queue Pointer to the queue handle @@ -434,14 +480,14 @@ extern cy_rslt_t cy_rtos_deinit_event(cy_event_t *event) ; * * @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize) ; +extern cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize); /** Put an item in a queue. * * This function puts an item in the queue. The item is copied * into the queue using a memory copy and the data pointed to by item_ptr * is no longer referenced once the call returns. - * + * * @note If in_isr is true, timeout_ms must be zero. * * @param[in] queue Pointer to the queue handle @@ -451,14 +497,14 @@ extern cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t ite * * @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR, CY_RTOS_QUEUE_FULL] */ -extern cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr) ; +extern cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr); /** Gets an item in a queue. * * This function gets an item fropm the queue. The item is copied - * out of the queue into the memory provide by item_ptr. This space must be + * out of the queue into the memory provide by item_ptr. This space must be * large enough to hold a queue entry as defined when the queue was initialized. - * + * * @note If in_isr is true, timeout_ms must be zero. * * @param[in] queue Pointer to the queue handle @@ -468,52 +514,52 @@ extern cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_t * * @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR, CY_RTOS_QUEUE_EMPTY] */ -extern cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr) ; +extern cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr); /** Return the number of items in the queue. * * This function returns the number of items currently in the queue. - * + * * @param[in] queue Pointer to the queue handle * @param[out] num_waiting Pointer to the return count * * @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting) ; +extern cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting); /** Return the amount of empty space in the queue. * - * This function returns the amount of empty space in the + * This function returns the amount of empty space in the * queue. For instance, if the queue was created with 10 entries max and there * are currently 2 entries in the queue, this will return 8. - * + * * @param[in] queue Pointer to the queue handle * @param[out] num_spaces Pointer to the return count. * * @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces) ; +extern cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces); /** Reset the queue. * * This function sets the queue to empty. - * + * * @param[in] queue pointer to the queue handle * * @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue) ; +extern cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue); /** Deinitialize the queue handle. * * This function deinitializes the queue and returns all * resources used by the queue. - * + * * @param[in] queue Pointer to the queue handle * * @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue) ; +extern cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue); /*********************************************** Timers **********************************************/ @@ -521,7 +567,7 @@ extern cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue) ; * * This function intializes a timer object. @note The timer is * not active until start is called. - * + * * @param[out] timer Pointer to the timer handle to initalize * @param[in] type Type of timer (periodic or once) * @param[in] fun The functiuon @@ -529,19 +575,19 @@ extern cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue) ; * * @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, - cy_timer_callback_t fun, cy_timer_callback_arg_t arg) ; +extern cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, + cy_timer_callback_t fun, cy_timer_callback_arg_t arg); /** Start a timer. - * + * * @note The callback may be (likely will be) called from a different thread. - * + * * @param[in] timer Pointer to the timer handle * @param[in] num_ms The number of miliseconds to wait before the timer fires * * @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms) ; +extern cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms); /** Stop a timer. * @@ -549,7 +595,7 @@ extern cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms) ; * * @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer) ; +extern cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer); /** Returns state of a timer. * @@ -558,7 +604,7 @@ extern cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer) ; * * @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state) ; +extern cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state); /** Deinit the timer. * @@ -569,7 +615,7 @@ extern cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state) ; * * @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR] */ -extern cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer) ; +extern cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer); /*********************************************** Time **********************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/source/COMPONENT_RTX/cyabs_rtos_rtxv5.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/source/COMPONENT_RTX/cyabs_rtos_rtxv5.c index 9987673a0db..3bdf7d04c60 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/source/COMPONENT_RTX/cyabs_rtos_rtxv5.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/source/COMPONENT_RTX/cyabs_rtos_rtxv5.c @@ -76,7 +76,7 @@ static cy_rslt_t error_converter(cy_rtos_error_t internalError) * Threads ******************************************************/ -cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, +cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg) { cy_rslt_t status = CY_RSLT_SUCCESS; @@ -145,19 +145,54 @@ cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread) return status; } -cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *state) +cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *running) { cy_rslt_t status = CY_RSLT_SUCCESS; - if ((thread == NULL) || (state == NULL)) + if ((thread == NULL) || (running == NULL)) status = CY_RTOS_BAD_PARAM; else { - *state = (osThreadGetState(*thread) == osThreadRunning) ? true : false; + *running = (osThreadGetState(*thread) == osThreadRunning) ? true : false; } return status; +} + +cy_rslt_t cy_rtos_get_thread_state(cy_thread_t *thread, cy_thread_state_t *state) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + if ((thread == NULL) || (state == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + switch (osThreadGetState(*thread)) + { + case osThreadInactive: + *state = CY_THREAD_STATE_INACTIVE; + break; + case osThreadReady: + *state = CY_THREAD_STATE_READY; + break; + case osThreadRunning: + *state = CY_THREAD_STATE_RUNNING; + break; + case osThreadBlocked: + *state = CY_THREAD_STATE_BLOCKED; + break; + case osThreadTerminated: + *state = CY_THREAD_STATE_TERMINATED; + break; + case osThreadError: + case osThreadReserved: + default: + *state = CY_THREAD_STATE_UNKNOWN; + break; + } + } + + return status; } cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread) @@ -198,9 +233,9 @@ cy_rslt_t cy_rtos_init_mutex(cy_mutex_t *mutex) { attr.name = NULL; attr.attr_bits = osMutexRecursive | osMutexPrioInherit; - attr.cb_mem = malloc(osRtxMutexCbSize); + attr.cb_mem = malloc(osRtxMutexCbSize); attr.cb_size = osRtxMutexCbSize; - + if (attr.cb_mem == NULL) status = CY_RTOS_NO_MEMORY; else @@ -216,14 +251,14 @@ cy_rslt_t cy_rtos_init_mutex(cy_mutex_t *mutex) } cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms) -{ +{ cy_rslt_t status; cy_rtos_error_t statusInternal; if (mutex == NULL) status = CY_RTOS_BAD_PARAM; else - { + { statusInternal = osMutexAcquire(*mutex, timeout_ms); status = error_converter(statusInternal); } @@ -285,9 +320,9 @@ cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, u { attr.name = NULL; attr.attr_bits = 0U; - attr.cb_mem = malloc(osRtxSemaphoreCbSize); + attr.cb_mem = malloc(osRtxSemaphoreCbSize); attr.cb_size = osRtxSemaphoreCbSize; - + if (attr.cb_mem == NULL) status = CY_RTOS_NO_MEMORY; else @@ -316,7 +351,7 @@ cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, statusInternal = osSemaphoreAcquire(*semaphore, timeout_ms); else statusInternal = osErrorISR; - + status = error_converter(statusInternal); } @@ -380,9 +415,9 @@ cy_rslt_t cy_rtos_init_event(cy_event_t *event) { attr.name = NULL; attr.attr_bits = 0U; - attr.cb_mem = malloc(osRtxEventFlagsCbSize); + attr.cb_mem = malloc(osRtxEventFlagsCbSize); attr.cb_size = osRtxEventFlagsCbSize; - + if (attr.cb_mem == NULL) status = CY_RTOS_NO_MEMORY; else @@ -509,7 +544,7 @@ cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize) attr.cb_size = osRtxMessageQueueCbSize; uint32_t blockSize = ((itemsize + 3U) & ~3UL) + sizeof(osRtxMessage_t); attr.mq_size = blockSize * length; - + /* Note: 1 malloc for both so that they can be freed with 1 call */ uint32_t cb_mem_pad = (8 - (osRtxMessageQueueCbSize & 0x07)) & 0x07; attr.cb_mem = malloc(osRtxMessageQueueCbSize + cb_mem_pad + attr.mq_size); @@ -545,7 +580,7 @@ cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t t statusInternal = osMessageQueuePut(*queue, (uint8_t *)item_ptr, 0u, timeout_ms); else statusInternal = osErrorISR; - + status = error_converter(statusInternal); } @@ -566,7 +601,7 @@ cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout statusInternal = osMessageQueueGet(*queue, (uint8_t *)item_ptr, 0u, timeout_ms); else statusInternal = osErrorISR; - + status = error_converter(statusInternal); } @@ -594,7 +629,7 @@ cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces) else *num_spaces = osMessageQueueGetSpace(*queue); - return status; + return status; } cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue) @@ -610,7 +645,7 @@ cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue) status = error_converter(statusInternal); } - return status; + return status; } cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue) @@ -624,7 +659,7 @@ cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue) { statusInternal = osMessageQueueDelete(*queue); status = error_converter(statusInternal); - + if (status == CY_RSLT_SUCCESS) { free(*queue); @@ -632,7 +667,7 @@ cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue) } } - return status; + return status; } @@ -640,7 +675,7 @@ cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue) * Timers ******************************************************/ -cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, +cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, cy_timer_callback_t fun, cy_timer_callback_arg_t arg) { cy_rslt_t status; @@ -659,7 +694,7 @@ cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, status = CY_RTOS_NO_MEMORY; else { - osTimerType_t osTriggerType = (cy_timer_type_periodic == type) + osTimerType_t osTriggerType = (CY_TIMER_TYPE_PERIODIC == type) ? osTimerPeriodic : osTimerOnce; @@ -696,7 +731,7 @@ cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms) status = CY_RTOS_GENERAL_ERROR; } - return status; + return status; } cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer) @@ -712,7 +747,7 @@ cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer) status = error_converter(statusInternal); } - return status; + return status; } cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state) @@ -724,7 +759,7 @@ cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state) else *state = osTimerIsRunning(*timer); - return status; + return status; } cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer) @@ -746,7 +781,7 @@ cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer) } } - return status; + return status; } @@ -773,7 +808,7 @@ cy_rslt_t cy_rtos_get_time(cy_time_t *tval) status = CY_RTOS_GENERAL_ERROR; } - return status; + return status; } cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms) @@ -784,7 +819,7 @@ cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms) statusInternal = osDelay(num_ms); status = error_converter(statusInternal); - return status; + return status; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/source/cyabs_resource.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/source/cyabs_resource.c index c128261d41f..713420d9e4c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/source/cyabs_resource.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/source/cyabs_resource.c @@ -1,5 +1,5 @@ /***************************************************************************//** -* \file cy_resource_access.c +* \file cyabs_resource.c * * \brief * Provides API for reading data from resource files however they are stored. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h index 1887e37e955..d80830b9073 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h @@ -108,7 +108,7 @@ extern "C" { /** Base identifier for environment abstraction modules */ #define CY_RSLT_MODULE_ABSTRACTION_ENV (0x0184U) -/**** Middleware Module codes: 0x0200 - 0x02FF ****/ +/** Middleware Module codes: 0x0200 - 0x02FF */ #define CY_RSLT_MODULE_MIDDLEWARE_BASE (0x0200U) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_utils.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_utils.h index c96cd8bdcfa..30a99344c1e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_utils.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_utils.h @@ -45,6 +45,9 @@ extern "C" { /** Simple macro to supress the unused parameter warning by casting to void. */ #define CY_UNUSED_PARAMETER(x) ( (void)(x) ) +/** Halt the processor in the debug state + * @return + */ static inline uint32_t CY_HALT() { __asm(" bkpt 1"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h index 0d6f6d15698..29891e4a9cd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h @@ -6,10 +6,15 @@ * will pull in all of the specific HAL files needed. Not all of these may be * supported in the target device. The target device must provide a * cyhal_hw_types.h file that is in the include path for the hal headers to -* depend on. The cyhal_hw_types.h file must provide definitions for each of -* the resource types consumed by the HAL driver functions. Additionally, the -* implementation may define a cyhal_implementation.h file that provides any -* custom includes. This file is optional per implementation. +* depend on. The cyhal_hw_types.h file must provide the following: +* 1) definitions for each of the resource types consumed by the HAL driver +* functions. +* 2) A CYHAL_ISR_PRIORITY_DEFAULT define for the default interrupt priority +* 3) A CYHAL_MAIN_FLASH_BASE define for the base address of flash memory +* 4) OPTIONAL: Implementation specific header files can be used by creating +* a #define in cyhal_hw_types.h with a name of CYHAL__IMPL_HEADER +* and the value being the name of the header file. eg: +* #define CYHAL_GPIO_IMPL_HEADER "cyhal_gpio_impl.h" * ******************************************************************************** * \copyright @@ -39,21 +44,18 @@ #pragma once +#include "cyhal_modules.h" +#include "cyhal_hw_types.h" + #include "cyhal_adc.h" -#include "cyhal_comp.h" #include "cyhal_crc.h" -#include "cyhal_crc_impl.h" #include "cyhal_dac.h" -#include "cyhal_dma.h" #include "cyhal_flash.h" #include "cyhal_gpio.h" #include "cyhal_hwmgr.h" #include "cyhal_i2c.h" -#include "cyhal_i2s.h" #include "cyhal_interconnect.h" #include "cyhal_lptimer.h" -#include "cyhal_opamp.h" -#include "cyhal_pdmpcm.h" #include "cyhal_pwm.h" #include "cyhal_qspi.h" #include "cyhal_rtc.h" @@ -65,6 +67,7 @@ #include "cyhal_trng.h" #include "cyhal_uart.h" #include "cyhal_usb_dev.h" +#include "cyhal_wdt.h" /** \} group_hal */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h index 1d071b18558..ea60e0d7216 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h @@ -44,7 +44,7 @@ #include #include "cy_result.h" #include "cyhal_hw_types.h" -#include "cyhal_hwmgr.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { @@ -56,7 +56,7 @@ extern "C" { */ /** Maximum value that the ADC can return */ -#define CYHAL_ADC_MAX_VALUE 0x0FFF +#define CYHAL_ADC_MAX_VALUE 0xFFFF /** Bad argument */ #define CYHAL_ADC_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_ADC, 0)) @@ -75,22 +75,22 @@ extern "C" { * \{ */ -/** Initialize adc peripheral +/** Initialize ADC peripheral * * @param[out] obj The adc object to initialize * @param[in] pin A pin corresponding to the ADC block to initialize * Note: This pin is not reserved, it is just used to identify which ADC block to allocate. * If multiple channels will be allocated for a single ADC instance, only one pin should be - * passed here; it does not matter which one. After calling this function once, call + * passed here; it does not matter which one. After calling this function once, call * cyhal_adc_channel_init once for each pin whose value should be measured. * @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated * @return The status of the init request */ cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_divider_t *clk); -/** Uninitialize the adc peripheral and cyhal_adc_t object +/** Uninitialize the ADC peripheral and cyhal_adc_t object * - * @param[in,out] obj The adc object + * @param[in,out] obj The ADC object */ void cyhal_adc_free(cyhal_adc_t *obj); @@ -101,9 +101,9 @@ void cyhal_adc_free(cyhal_adc_t *obj); * \{ */ -/** Initialize a single-ended adc channel. +/** Initialize a single-ended ADC channel. * - * Configures the pin used by adc. + * Configures the pin used by ADC. * @param[out] obj The adc channel object to initialize * @param[in] adc The adc for which the channel should be initialized * @param[in] pin The adc pin name @@ -111,17 +111,17 @@ void cyhal_adc_free(cyhal_adc_t *obj); */ cy_rslt_t cyhal_adc_channel_init(cyhal_adc_channel_t *obj, cyhal_adc_t* adc, cyhal_gpio_t pin); -/** Uninitialize the adc channel and cyhal_adc_channel_t object +/** Uninitialize the ADC channel and cyhal_adc_channel_t object * - * @param[in,out] obj The adc channel object + * @param[in,out] obj The ADC channel object */ void cyhal_adc_channel_free(cyhal_adc_channel_t *obj); -/** Read the value from adc pin, represented as an unsigned 16bit value +/** Read the value from ADC pin, represented as an unsigned 16bit value * where 0x0000 represents the minimum value in the ADC's range, and 0xFFFF * represents the maximum value in the ADC's range. * - * @param[in] obj The adc object + * @param[in] obj The ADC object * @return An unsigned 16bit value representing the current input voltage */ uint16_t cyhal_adc_read_u16(const cyhal_adc_channel_t *obj); @@ -132,4 +132,8 @@ uint16_t cyhal_adc_read_u16(const cyhal_adc_channel_t *obj); } #endif +#ifdef CYHAL_ADC_IMPL_HEADER +#include CYHAL_ADC_IMPL_HEADER +#endif /* CYHAL_ADC_IMPL_HEADER */ + /** \} group_hal_adc */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h index 88ddd62e10e..b42549ef4df 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h @@ -2,7 +2,7 @@ * \file cyhal_crc.h * * \brief -* Provides a high level interface for interacting with the Cypress CRC. +* Provides a high level interface for interacting with the Cypress CRC accelerator. * This interface abstracts out the chip specific details. If any chip specific * functionality is necessary, or performance is critical the low level functions * can be used directly. @@ -43,6 +43,7 @@ #include #include "cy_result.h" #include "cyhal_hw_types.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { @@ -77,8 +78,8 @@ typedef struct * If 0, data is processed MSB first. * If 1, data is processed LSB first. */ - uint8_t dataReverse; - uint8_t remReverse; //!< If 1, the remainder is reversed. If 0, it is not. + bool dataReverse; + bool remReverse; //!< If 1, the remainder is reversed. If 0, it is not. } crc_algorithm_t; /** \} group_hal_crc_data_structures */ @@ -136,4 +137,8 @@ cy_rslt_t cyhal_crc_finish(const cyhal_crc_t *obj, uint32_t *crc); } #endif +#ifdef CYHAL_CRC_IMPL_HEADER +#include CYHAL_CRC_IMPL_HEADER +#endif /* CYHAL_CRC_IMPL_HEADER */ + /** \} group_hal_crc */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h index cf386e4d0cb..3ab58d2ba00 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h @@ -1,9 +1,9 @@ -/***************************************************************************//** -* \file cyhal_crc_impl.h +/***************************************************************************//** + * \file cyhal_crc_impl.h * * Description: -* Provides a high level interface for interacting with the Cypress GPIO. This is -* a wrapper around the lower level PDL API. +* Provides a high level interface for interacting with the Cypress CRC accelerator. +* This is a wrapper around the lower level PDL API. * ******************************************************************************** * \copyright @@ -35,27 +35,31 @@ extern "C" { #endif /* __cplusplus */ +// This helper function mirrors the definition of cyhal_crc_start __STATIC_INLINE cy_rslt_t cyhal_crc_start_internal(cyhal_crc_t *obj, const crc_algorithm_t *algorithm) { - if(NULL == obj || NULL == algorithm) + CY_ASSERT(NULL != obj); + if(NULL == algorithm) return CYHAL_CRC_RSLT_ERR_BAD_ARGUMENT; obj->crc_width = algorithm->width; return Cy_Crypto_Core_Crc_CalcInit(obj->base, algorithm->width, algorithm->polynomial, - algorithm->dataReverse, + algorithm->dataReverse ? 1u : 0u, algorithm->dataXor, - algorithm->remReverse, + algorithm->remReverse ? 1u : 0u, algorithm->remXor, algorithm->lfsrInitState); } #define cyhal_crc_start(obj, algorithm) cyhal_crc_start_internal(obj, algorithm) +// This helper function mirrors the definition of cyhal_crc_compute __STATIC_INLINE cy_rslt_t cyhal_crc_compute_internal(const cyhal_crc_t *obj, const uint8_t *data, size_t length) { - if(NULL == obj || NULL == data || 0 == length) + CY_ASSERT(NULL != obj); + if(NULL == data || 0 == length) return CYHAL_CRC_RSLT_ERR_BAD_ARGUMENT; return Cy_Crypto_Core_Crc_CalcPartial(obj->base, data, length); @@ -63,9 +67,11 @@ __STATIC_INLINE cy_rslt_t cyhal_crc_compute_internal(const cyhal_crc_t *obj, con #define cyhal_crc_compute(obj, data, length) cyhal_crc_compute_internal(obj, data, length) +// This helper function mirrors the definition of cyhal_crc_finish __STATIC_INLINE cy_rslt_t cyhal_crc_finish_internal(const cyhal_crc_t *obj, uint32_t *crc) { - if(NULL == obj || NULL == crc) + CY_ASSERT(NULL != obj); + if(NULL == crc) return CYHAL_CRC_RSLT_ERR_BAD_ARGUMENT; return Cy_Crypto_Core_Crc_CalcFinish(obj->base, obj->crc_width, crc); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h index 8e26a3d0822..df7bd3898db 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h @@ -2,8 +2,8 @@ * \file cyhal_crypto_common.h * * Description: -* This file provides common defines and addresses required by drivers using the -* Crypto block. +* This file provides common defines, addresses, and functions required by drivers +* using the Crypto block. * ******************************************************************************** * \copyright @@ -39,23 +39,34 @@ extern "C" { /** Block count for CRYPTO blocks */ #define CYHAL_CRYPTO_INST_COUNT CY_IP_MXCRYPTO_INSTANCES -/** The start address of the CRYPTO blocks */ -extern CRYPTO_Type* cyhal_CRYPTO_BASE_ADDRESSES[CYHAL_CRYPTO_INST_COUNT]; +typedef enum +{ + /** CRC hardware acceleration */ + CYHAL_CRYPTO_CRC, + /** TRNG hardware acceleration */ + CYHAL_CRYPTO_TRNG, + /** VU hardware acceleration */ + CYHAL_CRYPTO_VU, + /** Common features of the Crypto block */ + CYHAL_CRYPTO_COMMON, +} cyhal_crypto_feature_t; /** Reserve the Crypto block and enable it. * * @param[out] base Base address to the Crypto block. - * @param[out] obj resource inst for the function (eg. CRC, TRNG) in the Crypto block. + * @param[out] obj Resource inst for the function (eg. CRC, TRNG) in the Crypto block. + * @param[in] feature feature to reserve on the Crypto block (eg. TRNG, CRC, etc.). * @return The status of the reserve request. */ -cy_rslt_t cyhal_crypto_reserve(CRYPTO_Type** base, cyhal_resource_inst_t *resource); +cy_rslt_t cyhal_crypto_reserve(CRYPTO_Type** base, cyhal_resource_inst_t *resource, cyhal_crypto_feature_t feature); /** Free the Crypto block and disable it. * * @param[in] base Base address to the Crypto block. - * @param[in] obj resource inst for the funtion in Crypto block. + * @param[in] obj Resource inst for the funtion in Crypto block. + * @param[in] feature Feature to free on the Crypto block (eg. TRNG, CRC, etc.). */ -void cyhal_crypto_free(CRYPTO_Type* base, const cyhal_resource_inst_t *resource); +void cyhal_crypto_free(CRYPTO_Type* base, cyhal_resource_inst_t *resource, cyhal_crypto_feature_t feature); #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h index 685b69cb3f8..900944823bc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h @@ -43,7 +43,7 @@ #include #include "cy_result.h" #include "cyhal_hw_types.h" -#include "cyhal_hwmgr.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { @@ -67,7 +67,7 @@ extern "C" { * \{ */ -/** Initialize the dac peripheral +/** Initialize the DAC peripheral * * Configures the pin used by dac. * @param[in] obj The dac object to initialize @@ -91,10 +91,10 @@ void cyhal_dac_free(cyhal_dac_t *obj); */ void cyhal_dac_write(const cyhal_dac_t *obj, uint16_t value); -/** Read the current DAC output voltage setting, as a normalized unsigned +/** Read the current DAC output voltage setting, as a normalized unsigned * 16-bit value (where 0 is the lowest value the DAC can output and 0xFFFF * is the highest). - * Note: Depending on the precision of the underlying hardware, this may not + * Note: Depending on the precision of the underlying hardware, this may not * precisely match the most recent value passed in to cyhal_dac_write. * * @param[in] obj The dac object @@ -108,4 +108,8 @@ uint16_t cyhal_dac_read(cyhal_dac_t *obj); } #endif +#ifdef CYHAL_DAC_IMPL_HEADER +#include CYHAL_DAC_IMPL_HEADER +#endif /* CYHAL_DAC_IMPL_HEADER */ + /** \} group_hal_dac */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h index 8b236c22b5e..a1875d5fd4e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h @@ -44,6 +44,7 @@ #include #include "cy_result.h" #include "cyhal_hw_types.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { @@ -64,14 +65,21 @@ extern "C" { * \{ */ -/** Information about a flash memory */ +/** Information about a single block of flash memory */ typedef struct { uint32_t start_address; //!< Start address of the memory - uint32_t size; //!< Size of the flash memory - uint32_t sector_size; //!< Sector size of the memory - uint32_t page_size; //!< Sector size of the memory - uint8_t erase_value; //!< The flash erase value + uint32_t size; //!< Size of the flash memory + uint32_t sector_size; //!< Sector size of the memory + uint32_t page_size; //!< Sector size of the memory + uint8_t erase_value; //!< The flash erase value +} cyhal_flash_block_info_t; + +/** Information about all of the blocks of flash memory */ +typedef struct +{ + uint8_t block_count; //!< The number of distinct flash blocks + const cyhal_flash_block_info_t *blocks; //!< Array of the distinct flash blocks } cyhal_flash_info_t; /** \} group_hal_flash_data_structures */ @@ -86,20 +94,20 @@ typedef struct * \{ */ -/** Initialize the flash peripheral and the flash_t object +/** Initialize the flash_t object for access to flash through the HAL * * @param[out] obj The flash object * @return The status of the init request */ cy_rslt_t cyhal_flash_init(cyhal_flash_t *obj); -/** Uninitialize the flash peripheral and the flash_t object +/** Free resources associated with access to flash through the HAL * * @param[out] obj The flash object. */ void cyhal_flash_free(cyhal_flash_t *obj); -/** Gets key flash charactoristics including the start address size, +/** Gets key flash characteristics including the start address size, * and erase values * * @param[in] obj The flash object. @@ -131,6 +139,7 @@ cy_rslt_t cyhal_flash_erase(cyhal_flash_t *obj, uint32_t address); /** Write one page starting at defined address. The address must be at page boundary. This * will block until the write operation is complete. + * This function erases the page prior to writing the new data. * * @see cyhal_flash_get_info() to get the flash charactoristics for legal address values and * the total write size. The provided data buffer must be at least as large as the flash @@ -145,6 +154,8 @@ cy_rslt_t cyhal_flash_write(cyhal_flash_t *obj, uint32_t address, const uint32_t /** Program one page starting at defined address. The address must be at page boundary. This * will block until the write operation is complete. + * Note: This function does not erase the page prior to writing. The page must be erased + * first via a separate call to erase. * * @see cyhal_flash_get_info() to get the flash charactoristics for legal address values and * the total program size. The provided data buffer must be at least as large as the flash @@ -212,4 +223,8 @@ bool cyhal_flash_is_operation_complete(cyhal_flash_t *obj); } #endif +#ifdef CYHAL_FLASH_IMPL_HEADER +#include CYHAL_FLASH_IMPL_HEADER +#endif /* CYHAL_FLASH_IMPL_HEADER */ + /** \} group_hal_flash */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h index 61d6f1deec0..c19b8cabd2d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h @@ -2,7 +2,7 @@ * \file cyhal_gpio.h * * \brief -* Provides a high level interface for interacting with the Cypress GPIO. +* Provides a high level interface for interacting with the GPIO on Cypress devices. * This interface abstracts out the chip specific details. If any chip specific * functionality is necessary, or performance is critical the low level functions * can be used directly. @@ -72,30 +72,31 @@ extern "C" { * Enumerations *******************************************************************************/ -/** Pin IRQ events */ +/** Pin events */ typedef enum { - CYHAL_GPIO_IRQ_NONE = 0, /**< No interrupt */ - CYHAL_GPIO_IRQ_RISE = 1, /**< Interrupt on rising edge */ - CYHAL_GPIO_IRQ_FALL = 2, /**< Interrupt on falling edge */ - CYHAL_GPIO_IRQ_BOTH = 3, /**< Interrupt on both rising and falling edges */ -} cyhal_gpio_irq_event_t; + CYHAL_GPIO_IRQ_NONE, /**< No interrupt */ + CYHAL_GPIO_IRQ_RISE, /**< Interrupt on rising edge */ + CYHAL_GPIO_IRQ_FALL, /**< Interrupt on falling edge */ + CYHAL_GPIO_IRQ_BOTH, /**< Interrupt on both rising and falling edges */ +} cyhal_gpio_event_t; /** Pin direction */ typedef enum { - CYHAL_GPIO_DIR_INPUT = 0, /**< Input pin */ - CYHAL_GPIO_DIR_OUTPUT = 1, /**< Output pin */ - CYHAL_GPIO_DIR_BIDIRECTIONAL = 2, /**< Input and output pin */ + CYHAL_GPIO_DIR_INPUT, /**< Input pin */ + CYHAL_GPIO_DIR_OUTPUT, /**< Output pin */ + CYHAL_GPIO_DIR_BIDIRECTIONAL, /**< Input and output pin */ } cyhal_gpio_direction_t; /** Pin drive mode */ typedef enum { - CYHAL_GPIO_DRIVE_ANALOG = 0, /**< Analog Hi-Z */ - CYHAL_GPIO_DRIVE_PULLUP = 2, /**< Pull-up resistor */ - CYHAL_GPIO_DRIVE_PULLDOWN = 3, /**< Pull-down resistor */ - CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW = 4, /**< Open-drain, Drives Low */ - CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH = 5, /**< Open-drain, Drives High */ - CYHAL_GPIO_DRIVE_STRONG = 6, /**< Strong output */ - CYHAL_GPIO_DRIVE_PULLUPDOWN = 7, /**< Pull-up and pull-down resistors */ + CYHAL_GPIO_DRIVE_NONE, /**< No drive; Hi-Z */ + CYHAL_GPIO_DRIVE_ANALOG, /**< Analog Hi-Z */ + CYHAL_GPIO_DRIVE_PULLUP, /**< Pull-up resistor */ + CYHAL_GPIO_DRIVE_PULLDOWN, /**< Pull-down resistor */ + CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW, /**< Open-drain, Drives Low */ + CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH, /**< Open-drain, Drives High */ + CYHAL_GPIO_DRIVE_STRONG, /**< Strong output */ + CYHAL_GPIO_DRIVE_PULLUPDOWN, /**< Pull-up and pull-down resistors */ } cyhal_gpio_drive_mode_t; /** \} group_hal_gpio_enums */ @@ -107,7 +108,7 @@ typedef enum { */ /** GPIO callback function type */ -typedef void (*cyhal_gpio_irq_handler_t)(void *handler_arg, cyhal_gpio_irq_event_t event); +typedef void (*cyhal_gpio_event_callback_t)(void *callback_arg, cyhal_gpio_event_t event); /** \} group_hal_gpio_data_structures */ @@ -123,10 +124,10 @@ typedef void (*cyhal_gpio_irq_handler_t)(void *handler_arg, cyhal_gpio_irq_event /** Initialize the GPIO pin * - * @param[in] pin The GPIO pin to initialize - * @param[in] direction The pin direction (input/output) - * @param[in] drvMode The pin drive mode - * @param[in] initVal Initial value on the pin + * @param[in] pin The GPIO pin to initialize + * @param[in] direction The pin direction + * @param[in] drvMode The pin drive mode + * @param[in] initVal Initial value on the pin * * @return The status of the init request */ @@ -138,22 +139,15 @@ cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cy */ void cyhal_gpio_free(cyhal_gpio_t pin); -/** Set the pin direction +/** Configure the GPIO pin * - * @param[in] pin The pin number - * @param[in] direction The pin direction to be set - * @return The status of the dir request - */ -cy_rslt_t cyhal_gpio_direction(cyhal_gpio_t pin, cyhal_gpio_direction_t direction); - -/** Set the input pin mode + * @param[in] pin The GPIO pin + * @param[in] direction The pin direction + * @param[in] drvMode The pin drive mode * - * @param[in] pin The GPIO object - * @param[in] drvMode The pin mode to be set - * - * @return The status of the mode request + * @return The status of the configure request */ -cy_rslt_t cyhal_gpio_drivemode(cyhal_gpio_t pin, cyhal_gpio_drive_mode_t drvMode); +cy_rslt_t cyhal_gpio_configure(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode); /** Set the output value for the pin. This only works for output & in_out pins. * @@ -175,27 +169,41 @@ bool cyhal_gpio_read(cyhal_gpio_t pin); */ void cyhal_gpio_toggle(cyhal_gpio_t pin); -/** Register/clear an interrupt handler for the pin toggle pin IRQ event +/** Register/clear a callback handler for pin events * - * @param[in] pin The pin number - * @param[in] intrPriority The NVIC interrupt channel priority - * @param[in] handler The function to call when the specified event happens - * @param[in] handler_arg Generic argument that will be provided to the handler when called + * @param[in] pin The pin number + * @param[in] callback The function to call when the specified event happens. Pass NULL to unregister the handler. + * @param[in] callback_arg Generic argument that will be provided to the callback when called, can be NULL */ -void cyhal_gpio_register_irq(cyhal_gpio_t pin, uint8_t intrPriority, cyhal_gpio_irq_handler_t handler, void *handler_arg); +void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t callback, void *callback_arg); -/** Enable or Disable the GPIO IRQ +/** Enable or Disable the specified GPIO event * - * @param[in] pin The GPIO object - * @param[in] event The GPIO IRQ event - * @param[in] enable True to turn on interrupts, False to turn off + * @param[in] pin The GPIO object + * @param[in] event The GPIO event + * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off */ -void cyhal_gpio_irq_enable(cyhal_gpio_t pin, cyhal_gpio_irq_event_t event, bool enable); +void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intrPriority, bool enable); /** \} group_hal_gpio_functions */ +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +#define cyhal_gpio_register_irq(pin, priority, handler, handler_arg) cyhal_gpio_register_callback(pin, handler, handler_arg) +#define cyhal_gpio_irq_enable(pin, event, enable) cyhal_gpio_enable_event(pin, event, CYHAL_ISR_PRIORITY_DEFAULT, enable) +typedef cyhal_gpio_event_t cyhal_gpio_irq_event_t; +/** \endcond */ + #ifdef __cplusplus } #endif /* __cplusplus */ +#ifdef CYHAL_GPIO_IMPL_HEADER +#include CYHAL_GPIO_IMPL_HEADER +#endif /* CYHAL_GPIO_IMPL_HEADER */ + /** \} group_hal_gpio */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h index cbc50484b6d..a4f1c0ccbc2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h @@ -54,7 +54,7 @@ typedef enum CYHAL_RSC_CAN, /*!< CAN communication block */ CYHAL_RSC_CLKPATH, /*!< System clock clock path, used to drive hfclks */ CYHAL_RSC_CLOCK, /*!< Clock divider */ - CYHAL_RSC_CRC, /*!< CRC hardware accelerator */ + CYHAL_RSC_CRYPTO, /*!< Crypto hardware accelerator */ CYHAL_RSC_DAC, /*!< Digital to analog converter */ CYHAL_RSC_DMA, /*!< DMA controller */ CYHAL_RSC_GPIO, /*!< General purpose I/O pin */ @@ -65,7 +65,6 @@ typedef enum CYHAL_RSC_OPAMP, /*!< Opamp */ CYHAL_RSC_PDM, /*!< PCM/PDM communications block */ CYHAL_RSC_SMIF, /*!< Quad-SPI communications block */ - CYHAL_RSC_TRNG, /*!< Hardware random number generator */ CYHAL_RSC_RTC, /*!< Real time clock */ CYHAL_RSC_SCB, /*!< Serial Communications Block */ CYHAL_RSC_SDHC, /*!< SD Host Controller */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h index 6bbb218aca7..da78744306f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h @@ -29,9 +29,7 @@ * Struct definitions for configuration resources in the PDL. * * \defgroup group_hal_hw_types_macros Macros -* \defgroup group_hal_hw_types_functions Functions * \defgroup group_hal_hw_types_data_structures Data Structures -* \defgroup group_hal_hw_types_enums Enumerated Types */ #pragma once @@ -49,6 +47,25 @@ extern "C" { #endif +/** +* \addtogroup group_hal_hw_types_macros +* \{ +*/ + +/** Default priority for interrupts */ +#ifndef CYHAL_ISR_PRIORITY_DEFAULT +#define CYHAL_ISR_PRIORITY_DEFAULT (7) +#endif + +#define CYHAL_CRC_IMPL_HEADER "cyhal_crc_impl.h" //!< Implementation specific header for CRC +#define CYHAL_GPIO_IMPL_HEADER "cyhal_gpio_impl.h" //!< Implementation specific header for GPIO +#define CYHAL_PWM_IMPL_HEADER "cyhal_pwm_impl.h" //!< Implementation specific header for PWM +#define CYHAL_SYSTEM_IMPL_HEADER "cyhal_system_impl.h" //!< Implementation specific header for System +#define CYHAL_TIMER_IMPL_HEADER "cyhal_timer_impl.h" //!< Implementation specific header for Timer +#define CYHAL_TRNG_IMPL_HEADER "cyhal_trng_impl.h" //!< Implementation specific header for TRNG + +/** \} group_hal_hw_types_macros */ + /** * \addtogroup group_hal_hw_types_data_structures * \{ @@ -66,6 +83,12 @@ typedef struct { uint8_t div_num; } cyhal_clock_divider_t; +/** Event callback data object */ +typedef struct { + cy_israddress callback; + void* callback_arg; +} cyhal_event_callback_data_t; + /** ADC object */ typedef struct { @@ -74,9 +97,9 @@ typedef struct { cyhal_resource_inst_t resource; cyhal_clock_divider_t clock; bool dedicated_clock; - // channel_used is a bit field. The maximum channel count + // channel_used is a bit field. The maximum channel count // supported by the SAR IP is 16 - uint16_t channel_used; + uint16_t channel_used; #else void *empty; #endif @@ -155,8 +178,7 @@ typedef struct { uint32_t irq_cause; uint16_t pending; uint16_t events; - uint32_t handler; - + cyhal_event_callback_data_t callback_data; #else void *empty; #endif @@ -175,8 +197,9 @@ typedef struct { /** LPTIMER object */ typedef struct { #ifdef CY_IP_MXS40SRSS_MCWDT_INSTANCES - MCWDT_STRUCT_Type *base; - cyhal_resource_inst_t resource; + MCWDT_STRUCT_Type *base; + cyhal_resource_inst_t resource; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif @@ -205,12 +228,13 @@ typedef struct { /** PWM object */ typedef struct { #ifdef CY_IP_MXTCPWM - TCPWM_Type* base; - cyhal_resource_inst_t resource; - cyhal_gpio_t pin; - cyhal_clock_divider_t clock; - uint32_t clock_hz; - bool dedicated_clock; + TCPWM_Type* base; + cyhal_resource_inst_t resource; + cyhal_gpio_t pin; + cyhal_clock_divider_t clock; + uint32_t clock_hz; + bool dedicated_clock; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif @@ -219,24 +243,18 @@ typedef struct { /** SMIF object */ typedef struct { #ifdef CY_IP_MXSMIF - SMIF_Type* base; - cyhal_resource_inst_t resource; - cyhal_gpio_t pin_io0; - cyhal_gpio_t pin_io1; - cyhal_gpio_t pin_io2; - cyhal_gpio_t pin_io3; - cyhal_gpio_t pin_io4; - cyhal_gpio_t pin_io5; - cyhal_gpio_t pin_io6; - cyhal_gpio_t pin_io7; - cyhal_gpio_t pin_sclk; - cyhal_gpio_t pin_ssel; - uint32_t frequency; - uint8_t mode; - cy_stc_smif_context_t context; - cy_en_smif_slave_select_t slave_select; - cy_en_smif_data_select_t data_select; - uint32_t irq_cause; + SMIF_Type* base; + cyhal_resource_inst_t resource; + cyhal_gpio_t pin_ios[8]; + cyhal_gpio_t pin_sclk; + cyhal_gpio_t pin_ssel; + uint32_t frequency; + uint8_t mode; + cy_stc_smif_context_t context; + cy_en_smif_slave_select_t slave_select; + cy_en_smif_data_select_t data_select; + uint32_t irq_cause; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif /* ifdef CY_IP_MXSMIF */ @@ -258,28 +276,23 @@ typedef struct { /** SDHC object */ typedef struct { #ifdef CY_IP_MXSDHC - SDHC_Type* base; - cyhal_resource_inst_t resource; - bool emmc; - cy_en_sd_host_dma_type_t dmaType; - bool enableLedControl; - cy_stc_sd_host_context_t context; - cyhal_gpio_t pin_clk; - cyhal_gpio_t pin_cmd; - cyhal_gpio_t pin_data0; - cyhal_gpio_t pin_data1; - cyhal_gpio_t pin_data2; - cyhal_gpio_t pin_data3; - cyhal_gpio_t pin_data4; - cyhal_gpio_t pin_data5; - cyhal_gpio_t pin_data6; - cyhal_gpio_t pin_data7; - cyhal_gpio_t pin_cardDetect; - cyhal_gpio_t pin_ioVoltSel; - cyhal_gpio_t pin_cardIfPwrEn; - cyhal_gpio_t pin_cardMechWriteProt; - cyhal_gpio_t pin_ledCtrl; - cyhal_gpio_t pin_cardEmmcReset; + SDHC_Type* base; + cyhal_resource_inst_t resource; + bool emmc; + cy_en_sd_host_dma_type_t dmaType; + bool enableLedControl; + cy_stc_sd_host_context_t context; + cyhal_gpio_t pin_clk; + cyhal_gpio_t pin_cmd; + cyhal_gpio_t pin_data[8]; + cyhal_gpio_t pin_cardDetect; + cyhal_gpio_t pin_ioVoltSel; + cyhal_gpio_t pin_cardIfPwrEn; + cyhal_gpio_t pin_cardMechWriteProt; + cyhal_gpio_t pin_ledCtrl; + cyhal_gpio_t pin_cardEmmcReset; + uint32_t irq_cause; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif @@ -288,41 +301,46 @@ typedef struct { /** SDIO object */ typedef struct { #if defined(CY_IP_MXSDHC) - SDHC_Type* base; - cyhal_resource_inst_t resource; - bool emmc; - cy_en_sd_host_dma_type_t dmaType; - cy_stc_sd_host_context_t context; - cyhal_gpio_t pin_clk; - cyhal_gpio_t pin_cmd; - cyhal_gpio_t pin_data0; - cyhal_gpio_t pin_data1; - cyhal_gpio_t pin_data2; - cyhal_gpio_t pin_data3; - uint32_t frequencyhal_hz; - uint16_t block_size; - uint32_t irq_cause; + SDHC_Type* base; + cyhal_resource_inst_t resource; + bool emmc; + cy_en_sd_host_dma_type_t dmaType; + cy_stc_sd_host_context_t context; + cyhal_gpio_t pin_clk; + cyhal_gpio_t pin_cmd; + cyhal_gpio_t pin_data0; + cyhal_gpio_t pin_data1; + cyhal_gpio_t pin_data2; + cyhal_gpio_t pin_data3; + uint32_t frequencyhal_hz; + uint16_t block_size; + uint32_t irq_cause; + cy_stc_syspm_callback_params_t pm_params; + cy_stc_syspm_callback_t pm_callback; + uint32_t events; + cyhal_event_callback_data_t callback_data; #elif defined(CYHAL_UDB_SDIO) - cyhal_resource_inst_t resource; - cyhal_gpio_t pin_clk; - cyhal_gpio_t pin_cmd; - cyhal_gpio_t pin_data0; - cyhal_gpio_t pin_data1; - cyhal_gpio_t pin_data2; - cyhal_gpio_t pin_data3; - - cyhal_clock_divider_t clock; - - cyhal_dma_t dma0Ch0; - cyhal_dma_t dma0Ch1; - cyhal_dma_t dma1Ch1; - cyhal_dma_t dma1Ch3; - - uint32_t frequencyhal_hz; - uint16_t block_size; - - stc_sdio_irq_cb_t* pfuCb; - uint32_t irq_cause; + cyhal_resource_inst_t resource; + cyhal_gpio_t pin_clk; + cyhal_gpio_t pin_cmd; + cyhal_gpio_t pin_data0; + cyhal_gpio_t pin_data1; + cyhal_gpio_t pin_data2; + cyhal_gpio_t pin_data3; + + cyhal_clock_divider_t clock; + + cyhal_dma_t dma0Ch0; + cyhal_dma_t dma0Ch1; + cyhal_dma_t dma1Ch1; + cyhal_dma_t dma1Ch3; + + uint32_t frequencyhal_hz; + uint16_t block_size; + stc_sdio_irq_cb_t* pfuCb; + uint32_t irq_cause; + uint32_t events; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif /* defined(CY_IP_MXSDHC) */ @@ -331,35 +349,36 @@ typedef struct { /** SPI object */ typedef struct { #ifdef CY_IP_MXSCB - CySCB_Type* base; - cyhal_resource_inst_t resource; - cyhal_gpio_t pin_miso; - cyhal_gpio_t pin_mosi; - cyhal_gpio_t pin_sclk; - cyhal_gpio_t pin_ssel; - cyhal_clock_divider_t clock; - cy_en_scb_spi_sclk_mode_t clk_mode; - uint8_t mode; - uint8_t data_bits; - bool is_slave; - bool alloc_clock; - uint8_t oversample_value; - bool msb_first; - cy_stc_scb_spi_context_t context; - uint32_t irq_cause; - uint16_t pending; - void *rx_buffer; - uint32_t rx_buffer_size; - const void *tx_buffer; - uint32_t tx_buffer_size; - bool is_async; + CySCB_Type* base; + cyhal_resource_inst_t resource; + cyhal_gpio_t pin_miso; + cyhal_gpio_t pin_mosi; + cyhal_gpio_t pin_sclk; + cyhal_gpio_t pin_ssel; + cyhal_clock_divider_t clock; + cy_en_scb_spi_sclk_mode_t clk_mode; + uint8_t mode; + uint8_t data_bits; + bool is_slave; + bool alloc_clock; + uint8_t oversample_value; + bool msb_first; + cy_stc_scb_spi_context_t context; + uint32_t irq_cause; + uint16_t pending; + void *rx_buffer; + uint32_t rx_buffer_size; + const void *tx_buffer; + uint32_t tx_buffer_size; + bool is_async; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif } cyhal_spi_t; /** Callbacks for Sleep and Deepsleep APIs */ -#define cyhal_system_call_back_t cy_stc_syspm_callback_t +#define cyhal_system_callback_t cy_stc_syspm_callback_t /** Enum for clock type to configure. HFCLKs are configured using different APIs and does not using this enum */ typedef enum @@ -375,14 +394,16 @@ typedef uint16_t cyhal_system_divider_t; /** Timer object */ typedef struct { #ifdef CY_IP_MXTCPWM - TCPWM_Type* base; - cyhal_resource_inst_t resource; - cyhal_gpio_t pin; - cyhal_clock_divider_t clock; - uint32_t clock_hz; - uint8_t direction; - bool is_continuous; - bool is_compare; + TCPWM_Type* base; + cyhal_resource_inst_t resource; + cyhal_gpio_t pin; + cyhal_clock_divider_t clock; + bool dedicated_clock; + uint32_t clock_hz; + uint8_t direction; + bool is_continuous; + bool is_compare; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif @@ -391,21 +412,22 @@ typedef struct { /** UART object */ typedef struct { #ifdef CY_IP_MXSCB - CySCB_Type* base; - cyhal_resource_inst_t resource; - cyhal_gpio_t pin_rx; - cyhal_gpio_t pin_tx; - cyhal_gpio_t pin_cts; - cyhal_gpio_t pin_rts; - bool is_user_clock; - cyhal_clock_divider_t clock; - cy_stc_scb_uart_context_t context; - cy_stc_scb_uart_config_t config; - uint32_t irq_cause; - cy_stc_syspm_callback_params_t pm_params; - cy_stc_syspm_callback_t pm_callback; - en_hsiom_sel_t saved_tx_hsiom; - en_hsiom_sel_t saved_rts_hsiom; + CySCB_Type* base; + cyhal_resource_inst_t resource; + cyhal_gpio_t pin_rx; + cyhal_gpio_t pin_tx; + cyhal_gpio_t pin_cts; + cyhal_gpio_t pin_rts; + bool is_user_clock; + cyhal_clock_divider_t clock; + cy_stc_scb_uart_context_t context; + cy_stc_scb_uart_config_t config; + uint32_t irq_cause; + cy_stc_syspm_callback_params_t pm_params; + cy_stc_syspm_callback_t pm_callback; + en_hsiom_sel_t saved_tx_hsiom; + en_hsiom_sel_t saved_rts_hsiom; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif @@ -429,6 +451,11 @@ typedef struct { #endif } cyhal_usb_dev_t; +/** WDT object */ +typedef struct { + uint8_t placeholder; +} cyhal_wdt_t; + /** \} group_hal_hw_types_data_structures */ #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h index 5d641070c45..b7c48eb7c85 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h @@ -33,7 +33,6 @@ * \defgroup group_hal_hwmgr_macros Macros * \defgroup group_hal_hwmgr_functions Functions * \defgroup group_hal_hwmgr_data_structures Data Structures -* \defgroup group_hal_hwmgr_enums Enumerated Types */ #pragma once @@ -42,49 +41,12 @@ #include #include "cy_result.h" #include "cyhal_hw_types.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { #endif -/** -* \addtogroup group_hal_hwmgr_enums -* \{ -*/ - -/** Enum to in indicate which module an errors occurred in. */ -enum cyhal_rslt_module_chip -{ - CYHAL_RSLT_MODULE_CHIP_HWMGR = CY_RSLT_MODULE_ABSTRACTION_HAL_BASE, //!< An error occurred in hardware management module - CYHAL_RSLT_MODULE_ADC, //!< An error occurred in ADC module - CYHAL_RSLT_MODULE_COMP, //!< An error occurred in comparator module - CYHAL_RSLT_MODULE_CRC, //!< An error occurred in crypto CRC module - CYHAL_RSLT_MODULE_DAC, //!< An error occurred in DAC module - CYHAL_RSLT_MODULE_DMA, //!< An error occurred in DMA module - CYHAL_RSLT_MODULE_FLASH, //!< An error occurred in flash module - CYHAL_RSLT_MODULE_GPIO, //!< An error occurred in GPIO module - CYHAL_RSLT_MODULE_I2C, //!< An error occurred in I2C module - CYHAL_RSLT_MODULE_I2S, //!< An error occurred in I2S module - CYHAL_RSLT_MODULE_INTERCONNECT, //!< An error occurred in Interconnct module - CYHAL_RSLT_MODULE_OPAMP, //!< An error occurred in OpAmp module - CYHAL_RSLT_MODULE_PDMPCM, //!< An error occurred in PDM/PCM module - CYHAL_RSLT_MODULE_PWM, //!< An error occurred in PWM module - CYHAL_RSLT_MODULE_QSPI, //!< An error occurred in QSPI module - CYHAL_RSLT_MODULE_RTC, //!< An error occurred in RTC module - CYHAL_RSLT_MODULE_SDHC, //!< An error occurred in SDHC module - CYHAL_RSLT_MODULE_SDIO, //!< An error occurred in SDIO module - CYHAL_RSLT_MODULE_SPI, //!< An error occurred in SPI module - CYHAL_RSLT_MODULE_SYSTEM, //!< An error occurred in System module - CYHAL_RSLT_MODULE_TIMER, //!< An error occurred in Timer module - CYHAL_RSLT_MODULE_TRNG, //!< An error occurred in RNG module - CYHAL_RSLT_MODULE_UART, //!< An error occurred in UART module - CYHAL_RSLT_MODULE_USB, //!< An error occurred in USB module - CYHAL_RSLT_MODULE_WDT, //!< An error occurred in WDT module -}; - -/** \} group_hal_hwmgr_enums */ - - /** * \addtogroup group_hal_hwmgr_macros * \{ @@ -127,18 +89,10 @@ cy_rslt_t cyhal_hwmgr_reserve(const cyhal_resource_inst_t* obj); */ void cyhal_hwmgr_free(const cyhal_resource_inst_t* obj); -/** Reserve the specified resource. - * - * @param[in] type The type of resource that should be reserved - * @param[out] obj The resource object that was be reserved - * @return The status of the allocate request - */ -cy_rslt_t cyhal_hwmgr_allocate(cyhal_resource_t type, cyhal_resource_inst_t* obj); - /** Allocates a free block of the specified type if available * * @param[in] type The type of resource to allocate - * @param[out] obj The resource object to free + * @param[out] obj The resource object that was allocated * @return The status of the allocate request */ cy_rslt_t cyhal_hwmgr_allocate(cyhal_resource_t type, cyhal_resource_inst_t* obj); @@ -165,37 +119,14 @@ cy_rslt_t cyhal_hwmgr_allocate_clock(cyhal_clock_divider_t* obj, cyhal_clock_div */ void cyhal_hwmgr_free_clock(cyhal_clock_divider_t* obj); -/** Marks the specified resource as having already been configured (eg: it doesn't need to be configured again). - * - * @param[in] type The type of hardware block to reserve - * @param[in] block The block number of to reserve - * @param[in] channel The block's channel instance number to reserve (0 if there are no channels in the block) - * @return The status of the set request - */ -cy_rslt_t cyhal_hwmgr_set_configured(cyhal_resource_t type, uint8_t block, uint8_t channel); - -/** Marks the specified resource as not having already been configured (eg: it still needs to be configured before being used). - * - * @param[in] type The type of hardware block to reserve - * @param[in] block The block number of to reserve - * @param[in] channel The block's channel instance number to reserve (0 if there are no channels in the block) - * @return The status of the set request - */ -cy_rslt_t cyhal_hwmgr_set_unconfigured(cyhal_resource_t type, uint8_t block, uint8_t channel); - -/** Checks to see if the specified resource has already been configured (eg: it doesn't need to be configured again). - * - * @param[in] type The type of hardware block to reserve - * @param[in] block The block number of to reserve - * @param[in] channel The block's channel instance number to reserve (0 if there are no channels in the block) - * @return Whether the block is currently configured - */ -bool cyhal_hwmgr_is_configured(cyhal_resource_t type, uint8_t block, uint8_t channel); - /** \} group_hal_hwmgr_functions */ #if defined(__cplusplus) } #endif +#ifdef CYHAL_HWMGR_IMPL_HEADER +#include CYHAL_HWMGR_IMPL_HEADER +#endif /* CYHAL_HWMGR_IMPL_HEADER */ + /** \} group_hal_hwmgr */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h index b22f0f9a362..5b8dfbfd39f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h @@ -43,6 +43,7 @@ #include #include "cy_result.h" #include "cyhal_hw_types.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { @@ -56,9 +57,9 @@ extern "C" { /** The requested resource type is invalid */ #define CYHAL_I2C_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 0)) /** Can not reach desired data rate */ -#define CYHAL_I2C_RSLT_ERR_CAN_NOT_REACH_DR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 0)) +#define CYHAL_I2C_RSLT_ERR_CAN_NOT_REACH_DR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 1)) /** Address size is not correct, should be 1 or two */ -#define CYHAL_I2C_RSLT_ERR_INVALID_ADDRESS_SIZE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 0)) +#define CYHAL_I2C_RSLT_ERR_INVALID_ADDRESS_SIZE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 2)) /** \} group_hal_i2c_macros */ @@ -71,7 +72,7 @@ extern "C" { /** Enum to enable/disable/report interrupt cause flags. */ typedef enum { - CYHAL_I2C_IRQ_NONE = 0, //!< Disable all interrupt call backs + CYHAL_I2C_EVENT_NONE = 0, /* No event */ CYHAL_I2C_SLAVE_READ_EVENT = 1 << 1, /* Indicates that the slave was addressed and the master wants to read data. */ CYHAL_I2C_SLAVE_WRITE_EVENT = 1 << 2, /* Indicates that the slave was addressed and the master wants to write data. */ CYHAL_I2C_SLAVE_RD_IN_FIFO_EVENT = 1 << 3, /* All slave data from the configured Read buffer has been loaded into the TX FIFO. */ @@ -83,7 +84,7 @@ typedef enum CYHAL_I2C_MASTER_WR_CMPLT_EVENT = 1 << 18, /* The master write started by Cy_SCB_I2C_MasterWrite is complete.*/ CYHAL_I2C_MASTER_RD_CMPLT_EVENT = 1 << 19, /* The master read started by Cy_SCB_I2C_MasterRead is complete.*/ CYHAL_I2C_MASTER_ERR_EVENT = 1 << 20, /* Indicates the I2C hardware has detected an error. */ -} cyhal_i2c_irq_event_t; +} cyhal_i2c_event_t; /** \} group_hal_i2c_enums */ @@ -93,9 +94,8 @@ typedef enum * \{ */ - -/** Handler for I2C interrupts */ -typedef void (*cyhal_i2c_irq_handler_t)(void *handler_arg, cyhal_i2c_irq_event_t event); +/** Handler for I2C events */ +typedef void (*cyhal_i2c_event_callback_t)(void *callback_arg, cyhal_i2c_event_t event); /** Initial I2C configuration */ typedef struct @@ -114,9 +114,9 @@ typedef struct */ /** Initialize the I2C peripheral, and configures its specifieds pins. By default - * it is setup as a Master running at 400kHz. This can be changed by calling - * cyhal_i2c_set_config(). - * NOTE: Master/Slave specific functions only work when the block is configured + * it is setup as a Master running at 400kHz. This can be changed by calling + * cyhal_i2c_configure(). + * NOTE: Master/Slave specific functions only work when the block is configured * to be in that mode. * * @param[out] obj The I2C object @@ -137,61 +137,61 @@ void cyhal_i2c_free(cyhal_i2c_t *obj); * * @param[in] obj The I2C object * @param[in] cfg Configuration settings to apply - * @return The status of the set_config request + * @return The status of the configure request */ -cy_rslt_t cyhal_i2c_set_config(cyhal_i2c_t *obj, const cyhal_i2c_cfg_t *cfg); +cy_rslt_t cyhal_i2c_configure(cyhal_i2c_t *obj, const cyhal_i2c_cfg_t *cfg); /** - * I2C master send + * I2C master write * - * @param[in] obj The I2C object - * @param[in] dev_addr device address (7-bit) - * @param[in] data i2c send data - * @param[in] size i2c send data size - * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever + * @param[in] obj The I2C object + * @param[in] dev_addr device address (7-bit) + * @param[in] data i2c send data + * @param[in] size i2c send data size + * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever + * @param[in] send_stop whether the stop should be send, used to support repeat start conditions * - * @return The status of the master_send request + * @return The status of the master_write request */ -cy_rslt_t cyhal_i2c_master_send(cyhal_i2c_t *obj, uint16_t dev_addr, const uint8_t *data, uint16_t size, uint32_t timeout); +cy_rslt_t cyhal_i2c_master_write(cyhal_i2c_t *obj, uint16_t dev_addr, const uint8_t *data, uint16_t size, uint32_t timeout, bool send_stop); /** - * I2C master recv + * I2C master read * - * @param[in] obj The I2C object - * @param[in] dev_addr device address (7-bit) - * @param[out] data i2c receive data - * @param[in] size i2c receive data size - * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever + * @param[in] obj The I2C object + * @param[in] dev_addr device address (7-bit) + * @param[out] data i2c receive data + * @param[in] size i2c receive data size + * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever + * @param[in] send_stop whether the stop should be send, used to support repeat start conditions * - * @return The status of the master_recv request + * @return The status of the master_read request */ -cy_rslt_t cyhal_i2c_master_recv(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *data, uint16_t size, uint32_t timeout); +cy_rslt_t cyhal_i2c_master_read(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *data, uint16_t size, uint32_t timeout, bool send_stop); /** - * I2C slave send + * I2C slave config write buffer * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up) * * @param[in] obj The I2C object * @param[in] data i2c slave send data * @param[in] size i2c slave send data size - * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever * - * @return The status of the slave_send request + * @return The status of the slave_config_write_buff request */ -cy_rslt_t cyhal_i2c_slave_send(cyhal_i2c_t *obj, const uint8_t *data, uint16_t size, uint32_t timeout); +cy_rslt_t cyhal_i2c_slave_config_write_buff(cyhal_i2c_t *obj, const uint8_t *data, uint16_t size); /** - * I2C slave receive + * I2C slave config read buffer * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up) * * @param[in] obj The I2C object * @param[out] data i2c slave receive data * @param[in] size i2c slave receive data size - * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever * - * @return The status of the slave_recv request + * @return The status of the slave_config_read_buff request */ -cy_rslt_t cyhal_i2c_slave_recv(cyhal_i2c_t *obj, uint8_t *data, uint16_t size, uint32_t timeout); +cy_rslt_t cyhal_i2c_slave_config_read_buff(cyhal_i2c_t *obj, uint8_t *data, uint16_t size); /** Perform an i2c write using a block of data stored at the specified memory location * @@ -204,7 +204,7 @@ cy_rslt_t cyhal_i2c_slave_recv(cyhal_i2c_t *obj, uint8_t *data, uint16_t size, u * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever * @return The status of the write request */ -cy_rslt_t cyhal_i2c_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, const uint8_t *data, uint16_t size, uint32_t timeout); +cy_rslt_t cyhal_i2c_master_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, const uint8_t *data, uint16_t size, uint32_t timeout); /** Perform an i2c read using a block of data stored at the specified memory location * @@ -217,19 +217,19 @@ cy_rslt_t cyhal_i2c_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_a * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever * @return The status of the read request */ -cy_rslt_t cyhal_i2c_mem_read(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, uint8_t *data, uint16_t size, uint32_t timeout); +cy_rslt_t cyhal_i2c_master_mem_read(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, uint8_t *data, uint16_t size, uint32_t timeout); -/** Start I2C asynchronous transfer +/** Start I2C master asynchronous transfer * * @param[in] obj The I2C object + * @param[in] address device address (7-bit) * @param[in] tx The transmit buffer * @param[in] tx_size The number of bytes to transmit * @param[out] rx The receive buffer * @param[in] rx_size The number of bytes to receive - * @param[in] address device address (7-bit) - * @return The status of the transfer_async request + * @return The status of the master_transfer_async request */ -cy_rslt_t cyhal_i2c_transfer_async(cyhal_i2c_t *obj, const void *tx, size_t tx_size, void *rx, size_t rx_size, uint16_t address); +cy_rslt_t cyhal_i2c_master_transfer_async(cyhal_i2c_t *obj, uint16_t address, const void *tx, size_t tx_size, void *rx, size_t rx_size); /** Abort asynchronous transfer * @@ -239,26 +239,41 @@ cy_rslt_t cyhal_i2c_transfer_async(cyhal_i2c_t *obj, const void *tx, size_t tx_s */ cy_rslt_t cyhal_i2c_abort_async(cyhal_i2c_t *obj); -/** The I2C interrupt handler registration +/** The I2C event callback handler registration * - * @param[in] obj The I2C object - * @param[in] handler The callback handler which will be invoked when the interrupt fires - * @param[in] handler_arg Generic argument that will be provided to the handler when called + * @param[in] obj The I2C object + * @param[in] callback The callback handler which will be invoked when an event triggers + * @param[in] callback_arg Generic argument that will be provided to the callback when called */ -void cyhal_i2c_register_irq(cyhal_i2c_t *obj, cyhal_i2c_irq_handler_t handler, void *handler_arg); +void cyhal_i2c_register_callback(cyhal_i2c_t *obj, cyhal_i2c_event_callback_t callback, void *callback_arg); /** Configure and Enable or Disable I2C Interrupt. * - * @param[in] obj The I2C object - * @param[in] event The I2C IRQ type - * @param[in] enable True to turn on interrupts, False to turn off + * @param[in] obj The I2C object + * @param[in] event The I2C event type + * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off */ -void cyhal_i2c_irq_enable(cyhal_i2c_t *obj, cyhal_i2c_irq_event_t event, bool enable); +void cyhal_i2c_enable_event(cyhal_i2c_t *obj, cyhal_i2c_event_t event, uint8_t intrPriority, bool enable); /** \} group_hal_i2c_functions */ +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +#define cyhal_i2c_register_irq cyhal_i2c_register_callback +#define cyhal_i2c_irq_enable(obj, event, enable) cyhal_i2c_enable_event(obj, event, CYHAL_ISR_PRIORITY_DEFAULT, enable) +typedef cyhal_i2c_event_t cyhal_i2c_irq_event_t; +/** \endcond */ + #if defined(__cplusplus) } #endif +#ifdef CYHAL_I2C_IMPL_HEADER +#include CYHAL_I2C_IMPL_HEADER +#endif /* CYHAL_I2C_IMPL_HEADER */ + /** \} group_hal_i2c */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h index b83dfcdade0..1875c015608 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h @@ -43,6 +43,7 @@ #include #include "cy_result.h" #include "cyhal_hw_types.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { @@ -57,8 +58,11 @@ extern "C" { #define CYHAL_CONNECT_RSLT_NO_CONNECTION (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_INTERCONNECT, 0)) /** The connections source and destination are already connected */ #define CYHAL_CONNECT_RSLT_ALREADY_CONNECTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_INTERCONNECT, 1)) -/** Invalid 1-to-1 trigger connection */ -#define CYHAL_CONNECT_RSLT_INVALID_1TO1_CONNECTION (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_INTERCONNECT, 2)) +/** Invalid trigger connection */ +#define CYHAL_CONNECT_RSLT_INVALID_TRIGGER_CONNECTION (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_INTERCONNECT, 2)) + +/** Indicates that a mux output does not continue to another mux */ +#define CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION 0xFF /** \} group_hal_interconnect_macros */ @@ -68,16 +72,6 @@ extern "C" { * \{ */ -/** Connects two digital terminals. The source will be routed to the destination via the trigger routing - * framework in the device. This supports both the trigger mux routing and the 1:1 triggers. As expected, - * a single source can drive multiple destinations, but a destination can only be driven by a single source. - * If the output is already connected, or the connection can not be established an error will be returned. - * @param[in] source The source of the signal to connect - * @param[in] dest The destination of the signal to connect - * @return The status of the connect request - */ -cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest); - /** Connect a pin to a peripheral terminal. This will route a direct connect from the pin to the peripheral. * Any previous direct connection from the pin will be overriden. * @param[in] pin_connection Details about the pin and its target connection @@ -91,10 +85,24 @@ cy_rslt_t cyhal_connect_pin(const cyhal_resource_pin_mapping_t *pin_connection); */ cy_rslt_t cyhal_disconnect_pin(cyhal_gpio_t pin); +/** WORK IN PROGRESS. This function is not yet fully implemented. + * Connects two digital terminals on the device using any internal interconnect. As expected, a single + * source can drive multiple destinations, but a destination can only be driven by a single source. + * If the output is already connected, or the connection can not be established an error will be returned. + * @param[in] source The source of the signal to connect + * @param[in] dest The destination of the signal to connect + * @return The status of the connect request + */ +cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest); + +/** \} group_hal_interconnect_functions */ + #if defined(__cplusplus) } #endif -/** \} group_hal_interconnect_functions */ +#ifdef CYHAL_INTERCONNECT_IMPL_HEADER +#include CYHAL_INTERCONNECT_IMPL_HEADER +#endif /* CYHAL_INTERCONNECT_IMPL_HEADER */ /** \} group_hal_interconnect */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h index 1cedd32e4d3..b38cee8c132 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h @@ -56,7 +56,7 @@ extern "C" { /** LPTIMER interrupt triggers */ typedef enum { CYHAL_LPTIMER_COMPARE_MATCH, -} cyhal_lptimer_irq_event_t; +} cyhal_lptimer_event_t; /** \} group_hal_lptimer_enums */ @@ -67,7 +67,7 @@ typedef enum { */ /** Handler for LPTIMER interrupts */ -typedef void (*cyhal_lptimer_irq_handler_t)(void *handler_arg, cyhal_lptimer_irq_event_t event); +typedef void (*cyhal_lptimer_event_callback_t)(void *callback_arg, cyhal_lptimer_event_t event); /** \} group_hal_lptimer_data_structures */ @@ -122,7 +122,7 @@ cy_rslt_t cyhal_lptimer_set_time(cyhal_lptimer_t *obj, uint32_t time); /** Update the match/compare value * - * Quickly update the match value of an already configured LPTIMER set up + * Update the match value of an already configured LPTIMER set up * to generate an interrupt on match. Note that this function does not * reinitialize the counter or the associated peripheral initialization * sequence. @@ -145,21 +145,22 @@ cy_rslt_t cyhal_lptimer_set_match(cyhal_lptimer_t *obj, uint32_t value); */ uint32_t cyhal_lptimer_read(const cyhal_lptimer_t *obj); -/** The LPTIMER match interrupt handler registration +/** The LPTIMER match event handler registration * - * @param[in] obj The LPTIMER object - * @param[in] handler The callback handler which will be invoked when the interrupt triggers - * @param[in] handler_arg Generic argument that will be provided to the handler when called + * @param[in] obj The LPTIMER object + * @param[in] callback The callback handler which will be invoked when the interrupt triggers + * @param[in] callback_arg Generic argument that will be provided to the handler when called */ -void cyhal_lptimer_register_irq(cyhal_lptimer_t *obj, cyhal_lptimer_irq_handler_t handler, void *handler_arg); +void cyhal_lptimer_register_callback(cyhal_lptimer_t *obj, cyhal_lptimer_event_callback_t callback, void *callback_arg); -/** Configure and Enable/Disable the LPTIMER interrupt +/** Configure and Enable/Disable the LPTIMER events * - * @param[in] obj The LPTIMER object - * @param[in] event The LPTIMER IRQ type - * @param[in] enable True to turn on interrupts, False to turn off + * @param[in] obj The LPTIMER object + * @param[in] event The LPTIMER event type + * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] enable True to turn on event, False to turn off */ -void cyhal_lptimer_irq_enable(cyhal_lptimer_t *obj, cyhal_lptimer_irq_event_t event, bool enable); +void cyhal_lptimer_enable_event(cyhal_lptimer_t *obj, cyhal_lptimer_event_t event, uint8_t intrPriority, bool enable); /** Manually trigger the LPTIMER interrupt. * @@ -173,4 +174,8 @@ void cyhal_lptimer_irq_trigger(cyhal_lptimer_t *obj); } #endif +#ifdef CYHAL_LPTIMER_IMPL_HEADER +#include CYHAL_LPTIMER_IMPL_HEADER +#endif /* CYHAL_LPTIMER_IMPL_HEADER */ + /** \} group_hal_lptimer */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h new file mode 100644 index 00000000000..f7855517489 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h @@ -0,0 +1,85 @@ +/***************************************************************************//** +* \file cyhal_modules.h +* +* \brief +* Provides an enum of all HAL modules types that can be used for generating +* custom cy_rslt_t items. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_modules Driver Modules +* \ingroup group_hal +* \{ +* Enum definition for all HAL resource modules. +* +* \defgroup group_hal_modules_enums Enumerated Types +*/ + +#pragma once + +#include "cy_result.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/** +* \addtogroup group_hal_modules_enums +* \{ +*/ + +/** Enum to in indicate which module an errors occurred in. */ +enum cyhal_rslt_module_chip +{ + CYHAL_RSLT_MODULE_CHIP_HWMGR = CY_RSLT_MODULE_ABSTRACTION_HAL_BASE, //!< An error occurred in hardware management module + CYHAL_RSLT_MODULE_ADC, //!< An error occurred in ADC module + CYHAL_RSLT_MODULE_COMP, //!< An error occurred in comparator module + CYHAL_RSLT_MODULE_CRC, //!< An error occurred in crypto CRC module + CYHAL_RSLT_MODULE_DAC, //!< An error occurred in DAC module + CYHAL_RSLT_MODULE_DMA, //!< An error occurred in DMA module + CYHAL_RSLT_MODULE_FLASH, //!< An error occurred in flash module + CYHAL_RSLT_MODULE_GPIO, //!< An error occurred in GPIO module + CYHAL_RSLT_MODULE_I2C, //!< An error occurred in I2C module + CYHAL_RSLT_MODULE_I2S, //!< An error occurred in I2S module + CYHAL_RSLT_MODULE_INTERCONNECT, //!< An error occurred in Interconnct module + CYHAL_RSLT_MODULE_OPAMP, //!< An error occurred in OpAmp module + CYHAL_RSLT_MODULE_PDMPCM, //!< An error occurred in PDM/PCM module + CYHAL_RSLT_MODULE_PWM, //!< An error occurred in PWM module + CYHAL_RSLT_MODULE_QSPI, //!< An error occurred in QSPI module + CYHAL_RSLT_MODULE_RTC, //!< An error occurred in RTC module + CYHAL_RSLT_MODULE_SDHC, //!< An error occurred in SDHC module + CYHAL_RSLT_MODULE_SDIO, //!< An error occurred in SDIO module + CYHAL_RSLT_MODULE_SPI, //!< An error occurred in SPI module + CYHAL_RSLT_MODULE_SYSTEM, //!< An error occurred in System module + CYHAL_RSLT_MODULE_TIMER, //!< An error occurred in Timer module + CYHAL_RSLT_MODULE_TRNG, //!< An error occurred in RNG module + CYHAL_RSLT_MODULE_UART, //!< An error occurred in UART module + CYHAL_RSLT_MODULE_USB, //!< An error occurred in USB module + CYHAL_RSLT_MODULE_WDT, //!< An error occurred in WDT module +}; + +/** \} group_hal_modules_enums */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/** \} group_hal_modules */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h index 96c24922200..6957d909482 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h @@ -76,14 +76,14 @@ typedef enum { */ /** GPIO pin configuration object */ -typedef uint16_t cyhal_gpio_cfg_t; // 8bit hsiom, 8bit mode +typedef uint16_t cyhal_gpio_mapping_cfg_t; // 8bit hsiom, 8bit mode /** \} group_hal_pin_package_data_structures */ /** \cond INTERNAL */ -#define CY_GPIO_CFG_CREATE(hsiom, mode) ((cyhal_gpio_cfg_t)(((hsiom) << 8) + (mode))) +#define CY_GPIO_CFG_CREATE(hsiom, mode) ((cyhal_gpio_mapping_cfg_t)(((hsiom) << 8) + (mode))) #define CY_GPIO_CFG_GET_MODE(x) ((uint8_t)((x) & 0xFF)) #define CY_GPIO_CFG_GET_HSIOM(x) ((en_hsiom_sel_t)(((x) >> 8) & 0xFF)) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h index 28b290a26ff..4ea56fb1558 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h @@ -41,8 +41,8 @@ #include #include "cy_result.h" -#include "cyhal_hwmgr.h" #include "cyhal_hw_types.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { @@ -56,13 +56,40 @@ extern "C" { /** Bad argument */ #define CYHAL_PWM_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_PWM, 0)) /** Failed to initialize PWM clock */ -#define CYHAL_PWM_RSLT_FAILED_CLOCK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_PWM, 1)) +#define CYHAL_PWM_RSLT_FAILED_CLOCK_INIT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_PWM, 1)) /** Failed to initialize PWM */ #define CYHAL_PWM_RSLT_FAILED_INIT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_PWM, 2)) /** \} group_hal_pwm_macros */ +/** +* \addtogroup group_hal_pwm_enums +* \{ +*/ + +/** PWM interrupt triggers */ +typedef enum { + CYHAL_PWM_IRQ_NONE = 0, + CYHAL_PWM_IRQ_TERMINAL_COUNT = 1 << 0, + CYHAL_PWM_IRQ_CAPTURE_COMPARE = 1 << 1, + CYHAL_PWM_IRQ_ALL = (1 << 2) - 1, +} cyhal_pwm_event_t; + +/** \} group_hal_pwm_enums */ + + +/** +* \addtogroup group_hal_pwm_data_structures +* \{ +*/ + +/** Handler for PWM interrupts */ +typedef void(*cyhal_pwm_event_callback_t)(void *callback_arg, cyhal_pwm_event_t event); + +/** \} group_hal_pwm_data_structures */ + + /** * \addtogroup group_hal_pwm_functions * \{ @@ -90,7 +117,7 @@ void cyhal_pwm_free(cyhal_pwm_t *obj); * @param[in] pulse_width_us The pulse width in microseconds * @return The status of the period request */ -cy_rslt_t cyhal_pwm_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us); +cy_rslt_t cyhal_pwm_set_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us); /** Set the PWM pulsewidth specified in microseconds, keeping the period the same. * @@ -99,7 +126,7 @@ cy_rslt_t cyhal_pwm_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_ * @param[in] frequencyhal_hz The frequency of the PWM * @return The status of the pulsewidth request */ -cy_rslt_t cyhal_pwm_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz); +cy_rslt_t cyhal_pwm_set_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz); /** Starts the PWM with the provided period and pulsewidth * @@ -115,10 +142,31 @@ cy_rslt_t cyhal_pwm_start(cyhal_pwm_t *obj); */ cy_rslt_t cyhal_pwm_stop(cyhal_pwm_t *obj); +/** The PWM interrupt handler registration + * + * @param[in] obj The PWM object + * @param[in] callback The callback handler which will be invoked when the event occurs + * @param[in] callback_arg Generic argument that will be provided to the callback when called + */ +void cyhal_pwm_register_callback(cyhal_pwm_t *obj, cyhal_pwm_event_callback_t callback, void *callback_arg); + +/** Configure PWM event enablement. + * + * @param[in] obj The PWM object + * @param[in] event The PWM event type + * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] enable True to turn on events, False to turn off + */ +void cyhal_pwm_enable_event(cyhal_pwm_t *obj, cyhal_pwm_event_t event, uint8_t intrPriority, bool enable); + /** \} group_hal_pwm_functions */ #if defined(__cplusplus) } #endif +#ifdef CYHAL_PWM_IMPL_HEADER +#include CYHAL_PWM_IMPL_HEADER +#endif /* CYHAL_PWM_IMPL_HEADER */ + /** \} group_hal_pwm */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h new file mode 100644 index 00000000000..957a86c9e94 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h @@ -0,0 +1,69 @@ +/***************************************************************************//** +* \file cyhal_pwm_impl.h +* +* Description: +* Provides a high level interface for interacting with the Cypress PWM. +* +******************************************************************************** +* \copyright +* Copyright 2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cyhal_pwm.h" +#include "cyhal_tcpwm_common.h" + +#if defined(CY_IP_MXTCPWM_INSTANCES) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +__STATIC_INLINE uint32_t cyhal_pwm_convert_event(cyhal_pwm_event_t event) +{ + uint32_t pdl_event = 0U; + if (event & CYHAL_PWM_IRQ_TERMINAL_COUNT) + { + pdl_event |= CY_TCPWM_INT_ON_TC; + } + if (event & CYHAL_PWM_IRQ_CAPTURE_COMPARE) + { + pdl_event |= CY_TCPWM_INT_ON_CC; + } + return pdl_event; +} + +__STATIC_INLINE void cyhal_pwm_register_callback_internal(cyhal_pwm_t *obj, cyhal_pwm_event_callback_t callback, void *callback_arg) +{ + cyhal_tcpwm_register_callback(&(obj->resource), (cy_israddress) callback, callback_arg); +} + +#define cyhal_pwm_register_callback(obj, callback, callback_arg) cyhal_pwm_register_callback_internal(obj, callback, callback_arg) + +__STATIC_INLINE void cyhal_pwm_enable_event_internal(cyhal_pwm_t *obj, cyhal_pwm_event_t event, uint8_t intrPriority, bool enable) +{ + uint32_t converted = cyhal_pwm_convert_event(event); + cyhal_tcpwm_enable_event(obj->base, &(obj->resource), converted, intrPriority, enable); +} + +#define cyhal_pwm_enable_event(obj, event, intrPriority, enable) cyhal_pwm_enable_event_internal(obj, event, intrPriority, enable) + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* defined(CY_IP_MXTCPWM_INSTANCES) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h index 75facd0c9d3..d99c8732586 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h @@ -43,6 +43,7 @@ #include #include "cy_result.h" #include "cyhal_hw_types.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { @@ -58,26 +59,26 @@ extern "C" { * Some parts of commands provide variable bus width */ typedef enum cyhal_qspi_bus_width { - CYHAL_QSPI_CFG_BUS_SINGLE, - CYHAL_QSPI_CFG_BUS_DUAL, - CYHAL_QSPI_CFG_BUS_QUAD, - CYHAL_QSPI_CFG_BUS_OCTAL + CYHAL_QSPI_CFG_BUS_SINGLE = 1, + CYHAL_QSPI_CFG_BUS_DUAL = 2, + CYHAL_QSPI_CFG_BUS_QUAD = 4, + CYHAL_QSPI_CFG_BUS_OCTAL = 8, } cyhal_qspi_bus_width_t; /** Size in bits */ typedef enum cyhal_qspi_size { - CYHAL_QSPI_CFG_SIZE_8, - CYHAL_QSPI_CFG_SIZE_16, - CYHAL_QSPI_CFG_SIZE_24, - CYHAL_QSPI_CFG_SIZE_32 + CYHAL_QSPI_CFG_SIZE_8 = 8, + CYHAL_QSPI_CFG_SIZE_16 = 16, + CYHAL_QSPI_CFG_SIZE_24 = 24, + CYHAL_QSPI_CFG_SIZE_32 = 32, } cyhal_qspi_size_t; /** QSPI interrupt triggers */ typedef enum { - CYHAL_QSPI_IRQ_NONE = 0, /**< Disable all interrupts. >*/ + CYHAL_QSPI_EVENT_NONE = 0, /**< No event >*/ CYHAL_QSPI_IRQ_TRANSMIT_DONE = 1 << 0, /**< Async transmit done. >*/ CYHAL_QSPI_IRQ_RECEIVE_DONE = 1 << 1, /**< Async receive done. >*/ -} cyhal_qspi_irq_event_t; +} cyhal_qspi_event_t; /** \} group_hal_qspi_enums */ @@ -113,19 +114,19 @@ typedef struct cyhal_qspi_command { bool disabled; /**< Address phase skipped if disabled is set to true >*/ } address; struct { - cyhal_qspi_bus_width_t bus_width; /**< Bus width for alternative >*/ - cyhal_qspi_size_t size; /**< Alternative size >*/ - uint32_t value; /**< Alternative value >*/ - bool disabled; /**< Alternative phase skipped if disabled is set to true >*/ - } alt; + cyhal_qspi_bus_width_t bus_width; /**< Bus width for mode bits >*/ + cyhal_qspi_size_t size; /**< Mode bits size >*/ + uint32_t value; /**< Mode bits value >*/ + bool disabled; /**< Mode bits phase skipped if disabled is set to true >*/ + } mode_bits; uint8_t dummy_count; /**< Dummy cycles count >*/ struct { cyhal_qspi_bus_width_t bus_width; /**< Bus width for data >*/ } data; } cyhal_qspi_command_t; -/** Handler for QSPI interrupts */ -typedef void (*cyhal_qspi_irq_handler_t)(void *handler_arg, cyhal_qspi_irq_event_t event); +/** Handler for QSPI callbacks */ +typedef void (*cyhal_qspi_event_callback_t)(void *callback_arg, cyhal_qspi_event_t event); /** \} group_hal_qspi_data_structures */ @@ -137,7 +138,7 @@ typedef void (*cyhal_qspi_irq_handler_t)(void *handler_arg, cyhal_qspi_irq_event /** Initialize QSPI peripheral. * - * It should initialize QSPI pins (io0-io3, sclk and ssel), set frequency, clock polarity and phase mode. + * It should initialize QSPI pins (io0-io7, sclk and ssel), set frequency, clock polarity and phase mode. * The clock for the peripheral should be enabled * * @param[out] obj QSPI object @@ -173,13 +174,13 @@ void cyhal_qspi_free(cyhal_qspi_t *obj); * * Actual frequency may differ from the desired frequency due to available dividers and the bus clock * Configures the QSPI peripheral's baud rate - * @param[in] obj The SPI object to configure + * @param[in] obj The QSPI object to configure * @param[in] hz The baud rate in Hz - * @return The status of the frequency request + * @return The status of the set_frequency request */ -cy_rslt_t cyhal_qspi_frequency(cyhal_qspi_t *obj, uint32_t hz); +cy_rslt_t cyhal_qspi_set_frequency(cyhal_qspi_t *obj, uint32_t hz); -/** Receive a command and block of data +/** Receive a command and block of data, synchronously. * * @param[in] obj QSPI object * @param[in] command QSPI command @@ -189,7 +190,9 @@ cy_rslt_t cyhal_qspi_frequency(cyhal_qspi_t *obj, uint32_t hz); */ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, void *data, size_t *length); -/** Receive a command and block of data in asynchronous mode. Require __enable_irq() call in order to work. +/** Receive a command and block of data in asynchronous mode. This requires __enable_irq() to have been called + * in order to work. To receive a notification when the read is complete, enable and register a callback + * using cyhal_qspi_irq_enable and cyhal_qspi_register_irq. * * @param[in] obj QSPI object * @param[in] command QSPI command @@ -199,7 +202,7 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command */ cy_rslt_t cyhal_qspi_read_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, void *data, size_t *length); -/** Send a command and block of data +/** Send a command and block of data, synchronously. * * @param[in] obj QSPI object * @param[in] command QSPI command @@ -209,7 +212,9 @@ cy_rslt_t cyhal_qspi_read_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *c */ cy_rslt_t cyhal_qspi_write(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, const void *data, size_t *length); -/** Send a command and block of data in asynchronous mode. Require __enable_irq() call in order to work. +/** Send a command and block of data in asynchronous mode. This requires __enable_irq() to have been called + * in order to work. To receive a notification when the read is complete, enable and register a callback + * using cyhal_qspi_irq_enable and cyhal_qspi_register_irq. * * @param[in] obj QSPI object * @param[in] command QSPI command @@ -234,21 +239,22 @@ cy_rslt_t cyhal_qspi_transfer( size_t rx_size ); -/** The QSPI interrupt handler registration +/** The QSPI event handler registration * * @param[in] obj The QSPI object - * @param[in] handler The callback handler which will be invoked when the interrupt fires - * @param[in] handler_arg Generic argument that will be provided to the handler when called + * @param[in] callback The callback handler which will be invoked when the interrupt fires + * @param[in] callback_arg Generic argument that will be provided to the handler when called */ -void cyhal_qspi_register_irq(cyhal_qspi_t *obj, cyhal_qspi_irq_handler_t handler, void *handler_arg); +void cyhal_qspi_register_callback(cyhal_qspi_t *obj, cyhal_qspi_event_callback_t callback, void *callback_arg); /** Configure QSPI interrupt enablement. * - * @param[in] obj The QSPI object - * @param[in] event The QSPI IRQ type - * @param[in] enable True to turn on interrupts, False to turn off + * @param[in] obj The QSPI object + * @param[in] event The QSPI event type + * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off */ -void cyhal_qspi_irq_enable(cyhal_qspi_t *obj, cyhal_qspi_irq_event_t event, bool enable); +void cyhal_qspi_enable_event(cyhal_qspi_t *obj, cyhal_qspi_event_t event, uint8_t intrPriority, bool enable); /** \} group_hal_qspi_functions */ @@ -256,4 +262,8 @@ void cyhal_qspi_irq_enable(cyhal_qspi_t *obj, cyhal_qspi_irq_event_t event, bool } #endif +#ifdef CYHAL_QSPI_IMPL_HEADER +#include CYHAL_QSPI_IMPL_HEADER +#endif /* CYHAL_QSPI_IMPL_HEADER */ + /** \} group_hal_qspi */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h index 8e553dae7a8..18e4fc5f3d2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h @@ -2,10 +2,10 @@ * \file cyhal_rtc.h * * \brief -* Provides a high level interface for interacting with the Cypress Real-Time Clock. -* This interface abstracts out the chip specific details. If any chip specific -* functionality is necessary, or performance is critical the low level functions -* can be used directly. +* Provides a high level interface for interacting with the Real Time Clock on +* Cypress devices. This interface abstracts out the chip specific details. +* If any chip specific functionality is necessary, or performance is critical +* the low level functions can be used directly. * ******************************************************************************** * \copyright @@ -44,6 +44,7 @@ #include #include "cy_result.h" #include "cyhal_hw_types.h" +#include "cyhal_modules.h" /** RTC not initialized */ #define CY_RSLT_RTC_NOT_INITIALIZED CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_RTC, 0) @@ -60,7 +61,7 @@ extern "C" { /** RTC interrupt triggers */ typedef enum { CYHAL_RTC_ALARM, -} cyhal_rtc_irq_event_t; +} cyhal_rtc_event_t; /** \} group_hal_rtc_enums */ @@ -81,8 +82,8 @@ typedef struct uint8_t en_month : 1; /** !< Enable match of month */ } cyhal_alarm_active_t; -/** Handler for RTC interrupts */ -typedef void (*cyhal_rtc_irq_handler_t)(void *handler_arg, cyhal_rtc_irq_event_t event); +/** Handler for RTC events */ +typedef void (*cyhal_rtc_event_callback_t)(void *callback_arg, cyhal_rtc_event_t event); /** \} group_hal_rtc_data_structures */ @@ -94,10 +95,10 @@ typedef void (*cyhal_rtc_irq_handler_t)(void *handler_arg, cyhal_rtc_irq_event_t /** Initialize the RTC peripheral * - * Powerup the RTC in perpetration for access. This function must be called - * before any other RTC functions ares called. This does not change the state - * of the RTC. It just enables access to it. - * NOTE: Before calling this, make sure all necessary System Clocks are setup + * Powerup the RTC in preparation for access. This function must be called + * before any other RTC functions are called. This does not change the state + * of the RTC. It just enables access to it. + * NOTE: Before calling this, make sure all necessary System Clocks are setup * correctly. Generally this means making sure the RTC has access to a Crystal * for optimal accuracy and operation in low power. * @@ -108,8 +109,8 @@ cy_rslt_t cyhal_rtc_init(cyhal_rtc_t *obj); /** Deinitialize RTC * - * Powerdown the RTC in preparation for sleep, powerdown or reset. That should only - * affect the CPU domain and not the time keeping logic. + * Frees resources associated with the RTC and disables CPU access. This + * only affects the CPU domain and not the time keeping logic. * After this function is called no other RTC functions should be called * except for rtc_init. * @@ -145,25 +146,26 @@ cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time); * @param[in] obj RTC object * @param[in] time The alarm time to be set (see: https://en.cppreference.com/w/cpp/chrono/c/tm) * @param[in] active The set of fields that are checked to trigger the alarm - * @return The status of the alarm request + * @return The status of the set_alarm request */ -cy_rslt_t cyhal_rtc_alarm(cyhal_rtc_t *obj, const struct tm *time, cyhal_alarm_active_t active); +cy_rslt_t cyhal_rtc_set_alarm(cyhal_rtc_t *obj, const struct tm *time, cyhal_alarm_active_t active); -/** The RTC alarm interrupt handler registration +/** The RTC event callback handler registration * - * @param[in] obj The RTC object - * @param[in] handler The callback handler which will be invoked when the alarm fires - * @param[in] handler_arg Generic argument that will be provided to the handler when called + * @param[in] obj The RTC object + * @param[in] callback The callback handler which will be invoked when the alarm fires + * @param[in] callback_arg Generic argument that will be provided to the callback when called */ -void cyhal_rtc_register_irq(cyhal_rtc_t *obj, cyhal_rtc_irq_handler_t handler, void *handler_arg); +void cyhal_rtc_register_callback(cyhal_rtc_t *obj, cyhal_rtc_event_callback_t callback, void *callback_arg); -/** Configure RTC alarm interrupt enablement. +/** Configure RTC event enablement. * - * @param[in] obj The RTC object - * @param[in] event The RTC IRQ type - * @param[in] enable True to turn on interrupts, False to turn off + * @param[in] obj The RTC object + * @param[in] event The RTC event type + * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off */ -void cyhal_rtc_irq_enable(cyhal_rtc_t *obj, cyhal_rtc_irq_event_t event, bool enable); +void cyhal_rtc_enable_event(cyhal_rtc_t *obj, cyhal_rtc_event_t event, uint8_t intrPriority, bool enable); /** \} group_hal_rtc_functions */ @@ -171,4 +173,8 @@ void cyhal_rtc_irq_enable(cyhal_rtc_t *obj, cyhal_rtc_irq_event_t event, bool en } #endif +#ifdef CYHAL_RTC_IMPL_HEADER +#include CYHAL_RTC_IMPL_HEADER +#endif /* CYHAL_RTC_IMPL_HEADER */ + /** \} group_hal_rtc */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h index 4b5bf01f346..6fcd9e73547 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h @@ -22,20 +22,72 @@ * limitations under the License. *******************************************************************************/ +/** + * \addtogroup group_hal_scb_common PSoC 6 SCB Common Functionality + * \ingroup group_hal_psoc6 + * \{ + * Code shared between the SCB resources (UART, I2C, and SPI). + * + * \defgroup group_hal_scb_common_macros Macros + * \defgroup group_hal_scb_common_constants Constants + * \defgroup group_hal_scb_common_functions Functions + * \defgroup group_hal_scb_common_data_structures Data Structures + * \defgroup group_hal_scb_common_enums Enumerated Types + */ + #pragma once #include "cy_device.h" #include "cy_pdl.h" +#include "cyhal_utils.h" #if defined(__cplusplus) extern "C" { #endif +/** + * \addtogroup group_hal_scb_common_constants + * \{ + */ + /** The start address of the SCB blocks */ -extern CySCB_Type* CY_SCB_BASE_ADDRESSES[CY_IP_MXSCB_INSTANCES]; +extern CySCB_Type* CYHAL_SCB_BASE_ADDRESSES[CY_IP_MXSCB_INSTANCES]; /** The interrupt number of the SCB blocks. */ -extern IRQn_Type CY_SCB_IRQ_N[CY_IP_MXSCB_INSTANCES]; +extern IRQn_Type CYHAL_SCB_IRQ_N[CY_IP_MXSCB_INSTANCES]; + +/** The configuration structs for the resource in use on each SCB block (e.g. cyhal_i2c_t) */ +extern void *cyhal_scb_config_structs[CY_IP_MXSCB_INSTANCES]; + +/** \} group_hal_scb_common_constants */ + + +/** + * \addtogroup group_hal_scb_common_functions + * \{ + */ + +/** Get the SCB block corresponding to an IRQn. + * + * @param[in] irqn The IRQn to get the corresponding block from + * @return The corresponding SCB block + */ +uint8_t cyhal_scb_get_block_from_irqn(IRQn_Type irqn); + +/** Get the SCB object corresponding to the currently running ISR. + * + * @return A pointer to the SCB object corresponding to the currently running ISR. + */ +__STATIC_INLINE void *cyhal_scb_get_irq_obj(void) +{ + IRQn_Type irqn = CYHAL_GET_CURRENT_IRQN(); + uint8_t block = cyhal_scb_get_block_from_irqn(irqn); + return cyhal_scb_config_structs[block]; +} + +/** \} group_hal_scb_common_functions */ #if defined(__cplusplus) } #endif + +/** \} group_hal_scb_common */ \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h index e2129adbf88..c1e400d44b7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h @@ -48,6 +48,16 @@ extern "C" { #endif +/** +* \addtogroup group_hal_sdhc_macros +* \{ +*/ + +#define CYHAL_SDHC_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 0)) /**< Pin related Error. >*/ + +/** \} group_hal_sdhc_macros */ + + /** * \addtogroup group_hal_sdhc_enums * \{ @@ -83,23 +93,35 @@ typedef enum { CYHAL_SDHC_CQE_EVENT, //!> This status is set if Command Queuing/Crypto event has occurred CYHAL_SDHC_ERR_INTERRUPT, //!> If any of the bits in the Error Interrupt Status register are set CYHAL_SDHC_ALL_INTERRUPTS, //!> Is used to enable/disable all interrupts -} cyhal_sdhc_irq_event_t; +} cyhal_sdhc_event_t; /** \} group_hal_sdhc_enums */ + +/** +* \addtogroup group_hal_sdhc_macros +* \{ +*/ + +#define CYHAL_SDHC_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 0)) /**< Pin related Error. >*/ + +/** \} group_hal_sdhc_macros */ + + /** * \addtogroup group_hal_sdhc_data_structures * \{ */ /** Handler for SDHC interrupts */ -typedef void (*cyhal_sdhc_irq_handler_t)(void *handler_arg, cyhal_sdhc_irq_event_t event); +typedef void (*cyhal_sdhc_event_callback_t)(void *callback_arg, cyhal_sdhc_event_t event); /** Defines configuration options for the SDHC block */ typedef struct { bool enableLedControl; //!< Drive one IO to indicate when the card is being accessed bool lowVoltageSignaling; //!< Whether 1.8V signaling is supported + bool isEmmc; //!< true if eMMC card, other way false uint8_t busWidth; //!< The desired bus width } cyhal_sdhc_config_t; @@ -114,6 +136,7 @@ typedef struct /** Initialize the SDHC peripheral * * @param[out] obj The SDHC object + * @param[in] config The card configuration object * @param[out] clk The pin connected to the clk signal * @param[in] cmd The pin connected to the command signal * @param[in] data0 The pin connected to the data0 signal @@ -133,22 +156,23 @@ typedef struct * @return The status of the init request */ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, - cyhal_gpio_t cmd, - cyhal_gpio_t clk, - cyhal_gpio_t data0, - cyhal_gpio_t data1, - cyhal_gpio_t data2, - cyhal_gpio_t data3, - cyhal_gpio_t data4, - cyhal_gpio_t data5, - cyhal_gpio_t data6, - cyhal_gpio_t data7, - cyhal_gpio_t cardDetect, - cyhal_gpio_t ioVoltSel, - cyhal_gpio_t cardIfPwrEn, - cyhal_gpio_t cardMechWriteProt, - cyhal_gpio_t ledCtrl, - cyhal_gpio_t cardEmmcReset); + const cyhal_sdhc_config_t *config, + cyhal_gpio_t cmd, + cyhal_gpio_t clk, + cyhal_gpio_t data0, + cyhal_gpio_t data1, + cyhal_gpio_t data2, + cyhal_gpio_t data3, + cyhal_gpio_t data4, + cyhal_gpio_t data5, + cyhal_gpio_t data6, + cyhal_gpio_t data7, + cyhal_gpio_t cardDetect, + cyhal_gpio_t ioVoltSel, + cyhal_gpio_t cardIfPwrEn, + cyhal_gpio_t cardMechWriteProt, + cyhal_gpio_t ledCtrl, + cyhal_gpio_t cardEmmcReset); /** Release the SDHC peripheral, not currently invoked. It requires further * resource management. @@ -157,14 +181,6 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, */ void cyhal_sdhc_free(cyhal_sdhc_t *obj); -/** Configure the SDHC block. - * - * @param[in,out] obj The SDHC object - * @param[in] config The card configuration object - * @return The status of the configure request - */ -cy_rslt_t cyhal_sdhc_configure(cyhal_sdhc_t *obj, const cyhal_sdhc_config_t *config); - /** Attempts to read data over the SDHC peripheral. * * @param[in] obj The SDHC object @@ -228,21 +244,22 @@ bool cyhal_sdhc_is_busy(const cyhal_sdhc_t *obj); */ cy_rslt_t cyhal_sdhc_abort_async(const cyhal_sdhc_t *obj); -/** The SDHC interrupt handler registration +/** The SDHC callback handler registration * - * @param[in] obj The SDHC object - * @param[in] handler The callback handler which will be invoked when the interrupt fires - * @param[in] handler_arg Generic argument that will be provided to the handler when called + * @param[in] obj The SDHC object + * @param[in] callback The callback handler which will be invoked when the interrupt fires + * @param[in] callback_arg Generic argument that will be provided to the callback when called */ -void cyhal_sdhc_register_irq(cyhal_sdhc_t *obj, cyhal_sdhc_irq_handler_t handler, void *handler_arg); +void cyhal_sdhc_register_callback(cyhal_sdhc_t *obj, cyhal_sdhc_event_callback_t callback, void *callback_arg); -/** Configure SDHC interrupt enablement. +/** Configure SDHC event enablement. * - * @param[in] obj The SDHC object - * @param[in] event The SDHC IRQ type - * @param[in] enable True to turn on interrupts, False to turn off + * @param[in] obj The SDHC object + * @param[in] event The SDHC event type + * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off */ -void cyhal_sdhc_irq_enable(cyhal_sdhc_t *obj, cyhal_sdhc_irq_event_t event, bool enable); +void cyhal_sdhc_enable_event(cyhal_sdhc_t *obj, cyhal_sdhc_event_t event, uint8_t intrPriority, bool enable); /** \} group_hal_sdhc_functions */ @@ -250,4 +267,8 @@ void cyhal_sdhc_irq_enable(cyhal_sdhc_t *obj, cyhal_sdhc_irq_event_t event, bool } #endif +#ifdef CYHAL_SDHC_IMPL_HEADER +#include CYHAL_SDHC_IMPL_HEADER +#endif /* CYHAL_SDHC_IMPL_HEADER */ + /** \} group_hal_sdhc */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h index 6066f433737..21ae340a184 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h @@ -54,20 +54,21 @@ extern "C" { * \{ */ -#define CYHAL_SDIO_RET_NO_ERRORS (0x00) /**< No error*/ -#define CYHAL_SDIO_RET_NO_SP_ERRORS (0x01) /**< Non-specific error code*/ -#define CYHAL_SDIO_RET_CMD_CRC_ERROR (0x02) /**< There was a CRC error on the Command/Response*/ -#define CYHAL_SDIO_RET_CMD_IDX_ERROR (0x04) /**< The index for the command didn't match*/ -#define CYHAL_SDIO_RET_CMD_EB_ERROR (0x08) /**< There was an end bit error on the command*/ -#define CYHAL_SDIO_RET_DAT_CRC_ERROR (0x10) /**< There was a data CRC Error*/ -#define CYHAL_SDIO_RET_CMD_TIMEOUT (0x20) /**< The command didn't finish before the timeout period was over*/ -#define CYHAL_SDIO_RET_DAT_TIMEOUT (0x40) /**< The data didn't finish before the timeout period was over*/ -#define CYHAL_SDIO_RET_RESP_FLAG_ERROR (0x80) /**< There was an error in the resposne flag for command 53*/ - -#define CYHAL_SDIO_CLOCK_ERROR (0x100) /**< Failed to initial clock for SDIO */ -#define CYHAL_SDIO_BAD_ARGUMENT (0x200) /**< Bad argument passed for SDIO */ -#define CYHAL_SDIO_SEMA_NOT_INITED (0x400) /**< Semaphore is not initiated */ -#define CYHAL_SDIO_FUNC_NOT_SUPPORTED (0x800) /**< Function is not supported */ +#define CYHAL_SDIO_RET_NO_ERRORS (0x00) /**< No error*/ +#define CYHAL_SDIO_RET_NO_SP_ERRORS (0x01) /**< Non-specific error code*/ +#define CYHAL_SDIO_RET_CMD_CRC_ERROR (0x02) /**< There was a CRC error on the Command/Response*/ +#define CYHAL_SDIO_RET_CMD_IDX_ERROR (0x04) /**< The index for the command didn't match*/ +#define CYHAL_SDIO_RET_CMD_EB_ERROR (0x08) /**< There was an end bit error on the command*/ +#define CYHAL_SDIO_RET_DAT_CRC_ERROR (0x10) /**< There was a data CRC Error*/ +#define CYHAL_SDIO_RET_CMD_TIMEOUT (0x20) /**< The command didn't finish before the timeout period was over*/ +#define CYHAL_SDIO_RET_DAT_TIMEOUT (0x40) /**< The data didn't finish before the timeout period was over*/ +#define CYHAL_SDIO_RET_RESP_FLAG_ERROR (0x80) /**< There was an error in the resposne flag for command 53*/ + +#define CYHAL_SDIO_CLOCK_ERROR (0x100) /**< Failed to initial clock for SDIO */ +#define CYHAL_SDIO_BAD_ARGUMENT (0x200) /**< Bad argument passed for SDIO */ +#define CYHAL_SDIO_SEMA_NOT_INITED (0x400) /**< Semaphore is not initiated */ +#define CYHAL_SDIO_FUNC_NOT_SUPPORTED (0x800) /**< Function is not supported */ +#define CYHAL_SDIO_CANCELED (0x1000) /**< Operation canceled */ /* HAL return value defines */ @@ -90,8 +91,12 @@ extern "C" { #define CYHAL_SDIO_RSLT_ERR_FUNC_RET(retVal) CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, \ CYHAL_RSLT_MODULE_SDIO, (retVal)) -/** \} group_hal_sdio_macros */ +/** Define to indicate canceled operation */ +#define CYHAL_SDIO_RSLT_CANCELED CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, \ + CYHAL_RSLT_MODULE_SDIO, \ + CYHAL_SDIO_CANCELED) +/** \} group_hal_sdio_macros */ /** * \addtogroup group_hal_sdio_enums @@ -101,13 +106,13 @@ extern "C" { /** Commands that can be issued */ typedef enum { - CYHAL_SDIO_CMD_GO_IDLE_STATE = 0, //!> Go to idle state - CYHAL_SDIO_CMD_SEND_RELATIVE_ADDR = 3, //!> Send a relative address - CYHAL_SDIO_CMD_IO_SEND_OP_COND = 5, //!> Send an OP IO - CYHAL_SDIO_CMD_SELECT_CARD = 7, //!> Send a card select - CYHAL_SDIO_CMD_GO_INACTIVE_STATE = 15, //!> Go to inactive state - CYHAL_SDIO_CMD_IO_RW_DIRECT = 52, //!> Perform a direct read/write - CYHAL_SDIO_CMD_IO_RW_EXTENDED = 53, //!> Perform an extended read/write + CYHAL_SDIO_CMD_GO_IDLE_STATE = 0, //!> Go to idle state + CYHAL_SDIO_CMD_SEND_RELATIVE_ADDR = 3, //!> Send a relative address + CYHAL_SDIO_CMD_IO_SEND_OP_COND = 5, //!> Send an OP IO + CYHAL_SDIO_CMD_SELECT_CARD = 7, //!> Send a card select + CYHAL_SDIO_CMD_GO_INACTIVE_STATE = 15, //!> Go to inactive state + CYHAL_SDIO_CMD_IO_RW_DIRECT = 52, //!> Perform a direct read/write + CYHAL_SDIO_CMD_IO_RW_EXTENDED = 53, //!> Perform an extended read/write } cyhal_sdio_command_t; /** Types of transfer that can be performed */ @@ -117,26 +122,32 @@ typedef enum CYHAL_WRITE //!> Write to the card } cyhal_transfer_t; -/** Events that can cause an SDIO interrupt */ +/** Types of events that could be asserted by SDIO */ typedef enum { - CYHAL_SDIO_CMD_COMPLETE = 0x0001, //!> Command Complete - CYHAL_SDIO_XFER_COMPLETE = 0x0002, //!> Host read/write transfer is complete - CYHAL_SDIO_BGAP_EVENT = 0x0004, //!> This bit is set when both read/write transaction is stopped - CYHAL_SDIO_DMA_INTERRUPT = 0x0008, //!> Host controller detects an SDMA Buffer Boundary during transfer - CYHAL_SDIO_BUF_WR_READY = 0x0010, //!> This bit is set if the Buffer Write Enable changes from 0 to 1 - CYHAL_SDIO_BUF_RD_READY = 0x0020, //!> This bit is set if the Buffer Read Enable changes from 0 to 1 - CYHAL_SDIO_CARD_INSERTION = 0x0040, //!> This bit is set if the Card Inserted in the Present State - CYHAL_SDIO_CARD_REMOVAL = 0x0080, //!> This bit is set if the Card Inserted in the Present State - CYHAL_SDIO_CARD_INTERRUPT = 0x0100, //!> The synchronized value of the DAT[1] interrupt input for SD mode - CYHAL_SDIO_INT_A = 0x0200, //!> Reserved: set to 0 - CYHAL_SDIO_INT_B = 0x0400, //!> Reserved: set to 0 - CYHAL_SDIO_INT_C = 0x0800, //!> Reserved: set to 0, - CYHAL_SDIO_RE_TUNE_EVENT = 0x1000, //!> Reserved: set to 0, - CYHAL_SDIO_FX_EVENT = 0x2000, //!> This status is set when R[14] of response register is set to 1 - CYHAL_SDIO_CQE_EVENT = 0x4000, //!> This status is set if Command Queuing/Crypto event has occurred - CYHAL_SDIO_ERR_INTERRUPT = 0x8000, //!> If any of the bits in the Error Interrupt Status register are set - CYHAL_SDIO_ALL_INTERRUPTS = 0xE1FF, //!> Is used to enable/disable all interrupts -} cyhal_sdio_irq_event_t; + /* Interrupt-based thread events */ + CYHAL_SDIO_CMD_COMPLETE = 0x00001, //!> Command Complete + CYHAL_SDIO_XFER_COMPLETE = 0x00002, //!> Host read/write transfer is complete + CYHAL_SDIO_BGAP_EVENT = 0x00004, //!> This bit is set when both read/write transaction is stopped + CYHAL_SDIO_DMA_INTERRUPT = 0x00008, //!> Host controller detects an SDMA Buffer Boundary during transfer + CYHAL_SDIO_BUF_WR_READY = 0x00010, //!> This bit is set if the Buffer Write Enable changes from 0 to 1 + CYHAL_SDIO_BUF_RD_READY = 0x00020, //!> This bit is set if the Buffer Read Enable changes from 0 to 1 + CYHAL_SDIO_CARD_INSERTION = 0x00040, //!> This bit is set if the Card Inserted in the Present State + CYHAL_SDIO_CARD_REMOVAL = 0x00080, //!> This bit is set if the Card Inserted in the Present State + CYHAL_SDIO_CARD_INTERRUPT = 0x00100, //!> The synchronized value of the DAT[1] interrupt input for SD mode + CYHAL_SDIO_INT_A = 0x00200, //!> Reserved: set to 0 + CYHAL_SDIO_INT_B = 0x00400, //!> Reserved: set to 0 + CYHAL_SDIO_INT_C = 0x00800, //!> Reserved: set to 0 + CYHAL_SDIO_RE_TUNE_EVENT = 0x01000, //!> Reserved: set to 0 + CYHAL_SDIO_FX_EVENT = 0x02000, //!> This status is set when R[14] of response register is set to 1 + CYHAL_SDIO_CQE_EVENT = 0x04000, //!> This status is set if Command Queuing/Crypto event has occurred + CYHAL_SDIO_ERR_INTERRUPT = 0x08000, //!> If any of the bits in the Error Interrupt Status register are set + + /* Non-interrupt-based thread events */ + CYHAL_SDIO_GOING_DOWN = 0x10000, //!> The interface is going away (eg: powering down for some period of time) + CYHAL_SDIO_COMING_UP = 0x20000, //!> The interface is back up (eg: came back from a low power state) + + CYHAL_SDIO_ALL_INTERRUPTS = 0x0E1FF, //!> Is used to enable/disable all interrupts events +} cyhal_sdio_event_t; /** \} group_hal_sdio_enums */ @@ -150,11 +161,11 @@ typedef enum { typedef struct { uint32_t frequencyhal_hz; //!< Clock frequency, in hertz - uint16_t block_size; //!< Block size + uint16_t block_size; //!< Block size } cyhal_sdio_cfg_t; -/** Handler for SDIO interrupts */ -typedef void (*cyhal_sdio_irq_handler_t)(void *handler_arg, cyhal_sdio_irq_event_t event); +/** Callback for SDIO events */ +typedef void (*cyhal_sdio_event_callback_t)(void *callback_arg, cyhal_sdio_event_t event); /** \} group_hal_sdio_data_structures */ @@ -187,7 +198,7 @@ void cyhal_sdio_free(cyhal_sdio_t *obj); /** Configure the SDIO block. * * @param[in,out] obj The SDIO object - * @param[in] config The sdio configuration to apply + * @param[in] config The SDIO configuration to apply * @return The status of the configure request */ cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config); @@ -242,26 +253,42 @@ bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj); */ cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj); -/** The sdio interrupt handler registration +/** The SDIO event callback registration * - * @param[in] obj The SDIO object - * @param[in] handler The callback handler which will be invoked when the interrupt fires - * @param[in] handler_arg Generic argument that will be provided to the handler when called + * @param[in] obj The SDIO object + * @param[in] callback The callback function which will be invoked when the event triggers + * @param[in] callback_arg Generic argument that will be provided to the callback when executed */ -void cyhal_sdio_register_irq(cyhal_sdio_t *obj, cyhal_sdio_irq_handler_t handler, void *handler_arg); +void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_event_callback_t callback, void *callback_arg); -/** Configure sdio interrupt. +/** Configure which SDIO events trigger callbacks. * - * @param[in] obj The SDIO object - * @param[in] event The sdio IRQ type - * @param[in] enable Set to non-zero to enable events, or zero to disable them + * @param[in] obj The SDIO object + * @param[in] event The SDIO event type + * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] enable Set to true to enable events, or false to disable them */ -void cyhal_sdio_irq_enable(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, bool enable); +void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_event_t event, uint8_t intrPriority, bool enable); /** \} group_hal_sdio_functions */ +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +#define cyhal_sdio_register_irq cyhal_sdio_register_callback +#define cyhal_sdio_irq_enable(obj, event, enable) cyhal_sdio_enable_event(obj, event, CYHAL_ISR_PRIORITY_DEFAULT, enable) +typedef cyhal_sdio_event_t cyhal_sdio_irq_event_t; +typedef cyhal_sdio_event_callback_t cyhal_sdio_irq_handler_t; +/** \endcond */ + #if defined(__cplusplus) } #endif +#ifdef CYHAL_SDIO_IMPL_HEADER +#include CYHAL_SDIO_IMPL_HEADER +#endif /* CYHAL_SDIO_IMPL_HEADER */ + /** \} group_hal_sdio */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h index 65a38448794..d242c050e40 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h @@ -42,8 +42,8 @@ #include #include #include "cy_result.h" -#include "cyhal_implementation.h" -#include "cyhal_hwmgr.h" +#include "cyhal_hw_types.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { @@ -72,20 +72,21 @@ extern "C" { /** \} group_hal_spi_macros */ +/** Compatibility define for cyhal_spi_set_frequency. */ +#define cyhal_spi_frequency cyhal_spi_set_frequency /** SPI interrupt triggers */ typedef enum { - CYHAL_SPI_IRQ_NONE = 0, //!< Disable all interrupt call backs /** All transfer data has been moved into data FIFO */ CYHAL_SPI_IRQ_DATA_IN_FIFO = 1 << 1, /** Transfer complete. */ CYHAL_SPI_IRQ_DONE = 1 << 2, /** An error occurred while transferring data */ CYHAL_SPI_IRQ_ERROR = 1 << 3, -} cyhal_spi_irq_event_t; +} cyhal_spi_event_t; /** Handler for SPI interrupts */ -typedef void (*cyhal_spi_irq_handler_t)(void *handler_arg, cyhal_spi_irq_event_t event); +typedef void (*cyhal_spi_event_callback_t)(void *callback_arg, cyhal_spi_event_t event); /** SPI operating modes */ typedef enum @@ -152,24 +153,27 @@ void cyhal_spi_free(cyhal_spi_t *obj); * Configures the SPI peripheral's baud rate * @param[in,out] obj The SPI object to configure * @param[in] hz The baud rate in Hz - * @return The status of the frequency request + * @return The status of the set_frequency request */ -cy_rslt_t cyhal_spi_frequency(cyhal_spi_t *obj, uint32_t hz); +cy_rslt_t cyhal_spi_set_frequency(cyhal_spi_t *obj, uint32_t hz); /** Get a received value out of the SPI receive buffer * - * Blocks until a value is available + * In Master mode - transmits fill-in value and read the data from RxFifo + * In Slave mode - Blocks until a value is available * @param[in] obj The SPI peripheral to read * @param[in] value The value received * @return The status of the read request - * @note + * @note * - In Master mode, MISO pin required to be non-NC for this API to operate * - In Slave mode, MOSI pin required to be non-NC for this API to operate */ -cy_rslt_t cyhal_spi_read(cyhal_spi_t *obj, uint32_t* value); +cy_rslt_t cyhal_spi_recv(cyhal_spi_t *obj, uint32_t* value); -/** Write a byte out +/** Send a byte out * + * In Master mode transmits value to slave and read/drop a value from the RxFifo. + * In Slave mode writes a value to TxFifo * @param[in] obj The SPI peripheral to use for sending * @param[in] value The value to send * @return The status of the write request @@ -177,7 +181,7 @@ cy_rslt_t cyhal_spi_read(cyhal_spi_t *obj, uint32_t* value); * - In Master mode, MOSI pin required to be non-NC for this API to operate * - In Slave mode, MISO pin required to be non-NC for this API to operate */ -cy_rslt_t cyhal_spi_write(cyhal_spi_t *obj, uint32_t value); +cy_rslt_t cyhal_spi_send(cyhal_spi_t *obj, uint32_t value); /** Write a block out and receive a value * @@ -222,24 +226,39 @@ bool cyhal_spi_is_busy(cyhal_spi_t *obj); */ cy_rslt_t cyhal_spi_abort_async(cyhal_spi_t *obj); -/** The SPI interrupt handler registration +/** The SPI callback handler registration * * @param[in] obj The SPI object - * @param[in] handler The callback handler which will be invoked when the interrupt fires - * @param[in] handler_arg Generic argument that will be provided to the handler when called + * @param[in] callback The callback handler which will be invoked when the interrupt fires + * @param[in] callback_arg Generic argument that will be provided to the callback when called */ -void cyhal_spi_register_irq(cyhal_spi_t *obj, cyhal_spi_irq_handler_t handler, void *handler_arg); +void cyhal_spi_register_callback(cyhal_spi_t *obj, cyhal_spi_event_callback_t callback, void *callback_arg); /** Configure SPI interrupt. This function is used for word-approach * * @param[in] obj The SPI object - * @param[in] event The SPI IRQ type + * @param[in] event The SPI event type + * @param[in] intrPriority The priority for NVIC interrupt events * @param[in] enable True to turn on interrupts, False to turn off */ -void cyhal_spi_irq_enable(cyhal_spi_t *obj, cyhal_spi_irq_event_t event, bool enable); +void cyhal_spi_enable_event(cyhal_spi_t *obj, cyhal_spi_event_t event, uint8_t intrPriority, bool enable); + +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +typedef cyhal_spi_event_t cyhal_spi_irq_event_t; +/** \endcond */ /** \} group_hal_spi_functions */ #if defined(__cplusplus) } #endif + +#ifdef CYHAL_SPI_IMPL_HEADER +#include CYHAL_SPI_IMPL_HEADER +#endif /* CYHAL_SPI_IMPL_HEADER */ + +/** \} group_hal_spi */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h index 59252226343..d30ff720253 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h @@ -42,9 +42,9 @@ #include #include -#include "cyhal_hwmgr.h" #include "cy_result.h" #include "cyhal_hw_types.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { @@ -95,7 +95,7 @@ uint32_t cyhal_system_critical_section_enter(void); void cyhal_system_critical_section_exit(uint32_t oldState); /** Send the device to sleep - * + * * * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the * system clock to the core is stopped until a reset or an interrupt occurs. @@ -119,34 +119,42 @@ cy_rslt_t cyhal_system_deepsleep(void); /** Register the specified handler with the power manager to be notified when the power * state changes. * - * @param[in] handler The handler to notify on power transitions + * @param[in] callback The handler to notify on power transitions * @return The status of the register_callback request */ -cy_rslt_t cyhal_system_register_callback(cyhal_system_call_back_t *handler); +cy_rslt_t cyhal_system_register_callback(cyhal_system_callback_t *callback); /** Removes the specified handler from the power manager so no future notification are made. * - * @param[in] handler The handler to remove from receiving notifications + * @param[in] callback The handler to remove from receiving notifications * @return The status of the unregister_callback request */ -cy_rslt_t cyhal_system_unregister_callback(cyhal_system_call_back_t const *handler); +cy_rslt_t cyhal_system_unregister_callback(cyhal_system_callback_t const *callback); + +/** Gets the specified clock's current frequency. + * + * @param[in] clock ID of clock to configure + * @param[out] frequency_hz The frequency the clock is currently running at + * @return The status of the get_frequency request + */ +cy_rslt_t cyhal_system_clock_get_frequency(uint8_t clock, uint32_t *frequency_hz); /** Sets the specified clock's frequency and enables it. * This will turn on any additional clocks needed to drive this. * * @param[in] clock ID of clock to configure - * @param[in] frequencyhal_hz The frequency to run the clock at - * @return The status of the clock_frequency request + * @param[in] frequency_hz The frequency to run the clock at + * @return The status of the set_frequency request */ -cy_rslt_t cyhal_system_clock_frequency(uint8_t clock, uint32_t frequencyhal_hz); +cy_rslt_t cyhal_system_clock_set_frequency(uint8_t clock, uint32_t frequency_hz); /** Divides the clock frequency by the divider - * + * * @param[in] clock The clock to configure divider value for * @param[in] divider The divider value to divide the frequency by - * @return The status of setting the divider + * @return The status of the set_divider request */ -cy_rslt_t cyhal_system_clock_divider(cyhal_system_clock_t clock, cyhal_system_divider_t divider); +cy_rslt_t cyhal_system_clock_set_divider(cyhal_system_clock_t clock, cyhal_system_divider_t divider); /** \} group_hal_system_functions */ @@ -154,4 +162,8 @@ cy_rslt_t cyhal_system_clock_divider(cyhal_system_clock_t clock, cyhal_system_di } #endif +#ifdef CYHAL_SYSTEM_IMPL_HEADER +#include CYHAL_SYSTEM_IMPL_HEADER +#endif /* CYHAL_SYSTEM_IMPL_HEADER */ + /** \} group_hal_system */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h new file mode 100644 index 00000000000..6371f80fe43 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h @@ -0,0 +1,108 @@ +/***************************************************************************//** +* \file cyhal_tcpwm_common.h +* +* \brief +* Code shared between the Cypress Timer/Counter and PWM. +* +******************************************************************************** +* \copyright +* Copyright 2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** + * \addtogroup group_hal_tcpwm_common PSoC 6 TCPWM Common Functionality + * \ingroup group_hal_psoc6 + * \{ + * Code shared between the Cypress Timer / Counter and PWM. + * + * \defgroup group_hal_tcpwm_common_macros Macros + * \defgroup group_hal_tcpwm_common_constants Constants + * \defgroup group_hal_tcpwm_common_functions Functions + * \defgroup group_hal_tcpwm_common_data_structures Data Structures + * \defgroup group_hal_tcpwm_common_enums Enumerated Types + */ + +#pragma once + +#include +#include +#include "cyhal_hw_types.h" + +/** + * \addtogroup group_hal_tcpwm_common_data_structures + * \{ + */ + +/** Handler for TCPWM interrupts */ +typedef void(*cyhal_tcpwm_event_callback_t)(void *callback_arg, int event); + +/** Holds data about a single TCPWM */ +typedef struct { + TCPWM_Type* base; //!< TCPWM base + en_clk_dst_t clock_dst; //!< TCPWM clock connections base + uint32_t max_count; //!< TCPWM counter width + uint8_t num_channels; //!< Number of channels on the TCPWM + uint8_t channel_offset; //!< Offset from channels on previous TCPWM + uint8_t isr_offset; //!< TCPWM base IRQn (channel 0 IRQn) +} cyhal_tcpwm_data_t; + +/** \} group_hal_tcpwm_common_data_structures */ + + +/** + * \addtogroup group_hal_tcpwm_common_constants + * \{ + */ + +/** Contains data about all of the TCPWMs */ +extern const cyhal_tcpwm_data_t CYHAL_TCPWM_DATA[CY_IP_MXTCPWM_INSTANCES]; + +/** \} group_hal_tcpwm_common_constants */ + + +/** + * \addtogroup group_hal_tcpwm_common_functions + * \{ + */ + +/** Initialize a timer/counter or PWM object's callback data. + * + * @param[in] resource The timer/counter or PWM resource + * @param[in,out] callback_data The callback data object belonging to the timer/counter or PWM + */ +void cyhal_tcpwm_init_callback_data(cyhal_resource_inst_t *resource, cyhal_event_callback_data_t *callback_data); + +/** The TCPWM interrupt handler registration + * + * @param[in] resource The timer/counter or PWM resource + * @param[in] callback The callback handler which will be invoked when the event occurs + * @param[in] callback_arg Generic argument that will be provided to the callback when called + */ +void cyhal_tcpwm_register_callback(cyhal_resource_inst_t *resource, cy_israddress callback, void *callback_arg); + +/** Configure TCPWM event enablement. + * + * @param[in] type The type of the timer/counter or PWM + * @param[in] resource The timer/counter or PWM resource + * @param[in] event The timer/counter or PWM event type + * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] enable True to turn on events, False to turn off + */ +void cyhal_tcpwm_enable_event(TCPWM_Type *type, cyhal_resource_inst_t *resource, uint32_t event, uint8_t intrPriority, bool enable); + +/** \} group_hal_tcpwm_common_functions */ + +/** \} group_hal_tcpwm_common */ \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h index f73c1deebd6..6b1197769ce 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h @@ -29,7 +29,7 @@ * \addtogroup group_hal_timer TIMER (Timer/Counter) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress GPIO. +* High level interface for interacting with the Cypress Timer. * * \defgroup group_hal_timer_macros Macros * \defgroup group_hal_timer_functions Functions @@ -43,6 +43,7 @@ #include #include "cy_result.h" #include "cyhal_hw_types.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { @@ -61,13 +62,13 @@ typedef enum CYHAL_TIMER_DIR_UP_DOWN, //!< Counts up and down, terminal count occurs on both overflow and underflow. } cyhal_timer_direction_t; -/** Timer interrupt triggers */ +/** Timer/counter interrupt triggers */ typedef enum { - CYHAL_TIMER_IRQ_NONE, - CYHAL_TIMER_IRQ_TERMINAL_COUNT, - CYHAL_TIMER_IRQ_CAPTURE_COMPARE, - CYHAL_TIMER_IRQ_ALL, -} cyhal_timer_irq_event_t; + CYHAL_TIMER_IRQ_NONE = 0, + CYHAL_TIMER_IRQ_TERMINAL_COUNT = 1 << 0, + CYHAL_TIMER_IRQ_CAPTURE_COMPARE = 1 << 1, + CYHAL_TIMER_IRQ_ALL = (1 << 2) - 1, +} cyhal_timer_event_t; /** \} group_hal_timer_enums */ @@ -93,25 +94,30 @@ typedef struct uint32_t value; //!< Current value of the timer/counter } cyhal_timer_cfg_t; -/** Handler for test interrupts */ -typedef void (*cyhal_timer_irq_handler_t)(void *handler_arg, cyhal_timer_irq_event_t event); +/** Handler for timer events */ +typedef void(*cyhal_timer_event_callback_t)(void *callback_arg, cyhal_timer_event_t event); /** \} group_hal_timer_data_structures */ /** -* \addtogroup group_hal_hwmgr_macros +* \addtogroup group_hal_timer_macros * \{ */ /** Bad argument. eg: null pointer */ #define CYHAL_TIMER_RSLT_ERR_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_TIMER, 0)) /** Failed to initialize Timer clock */ -#define CYHAL_TIMER_RSLT_ERR_CLOCK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_TIMER, 1)) +#define CYHAL_TIMER_RSLT_ERR_CLOCK_INIT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_TIMER, 1)) /** Failed to initialize Timer */ #define CYHAL_TIMER_RSLT_ERR_INIT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_TIMER, 2)) +/** Cannot change the timer frequency when a shared clock divider is in use */ +#define CYHAL_TIMER_RSLT_ERR_SHARED_CLOCK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_TIMER, 3)) -/** \} group_hal_hwmgr_macros */ +/** Default timer frequency, used when an existing clock divider is not provided to init */ +#define CYHAL_TIMER_DEFAULT_FREQ (1000000u) + +/** \} group_hal_timer_macros */ /** @@ -119,11 +125,12 @@ typedef void (*cyhal_timer_irq_handler_t)(void *handler_arg, cyhal_timer_irq_eve * \{ */ -/** Initialize the timer/counter peripheral and configure the pin +/** Initialize the timer/counter peripheral and configure the pin. * * @param[out] obj The timer/counter object to initialize * @param[in] pin optional - The timer/counter compare/capture pin to initialize * @param[in] clk optional - The shared clock to use, if not provided a new clock will be allocated + * and the timer frequency will be set to CYHAL_TIMER_DEFAULT_FREQ * @return The status of the init request */ cy_rslt_t cyhal_timer_init(cyhal_timer_t *obj, cyhal_gpio_t pin, const cyhal_clock_divider_t *clk); @@ -138,9 +145,18 @@ void cyhal_timer_free(cyhal_timer_t *obj); * * @param[in] obj The timer/counter object * @param[in] cfg The configuration of the timer/counter - * @return The status of the info request + * @return The status of the configure request + */ +cy_rslt_t cyhal_timer_configure(cyhal_timer_t *obj, const cyhal_timer_cfg_t *cfg); + +/** Configures the timer frequency. This is not valid to call if a non-null clock divider + * was provided to cyhal_timer_init + * + * @param[in] obj The timer/counter object + * @param[in] hz The frequency rate in Hz + * @return The status of the set_frequency request */ -cy_rslt_t cyhal_timer_set_config(cyhal_timer_t *obj, const cyhal_timer_cfg_t *cfg); +cy_rslt_t cyhal_timer_set_frequency(cyhal_timer_t *obj, uint32_t hz); /** Starts the timer/counter with the pre-set configuration. * @@ -156,22 +172,22 @@ cy_rslt_t cyhal_timer_start(cyhal_timer_t *obj); */ cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj); -/** The timer/counter interrupt handler registration +/** The timer/counter callback handler registration * - * @param[in] obj The timer/counter object - * @param[in] priority The NVIC interrupt channel priority - * @param[in] handler The callback handler which will be invoked when the interrupt fires - * @param[in] handler_arg Generic argument that will be provided to the handler when called + * @param[in] obj The timer/counter object + * @param[in] callback The callback handler which will be invoked when the event occurs + * @param[in] callback_arg Generic argument that will be provided to the callback when called */ -void cyhal_timer_register_irq(cyhal_timer_t *obj, uint8_t priority, cyhal_timer_irq_handler_t handler, void *handler_arg); +void cyhal_timer_register_callback(cyhal_timer_t *obj, cyhal_timer_event_callback_t callback, void *callback_arg); -/** Configure timer/counter interrupt enablement. +/** Configure timer/counter event enablement. * - * @param[in] obj The timer/counter object - * @param[in] event The timer/counter IRQ type - * @param[in] enable True to turn on interrupts, False to turn off + * @param[in] obj The timer/counter object + * @param[in] event The timer/counter event type + * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off */ -void cyhal_timer_irq_enable(cyhal_timer_t *obj, cyhal_timer_irq_event_t event, bool enable); +void cyhal_timer_enable_event(cyhal_timer_t *obj, cyhal_timer_event_t event, uint8_t intrPriority, bool enable); /** \} group_hal_timer_functions */ @@ -179,4 +195,8 @@ void cyhal_timer_irq_enable(cyhal_timer_t *obj, cyhal_timer_irq_event_t event, b } #endif +#ifdef CYHAL_TIMER_IMPL_HEADER +#include CYHAL_TIMER_IMPL_HEADER +#endif /* CYHAL_TIMER_IMPL_HEADER */ + /** \} group_hal_timer */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h new file mode 100644 index 00000000000..9693bb83910 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h @@ -0,0 +1,69 @@ +/***************************************************************************//** +* \file cyhal_timer_impl.h +* +* Description: +* Provides a high level interface for interacting with the Cypress Timer/Counter. +* +******************************************************************************** +* \copyright +* Copyright 2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cyhal_timer.h" +#include "cyhal_tcpwm_common.h" + +#if defined(CY_IP_MXTCPWM_INSTANCES) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +__STATIC_INLINE uint32_t cyhal_timer_convert_event(cyhal_timer_event_t event) +{ + uint32_t pdl_event = 0U; + if (event & CYHAL_TIMER_IRQ_TERMINAL_COUNT) + { + pdl_event |= CY_TCPWM_INT_ON_TC; + } + if (event & CYHAL_TIMER_IRQ_CAPTURE_COMPARE) + { + pdl_event |= CY_TCPWM_INT_ON_CC; + } + return pdl_event; +} + +__STATIC_INLINE void cyhal_timer_register_callback_internal(cyhal_timer_t *obj, cyhal_timer_event_callback_t callback, void *callback_arg) +{ + cyhal_tcpwm_register_callback(&(obj->resource), (cy_israddress) callback, callback_arg); +} + +#define cyhal_timer_register_callback(obj, callback, callback_arg) cyhal_timer_register_callback_internal(obj, callback, callback_arg) + +__STATIC_INLINE void cyhal_timer_enable_event_internal(cyhal_timer_t *obj, cyhal_timer_event_t event, uint8_t intrPriority, bool enable) +{ + uint32_t converted = cyhal_timer_convert_event(event); + cyhal_tcpwm_enable_event(obj->base, &(obj->resource), converted, intrPriority, enable); +} + +#define cyhal_timer_enable_event(obj, event, intrPriority, enable) cyhal_timer_enable_event_internal(obj, event, intrPriority, enable) + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* defined(CY_IP_MXTCPWM_INSTANCES) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h index 05e2c9ee921..fe2ca19539c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h @@ -43,12 +43,13 @@ #include #include "cy_result.h" #include "cyhal_hw_types.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { #endif -/** Arguments passed the function are not valid. */ +/** An invalid argument was passed to a function. */ #define CYHAL_TRNG_RSLT_ERR_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_TRNG, 0)) /** Hardware error in the crypto block. This will only occur if the Ring oscillators in the TRNG generator are explicitly * disabled during TRNG generation. @@ -86,4 +87,8 @@ uint32_t cyhal_trng_generate(const cyhal_trng_t *obj); } #endif +#ifdef CYHAL_TRNG_IMPL_HEADER +#include CYHAL_TRNG_IMPL_HEADER +#endif /* CYHAL_TRNG_IMPL_HEADER */ + /** \} group_hal_trng */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h index 5a6622c0a07..a42176d991d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h @@ -38,6 +38,7 @@ extern "C" { #define MAX_TRNG_BIT_SIZE (32UL) +// This helper function mirrors the definition of cyhal_trng_generate static inline uint32_t cyhal_trng_generate_internal(const cyhal_trng_t *obj) { CY_ASSERT(NULL != obj); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h index 89a175ea51a..29cb37b7daa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h @@ -43,6 +43,7 @@ #include #include "cy_result.h" #include "cyhal_hw_types.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { @@ -55,13 +56,13 @@ extern "C" { /** The requested resource type is invalid */ #define CYHAL_UART_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_UART, 0)) -/** Failed to confiugre power management callback */ +/** Failed to configure power management callback */ #define CYHAL_UART_RSLT_ERR_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_UART, 1)) /** The getc call timed out with no received data */ #define CY_RSLT_ERR_CSP_UART_GETC_TIMEOUT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_UART, 2)) /** The actual baud rate is greater than 10% off the requested baud rate */ #define CY_RSLT_WRN_CSP_UART_BAUD_TOLERANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_WARNING, CYHAL_RSLT_MODULE_UART, 3)) -/** The baud rate to set to if no clock is specfied in the init function */ +/** The baud rate to set to if no clock is specified in the init function */ #define CYHAL_UART_DEFAULT_BAUD 115200 /** The maximum allowable difference between baud requested and actual baud **/ #define CYHAL_UART_MAX_BAUD_PERCENT_DIFFERENCE 10 @@ -84,7 +85,7 @@ typedef enum /** Enum to enable/disable/report interrupt cause flags. */ typedef enum { - CYHAL_UART_IRQ_NONE = 0, //!< Disable all interrupt call backs + CYHAL_UART_IRQ_NONE = 0, //!< No interrupt CYHAL_UART_IRQ_TX_TRANSMIT_IN_FIFO = 1 << 1, //!< All tx data from transmit has been moved to uart FIFO CYHAL_UART_IRQ_TX_DONE = 1 << 2, //!< All tx data has been transmitted CYHAL_UART_IRQ_TX_ERROR = 1 << 3, //!< An error occurred in tx @@ -92,8 +93,8 @@ typedef enum CYHAL_UART_IRQ_RX_DONE = 1 << 5, //!< All rx data has been received CYHAL_UART_IRQ_RX_ERROR = 1 << 6, //!< An error occurred in rx CYHAL_UART_IRQ_RX_NOT_EMPTY = 1 << 7, //!< The rx hardware buffer is not empty - CYHAL_UART_IRQ_TX_EMPTY = 1 << 8, //!< The tx hardware buffer is empty -} cyhal_uart_irq_event_t; + CYHAL_UART_IRQ_TX_EMPTY = 1 << 8, //!< The tx hardware buffer is empty +} cyhal_uart_event_t; /** \} group_hal_uart_enums */ @@ -114,7 +115,7 @@ typedef struct } cyhal_uart_cfg_t; /** UART callback function type */ -typedef void (*cyhal_uart_irq_handler_t)(void *handler_arg, cyhal_uart_irq_event_t event); +typedef void (*cyhal_uart_event_callback_t)(void *callback_arg, cyhal_uart_event_t event); /** \} group_hal_uart_data_structures */ @@ -151,18 +152,18 @@ void cyhal_uart_free(cyhal_uart_t *obj); * @param[in] baudrate The baud rate to be configured * @param[out] actualbaud The actual baud rate achieved by the HAL * Specify NULL if you do not want this information. - * @return The status of the baud request + * @return The status of the set_baud request */ -cy_rslt_t cyhal_uart_baud(cyhal_uart_t *obj, uint32_t baudrate, uint32_t *actualbaud); +cy_rslt_t cyhal_uart_set_baud(cyhal_uart_t *obj, uint32_t baudrate, uint32_t *actualbaud); /** Configure the data bits, stop bits, and parity * * @param[in,out] obj The uart object * @param[in] cfg The uart configuration data for data bits, stop bits and parity. * rx_buffer and rx_buffer_size are ignored. - * @return The status of the format request + * @return The status of the configure request */ -cy_rslt_t cyhal_uart_format(cyhal_uart_t *obj, const cyhal_uart_cfg_t *cfg); +cy_rslt_t cyhal_uart_configure(cyhal_uart_t *obj, const cyhal_uart_cfg_t *cfg); /** Get character. This is a blocking call, waiting for a character * @@ -174,7 +175,7 @@ cy_rslt_t cyhal_uart_format(cyhal_uart_t *obj, const cyhal_uart_cfg_t *cfg); */ cy_rslt_t cyhal_uart_getc(cyhal_uart_t *obj, uint8_t *value, uint32_t timeout); -/** Send a character. This is a blocking call, waiting for a peripheral to be available +/** Send a character. This is a blocking call, waiting for the peripheral to be available * for writing * * @param[in] obj The uart object @@ -193,7 +194,7 @@ uint32_t cyhal_uart_readable(cyhal_uart_t *obj); /** Check the number of bytes than can be written to the transmit buffer * * @param[in] obj The uart object - * @return The number of bytes that can be written + * @return The number of bytes that can be written */ uint32_t cyhal_uart_writable(cyhal_uart_t *obj); @@ -222,7 +223,7 @@ cy_rslt_t cyhal_uart_set_flow_control(cyhal_uart_t *obj, cyhal_gpio_t cts, cyhal * @param[in,out] tx_length [in] The number of bytes to transmit, [out] number actually transmitted * @return The status of the tx request */ -cy_rslt_t cyhal_uart_tx(cyhal_uart_t *obj, void *tx, size_t *tx_length); +cy_rslt_t cyhal_uart_write(cyhal_uart_t *obj, void *tx, size_t *tx_length); /** Begin synchronous RX transfer (enable interrupt for data collecting) * The used buffer is specified in the uart object - rx_buff @@ -232,11 +233,11 @@ cy_rslt_t cyhal_uart_tx(cyhal_uart_t *obj, void *tx, size_t *tx_length); * @param[in,out] rx_length [in] The number of bytes to receive, [out] number actually received * @return The status of the rx request */ -cy_rslt_t cyhal_uart_rx(cyhal_uart_t *obj, void *rx, size_t *rx_length); +cy_rslt_t cyhal_uart_read(cyhal_uart_t *obj, void *rx, size_t *rx_length); -/** Begin asynchronous TX transfer. The transmit buffer is a user defined buffer that will be - * sent on the uart. The user must register a callback with cyhal_uart_irq_register_irq. If - * desired, TX callback events can be enabled using cyhal_uart_irq_enable with the appropriate +/** Begin asynchronous TX transfer. The transmit buffer is a user defined buffer that will be + * sent on the uart. The user must register a callback with cyhal_uart_irq_register_callback. If + * desired, TX callback events can be enabled using cyhal_uart_enable_event with the appropriate * events. * * @param[in] obj The uart object @@ -244,18 +245,18 @@ cy_rslt_t cyhal_uart_rx(cyhal_uart_t *obj, void *rx, size_t *rx_length); * @param[in] length The number of bytes to transmit * @return The status of the tx_async request */ -cy_rslt_t cyhal_uart_tx_async(cyhal_uart_t *obj, void *tx, size_t length); +cy_rslt_t cyhal_uart_write_async(cyhal_uart_t *obj, void *tx, size_t length); /** Begin asynchronous RX transfer. Recevied data is placed in the user specified buffer. - * The user must register a callback with cyhal_uart_irq_register_irq. RX callback events - * can be enabled using cyhal_uart_irq_enable with the appropriate events. + * The user must register a callback with cyhal_uart_irq_register_callback. RX callback events + * can be enabled using cyhal_uart_enable_event with the appropriate events. * * @param[in] obj The uart object * @param[out] rx The user specified receive buffer * @param[in] length The number of bytes to receive * @return The status of the rx_async request */ -cy_rslt_t cyhal_uart_rx_async(cyhal_uart_t *obj, void *rx, size_t length); +cy_rslt_t cyhal_uart_read_async(cyhal_uart_t *obj, void *rx, size_t length); /** Attempts to determine if the uart peripheral is already in use for TX * @@ -277,36 +278,42 @@ bool cyhal_uart_is_rx_active(cyhal_uart_t *obj); * @param[in] obj The uart object * @return The status of the tx_abort request */ -cy_rslt_t cyhal_uart_tx_abort(cyhal_uart_t *obj); +cy_rslt_t cyhal_uart_write_abort(cyhal_uart_t *obj); -/** Abort the ongoing RX transaction. It disables the enabled interrupt for RX and +/** Abort the ongoing read transaction. It disables the enabled interrupt for RX and * flushes the RX hardware buffer if RX FIFO is used * * @param[in] obj The uart object - * @return The status of the rx_abort request + * @return The status of the read_abort request */ -cy_rslt_t cyhal_uart_rx_abort(cyhal_uart_t *obj); +cy_rslt_t cyhal_uart_read_abort(cyhal_uart_t *obj); -/** The uart interrupt handler registration +/** The uart callback handler registration * - * @param[in] obj The uart object - * @param[in] handler The callback handler which will be invoked when the interrupt fires - * @param[in] handler_arg Generic argument that will be provided to the handler when called + * @param[in] obj The uart object + * @param[in] callback The callback handler which will be invoked when the interrupt fires + * @param[in] callback_arg Generic argument that will be provided to the callback when called */ -void cyhal_uart_register_irq(cyhal_uart_t *obj, cyhal_uart_irq_handler_t handler, void *handler_arg); +void cyhal_uart_register_callback(cyhal_uart_t *obj, cyhal_uart_event_callback_t callback, void *callback_arg); /** Configure uart interrupt. This function is used for word-approach * - * @param[in] obj The uart object - * @param[in] event The uart IRQ type, this argument supports the bitwise-or of multiple enum flag values - * @param[in] enable True to turn on interrupts, False to turn off + * @param[in] obj The uart object + * @param[in] event The uart event type, this argument supports the bitwise-or of multiple enum flag values + * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off */ -void cyhal_uart_irq_enable(cyhal_uart_t *obj, cyhal_uart_irq_event_t event, bool enable); +void cyhal_uart_enable_event(cyhal_uart_t *obj, cyhal_uart_event_t event, uint8_t intrPriority, bool enable); /** \} group_hal_uart_functions */ + #if defined(__cplusplus) } #endif +#ifdef CYHAL_UART_IMPL_HEADER +#include CYHAL_UART_IMPL_HEADER +#endif /* CYHAL_UART_IMPL_HEADER */ + /** \} group_hal_uart */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h index 36395ff19db..d84d01aebfe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h @@ -3,10 +3,10 @@ * * \brief * Provides a high level interface for interacting with the Cypress USB Device. -* This interface abstracts out the chip specific details. -* If any chip specific functionality is necessary, or performance is critical +* This interface abstracts out the chip specific details. +* If any chip specific functionality is necessary, or performance is critical * the low level functions can be used directly. -* +* ******************************************************************************** * \copyright * Copyright 2019 Cypress Semiconductor Corporation @@ -42,7 +42,8 @@ #include #include #include "cy_result.h" -#include "cyhal_hwmgr.h" +#include "cyhal_hw_types.h" +#include "cyhal_modules.h" #if defined(__cplusplus) extern "C" { @@ -58,7 +59,7 @@ extern "C" { /** The driver configuration is not supported by the HAL */ #define CYHAL_USB_DEV_RSLT_ERR_BAD_DRV_CFG (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_USB, 1)) - + /** The configuration of USB clock failed */ #define CYHAL_USB_DEV_RSLT_ERR_CLK_CFG (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_USB, 2)) @@ -80,7 +81,7 @@ extern "C" { */ /** USB Device Endpoints types */ -typedef enum +typedef enum { CYHAL_USB_DEV_EP_TYPE_CTRL = 0, CYHAL_USB_DEV_EP_TYPE_ISO = 1, @@ -108,17 +109,17 @@ typedef enum /** USB endpoint address (it consists from endpoint number and direction) */ typedef uint8_t cyhal_usb_dev_ep_t; -/** Handler for USB Device interrupt */ -typedef void (*cyhal_usb_dev_irq_handler_t)(void); +/** Callback handler for USB Device interrupt */ +typedef void (*cyhal_usb_dev_irq_callback_t)(void); -/** Handler for the transfer completion event for data endpoints (not applicable for endpoint 0)*/ -typedef void (* cyhal_usb_dev_endpoint_handler_t)(cyhal_usb_dev_ep_t endpoint); +/** Callback handler for the transfer completion event for data endpoints (not applicable for endpoint 0)*/ +typedef void (* cyhal_usb_dev_endpoint_callback_t)(cyhal_usb_dev_ep_t endpoint); -/** Handler for the events for USB Device */ -typedef void (*cyhal_usb_dev_event_handler_t)(void); +/** Callback handler for the events for USB Device */ +typedef void (*cyhal_usb_dev_event_callback_t)(void); -/** Handler for the events for USB Device */ -typedef void (*cyhal_usb_dev_sof_handler_t)(uint32_t frame_number); +/** Callback handler for the events for USB Device */ +typedef void (*cyhal_usb_dev_sof_callback_t)(uint32_t frame_number); /** \} group_hal_usb_dev_data_structures */ @@ -140,7 +141,6 @@ typedef void (*cyhal_usb_dev_sof_handler_t)(uint32_t frame_number); */ cy_rslt_t cyhal_usb_dev_init(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, cyhal_gpio_t dm, const cyhal_clock_divider_t *clk); - /** * Power down this USBPhy instance * @@ -178,7 +178,7 @@ typedef void (*cyhal_usb_dev_sof_handler_t)(uint32_t frame_number); * * @param[in,out] obj The usb device object */ - void cyhal_usb_dev_configure(cyhal_usb_dev_t *obj); + void cyhal_usb_dev_set_configured(cyhal_usb_dev_t *obj); /** * Leave the configured state @@ -189,13 +189,13 @@ typedef void (*cyhal_usb_dev_sof_handler_t)(uint32_t frame_number); * * @param[in,out] obj The usb device object */ - void cyhal_usb_dev_unconfigure(cyhal_usb_dev_t *obj); + void cyhal_usb_dev_set_unconfigured(cyhal_usb_dev_t *obj); /** * Configure start of frame interrupt enablement. * * @param[in,out] obj The usb device object - * @param[in] enable True to turn on interrupt and start calling sof callback on every frame, + * @param[in] enable True to turn on interrupt and start calling sof callback on every frame, * False to turn off interrupt and stop calling sof callback. */ void cyhal_usb_dev_sof_enable(cyhal_usb_dev_t *obj, bool enable); @@ -209,7 +209,7 @@ typedef void (*cyhal_usb_dev_sof_handler_t)(uint32_t frame_number); void cyhal_usb_dev_set_address(cyhal_usb_dev_t *obj, uint8_t address); /** - * Get wMaxPacketSize of endpoint 0. + * Get wMaxPacketSize of endpoint 0. * The endpoint 0 has dedicated buffer. * * @param[in,out] obj The usb device object @@ -277,11 +277,11 @@ uint32_t cyhal_usb_dev_ep0_get_max_packet(cyhal_usb_dev_t *obj); * @param[in] type The type of endpoint (does not care when enable parameter is false) * * @return The status of the endpoint add request - * - * @note + * + * @note * - This function cannot be used to configure endpoint 0. That must be done * with cyhal_usb_dev_ep0_get_max_packet. - * - After endpoint was enabled it must be removed with cyhal_usb_dev_endpoint_remove + * - After endpoint was enabled it must be removed with cyhal_usb_dev_endpoint_remove * and then enabled again. */ cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enable ,cyhal_usb_dev_ep_t endpoint, uint32_t maxPacket, cyhal_usb_dev_ep_type_t type); @@ -291,7 +291,7 @@ cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enab * * @param[in,out] obj The usb device object * @param[in] endpoint Endpoint to disable - * + * * @return The status of the endpoint remove request */ cy_rslt_t cyhal_usb_dev_endpoint_remove(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint); @@ -304,7 +304,7 @@ cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enab * * @param[in,out] obj The usb device object * @param[in] endpoint Endpoint to stall - * + * * @return The status of the endpoint stall request */ cy_rslt_t cyhal_usb_dev_endpoint_stall(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint); @@ -317,7 +317,7 @@ cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enab * * @param[in,out] obj The usb device object * @param[in] endpoint Endpoint to stall - * + * * @return The status of the endpoint unstall request */ cy_rslt_t cyhal_usb_dev_endpoint_unstall(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint); @@ -327,7 +327,7 @@ cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enab * * @param[in,out] obj The usb device object * @param[in] endpoint Endpoint to check stall state - * + * * @return True if endpoint stalled, false otherwise. */ bool cyhal_usb_dev_endpoint_is_stalled(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint); @@ -340,7 +340,7 @@ cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enab * @param[in] data Buffer to fill with data * @param[in] size Size of the read buffer. This must be at least * the max packet size for this endpoint. - * + * * @return The status of start a read operation */ cy_rslt_t cyhal_usb_dev_endpoint_read(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, uint8_t *data, uint32_t size); @@ -378,64 +378,62 @@ cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enab * @return The status of an abort request * * @note - * For the ISOC endpoints in pending state this function does not wait for - * bus activity completion because these endpoints do not have handshake and are - * always accessible to the Host. Therefore it is safe to call this function for + * For the ISOC endpoints in pending state this function does not wait for + * bus activity completion because these endpoints do not have handshake and are + * always accessible to the Host. Therefore it is safe to call this function for * ISOC endpoint when the Host will not access them during abort. */ cy_rslt_t cyhal_usb_dev_endpoint_abort(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint); - /** The USB Device interrupt handler registration + /** The USB Device callback handler registration * * @param[in,out] obj The usb device object - * @param[in] handler The interrupt handler function which will be invoked when the interrupt fires + * @param[in] callback The event handler function which will be invoked when the event fires * - * @return The status of the register_irq request + * @return The status of the register_irq_callback request */ -cy_rslt_t cyhal_usb_dev_register_irq(cyhal_usb_dev_t *obj, cyhal_usb_dev_irq_handler_t handler); +cy_rslt_t cyhal_usb_dev_register_irq_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_irq_callback_t callback); -/** - * Configure USB Device interrupt enablement. +/** + * Configure USB Device event enablement. * * @param[in,out] obj The usb device object - * @param[in] enable True to turn on interrupts, False to turn off + * @param[in] enable True to turn on events, False to turn off */ void cyhal_usb_dev_irq_enable(cyhal_usb_dev_t *obj, bool enable); - -/** +/** * Default USB Device interrupt handler. * * @param[in,out] obj The usb device object */ void cyhal_usb_dev_process_irq(cyhal_usb_dev_t *obj); -/** +/** * The USB Device endpoint complete callback handler registration * * @param[in,out] obj The usb device object - * @param[in] endpoint Endpoint to registers handler - * @param[in] handler The callback handler which will be invoked when the endpoint comp + * @param[in] endpoint Endpoint to registers handler + * @param[in] callback The callback handler which will be invoked when the endpoint comp */ -void cyhal_usb_dev_register_endpoint_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, cyhal_usb_dev_endpoint_handler_t handler); +void cyhal_usb_dev_register_endpoint_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, cyhal_usb_dev_endpoint_callback_t callback); -/** +/** * The USB Device event complete callback handler registration. The events are defined by x type. * * @param[in,out] obj The usb device object * @param[in] event The event that triggers the callback, see /ref cyhal_usb_dev_event_t - * @param[in] handler The callback handler which will be invoked when the interrupt fires + * @param[in] callback The callback handler which will be invoked when the interrupt fires */ -void cyhal_usb_dev_register_event_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_event_t event, cyhal_usb_dev_event_handler_t handler); - +void cyhal_usb_dev_register_event_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_event_t event, cyhal_usb_dev_event_callback_t callback); -/** +/** * The USB Device start of frame (SOF) complete callback handler registration. * * @param[in,out] obj The usb device object - * @param[in] handler The callback handler which will be invoked when the interrupt fires + * @param[in] callback The callback handler which will be invoked when the interrupt fires */ -void cyhal_usb_dev_register_sof_callback( cyhal_usb_dev_t *obj, cyhal_usb_dev_sof_handler_t handler); +void cyhal_usb_dev_register_sof_callback( cyhal_usb_dev_t *obj, cyhal_usb_dev_sof_callback_t callback); /** \} group_hal_usb_dev_functions */ @@ -443,4 +441,8 @@ void cyhal_usb_dev_register_sof_callback( cyhal_usb_dev_t *obj, cyhal_usb_dev_so } #endif +#ifdef CYHAL_USB_DEV_IMPL_HEADER +#include CYHAL_USB_DEV_IMPL_HEADER +#endif /* CYHAL_USB_DEV_IMPL_HEADER */ + /** \} group_hal_usb_dev */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h index 7322c042b48..ab9f9b6532b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h @@ -51,6 +51,9 @@ extern "C" { #define CYHAL_GET_PIN(pin) ((uint8_t)(pin & 0xFFFFUL)) /**< Macro to extract the pin number */ #define CYHAL_GET_PORT(pin) ((uint8_t)((uint32_t)(pin >> 16) & 0xFFUL)) /**< Macro to extract the port number */ +#define CYHAL_IRQN_OFFSET 16 /**< Offset for implementation-defined ISR type numbers (IRQ0 = 16) */ +#define CYHAL_GET_CURRENT_IRQN() ((IRQn_Type) (__get_IPSR() - CYHAL_IRQN_OFFSET)) /**< Macro to get the IRQn of the current ISR */ + /** Looks up the resource block that connects to the specified pins from the provided resource pin mapping table. * This is a convinience utility for cyhal_utils_get_resource() if the mappings is an array of known size. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h new file mode 100644 index 00000000000..53bb6677ab3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h @@ -0,0 +1,143 @@ +/***************************************************************************//** +* \file cyhal_wdt.h +* +* \brief +* Provides a high level interface for interacting with the Cypress Watchdog Timer. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_wdt WDT (Watchdog Timer) +* \ingroup group_hal +* \{ +* High level interface for interacting with the Cypress WDT. +* +* \defgroup group_hal_wdt_macros Macros +* \defgroup group_hal_wdt_functions Functions +* \defgroup group_hal_wdt_data_structures Data Structures +* \defgroup group_hal_wdt_enums Enumerated Types +*/ + +#pragma once + +#include "cyhal_hwmgr.h" +#include "cy_result.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_hal_wdt_macros +* \{ +*/ + +/** WDT timeout out of range */ +#define CY_RSLT_WDT_INVALID_TIMEOUT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_WDT, 0)) +/** WDT already initialized */ +#define CY_RSLT_WDT_ALREADY_INITIALIZED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_WDT, 1)) + +/** \} group_hal_wdt_macros */ + + +/** +* \addtogroup group_hal_wdt_functions +* \{ +*/ + +/** Initialize and start the WDT +* +* Initialize or re-initialize the WDT. +* \attention The specified timeout must be at least 1ms and at most the WDT's maximum timeout (see cyhal_wdt_get_max_timeout_ms()). +* +* @param[out] obj The WDT object +* @param[in] timeout_ms The time in milliseconds before the WDT times out (1ms - max) (see cyhal_wdt_get_max_timeout_ms()) +* @return The status of the init request +*/ +cy_rslt_t cyhal_wdt_init(cyhal_wdt_t *obj, uint32_t timeout_ms); + +/** Deinitialize the WDT +* +* Powers down the WDT. +* After calling this function no other WDT functions should be called except +* cyhal_wdt_init(). Calling any function other than init after freeing is +* undefined. +* +* @param[inout] obj The WDT object +*/ +void cyhal_wdt_free(cyhal_wdt_t *obj); + +/** Refresh the WDT +* +* Refreshes the WDT. This function should be called periodically to prevent the WDT from timing out. +* In the event of a timeout, the WDT resets the system. +* +* @param[inout] obj The WDT object +*/ +void cyhal_wdt_kick(cyhal_wdt_t *obj); + +/** Start the WDT +* +* Enables the WDT. +* +* @param[inout] obj The WDT object +* @return The status of the start request +*/ +void cyhal_wdt_start(cyhal_wdt_t *obj); + +/** Stop the WDT +* +* Disables the WDT. +* +* @param[inout] obj The WDT object +* @return The status of the stop request +*/ +void cyhal_wdt_stop(cyhal_wdt_t *obj); + +/** Get the WDT timeout +* +* Gets the time in milliseconds before the WDT times out. +* +* @param[inout] obj The WDT object +* @return The time in milliseconds before the WDT times out +*/ +uint32_t cyhal_wdt_get_timeout_ms(cyhal_wdt_t *obj); + +/** Gets the maximum WDT timeout +* +* Gets the maximum timeout for the WDT. +* +* @return The maximum timeout for the WDT +*/ +uint32_t cyhal_wdt_get_max_timeout_ms(void); + +/** \} group_hal_wdt_functions */ + +#if defined(__cplusplus) +} +#endif + +#ifdef CYHAL_WDT_IMPL_HEADER +#include CYHAL_WDT_IMPL_HEADER +#endif /* CYHAL_WDT_IMPL_HEADER */ + +/** \} group_hal_wdt */ \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h index 4b782c992f1..c45650269f3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -128,7 +128,7 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ @@ -144,6 +144,23 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; @@ -153,6 +170,7 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; @@ -191,6 +209,8 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[68]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[68]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h index 4711d5fd39d..d09252f4242 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE-USB package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -130,7 +130,7 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ @@ -146,6 +146,23 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; @@ -155,6 +172,7 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h index 355fc670831..0dc0fa4c2d7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 116-BGA-BLE package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -136,7 +136,7 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ @@ -152,8 +152,26 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; @@ -199,6 +217,8 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[78]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[74]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h index 6122e602ba1..d615df7c83c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 116-BGA-USB package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -136,7 +136,7 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ @@ -152,8 +152,26 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h index 6053b358e87..55b576ad6ae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 124-BGA package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -164,7 +164,7 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ @@ -189,6 +189,7 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h index 32d37636cac..ab95e612f2d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 124-BGA-SIP package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -145,7 +145,7 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ @@ -161,6 +161,23 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h index 5f3c3ed52de..07646d2fee5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 43-SMT package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -90,7 +90,7 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ @@ -103,6 +103,29 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; @@ -133,8 +156,23 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[4]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[5]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[34]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h index 8f853769c80..3e3df464af1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 68-QFN-BLE package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -96,19 +96,49 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[2]; @@ -137,11 +167,18 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[40]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[38]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h index 661d3c556b8..b5d10fba7f6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 80-WLCSP package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -122,7 +122,7 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ @@ -135,6 +135,26 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; @@ -144,6 +164,7 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[6]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[4]; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h index 4a699ee5862..ddfc61981e2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h @@ -5,7 +5,7 @@ * PSoC6_02 device GPIO HAL header for 100-WLCSP package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -144,7 +144,7 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h index 05deac13b74..9ff888efd7c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h @@ -5,7 +5,7 @@ * PSoC6_02 device GPIO HAL header for 124-BGA package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -164,7 +164,7 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h index bd94dc39d45..d349f4561fc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h @@ -5,7 +5,7 @@ * PSoC6_02 device GPIO HAL header for 128-TQFP package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -166,7 +166,7 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h index 9ef59ba1e18..03a39420971 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h @@ -5,7 +5,7 @@ * PSoC6_02 device GPIO HAL header for 68-QFN package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -114,7 +114,7 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ @@ -127,6 +127,8 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[2]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[2]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; @@ -154,19 +156,27 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[50]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[52]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h index 832fae35161..3f22c20b989 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h @@ -5,7 +5,7 @@ * PSoC6_03 device GPIO HAL header for 100-TQFP package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -125,12 +125,12 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1]; -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h index adc19a59a6f..91aa011c1c6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h @@ -5,7 +5,7 @@ * PSoC6_03 device GPIO HAL header for 49-WLCSP package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -92,13 +92,17 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1]; -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[6]; @@ -123,15 +127,23 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[5]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[5]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[36]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h index d9aa3da7dca..685c10717d1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h @@ -5,7 +5,7 @@ * PSoC6_03 device GPIO HAL header for 68-QFN package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -114,12 +114,14 @@ typedef struct { cyhal_gpio_t pin; //!< The GPIO pin const cyhal_resource_inst_t *inst; //!< The associated resource instance - cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value + cyhal_gpio_mapping_cfg_t cfg; //!< The DriveMode and HSIOM configuration value } cyhal_resource_pin_mapping_t; /* Pin connections */ -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1]; -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c index 8e2165329f5..7311cabf118 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c @@ -30,6 +30,8 @@ #include "cyhal_adc.h" #include "cyhal_analog_common.h" #include "cyhal_gpio.h" +#include "cyhal_hwmgr.h" +#include "cyhal_interconnect.h" #include "cyhal_utils.h" #if defined(CY_IP_MXS40PASS_SAR_INSTANCES) @@ -39,7 +41,7 @@ extern "C" { #endif -static SAR_Type *const cyhal_sar_base[] = +static SAR_Type *const cyhal_sar_base[] = { #if (CY_IP_MXS40PASS_SAR_INSTANCES == 1) SAR, @@ -49,7 +51,7 @@ static SAR_Type *const cyhal_sar_base[] = #endif }; -static const en_clk_dst_t cyhal_sar_clock[] = +static const en_clk_dst_t cyhal_sar_clock[] = { #if (CY_IP_MXS40PASS_SAR_INSTANCES == 1) PCLK_PASS_CLOCK_SAR, @@ -60,7 +62,7 @@ static const en_clk_dst_t cyhal_sar_clock[] = }; #define CYHAL_SAR_DEFAULT_CTRL ((uint32_t)CY_SAR_VREF_PWR_100 | (uint32_t)CY_SAR_VREF_SEL_BGR \ - | (uint32_t)CY_SAR_BYPASS_CAP_DISABLE | (uint32_t)CY_SAR_NEG_SEL_VSSA_KELVIN \ + | (uint32_t)CY_SAR_BYPASS_CAP_DISABLE | (uint32_t)CY_SAR_NEG_SEL_VREF \ | (uint32_t)CY_SAR_CTRL_NEGVREF_HW | (uint32_t)CY_SAR_CTRL_COMP_DLY_12 \ | (uint32_t)CY_SAR_COMP_PWR_100 | (uint32_t)CY_SAR_DEEPSLEEP_SARMUX_OFF \ | (uint32_t)CY_SAR_SARSEQ_SWITCH_ENABLE) @@ -142,29 +144,29 @@ static uint32_t cyhal_adc_get_fw_switch_control(cyhal_gpio_t gpio, bool is_vplus return (uint32_t)(is_vplus ? vplus_lookup[pin] : vminus_lookup[pin]); } -static uint32_t cyhal_adc_get_pin_addr(cyhal_gpio_t gpio, bool is_vplus) +static uint8_t cyhal_adc_get_pin_addr(cyhal_gpio_t gpio, bool is_vplus) { - static const cy_en_sar_chan_config_pos_pin_addr_t vplus_lookup[] = + static const cy_en_sar_chan_config_pos_pin_addr_t vplus_lookup[] = { - CY_SAR_CHAN_POS_PIN_ADDR_0, - CY_SAR_CHAN_POS_PIN_ADDR_1, - CY_SAR_CHAN_POS_PIN_ADDR_2, - CY_SAR_CHAN_POS_PIN_ADDR_3, - CY_SAR_CHAN_POS_PIN_ADDR_4, - CY_SAR_CHAN_POS_PIN_ADDR_5, - CY_SAR_CHAN_POS_PIN_ADDR_6, + CY_SAR_CHAN_POS_PIN_ADDR_0, + CY_SAR_CHAN_POS_PIN_ADDR_1, + CY_SAR_CHAN_POS_PIN_ADDR_2, + CY_SAR_CHAN_POS_PIN_ADDR_3, + CY_SAR_CHAN_POS_PIN_ADDR_4, + CY_SAR_CHAN_POS_PIN_ADDR_5, + CY_SAR_CHAN_POS_PIN_ADDR_6, CY_SAR_CHAN_POS_PIN_ADDR_7 }; - static const cy_en_sar_chan_config_neg_pin_addr_t vminus_lookup[] = + static const cy_en_sar_chan_config_neg_pin_addr_t vminus_lookup[] = { - CY_SAR_CHAN_NEG_PIN_ADDR_0, - CY_SAR_CHAN_NEG_PIN_ADDR_1, - CY_SAR_CHAN_NEG_PIN_ADDR_2, - CY_SAR_CHAN_NEG_PIN_ADDR_3, - CY_SAR_CHAN_NEG_PIN_ADDR_4, - CY_SAR_CHAN_NEG_PIN_ADDR_5, - CY_SAR_CHAN_NEG_PIN_ADDR_6, + CY_SAR_CHAN_NEG_PIN_ADDR_0, + CY_SAR_CHAN_NEG_PIN_ADDR_1, + CY_SAR_CHAN_NEG_PIN_ADDR_2, + CY_SAR_CHAN_NEG_PIN_ADDR_3, + CY_SAR_CHAN_NEG_PIN_ADDR_4, + CY_SAR_CHAN_NEG_PIN_ADDR_5, + CY_SAR_CHAN_NEG_PIN_ADDR_6, CY_SAR_CHAN_NEG_PIN_ADDR_7 }; uint8_t pin = CYHAL_GET_PIN(gpio); @@ -179,72 +181,82 @@ cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_d { const uint32_t DESIRED_DIVIDER = 8000000u; // 8 MHz. Required range is 1.7 - 18 - if (NULL == obj || CYHAL_NC_PIN_VALUE == pin) - return CYHAL_ADC_RSLT_BAD_ARGUMENT; - - memset(obj, 0, sizeof(cyhal_adc_t)); - obj->base = NULL; - obj->channel_used = 0; - obj->clock.div_num = CYHAL_RSC_INVALID; - obj->resource.type = CYHAL_RSC_INVALID; - obj->dedicated_clock = false; - - cy_rslt_t result; - const cyhal_resource_pin_mapping_t *map = CY_UTILS_GET_RESOURCE(pin, cyhal_pin_map_pass_sarmux_pads); - if (NULL == map) - return CYHAL_ADC_RSLT_BAD_ARGUMENT; + CY_ASSERT(NULL != obj); - cyhal_resource_inst_t adc_inst = *map->inst; - if (CY_RSLT_SUCCESS != (result = cyhal_hwmgr_reserve(&adc_inst))) - return result; + cy_rslt_t result = CY_RSLT_SUCCESS; - obj->resource = adc_inst; + if (CYHAL_NC_PIN_VALUE == pin) + result = CYHAL_ADC_RSLT_BAD_ARGUMENT; - obj->base = cyhal_sar_base[adc_inst.block_num]; - en_clk_dst_t pclk = (en_clk_dst_t)(cyhal_sar_clock[adc_inst.block_num]); - if (NULL != clk) + if (CY_RSLT_SUCCESS == result) { - obj->clock = *clk; + memset(obj, 0, sizeof(cyhal_adc_t)); + obj->base = NULL; + obj->channel_used = 0; + obj->clock.div_num = CYHAL_RSC_INVALID; + obj->resource.type = CYHAL_RSC_INVALID; obj->dedicated_clock = false; } - else if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false))) + + const cyhal_resource_pin_mapping_t *map = CY_UTILS_GET_RESOURCE(pin, cyhal_pin_map_pass_sarmux_pads); + if (NULL == map) + result = CYHAL_ADC_RSLT_BAD_ARGUMENT; + + cyhal_resource_inst_t adc_inst; + if (CY_RSLT_SUCCESS == result) { - obj->dedicated_clock = true; + adc_inst = *map->inst; + result = cyhal_hwmgr_reserve(&adc_inst); } - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num)) - result = CYHAL_ADC_RSLT_FAILED_CLOCK; - - if(obj->dedicated_clock) + en_clk_dst_t pclk; + if (CY_RSLT_SUCCESS == result) { - uint32_t div = cy_PeriClkFreqHz / DESIRED_DIVIDER; - if (0 == div || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num)) + obj->resource = adc_inst; + + obj->base = cyhal_sar_base[adc_inst.block_num]; + pclk = (en_clk_dst_t)(cyhal_sar_clock[adc_inst.block_num]); + if (NULL != clk) { - result = CYHAL_ADC_RSLT_FAILED_CLOCK; + obj->clock = *clk; + obj->dedicated_clock = false; + } + else if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false))) + { + obj->dedicated_clock = true; } } - if (CY_RSLT_SUCCESS == result && - !cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num)) + if (CY_RSLT_SUCCESS == result) + { + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num)) + result = CYHAL_ADC_RSLT_FAILED_CLOCK; + } + + if (CY_RSLT_SUCCESS == result) { - cy_en_sar_status_t sar_rslt = Cy_SAR_Init(obj->base, &CYHAL_SAR_DEFAULT_CONFIG); - if(sar_rslt == CY_SAR_SUCCESS) - { - result = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - } - else + if(obj->dedicated_clock) { - result = CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_ADC, CY_RSLT_GET_CODE(sar_rslt)); + uint32_t div = cy_PeriClkFreqHz / DESIRED_DIVIDER; + if (0 == div || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num)) + { + result = CYHAL_ADC_RSLT_FAILED_CLOCK; + } } } + if (CY_RSLT_SUCCESS == result) + { + result = (cy_rslt_t)Cy_SAR_Init(obj->base, &CYHAL_SAR_DEFAULT_CONFIG); + } + if (result == CY_RSLT_SUCCESS) { Cy_SAR_SetVssaSarSeqCtrl(obj->base, CY_SAR_SWITCH_SEQ_CTRL_ENABLE); Cy_SAR_SetVssaVminusSwitch(obj->base, CY_SAR_SWITCH_CLOSE); - + cyhal_analog_init(); Cy_SAR_Enable(obj->base); } @@ -272,7 +284,6 @@ void cyhal_adc_free(cyhal_adc_t *obj) cyhal_analog_free(); cyhal_hwmgr_free(&obj->resource); - cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); obj->base = NULL; } @@ -282,7 +293,9 @@ void cyhal_adc_free(cyhal_adc_t *obj) *******************************************************************************/ cy_rslt_t cyhal_adc_channel_init(cyhal_adc_channel_t *obj, cyhal_adc_t* adc, cyhal_gpio_t pin) { - if (NULL == obj || NULL == adc || CYHAL_NC_PIN_VALUE == pin) + CY_ASSERT(obj != NULL); + CY_ASSERT(adc != NULL); + if (CYHAL_NC_PIN_VALUE == pin) return CYHAL_ADC_RSLT_BAD_ARGUMENT; // Check for invalid pin or pin belonging to a different SAR @@ -293,12 +306,14 @@ cy_rslt_t cyhal_adc_channel_init(cyhal_adc_channel_t *obj, cyhal_adc_t* adc, cyh memset(obj, 0, sizeof(cyhal_adc_channel_t)); cy_rslt_t result; - // We don't need any special configuration of the pin, so just reserve it cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin); if (CY_RSLT_SUCCESS != (result = cyhal_hwmgr_reserve(&pinRsc))) return result; obj->pin = pin; + if (CY_RSLT_SUCCESS == result) + result = cyhal_connect_pin(map); + // Find the first available channel uint8_t chosen_channel = __CLZ(__RBIT(~adc->channel_used)); if(chosen_channel >= CY_SAR_MAX_NUM_CHANNELS) // No channels available diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crc.c index 333dc2a7fad..867c0056afd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crc.c @@ -30,26 +30,32 @@ #if defined(CY_IP_MXCRYPTO) +#if defined(__cplusplus) +extern "C" +{ +#endif + /******************************************************************************* * Functions *******************************************************************************/ cy_rslt_t cyhal_crc_init(cyhal_crc_t *obj) { CY_ASSERT(NULL != obj); - - memset(obj, 0, sizeof(cyhal_crc_t)); - obj->resource.type = CYHAL_RSC_CRC; - return cyhal_crypto_reserve(&(obj->base), &(obj->resource)); + // Note: this takes care of enabling the Crypto block + return cyhal_crypto_reserve(&(obj->base), &(obj->resource), CYHAL_CRYPTO_CRC); } void cyhal_crc_free(cyhal_crc_t *obj) { - CY_ASSERT(NULL != obj || obj->resource.type != CYHAL_RSC_CRC); + CY_ASSERT(NULL != obj || obj->resource.type != CYHAL_RSC_CRYPTO); if (obj->resource.type != CYHAL_RSC_INVALID) { - cyhal_crypto_free(obj->base, &(obj->resource)); - obj->resource.type = CYHAL_RSC_INVALID; + cyhal_crypto_free(obj->base, &(obj->resource), CYHAL_CRYPTO_CRC); } } +#if defined(__cplusplus) +} +#endif + #endif /* defined(CY_IP_MXCRYPTO) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c index e1db25f8435..da73153d068 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c @@ -2,8 +2,8 @@ * File Name: cyhal_crypto_common.c * * Description: -* Provides a high level interface for interacting with the Cypress CRC. This is -* a wrapper around the lower level PDL API. +* Provides a high level interface for interacting with the Cypress Crypto Accelerator. +* This is a wrapper around the lower level PDL API. * ******************************************************************************** * \copyright @@ -24,51 +24,103 @@ *******************************************************************************/ #include "cyhal_hwmgr.h" -#include "cy_crypto_core_crc.h" #include "cyhal_crypto_common.h" #if defined(CY_IP_MXCRYPTO) -CRYPTO_Type* CYHAL_CRYPTO_BASE_ADDRESSES[CYHAL_CRYPTO_INST_COUNT] = +#if defined(__cplusplus) +extern "C" +{ +#endif + +static CRYPTO_Type* CYHAL_CRYPTO_BASE_ADDRESSES[CYHAL_CRYPTO_INST_COUNT] = { #ifdef CRYPTO CRYPTO, #endif }; -cy_rslt_t cyhal_crypto_reserve(CRYPTO_Type** base, cyhal_resource_inst_t *resource) +// Number of Crypto features +#define CRYPTO_FEATURES_NUM ((uint32_t)CYHAL_CRYPTO_COMMON + 1u) + +// Defines for maximum available features in Crypto block +#define CRYPTO_FEATURE_CRC_MAX_VAL (1u) +#define CRYPTO_FEATURE_TRNG_MAX_VAL (1u) +#define CRYPTO_FEATURE_VU_MAX_VAL (256u) +#define CRYPTO_FEATURE_COMMON_MAX_VAL (256u) + +static uint16_t cyhal_crypto_features[CYHAL_CRYPTO_INST_COUNT][CRYPTO_FEATURES_NUM] = {{0}}; +static uint16_t cyhal_crypto_features_max_val[CRYPTO_FEATURES_NUM] = {CRYPTO_FEATURE_CRC_MAX_VAL, + CRYPTO_FEATURE_TRNG_MAX_VAL, + CRYPTO_FEATURE_VU_MAX_VAL, + CRYPTO_FEATURE_COMMON_MAX_VAL}; + +static bool cy_crypto_enabled(uint32_t instance_count) { - cy_rslt_t result = CYHAL_HWMGR_RSLT_ERR_NONE_FREE; + uint8_t reserved = (cyhal_crypto_features[instance_count][CYHAL_CRYPTO_CRC] | + cyhal_crypto_features[instance_count][CYHAL_CRYPTO_TRNG] | + cyhal_crypto_features[instance_count][CYHAL_CRYPTO_VU] | + cyhal_crypto_features[instance_count][CYHAL_CRYPTO_COMMON]); + + return (reserved != 0); +} + +cy_rslt_t cyhal_crypto_reserve(CRYPTO_Type** base, cyhal_resource_inst_t *resource, cyhal_crypto_feature_t feature) +{ + cy_rslt_t result = CYHAL_HWMGR_RSLT_ERR_INUSE; + for (uint32_t i = 0u; i < CYHAL_CRYPTO_INST_COUNT; i++) { - resource->block_num = i; - result = cyhal_hwmgr_reserve(resource); - if (result == CY_RSLT_SUCCESS) + if (cyhal_crypto_features[i][feature] < cyhal_crypto_features_max_val[feature]) { + resource->type = CYHAL_RSC_CRYPTO; + resource->block_num = i; + resource->channel_num = 0; *base = CYHAL_CRYPTO_BASE_ADDRESSES[i]; - Cy_Crypto_Core_Enable(*base); - result = cyhal_hwmgr_set_configured(resource->type, resource->block_num, resource->channel_num); - if (result == CY_RSLT_SUCCESS) + + result = CY_RSLT_SUCCESS; + + //Enable block if this as this first feature that is reserved in block + if (!cy_crypto_enabled(i)) { - break; + result = cyhal_hwmgr_reserve(resource); + if (result == CY_RSLT_SUCCESS) + { + Cy_Crypto_Core_Enable(*base); + } } - else + + if(result == CY_RSLT_SUCCESS) { - cyhal_hwmgr_free(resource); + ++cyhal_crypto_features[i][feature]; + break; } } } return result; } -void cyhal_crypto_free(CRYPTO_Type* base, const cyhal_resource_inst_t *resource) +void cyhal_crypto_free(CRYPTO_Type* base, cyhal_resource_inst_t *resource, cyhal_crypto_feature_t feature) { - cyhal_hwmgr_set_unconfigured(resource->type, resource->block_num, resource->channel_num); - if (Cy_Crypto_Core_IsEnabled(base)) + if (cyhal_crypto_features[resource->block_num][feature] != 0) + { + --cyhal_crypto_features[resource->block_num][feature]; + } + + //If this was the last feature then free the underlying crypto block as well. + if (!cy_crypto_enabled(resource->block_num)) { - Cy_Crypto_Core_Disable(base); + if (Cy_Crypto_Core_IsEnabled(base)) + { + Cy_Crypto_Core_Disable(base); + } + cyhal_hwmgr_free(resource); + resource->type = CYHAL_RSC_INVALID; } - cyhal_hwmgr_free(resource); } +#if defined(__cplusplus) +} +#endif + #endif /* defined(CY_IP_MXCRYPTO) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c index 746b261afab..72178689eb8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c @@ -1,5 +1,5 @@ /***************************************************************************/ /** -* \file cyhal_adc.c +* \file cyhal_dac.c * * \brief * Provides a high level interface for interacting with the Cypress Digital/Analog converter. @@ -30,6 +30,8 @@ #include "cyhal_analog_common.h" #include "cyhal_dac.h" #include "cyhal_gpio.h" +#include "cyhal_hwmgr.h" +#include "cyhal_interconnect.h" #include "cyhal_utils.h" #include "cy_pdl.h" @@ -80,52 +82,55 @@ const cy_stc_ctdac_config_t CYHAL_CTDAC_DEFAULT_CONFIG = *******************************************************************************/ cy_rslt_t cyhal_dac_init(cyhal_dac_t *obj, cyhal_gpio_t pin) { - if (NULL == obj || CYHAL_NC_PIN_VALUE == pin) - return CYHAL_DAC_RSLT_BAD_ARGUMENT; + CY_ASSERT(NULL != obj); - obj->resource.type = CYHAL_RSC_INVALID; - obj->base = NULL; - obj->pin = CYHAL_NC_PIN_VALUE; + cy_rslt_t result = CY_RSLT_SUCCESS; + + if (CYHAL_NC_PIN_VALUE == pin) + result = CYHAL_DAC_RSLT_BAD_ARGUMENT; + + if (CY_RSLT_SUCCESS == result) + { + obj->resource.type = CYHAL_RSC_INVALID; + obj->base = NULL; + obj->pin = CYHAL_NC_PIN_VALUE; + } - cy_rslt_t result; const cyhal_resource_pin_mapping_t *map = CY_UTILS_GET_RESOURCE(pin, cyhal_pin_map_pass_ctdac_voutsw); if (NULL == map) - return CYHAL_DAC_RSLT_BAD_ARGUMENT; + result = CYHAL_DAC_RSLT_BAD_ARGUMENT; + + cyhal_resource_inst_t dac_inst; + if (CY_RSLT_SUCCESS == result) + { + dac_inst = *map->inst; + result = cyhal_hwmgr_reserve(&dac_inst); + } - cyhal_resource_inst_t dac_inst = *map->inst; - if (CY_RSLT_SUCCESS != (result = cyhal_hwmgr_reserve(&dac_inst))) - return result; + if (CY_RSLT_SUCCESS == result) + { + obj->resource = dac_inst; - obj->resource = dac_inst; + obj->base = cyhal_ctdac_base[dac_inst.block_num]; - obj->base = cyhal_ctdac_base[dac_inst.block_num]; + // We don't need any special configuration of the pin, so just reserve it + cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin); + if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_reserve(&pinRsc))) + obj->pin = pin; + } - // We don't need any special configuration of the pin, so just reserve it - cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin); - if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_reserve(&pinRsc))) - obj->pin = pin; + if (CY_RSLT_SUCCESS == result) + result = cyhal_connect_pin(map); - if (CY_RSLT_SUCCESS == result && - !cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num)) + if (CY_RSLT_SUCCESS == result) { - cy_en_ctdac_status_t ctdac_rslt = Cy_CTDAC_Init(obj->base, &CYHAL_CTDAC_DEFAULT_CONFIG); - if(ctdac_rslt == CY_CTDAC_SUCCESS) - { - result = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - } - else - { - if(ctdac_rslt == CY_CTDAC_BAD_PARAM) - result = CYHAL_DAC_RSLT_BAD_ARGUMENT; - else - result = CYHAL_DAC_RSLT_FAILED_INIT; - } + result = (cy_rslt_t)Cy_CTDAC_Init(obj->base, &CYHAL_CTDAC_DEFAULT_CONFIG); } if (result == CY_RSLT_SUCCESS) { - Cy_CTDAC_Enable(obj->base); cyhal_analog_init(); + Cy_CTDAC_Enable(obj->base); } else { @@ -142,7 +147,6 @@ void cyhal_dac_free(cyhal_dac_t *obj) cyhal_analog_free(); cyhal_hwmgr_free(&obj->resource); - cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); if(obj->pin != CYHAL_NC_PIN_VALUE) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_flash.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_flash.c index 925d5d66b24..6b0feb80d94 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_flash.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_flash.c @@ -36,11 +36,32 @@ extern "C" { typedef cy_en_flashdrv_status_t (*flash_operation)(uint32_t rowAddr, const uint32_t* data); +static const cyhal_flash_block_info_t FLASH_BLOCKS[2] = +{ + // Main Flash + { + .start_address = CY_FLASH_BASE, + .size = CY_FLASH_SIZE, + .sector_size = CY_FLASH_SIZEOF_ROW, + .page_size = CY_FLASH_SIZEOF_ROW, + .erase_value = 0x00U, + }, + // Working Flash + { + .start_address = CY_EM_EEPROM_BASE, + .size = CY_EM_EEPROM_SIZE, + .sector_size = CY_FLASH_SIZEOF_ROW, + .page_size = CY_FLASH_SIZEOF_ROW, + .erase_value = 0x00U, + }, +}; + static uint8_t writeBuf[CY_FLASH_SIZEOF_ROW]; static inline bool is_in_flash(uint32_t address) { - return (CY_FLASH_BASE <= address) && (address < (CY_FLASH_BASE + CY_FLASH_SIZE)); + return ((CY_FLASH_BASE <= address) && (address < (CY_FLASH_BASE + CY_FLASH_SIZE))) || + ((CY_EM_EEPROM_BASE <= address) && (address < (CY_EM_EEPROM_BASE + CY_EM_EEPROM_SIZE))); } static inline bool is_in_sram(uint32_t address) { @@ -72,7 +93,8 @@ static cy_rslt_t run_flash_operation( cy_rslt_t cyhal_flash_init(cyhal_flash_t *obj) { - return CY_RSLT_SUCCESS; + CY_ASSERT(NULL != obj); + return CY_RSLT_SUCCESS; } void cyhal_flash_free(cyhal_flash_t *obj) @@ -83,21 +105,19 @@ void cyhal_flash_free(cyhal_flash_t *obj) void cyhal_flash_get_info(const cyhal_flash_t *obj, cyhal_flash_info_t *info) { CY_ASSERT(NULL != obj); - info->start_address = CY_FLASH_BASE; - info->size = CY_FLASH_SIZE; - info->sector_size = CY_FLASH_SIZEOF_ROW; - info->page_size = CY_FLASH_SIZEOF_ROW; - info->erase_value = 0x00U; + + info->block_count = 2; + info->blocks = &FLASH_BLOCKS[0]; } cy_rslt_t cyhal_flash_read(cyhal_flash_t *obj, uint32_t address, uint8_t *data, size_t size) { CY_ASSERT(NULL != obj); - if (address < CY_FLASH_BASE || (address + size) > (CY_FLASH_BASE + CY_FLASH_SIZE)) + if (!is_in_flash(address) || !is_in_flash(address + size - 1)) { return CYHAL_FLASH_RSLT_ERR_ADDRESS; } - memmove(data, (void *)address, size); + memcpy(data, (void *)address, size); return CY_RSLT_SUCCESS; } @@ -162,7 +182,7 @@ cy_rslt_t cyhal_flash_start_write(cyhal_flash_t *obj, uint32_t address, const ui cy_rslt_t cyhal_flash_start_program(cyhal_flash_t *obj, uint32_t address, const uint32_t* data) { CY_ASSERT(NULL != obj); - + cy_rslt_t status = is_in_flash(address) ? run_flash_operation(Cy_Flash_StartProgram, address, data, false) : CYHAL_FLASH_RSLT_ERR_ADDRESS; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_gpio.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_gpio.c index b00ab4d5021..ede264f3597 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_gpio.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_gpio.c @@ -24,6 +24,7 @@ *******************************************************************************/ #include "cyhal_gpio_impl.h" +#include "cyhal_system_impl.h" #include "cyhal_hwmgr.h" #ifdef CY_IP_MXS40IOSS @@ -36,20 +37,20 @@ extern "C" { /******************************************************************************* * Internal *******************************************************************************/ -#define CYHAL_DIRECTION_INPUT_MASK (0x08UL) /**< Mask to enable the input buffer */ -#define CYHAL_DIRECTION_OUTPUT_MASK (0x07UL) /**< Mask to disable the input buffer */ +#define CYHAL_GPIO_DIRECTION_OUTPUT_MASK (0x07UL) /**< Mask to disable the input buffer */ /* Callback array for GPIO interrupts */ -static cyhal_gpio_irq_handler_t hal_gpio_callbacks[IOSS_GPIO_GPIO_PORT_NR][CY_GPIO_PINS_MAX]; +static cyhal_gpio_event_callback_t hal_gpio_callbacks[IOSS_GPIO_GPIO_PORT_NR][CY_GPIO_PINS_MAX]; static void *hal_gpio_callback_args[IOSS_GPIO_GPIO_PORT_NR][CY_GPIO_PINS_MAX]; - /******************************************************************************* -* Dispatcher Interrrupt Service Routine +* Internal Interrrupt Service Routine *******************************************************************************/ -static void ioss_interrupts_dispatcher_IRQHandler(uint32_t port) +static void ioss_irq_handler() { + IRQn_Type irqn = CYHAL_GET_CURRENT_IRQN(); + uint32_t port = irqn - ioss_interrupts_gpio_0_IRQn; GPIO_PRT_Type *portAddr = Cy_GPIO_PortToAddr(port); for (uint8_t cnt = 0u; cnt < CY_GPIO_PINS_MAX; cnt++) @@ -59,10 +60,9 @@ static void ioss_interrupts_dispatcher_IRQHandler(uint32_t port) if (hal_gpio_callbacks[port][cnt] != NULL) { /* Call registered callbacks here */ - cyhal_gpio_irq_event_t event, edge = (cyhal_gpio_irq_event_t)Cy_GPIO_GetInterruptEdge(portAddr, cnt); + cyhal_gpio_event_t event, edge = (cyhal_gpio_event_t)Cy_GPIO_GetInterruptEdge(portAddr, cnt); switch (edge) { - case CYHAL_GPIO_IRQ_NONE: case CYHAL_GPIO_IRQ_RISE: case CYHAL_GPIO_IRQ_FALL: event = edge; @@ -78,163 +78,54 @@ static void ioss_interrupts_dispatcher_IRQHandler(uint32_t port) } } - -/******************************************************************************* -* (Internal) Interrrupt Service Routines -*******************************************************************************/ -static void ioss_interrupts_gpio_0_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_1_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_2_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_3_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_4_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_5_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_6_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_7_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_8_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_9_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_10_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_11_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_12_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_13_IRQHandler (void) __attribute__((unused)); -static void ioss_interrupts_gpio_14_IRQHandler (void) __attribute__((unused)); - -static void ioss_interrupts_gpio_0_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_0); -} - -static void ioss_interrupts_gpio_1_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_1); -} - -static void ioss_interrupts_gpio_2_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_2); -} - -static void ioss_interrupts_gpio_3_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_3); -} - -static void ioss_interrupts_gpio_4_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_4); -} - -static void ioss_interrupts_gpio_5_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_5); -} - -static void ioss_interrupts_gpio_6_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_6); -} - -static void ioss_interrupts_gpio_7_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_7); -} - -static void ioss_interrupts_gpio_8_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_8); -} - -static void ioss_interrupts_gpio_9_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_9); -} - -static void ioss_interrupts_gpio_10_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_10); -} - -static void ioss_interrupts_gpio_11_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_11); -} - -static void ioss_interrupts_gpio_12_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_12); -} - -static void ioss_interrupts_gpio_13_IRQHandler (void) +static uint32_t cyhal_gpio_convert_drive_mode(cyhal_gpio_drive_mode_t drive_mode, cyhal_gpio_direction_t direction) { - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_13); -} + uint32_t drvMode; + switch (drive_mode) + { + case CYHAL_GPIO_DRIVE_NONE: + case CYHAL_GPIO_DRIVE_ANALOG: + drvMode = CY_GPIO_DM_HIGHZ; + break; + case CYHAL_GPIO_DRIVE_PULLUP: + drvMode = CY_GPIO_DM_PULLUP; + break; + case CYHAL_GPIO_DRIVE_PULLDOWN: + drvMode = CY_GPIO_DM_PULLDOWN; + break; + case CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW: + drvMode = CY_GPIO_DM_OD_DRIVESLOW; + break; + case CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH: + drvMode = CY_GPIO_DM_OD_DRIVESHIGH; + break; + case CYHAL_GPIO_DRIVE_STRONG: + drvMode = CY_GPIO_DM_STRONG; + break; + case CYHAL_GPIO_DRIVE_PULLUPDOWN: + drvMode = CY_GPIO_DM_PULLUP_DOWN; + break; + default: + CY_ASSERT(false); + drvMode = CY_GPIO_DM_HIGHZ; + } -static void ioss_interrupts_gpio_14_IRQHandler (void) -{ - ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_14); + if (direction == CYHAL_GPIO_DIR_OUTPUT) + { + drvMode &= CYHAL_GPIO_DIRECTION_OUTPUT_MASK; + } + return drvMode; } -static void (*ioss_interrupts_dispatcher_table[IOSS_GPIO_GPIO_PORT_NR])(void) = -{ -#if (IOSS_GPIO_GPIO_PORT_NR > 0) - ioss_interrupts_gpio_0_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 1) - ioss_interrupts_gpio_1_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 2) - ioss_interrupts_gpio_2_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 3) - ioss_interrupts_gpio_3_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 4) - ioss_interrupts_gpio_4_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 5) - ioss_interrupts_gpio_5_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 6) - ioss_interrupts_gpio_6_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 7) - ioss_interrupts_gpio_7_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 8) - ioss_interrupts_gpio_8_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 9) - ioss_interrupts_gpio_9_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 10) - ioss_interrupts_gpio_10_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 11) - ioss_interrupts_gpio_11_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 12) - ioss_interrupts_gpio_12_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 13) - ioss_interrupts_gpio_13_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 14) - ioss_interrupts_gpio_14_IRQHandler, -#endif -#if (IOSS_GPIO_GPIO_PORT_NR > 15) - #error "Unhandled port count" -#endif -}; - - /******************************************************************************* -* Functions +* HAL Implementation *******************************************************************************/ cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode, bool initVal) { - cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin); /* Mbed creates GPIOs for pins that are dedicated to other peripherals in some cases. */ #ifndef __MBED__ + cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin); cy_rslt_t status = cyhal_hwmgr_reserve(&pinRsc); #else cy_rslt_t status = CY_RSLT_SUCCESS; @@ -242,16 +133,8 @@ cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cy if (status == CY_RSLT_SUCCESS) { - /* Do not check for configured for resources we do not reserve. */ -#ifndef __MBED__ - bool configured = cyhal_hwmgr_is_configured(pinRsc.type, pinRsc.block_num, pinRsc.channel_num); - if (!configured) -#endif - { - Cy_GPIO_Pin_FastInit(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), drvMode, initVal, HSIOM_SEL_GPIO); - cyhal_gpio_direction(pin, direction); //always returns success - status = cyhal_hwmgr_set_configured(pinRsc.type, pinRsc.block_num, pinRsc.channel_num); - } + uint32_t pdlDrvMode = cyhal_gpio_convert_drive_mode(drvMode, direction); + Cy_GPIO_Pin_FastInit(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), pdlDrvMode, initVal, HSIOM_SEL_GPIO); } return status; @@ -261,52 +144,45 @@ void cyhal_gpio_free(cyhal_gpio_t pin) { if (pin != CYHAL_NC_PIN_VALUE) { - cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin); - Cy_GPIO_Pin_FastInit(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), CYHAL_GPIO_DRIVE_ANALOG, 0UL, HSIOM_SEL_GPIO); - cyhal_hwmgr_set_unconfigured(pinRsc.type, pinRsc.block_num, pinRsc.channel_num); + Cy_GPIO_SetInterruptMask(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), 0); + + Cy_GPIO_Pin_FastInit(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO); /* Do not attempt to free the resource we don't reserve in mbed. */ #ifndef __MBED__ + cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin); cyhal_hwmgr_free(&pinRsc); #endif } } -cy_rslt_t cyhal_gpio_direction(cyhal_gpio_t pin, cyhal_gpio_direction_t direction) +cy_rslt_t cyhal_gpio_configure(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode) { - uint32_t drvMode = Cy_GPIO_GetDrivemode(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin)); - if ((direction == CYHAL_GPIO_DIR_INPUT) | (direction == CYHAL_GPIO_DIR_BIDIRECTIONAL)) - { - Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (drvMode | CYHAL_DIRECTION_INPUT_MASK)); - } - else - { - Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (drvMode & CYHAL_DIRECTION_OUTPUT_MASK)); - } + uint32_t pdlDrvMode = cyhal_gpio_convert_drive_mode(drvMode, direction); + Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), pdlDrvMode); return CY_RSLT_SUCCESS; } -cy_rslt_t cyhal_gpio_drivemode(cyhal_gpio_t pin, cyhal_gpio_drive_mode_t drvMode) +void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t callback, void *callback_arg) { - uint32_t inputBuf = Cy_GPIO_GetDrivemode(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin)) & CYHAL_DIRECTION_INPUT_MASK; - Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), drvMode | inputBuf); - - return CY_RSLT_SUCCESS; + uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); + hal_gpio_callbacks[CYHAL_GET_PORT(pin)][CYHAL_GET_PIN(pin)] = callback; + hal_gpio_callback_args[CYHAL_GET_PORT(pin)][CYHAL_GET_PIN(pin)] = callback_arg; + cyhal_system_critical_section_exit(savedIntrStatus); } -void cyhal_gpio_register_irq(cyhal_gpio_t pin, uint8_t intrPriority, cyhal_gpio_irq_handler_t handler, void *handler_arg) +void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intrPriority, bool enable) { - IRQn_Type irqn = (IRQn_Type)(ioss_interrupts_gpio_0_IRQn + CYHAL_GET_PORT(pin)); - - hal_gpio_callbacks[CYHAL_GET_PORT(pin)][CYHAL_GET_PIN(pin)] = handler; - hal_gpio_callback_args[CYHAL_GET_PORT(pin)][CYHAL_GET_PIN(pin)] = handler_arg; - + Cy_GPIO_SetInterruptEdge(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (uint32_t)event); + Cy_GPIO_SetInterruptMask(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (uint32_t)enable); + /* Only enable if it's not already enabled */ + IRQn_Type irqn = (IRQn_Type)(ioss_interrupts_gpio_0_IRQn + CYHAL_GET_PORT(pin)); if (NVIC_GetEnableIRQ(irqn) == 0) { cy_stc_sysint_t irqCfg = {irqn, intrPriority}; - Cy_SysInt_Init(&irqCfg, ioss_interrupts_dispatcher_table[CYHAL_GET_PORT(pin)]); + Cy_SysInt_Init(&irqCfg, ioss_irq_handler); NVIC_EnableIRQ(irqn); } else @@ -315,12 +191,6 @@ void cyhal_gpio_register_irq(cyhal_gpio_t pin, uint8_t intrPriority, cyhal_gpio_ } } -void cyhal_gpio_irq_enable(cyhal_gpio_t pin, cyhal_gpio_irq_event_t event, bool enable) -{ - Cy_GPIO_SetInterruptEdge(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (uint32_t)event); - Cy_GPIO_SetInterruptMask(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (uint32_t)enable); -} - #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c index ced60912b76..237f043e813 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c @@ -24,9 +24,15 @@ * limitations under the License. *******************************************************************************/ -#include "cyhal_implementation.h" +#include "cyhal_hwmgr.h" +#include "cyhal_system.h" #include "cmsis_compiler.h" +#if defined(__cplusplus) +extern "C" +{ +#endif + /******************************************************************************* * Defines *******************************************************************************/ @@ -49,7 +55,7 @@ #if (CY_IP_MXTTCANFD_INSTANCES == 0) #define CY_CHANNEL_COUNT_CAN (0u) #elif (CY_IP_MXTTCANFD_INSTANCES == 1) - #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR) + #define CY_CHANNEL_COUNT_CAN (CANFD_CAN_NR) #elif (CY_IP_MXTTCANFD_INSTANCES == 2) #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR) #elif (CY_IP_MXTTCANFD_INSTANCES == 3) @@ -86,11 +92,11 @@ #define CY_CHANNEL_COUNT_CLOCK (PERI_DIV_8_NR + PERI_DIV_16_NR + PERI_DIV_16_5_NR + PERI_DIV_24_5_NR) #if defined(CY_IP_MXCRYPTO_INSTANCES) - #define CY_BLOCK_COUNT_CRC CY_IP_MXCRYPTO_INSTANCES + #define CY_BLOCK_COUNT_CRYPTO CY_IP_MXCRYPTO_INSTANCES #elif defined(CPUSS_CRYPTO_PRESENT) - #define CY_BLOCK_COUNT_CRC 1 + #define CY_BLOCK_COUNT_CRYPTO 1 #else - #define CY_BLOCK_COUNT_CRC 0 + #define CY_BLOCK_COUNT_CRYPTO 0 #endif #ifdef CY_IP_MXS40PASS_CTDAC_INSTANCES @@ -106,6 +112,9 @@ #define CY_BLOCK_COUNT_DMA 3 #define CY_CHANNEL_COUNT_DMA (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR + CPUSS_DMAC_CH_NR) +#else + #define CY_BLOCK_COUNT_DMA 0 + #define CY_CHANNEL_COUNT_DMA 0 #endif #ifdef IOSS_GPIO_GPIO_PORT_NR @@ -152,14 +161,6 @@ #define CY_BLOCK_COUNT_QSPI 0 #endif -#if defined(CY_IP_MXCRYPTO_INSTANCES) - #define CY_BLOCK_COUNT_RNG CY_IP_MXCRYPTO_INSTANCES -#elif defined(CPUSS_CRYPTO_PRESENT) - #define CY_BLOCK_COUNT_RNG 1 -#else - #define CY_BLOCK_COUNT_RNG 0 -#endif - #ifdef CY_IP_MXS40SRSS_RTC_INSTANCES #define CY_BLOCK_COUNT_RTC CY_IP_MXS40SRSS_RTC_INSTANCES #else @@ -224,9 +225,9 @@ #endif #ifdef CY_IP_MXS40SRSS_MCWDT_INSTANCES - #define CY_BLOCK_COUNT_WDT CY_IP_MXS40SRSS_MCWDT_INSTANCES + #define CY_BLOCK_COUNT_MCWDT CY_IP_MXS40SRSS_MCWDT_INSTANCES #else - #define CY_BLOCK_COUNT_WDT 0 + #define CY_BLOCK_COUNT_MCWDT 0 #endif @@ -252,9 +253,9 @@ #define CY_SIZE_CLK_PATH (CY_BLOCK_COUNT_CLK_PATH) #define CY_OFFSET_CLOCK (CY_OFFSET_CLK_PATH + CY_SIZE_CLK_PATH) #define CY_SIZE_CLOCK CY_CHANNEL_COUNT_CLOCK -#define CY_OFFSET_CRC (CY_OFFSET_CLOCK + CY_SIZE_CLOCK) -#define CY_SIZE_CRC CY_BLOCK_COUNT_CRC -#define CY_OFFSET_DAC (CY_OFFSET_CRC + CY_SIZE_CRC) +#define CY_OFFSET_CRYPTO (CY_OFFSET_CLOCK + CY_SIZE_CLOCK) +#define CY_SIZE_CRYPTO CY_BLOCK_COUNT_CRYPTO +#define CY_OFFSET_DAC (CY_OFFSET_CRYPTO + CY_SIZE_CRYPTO) #define CY_SIZE_DAC CY_BLOCK_COUNT_DAC #define CY_OFFSET_DMA (CY_OFFSET_DAC + CY_SIZE_DAC) #define CY_SIZE_DMA CY_CHANNEL_COUNT_DMA @@ -267,16 +268,14 @@ #define CY_OFFSET_LPCOMP (CY_OFFSET_LCD + CY_SIZE_LCD) #define CY_SIZE_LPCOMP CY_BLOCK_COUNT_LPCOMP #define CY_OFFSET_LPTIMER (CY_OFFSET_LPCOMP + CY_SIZE_LPCOMP) -#define CY_SIZE_LPTIMER CY_BLOCK_COUNT_WDT +#define CY_SIZE_LPTIMER CY_BLOCK_COUNT_MCWDT #define CY_OFFSET_OPAMP (CY_OFFSET_LPTIMER + CY_SIZE_LPTIMER) #define CY_SIZE_OPAMP CY_BLOCK_COUNT_OPAMP #define CY_OFFSET_PDMPCM (CY_OFFSET_OPAMP + CY_SIZE_OPAMP) #define CY_SIZE_PDMPCM CY_BLOCK_COUNT_PDMPCM #define CY_OFFSET_QSPI (CY_OFFSET_PDMPCM + CY_SIZE_PDMPCM) #define CY_SIZE_QSPI CY_BLOCK_COUNT_QSPI -#define CY_OFFSET_RNG (CY_OFFSET_QSPI + CY_SIZE_QSPI) -#define CY_SIZE_RNG CY_BLOCK_COUNT_RNG -#define CY_OFFSET_RTC (CY_OFFSET_RNG + CY_SIZE_RNG) +#define CY_OFFSET_RTC (CY_OFFSET_QSPI + CY_SIZE_QSPI) #define CY_SIZE_RTC CY_BLOCK_COUNT_RTC #define CY_OFFSET_SCB (CY_OFFSET_RTC + CY_SIZE_RTC) #define CY_SIZE_SCB CY_BLOCK_COUNT_SCB @@ -401,7 +400,6 @@ static const uint8_t cyhal_block_offsets_tcpwm[] = }; static uint8_t cyhal_used[(CY_TOTAL_ALLOCATABLE_ITEMS + 7) / 8] = {0}; -static uint8_t cyhal_configured[(CY_TOTAL_ALLOCATABLE_ITEMS + 7) / 8] = {0}; /** Array of pin to resource mappings, provided by the BSP. Must be terminated with a CYHAL_RSC_INVALID entry */ extern cyhal_resource_pin_mapping_t* cyhal_resource_pin_mapping; @@ -414,7 +412,7 @@ static const uint16_t cyhal_resource_offsets[] = CY_OFFSET_CAN, CY_OFFSET_CLK_PATH, CY_OFFSET_CLOCK, - CY_OFFSET_CRC, + CY_OFFSET_CRYPTO, CY_OFFSET_DAC, CY_OFFSET_DMA, CY_OFFSET_GPIO, @@ -425,7 +423,6 @@ static const uint16_t cyhal_resource_offsets[] = CY_OFFSET_OPAMP, CY_OFFSET_PDMPCM, CY_OFFSET_QSPI, - CY_OFFSET_RNG, CY_OFFSET_RTC, CY_OFFSET_SCB, CY_OFFSET_SDHC, @@ -445,9 +442,9 @@ static const uint32_t cyhal_has_channels = * This function is designed to verify that the number of valid resources in the cyhal_resource_t * enum and the number entries in the cyhal_resource_offsets array are identical. Any mismatch * between the two will lead to runtime failures. This will produce a divide by 0 error if they - * get of of sync. + * get of of sync. * NOTE: This function should never be called, it is only for a compile time error check - * NOTE: The Supress is to temporaraly disable the IAR warning about an uncalled function + * NOTE: The Supress is to temporaraly disable the IAR warning about an uncalled function */ static inline void check_array_size() __attribute__ ((deprecated)); #if __ICCARM__ @@ -715,27 +712,6 @@ cy_rslt_t cyhal_hwmgr_allocate_dma(cyhal_resource_inst_t* obj) return cyhal_hwmgr_allocate(CYHAL_RSC_DMA, obj); } -cy_rslt_t cyhal_hwmgr_set_configured(cyhal_resource_t type, uint8_t block, uint8_t channel) -{ - uint32_t state = cyhal_system_critical_section_enter(); - cy_rslt_t status = cyhal_set_bit(cyhal_configured, type, block, channel); - cyhal_system_critical_section_exit(state); - return status; -} - -cy_rslt_t cyhal_hwmgr_set_unconfigured(cyhal_resource_t type, uint8_t block, uint8_t channel) -{ - uint32_t state = cyhal_system_critical_section_enter(); - cy_rslt_t status = cyhal_clear_bit(cyhal_configured, type, block, channel); - cyhal_system_critical_section_exit(state); - return status; -} - -bool cyhal_hwmgr_is_configured(cyhal_resource_t type, uint8_t block, uint8_t channel) -{ - // This doesn't modify anything, so no need for a critical section - bool isConfigured = false; - cy_rslt_t status = cyhal_is_set(cyhal_configured, type, block, channel, &isConfigured); - CY_ASSERT(CY_RSLT_SUCCESS == status); - return isConfigured; +#if defined(__cplusplus) } +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c index 4a6eff8ae85..f696bd0b67c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c @@ -24,10 +24,20 @@ *******************************************************************************/ #include -#include "cyhal_implementation.h" +#include "cyhal_i2c.h" +#include "cyhal_scb_common.h" +#include "cyhal_gpio.h" +#include "cyhal_interconnect.h" +#include "cyhal_system_impl.h" +#include "cyhal_hwmgr.h" #ifdef CY_IP_MXSCB +#if defined(__cplusplus) +extern "C" +{ +#endif + #define PENDING_NONE 0 #define PENDING_RX 1 #define PENDING_TX 2 @@ -62,219 +72,11 @@ static const cy_stc_scb_i2c_config_t default_i2c_config = { .highPhaseDutyCycle = 8U, }; -static cyhal_i2c_irq_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause); -static en_clk_dst_t get_scb_cls(uint8_t scb_block_instance); - -static cyhal_i2c_t *cyhal_i2c_config_structs[CY_IP_MXSCB_INSTANCES]; -static cyhal_i2c_irq_handler_t cyhal_i2c_user_callbacks[CY_IP_MXSCB_INSTANCES]; -static void *cyhal_i2c_callback_args[CY_IP_MXSCB_INSTANCES]; - -static void cyhal_i2c_0_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_1_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_2_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_3_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_4_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_5_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_6_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_7_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_8_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_9_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_10_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_11_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_12_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_13_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_14_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_15_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_16_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_17_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_18_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_i2c_19_cb_wrapper(uint32_t event) __attribute__((unused)); - -static void cyhal_i2c_0_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_1_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_2_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_3_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_4_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_5_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_6_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_7_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_8_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_9_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_10_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_11_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_12_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_13_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_14_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_15_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_16_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_17_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_18_irq_handler(void) __attribute__((unused)); -static void cyhal_i2c_19_irq_handler(void) __attribute__((unused)); - -static __INLINE void cyhal_i2c_cb_wrapper_indexed(uint32_t event, uint8_t idx) -{ - cyhal_i2c_irq_event_t anded_events = (cyhal_i2c_irq_event_t)(cyhal_i2c_config_structs[idx]->irq_cause & (uint32_t)cyhal_convert_interrupt_cause(event)); - if (anded_events) - { - cyhal_i2c_user_callbacks[idx](cyhal_i2c_callback_args[idx], anded_events); - } -} -static void cyhal_i2c_0_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 0); -} -static void cyhal_i2c_1_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 1); -} -static void cyhal_i2c_2_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 2); -} -static void cyhal_i2c_3_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 3); -} -static void cyhal_i2c_4_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 4); -} -static void cyhal_i2c_5_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 5); -} -static void cyhal_i2c_6_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 6); -} -static void cyhal_i2c_7_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 7); -} -static void cyhal_i2c_8_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 8); -} -static void cyhal_i2c_9_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 9); -} -static void cyhal_i2c_10_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 10); -} -static void cyhal_i2c_11_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 11); -} -static void cyhal_i2c_12_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 12); -} -static void cyhal_i2c_13_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 13); -} -static void cyhal_i2c_14_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 14); -} -static void cyhal_i2c_15_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 15); -} -static void cyhal_i2c_16_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 16); -} -static void cyhal_i2c_17_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 17); -} -static void cyhal_i2c_18_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 18); -} -static void cyhal_i2c_19_cb_wrapper(uint32_t event) -{ - cyhal_i2c_cb_wrapper_indexed(event, 19); -} +static cyhal_i2c_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause); -static void (*cyhal_i2c_cb_wrapper_table[CY_IP_MXSCB_INSTANCES])(uint32_t event) = +static void cyhal_i2c_irq_handler(void) { -#if (CY_IP_MXSCB_INSTANCES > 0) - cyhal_i2c_0_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 1) - cyhal_i2c_1_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 2) - cyhal_i2c_2_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 3) - cyhal_i2c_3_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 4) - cyhal_i2c_4_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 5) - cyhal_i2c_5_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 6) - cyhal_i2c_6_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 7) - cyhal_i2c_7_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 8) - cyhal_i2c_8_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 9) - cyhal_i2c_9_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 10) - cyhal_i2c_10_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 11) - cyhal_i2c_11_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 12) - cyhal_i2c_12_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 13) - cyhal_i2c_13_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 14) - cyhal_i2c_14_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 15) - cyhal_i2c_15_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 16) - cyhal_i2c_16_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 17) - cyhal_i2c_17_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 18) - cyhal_i2c_18_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 19) - cyhal_i2c_19_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 20) - #error "Unhandled scb count" -#endif -}; - -static void cyhal_i2c_interrupts_dispatcher_IRQHandler(uint32_t i2c_num) -{ - cyhal_i2c_t *obj = cyhal_i2c_config_structs[i2c_num]; - - if (NULL == obj) - { - return; - } + cyhal_i2c_t *obj = (cyhal_i2c_t*) cyhal_scb_get_irq_obj(); Cy_SCB_I2C_Interrupt(obj->base, &(obj->context)); @@ -294,152 +96,17 @@ static void cyhal_i2c_interrupts_dispatcher_IRQHandler(uint32_t i2c_num) } } } -static void cyhal_i2c_0_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(0); -} -static void cyhal_i2c_1_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(1); -} -static void cyhal_i2c_2_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(2); -} -static void cyhal_i2c_3_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(3); -} -static void cyhal_i2c_4_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(4); -} -static void cyhal_i2c_5_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(5); -} -static void cyhal_i2c_6_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(6); -} -static void cyhal_i2c_7_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(7); -} -static void cyhal_i2c_8_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(8); -} -static void cyhal_i2c_9_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(9); -} -static void cyhal_i2c_10_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(10); -} -static void cyhal_i2c_11_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(11); -} -static void cyhal_i2c_12_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(12); -} -static void cyhal_i2c_13_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(13); -} -static void cyhal_i2c_14_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(14); -} -static void cyhal_i2c_15_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(15); -} -static void cyhal_i2c_16_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(16); -} -static void cyhal_i2c_17_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(17); -} -static void cyhal_i2c_18_irq_handler(void) -{ - cyhal_i2c_interrupts_dispatcher_IRQHandler(18); -} -static void cyhal_i2c_19_irq_handler(void) + +static void cyhal_i2c_cb_wrapper(uint32_t event) { - cyhal_i2c_interrupts_dispatcher_IRQHandler(19); + cyhal_i2c_t *obj = (cyhal_i2c_t*) cyhal_scb_get_irq_obj(); + cyhal_i2c_irq_event_t anded_events = (cyhal_i2c_irq_event_t)(obj->irq_cause & (uint32_t)cyhal_convert_interrupt_cause(event)); + if (anded_events) + { + cyhal_i2c_event_callback_t callback = (cyhal_i2c_event_callback_t) obj->callback_data.callback; + callback(obj->callback_data.callback_arg, anded_events); + } } -static void (*cyhal_i2c_interrupts_dispatcher_table[CY_IP_MXSCB_INSTANCES])(void) = -{ -#if (CY_IP_MXSCB_INSTANCES > 0) - cyhal_i2c_0_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 1) - cyhal_i2c_1_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 2) - cyhal_i2c_2_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 3) - cyhal_i2c_3_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 4) - cyhal_i2c_4_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 5) - cyhal_i2c_5_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 6) - cyhal_i2c_6_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 7) - cyhal_i2c_7_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 8) - cyhal_i2c_8_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 9) - cyhal_i2c_9_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 10) - cyhal_i2c_10_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 11) - cyhal_i2c_11_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 12) - cyhal_i2c_12_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 13) - cyhal_i2c_13_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 14) - cyhal_i2c_14_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 15) - cyhal_i2c_15_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 16) - cyhal_i2c_16_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 17) - cyhal_i2c_17_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 18) - cyhal_i2c_18_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 19) - cyhal_i2c_19_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 20) - #error "Unhandled scb count" -#endif -}; static uint32_t cyhal_set_peri_divider(cyhal_i2c_t *obj, uint32_t freq, bool is_slave) { @@ -465,7 +132,7 @@ static uint32_t cyhal_set_peri_divider(cyhal_i2c_t *obj, uint32_t freq, bool is_ { return 0; } - Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)get_scb_cls(obj->resource.block_num), obj->clock.div_type, obj->clock.div_num); + Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)((uint8_t)PCLK_SCB0_CLOCK + obj->resource.block_num), obj->clock.div_type, obj->clock.div_num); Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, cyhal_divider_value(peri_freq, 0u)); Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num); @@ -533,7 +200,7 @@ cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, c } - obj->base = CY_SCB_BASE_ADDRESSES[obj->resource.block_num]; + obj->base = CYHAL_SCB_BASE_ADDRESSES[obj->resource.block_num]; if (result == CY_RSLT_SUCCESS) { @@ -558,21 +225,27 @@ cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, c } } - bool configured = cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - if (result == CY_RSLT_SUCCESS && !configured) + if (result == CY_RSLT_SUCCESS) { - cy_stc_sysint_t irqCfg = {CY_SCB_IRQ_N[obj->resource.block_num], 7}; /* Configure I2C to operate */ result = (cy_rslt_t)Cy_SCB_I2C_Init(obj->base, &default_i2c_config, &(obj->context)); + } + + if (result == CY_RSLT_SUCCESS) + { /* Enable I2C to operate */ - (void) Cy_SCB_I2C_Enable(obj->base); - Cy_SysInt_Init(&irqCfg, cyhal_i2c_interrupts_dispatcher_table[obj->resource.block_num]); - NVIC_EnableIRQ(CY_SCB_IRQ_N[obj->resource.block_num]); - obj->irq_cause = CYHAL_I2C_IRQ_NONE; - cyhal_i2c_config_structs[obj->resource.block_num] = obj; - cyhal_i2c_config_structs[obj->resource.block_num]->irq_cause = CYHAL_I2C_IRQ_NONE; - result = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); + Cy_SCB_I2C_Enable(obj->base); + + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + obj->irq_cause = CYHAL_I2C_EVENT_NONE; + cyhal_scb_config_structs[obj->resource.block_num] = obj; + + cy_stc_sysint_t irqCfg = { CYHAL_SCB_IRQ_N[obj->resource.block_num], CYHAL_ISR_PRIORITY_DEFAULT }; + Cy_SysInt_Init(&irqCfg, cyhal_i2c_irq_handler); + NVIC_EnableIRQ(CYHAL_SCB_IRQ_N[obj->resource.block_num]); } + if (result != CY_RSLT_SUCCESS) { cyhal_i2c_free(obj); @@ -586,10 +259,9 @@ void cyhal_i2c_free(cyhal_i2c_t *obj) if (CYHAL_RSC_INVALID != obj->resource.type) { - IRQn_Type irqn = CY_SCB_IRQ_N[obj->resource.block_num]; + IRQn_Type irqn = CYHAL_SCB_IRQ_N[obj->resource.block_num]; NVIC_DisableIRQ(irqn); - cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); cyhal_hwmgr_free(&(obj->resource)); obj->base = NULL; obj->resource.type = CYHAL_RSC_INVALID; @@ -611,7 +283,7 @@ void cyhal_i2c_free(cyhal_i2c_t *obj) } } -cy_rslt_t cyhal_i2c_set_config(cyhal_i2c_t *obj, const cyhal_i2c_cfg_t *cfg) +cy_rslt_t cyhal_i2c_configure(cyhal_i2c_t *obj, const cyhal_i2c_cfg_t *cfg) { (void) Cy_SCB_I2C_Disable(obj->base, &obj->context); @@ -639,19 +311,15 @@ cy_rslt_t cyhal_i2c_set_config(cyhal_i2c_t *obj, const cyhal_i2c_cfg_t *cfg) cy_rslt_t result = (cy_rslt_t)Cy_SCB_I2C_Init(obj->base, &config_structure, &(obj->context)); (void) Cy_SCB_I2C_Enable(obj->base); - result = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); return result; } -cy_rslt_t cyhal_i2c_master_write(cyhal_i2c_t *obj, uint16_t dev_addr, const uint8_t *data, uint16_t size, uint32_t timeout) +cy_rslt_t cyhal_i2c_master_write(cyhal_i2c_t *obj, uint16_t dev_addr, const uint8_t *data, uint16_t size, uint32_t timeout, bool send_stop) { - cy_en_scb_i2c_status_t status = CY_SCB_I2C_SUCCESS; + cy_en_scb_i2c_status_t status = obj->context.state == CY_SCB_I2C_IDLE + ? Cy_SCB_I2C_MasterSendStart(obj->base, dev_addr, CY_SCB_I2C_WRITE_XFER, timeout, &obj->context) + : Cy_SCB_I2C_MasterSendReStart(obj->base, dev_addr, CY_SCB_I2C_WRITE_XFER, timeout, &obj->context); - /* Start transaction, send dev_addr. */ - if (obj->context.state == CY_SCB_I2C_IDLE) - { - status = Cy_SCB_I2C_MasterSendStart(obj->base, dev_addr, CY_SCB_I2C_WRITE_XFER, timeout, &obj->context); - } if (status == CY_SCB_I2C_SUCCESS) { while (size > 0) @@ -664,29 +332,27 @@ cy_rslt_t cyhal_i2c_master_write(cyhal_i2c_t *obj, uint16_t dev_addr, const uint --size; ++data; } - /* SCB in I2C mode is very time sensitive. In practice we have to request STOP after */ - /* each block, otherwise it may break the transmission */ - Cy_SCB_I2C_MasterSendStop(obj->base, timeout, &obj->context); } - if (status != CY_SCB_I2C_SUCCESS) + if (send_stop) { + /* SCB in I2C mode is very time sensitive. In practice we have to request STOP after */ + /* each block, otherwise it may break the transmission */ Cy_SCB_I2C_MasterSendStop(obj->base, timeout, &obj->context); } return status; } -cy_rslt_t cyhal_i2c_master_read(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *data, uint16_t size, uint32_t timeout) +cy_rslt_t cyhal_i2c_master_read(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *data, uint16_t size, uint32_t timeout, bool send_stop) { - cy_en_scb_i2c_status_t status = CY_SCB_I2C_SUCCESS; cy_en_scb_i2c_command_t ack = CY_SCB_I2C_ACK; /* Start transaction, send dev_addr */ - if (obj->context.state == CY_SCB_I2C_IDLE) - { - status = Cy_SCB_I2C_MasterSendStart(obj->base, dev_addr, CY_SCB_I2C_READ_XFER, timeout, &obj->context); - } + cy_en_scb_i2c_status_t status = obj->context.state == CY_SCB_I2C_IDLE + ? Cy_SCB_I2C_MasterSendStart(obj->base, dev_addr, CY_SCB_I2C_READ_XFER, timeout, &obj->context) + : Cy_SCB_I2C_MasterSendReStart(obj->base, dev_addr, CY_SCB_I2C_READ_XFER, timeout, &obj->context); + if (status == CY_SCB_I2C_SUCCESS) { while (size > 0) { @@ -702,16 +368,14 @@ cy_rslt_t cyhal_i2c_master_read(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *da --size; ++data; } - /* SCB in I2C mode is very time sensitive. In practice we have to request STOP after */ - /* each block, otherwise it may break the transmission */ - Cy_SCB_I2C_MasterSendStop(obj->base, timeout, &obj->context); } - if (status != CY_SCB_I2C_SUCCESS) + if (send_stop) { + /* SCB in I2C mode is very time sensitive. In practice we have to request STOP after */ + /* each block, otherwise it may break the transmission */ Cy_SCB_I2C_MasterSendStop(obj->base, timeout, &obj->context); } - return status; } @@ -735,30 +399,13 @@ cy_rslt_t cyhal_i2c_slave_config_read_buff(cyhal_i2c_t *obj, uint8_t *data, uint cy_rslt_t cyhal_i2c_master_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, const uint8_t *data, uint16_t size, uint32_t timeout) { - cy_en_scb_i2c_status_t status = CY_SCB_I2C_SUCCESS; - - /* Start transaction, send address. */ - if (obj->context.state == CY_SCB_I2C_IDLE) - { - status = Cy_SCB_I2C_MasterSendStart(obj->base, address, CY_SCB_I2C_WRITE_XFER, timeout, &obj->context); - } - - /* Check if mem_addr_size is in valid range */ - if (mem_addr_size == 0 || mem_addr_size > 2) - { - return CYHAL_I2C_RSLT_ERR_INVALID_ADDRESS_SIZE; - } + uint8_t mem_addr_buf[2]; + mem_addr_buf[0] = (uint8_t)(mem_addr >> 8); + mem_addr_buf[1] = (uint8_t)mem_addr; - /* Send mem_addr - start address in slave memory */ - if ((status == CY_SCB_I2C_SUCCESS) && mem_addr_size > 1) - { - status = Cy_SCB_I2C_MasterWriteByte(obj->base, (uint8_t)((mem_addr & 0xFF00) >> 8), timeout, &obj->context); - } - if ((status == CY_SCB_I2C_SUCCESS) && mem_addr_size > 0) - { - status = Cy_SCB_I2C_MasterWriteByte(obj->base, (uint8_t)(mem_addr & 0x00FF), timeout, &obj->context); - } - if (status == CY_SCB_I2C_SUCCESS) + cy_rslt_t status = cyhal_i2c_master_write(obj, address, mem_addr_buf, mem_addr_size, timeout, false); + + if (status == CY_RSLT_SUCCESS) { while (size > 0) { @@ -774,71 +421,20 @@ cy_rslt_t cyhal_i2c_master_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_ /* each block, otherwise it may break the transmission */ Cy_SCB_I2C_MasterSendStop(obj->base, timeout, &obj->context); } - if (status != CY_SCB_I2C_SUCCESS) - { - Cy_SCB_I2C_MasterSendStop(obj->base, timeout, &obj->context); - } return status; } cy_rslt_t cyhal_i2c_master_mem_read(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, uint8_t *data, uint16_t size, uint32_t timeout) { - cy_en_scb_i2c_status_t status = CY_SCB_I2C_SUCCESS; - cy_en_scb_i2c_command_t ack = CY_SCB_I2C_ACK; - - /* Start transaction, send address */ - if (obj->context.state == CY_SCB_I2C_IDLE) - { - status = Cy_SCB_I2C_MasterSendStart(obj->base, address, CY_SCB_I2C_WRITE_XFER, timeout, &obj->context); - } - - /* Check if mem_addr_size is in valid range */ - if (mem_addr_size == 0 || mem_addr_size > 2) - { - return CYHAL_I2C_RSLT_ERR_INVALID_ADDRESS_SIZE; - } - - /* Send mem_addr - start address in slave memory */ - if ((status == CY_SCB_I2C_SUCCESS) && mem_addr_size > 1) - { - status = Cy_SCB_I2C_MasterWriteByte(obj->base, (uint8_t)((mem_addr & 0xFF00) >> 8), timeout, &obj->context); - } - if ((status == CY_SCB_I2C_SUCCESS) && mem_addr_size > 0) - { - status = Cy_SCB_I2C_MasterWriteByte(obj->base, (uint8_t)(mem_addr & 0x00FF), timeout, &obj->context); - } + uint8_t mem_addr_buf[2]; + mem_addr_buf[0] = (uint8_t)(mem_addr >> 8); + mem_addr_buf[1] = (uint8_t)mem_addr; - if (status == CY_SCB_I2C_SUCCESS) + cy_rslt_t status = cyhal_i2c_master_write(obj, address, mem_addr_buf, mem_addr_size, timeout, false); + if (status == CY_RSLT_SUCCESS) { - status = Cy_SCB_I2C_MasterSendReStart(obj->base, address, CY_SCB_I2C_READ_XFER, timeout, &obj->context); + status = cyhal_i2c_master_read(obj, address, data, size, timeout, true); } - - if (status == CY_SCB_I2C_SUCCESS) - { - while (size > 0) - { - if (size == 1) - { - ack = CY_SCB_I2C_NAK; - } - status = Cy_SCB_I2C_MasterReadByte(obj->base, ack, (uint8_t *)data, timeout, &obj->context); - if (status != CY_SCB_I2C_SUCCESS) - { - break; - } - --size; - ++data; - } - /* SCB in I2C mode is very time sensitive. In practice we have to request STOP after */ - /* each block, otherwise it may break the transmission */ - Cy_SCB_I2C_MasterSendStop(obj->base, timeout, &obj->context); - } - - if (status != CY_SCB_I2C_SUCCESS) - { - Cy_SCB_I2C_MasterSendStop(obj->base, timeout, &obj->context); - } - return status; } @@ -897,9 +493,9 @@ cy_rslt_t cyhal_i2c_abort_async(cyhal_i2c_t *obj) return CY_RSLT_SUCCESS; } -static cyhal_i2c_irq_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause) +static cyhal_i2c_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause) { - cyhal_i2c_irq_event_t cause = CYHAL_I2C_IRQ_NONE; + cyhal_i2c_event_t cause; switch(pdl_cause) { case CY_SCB_I2C_SLAVE_READ_EVENT: @@ -936,88 +532,24 @@ static cyhal_i2c_irq_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause) cause = CYHAL_I2C_MASTER_ERR_EVENT; break; default: - cause = CYHAL_I2C_IRQ_NONE; + cause = CYHAL_I2C_EVENT_NONE; break; } return cause; } -static en_clk_dst_t get_scb_cls(uint8_t scb_block_instance) -{ - en_clk_dst_t source = PCLK_SCB0_CLOCK; - switch(scb_block_instance) - { - case 0: - source = PCLK_SCB0_CLOCK; - break; - case 1: - source = PCLK_SCB1_CLOCK; - break; - case 2: - source = PCLK_SCB2_CLOCK; - break; - case 3: - source = PCLK_SCB3_CLOCK; - break; - case 4: - source = PCLK_SCB4_CLOCK; - break; - case 5: - source = PCLK_SCB5_CLOCK; - break; - case 6: - source = PCLK_SCB6_CLOCK; - break; - case 7: - source = PCLK_SCB7_CLOCK; - break; - #ifdef SCB8 - case 8: - source = PCLK_SCB8_CLOCK; - break; - #endif - #ifdef SCB9 - case 9: - source = PCLK_SCB9_CLOCK; - break; - #endif - #ifdef SCB10 - case 10: - source = PCLK_SCB10_CLOCK; - break; - #endif - #ifdef SCB11 - case 11: - source = PCLK_SCB11_CLOCK; - break; - #endif - #ifdef SCB12 - case 12: - source = PCLK_SCB12_CLOCK; - break; - #endif - } - return source; -} - -void cyhal_i2c_register_irq(cyhal_i2c_t *obj, cyhal_i2c_irq_handler_t handler, void *handler_arg) +void cyhal_i2c_register_callback(cyhal_i2c_t *obj, cyhal_i2c_event_callback_t callback, void *callback_arg) { - uint8_t idx = obj->resource.block_num; - cyhal_i2c_config_structs[idx] = obj; - cyhal_i2c_user_callbacks[idx] = handler; - cyhal_i2c_callback_args[idx] = handler_arg; - Cy_SCB_I2C_RegisterEventCallback(obj->base, cyhal_i2c_cb_wrapper_table[idx], &(obj->context)); - if (NVIC_GetEnableIRQ(CY_SCB_IRQ_N[idx]) == 0UL) - { - /* Default interrupt priority of 7 (lowest possible priority). */ - cy_stc_sysint_t irqCfg = {CY_SCB_IRQ_N[idx], 7}; + uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); + obj->callback_data.callback = (cy_israddress) callback; + obj->callback_data.callback_arg = callback_arg; + cyhal_system_critical_section_exit(savedIntrStatus); + Cy_SCB_I2C_RegisterEventCallback(obj->base, cyhal_i2c_cb_wrapper, &(obj->context)); - Cy_SysInt_Init(&irqCfg, cyhal_i2c_interrupts_dispatcher_table[idx]); - NVIC_EnableIRQ(CY_SCB_IRQ_N[idx]); - } + obj->irq_cause = CYHAL_I2C_EVENT_NONE; } -void cyhal_i2c_irq_enable(cyhal_i2c_t *obj, cyhal_i2c_irq_event_t event, bool enable) +void cyhal_i2c_enable_event(cyhal_i2c_t *obj, cyhal_i2c_event_t event, uint8_t intrPriority, bool enable) { if (enable) { @@ -1027,6 +559,13 @@ void cyhal_i2c_irq_enable(cyhal_i2c_t *obj, cyhal_i2c_irq_event_t event, bool en { obj->irq_cause &= ~event; } + + IRQn_Type irqn = CYHAL_SCB_IRQ_N[obj->resource.block_num]; + NVIC_SetPriority(irqn, intrPriority); } +#if defined(__cplusplus) +} +#endif + #endif /* CY_IP_MXSCB */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_interconnect.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_interconnect.c index 62a1c1cd786..27c569a02f7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_interconnect.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_interconnect.c @@ -2,9 +2,9 @@ * \file cyhal_interconnect.c * * \brief -* Provides a high level interface for interacting with the internal digital +* Provides a high level interface for interacting with the internal digital * routing on the chip. This is a wrapper around the lower level PDL API. -* +* ******************************************************************************** * \copyright * Copyright 2018-2019 Cypress Semiconductor Corporation @@ -26,88 +26,14 @@ #include "cyhal_interconnect.h" #include "cyhal_hwmgr.h" #include "cyhal_gpio_impl.h" +#include "cyhal_hwmgr.h" #ifdef CY_IP_MXPERI -/** Trigger type */ -typedef enum +#if defined(__cplusplus) +extern "C" { - CY_TRIGGER_LEVEL, //!< Level triggered - CY_TRIGGER_EDGE, //!< Edge triggered - CY_TRIGGER_EITHER,//!< Level or edge triggered -} cyhal_trigger_type_t; - -/** Number of muxes */ -#define MUX_COUNT -/** Indicates that a mux output does not continue to another mux */ -#define NOT_CONTINUATION 0xFF -/** Mux identiifer the one-to-one triggers */ -#define ONE_TO_ONE_IDENT 0x80 -/** Determines whether a mux is one-to-one */ -#define IS_1TO1(muxId) (ONE_TO_ONE_IDENT == (muxId & ONE_TO_ONE_IDENT)) -#define WRITE_REGISTER(muxIdx, sourceId, destId) /* TODO */ - -/* Maps each cyhal_destination_t to a mux index ~100b */ -extern uint8_t* cyhal_dest_to_mux; -/* Maps each cyhal_destination_t to a specific output in its mux ~100b */ -extern uint8_t* cyhal_mux_dest_index; -/* Number of sources for each mux ~30b */ -extern uint8_t* cyhal_source_count_per_mux; -/* Mux index to a table of cyhal_source_t ~2400b (2b * 15muxes * 80sources_per_mux) (could be 1/2 the size if there are less than 255 sources) */ -extern cyhal_source_t** cyhal_mux_to_sources; -/* Mapping from cyhal_source_t to cyhal_destination_t for intra mux connections ~80b*/ -extern cyhal_dest_t* cyhal_intra_trigger_source; -/* Trigger type for each input ~400b */ -cyhal_trigger_type_t cyhal_trigger_type_source; -/* Trigger type for each output ~100b */ -cyhal_trigger_type_t cyhal_trigger_type_dest; - -bool cyhal_has_connection(uint8_t mux, uint8_t outputIdx) -{ - // TODO - return false; -} - -cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest) -{ - uint8_t muxIdx = cyhal_dest_to_mux[dest]; - uint8_t destId = dest - cyhal_mux_dest_index[dest]; - uint8_t sourceCount = cyhal_source_count_per_mux[muxIdx]; - - if (cyhal_has_connection(muxIdx, destId)) - { - return CYHAL_CONNECT_RSLT_ALREADY_CONNECTED; - } - - for (uint8_t sourceId = 0; sourceId < sourceCount; sourceId++) - { - cyhal_source_t foundSource = cyhal_mux_to_sources[muxIdx][sourceId]; - if (foundSource == source) - { - if (IS_1TO1(muxIdx) && sourceId != destId) - { - return CYHAL_CONNECT_RSLT_INVALID_1TO1_CONNECTION; - } - - WRITE_REGISTER (muxIdx, sourceId, destId); - return CY_RSLT_SUCCESS; - } - else - { - cyhal_dest_t intraDest = cyhal_intra_trigger_source[foundSource]; - if (NOT_CONTINUATION != intraDest) - { - cy_rslt_t result = cyhal_connect_trigger(source, intraDest); - if (result == CY_RSLT_SUCCESS) - { - WRITE_REGISTER (muxIdx, sourceId, destId); - return result; - } - } - } - } - return CYHAL_CONNECT_RSLT_NO_CONNECTION; -} +#endif cy_rslt_t cyhal_connect_pin(const cyhal_resource_pin_mapping_t *pin_connection) { @@ -128,16 +54,20 @@ cy_rslt_t cyhal_connect_pin(const cyhal_resource_pin_mapping_t *pin_connection) default: /* do nothing */ break; - } - + } + return CY_RSLT_SUCCESS; } cy_rslt_t cyhal_disconnect_pin(cyhal_gpio_t pin) -{ +{ GPIO_PRT_Type *port = Cy_GPIO_PortToAddr(CYHAL_GET_PORT(pin)); Cy_GPIO_Pin_FastInit(port, CYHAL_GET_PIN(pin), CY_GPIO_DM_HIGHZ, 1, HSIOM_SEL_GPIO); return CY_RSLT_SUCCESS; } +#if defined(__cplusplus) +} +#endif + #endif /* CY_IP_MXPERI */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c index eaff27e508c..8c3ceb70d2a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c @@ -1,5 +1,5 @@ /***************************************************************************//** -* \file cy_hal_lptimer.c +* \file cyhal_lptimer.c * * \brief * Provides a high level interface for interacting with the Cypress Low-Power Timer. @@ -31,6 +31,8 @@ #include "cy_sysint.h" #include "cyhal_lptimer.h" #include "cyhal_hwmgr.h" +#include "cyhal_system_impl.h" +#include "cyhal_utils.h" #ifdef CY_IP_MXS40SRSS_MCWDT_INSTANCES @@ -38,7 +40,7 @@ extern "C" { #endif -static MCWDT_STRUCT_Type * const cyhal_lptimer_base[] = { +static MCWDT_STRUCT_Type * const CYHAL_LPTIMER_BASE_ADDRESSES[] = { #if CY_IP_MXS40SRSS_MCWDT_INSTANCES >= 1 MCWDT_STRUCT0, #endif @@ -50,71 +52,84 @@ static MCWDT_STRUCT_Type * const cyhal_lptimer_base[] = { #endif }; -static const uint16_t CY_MCWDT_RESET_TIME_US = 62; -static const uint16_t CY_MCWDT_SETMATCH_TIME_US = 93; +#if !defined (CY_CFG_SYSCLK_CLKLF_FREQ_HZ) +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768UL /* Default to 32K ILO */ +#endif /* CY_CFG_SYSCLK_CLKLF_FREQ_HZ */ + +#define CY_MCWDT_COUNTER0_MAX_TICKS (0xffffUL) +#define CY_MCWDT_COUNTER1_MAX_TICKS (0xffffUL) +#define CY_MCWDT_COUNTER2_MAX_TICKS (0xffffffffUL) +#define CY_MCWDT_MAX_DELAY_TICKS (0xfff0ffffUL) /* ~36hours, Not set to 0xffffffff to avoid C0 and C1 both overflowing */ +#define CY_MCWDT_LPTIMER_CTRL (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2) + +#define CY_DEFAULT_MCWDT_PRIORITY 3 -typedef struct { - cyhal_lptimer_irq_handler_t handler; - void *handler_arg; -} cyhal_lptimer_irq_info_t; +static const uint16_t CY_MCWDT_RESET_TIME_US = 62; +static const uint16_t CY_MCWDT_SETMATCH_NOWAIT_TIME_US = 0; -static cyhal_lptimer_irq_info_t cyhal_lptimer_handlers[CY_IP_MXS40SRSS_MCWDT_INSTANCES]; +static cyhal_lptimer_t *cyhal_lptimer_config_structs[CY_IP_MXS40SRSS_MCWDT_INSTANCES]; -static void cyhal_lptimer_dispatch(void) +static void cyhal_lptimer_irq_handler(void) { - // IPSR is numbered from 0 (0-15 are exceptions); IRQn_Type is numbered from -16 - uint32_t instance = __get_IPSR() - 0x10 - (uint32_t)srss_interrupt_mcwdt_0_IRQn; - if (instance < CY_IP_MXS40SRSS_MCWDT_INSTANCES) + uint32_t instance = CYHAL_GET_CURRENT_IRQN() - (uint32_t) srss_interrupt_mcwdt_0_IRQn; + cyhal_lptimer_t *obj = cyhal_lptimer_config_structs[instance]; + + Cy_MCWDT_ClearInterrupt(obj->base, CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2); + + if (NULL != obj->callback_data.callback) { - Cy_MCWDT_ClearInterrupt(cyhal_lptimer_base[instance], CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2); - cyhal_lptimer_irq_info_t *info = &cyhal_lptimer_handlers[instance]; - if (NULL != info->handler) - (*info->handler)(info->handler_arg, CYHAL_LPTIMER_COMPARE_MATCH); + cyhal_lptimer_event_callback_t callback = (cyhal_lptimer_event_callback_t) obj->callback_data.callback; + (callback)(obj->callback_data.callback_arg, CYHAL_LPTIMER_COMPARE_MATCH); } } cy_rslt_t cyhal_lptimer_init(cyhal_lptimer_t *obj) { - cy_rslt_t rslt; + CY_ASSERT(NULL != obj); + obj->resource.type = CYHAL_RSC_INVALID; - if (CY_RSLT_SUCCESS == (rslt = cyhal_hwmgr_allocate(CYHAL_RSC_LPTIMER, &(obj->resource)))) + + cy_rslt_t rslt = cyhal_hwmgr_allocate(CYHAL_RSC_LPTIMER, &(obj->resource)); + if (CY_RSLT_SUCCESS == rslt) { - obj->base = cyhal_lptimer_base[obj->resource.block_num]; - cyhal_lptimer_handlers[obj->resource.block_num].handler = NULL; - IRQn_Type irq = (IRQn_Type)(srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); - static const uint32_t CY_DEFAULT_WDT_PRIORITY = 3; - cy_stc_sysint_t irqCfg = { irq, CY_DEFAULT_WDT_PRIORITY }; - if (NVIC_GetEnableIRQ(irq) || - CY_RSLT_SUCCESS == (rslt = (cy_rslt_t)Cy_SysInt_Init(&irqCfg, &cyhal_lptimer_dispatch))) + obj->base = CYHAL_LPTIMER_BASE_ADDRESSES[obj->resource.block_num]; + + const cy_stc_mcwdt_config_t cfg = { + .c0Match = CY_MCWDT_COUNTER0_MAX_TICKS, + .c1Match = CY_MCWDT_COUNTER1_MAX_TICKS, + .c0Mode = CY_MCWDT_MODE_INT, + .c1Mode = CY_MCWDT_MODE_INT, + .c2Mode = CY_MCWDT_MODE_NONE, + .c2ToggleBit = 0, + .c0ClearOnMatch = false, + .c1ClearOnMatch = false, + .c0c1Cascade = true, + .c1c2Cascade = false + }; + rslt = (cy_rslt_t) Cy_MCWDT_Init(obj->base, &cfg); + + if (CY_RSLT_SUCCESS == rslt) { - NVIC_EnableIRQ(irq); + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + cyhal_lptimer_config_structs[obj->resource.block_num] = obj; + + IRQn_Type irqn = (IRQn_Type) (srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); + cy_stc_sysint_t irqCfg = { irqn, CY_DEFAULT_MCWDT_PRIORITY }; + rslt = (cy_rslt_t) Cy_SysInt_Init(&irqCfg, &cyhal_lptimer_irq_handler); - bool configured = cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - if (!configured) + if (CY_RSLT_SUCCESS == rslt) { - static const cy_stc_mcwdt_config_t cfg = { - /* .c0Match = */ 0, - /* .c1Match = */ 0, - /* .c0Mode = */ CY_MCWDT_MODE_INT, - /* .c1Mode = */ CY_MCWDT_MODE_NONE, - /* .c2ToggleBit = */ 0, - /* .c2Mode = */ CY_MCWDT_MODE_NONE, - /* .c0ClearOnMatch = */ false, - /* .c1ClearOnMatch = */ false, - /* .c0c1Cascade = */ false, - /* .c1c2Cascade = */ false - }; - if (CY_RSLT_SUCCESS == (rslt = (cy_rslt_t)Cy_MCWDT_Init(obj->base, &cfg))) - { - Cy_MCWDT_Enable(obj->base, CY_MCWDT_CTR0, CY_MCWDT_RESET_TIME_US); - rslt = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - } + NVIC_EnableIRQ(irqn); + Cy_MCWDT_Enable(obj->base, CY_MCWDT_LPTIMER_CTRL, CY_MCWDT_RESET_TIME_US); } } } - + if (CY_RSLT_SUCCESS != rslt) + { cyhal_lptimer_free(obj); + } return rslt; } @@ -123,12 +138,15 @@ void cyhal_lptimer_free(cyhal_lptimer_t *obj) { if (CYHAL_RSC_INVALID != obj->resource.type) { - cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - cyhal_lptimer_handlers[obj->resource.block_num].handler = NULL; + IRQn_Type irqn = (IRQn_Type)(srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); + NVIC_DisableIRQ(irqn); + + cyhal_hwmgr_free(&(obj->resource)); obj->resource.type = CYHAL_RSC_INVALID; } if (NULL != obj->base) { + Cy_MCWDT_Disable(obj->base, CY_MCWDT_LPTIMER_CTRL, CY_MCWDT_RESET_TIME_US); Cy_MCWDT_DeInit(obj->base); obj->base = NULL; } @@ -136,51 +154,128 @@ void cyhal_lptimer_free(cyhal_lptimer_t *obj) cy_rslt_t cyhal_lptimer_reload(cyhal_lptimer_t *obj) { - Cy_MCWDT_ResetCounters(obj->base, CY_MCWDT_CTR0, CY_MCWDT_RESET_TIME_US); + Cy_MCWDT_ResetCounters(obj->base, (CY_MCWDT_CTR0 | CY_MCWDT_CTR1), CY_MCWDT_RESET_TIME_US); return CY_RSLT_SUCCESS; } -cy_rslt_t cyhal_lptimer_set_time(cyhal_lptimer_t *obj, uint32_t time) +cy_rslt_t cyhal_lptimer_set_time(cyhal_lptimer_t *obj, uint32_t ticks) { - Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER0, time, CY_MCWDT_SETMATCH_TIME_US); - Cy_MCWDT_SetClearOnMatch(obj->base, CY_MCWDT_COUNTER0, 1); - Cy_MCWDT_ResetCounters(obj->base, CY_MCWDT_CTR0, CY_MCWDT_RESET_TIME_US); - return CY_RSLT_SUCCESS; + return cyhal_lptimer_set_match(obj, ticks); } -cy_rslt_t cyhal_lptimer_set_match(cyhal_lptimer_t *obj, uint32_t value) +cy_rslt_t cyhal_lptimer_set_match(cyhal_lptimer_t *obj, uint32_t ticks) { - Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER0, value, 0); + uint16_t c0_match_ticks; + uint16_t c1_match_ticks; + uint32_t mcwdt_interrupt_mask; + uint16_t c0_current_ticks = Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER0); + uint16_t c1_current_ticks = Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER1); + + Cy_MCWDT_ClearInterrupt(obj->base, (CY_MCWDT_CTR0 | CY_MCWDT_CTR1)); + + /* Use MCWDT C0,C1 and C2 to implement a 32bit free running counter + C2 alone can not be used as it does not support interrupt on match feature + C2 is used to keep track of time, while C0 and C1 are used to set interrupts + To set an interrupt: + 1. delay = diff between timestamp(time in future) vs current value of C2 + 2. if delay > 2seconds (Max time that can be counted by C0) + Yes + - use both C0 and C1 + - Increment C0 by delay % (CY_MCWDT_COUNTER0_MAX_TICKS + 1) + - Increment C1 by delay / (CY_MCWDT_COUNTER1_MAX_TICKS + 1) + - Special case : In case delay is multiple of (CY_MCWDT_COUNTER0_MAX_TICKS + 1), then + delay % (CY_MCWDT_COUNTER0_MAX_TICKS + 1) will be 0, in this case + - Increment C0 by c0_current_ticks -1 + - Increment C1 by (delay / (CY_MCWDT_COUNTER1_MAX_TICKS + 1)) -1 + No + - Use only C0 + */ + if (ticks > CY_MCWDT_COUNTER0_MAX_TICKS) + { + uint16_t c0_increment; + uint16_t c1_increment; + + if (ticks > CY_MCWDT_MAX_DELAY_TICKS) + { + ticks = CY_MCWDT_MAX_DELAY_TICKS; + } + + c0_increment = ticks % (CY_MCWDT_COUNTER0_MAX_TICKS + 1); + c0_match_ticks = (c0_current_ticks + c0_increment) % (CY_MCWDT_COUNTER0_MAX_TICKS + 1); + c1_increment = (ticks) / (CY_MCWDT_COUNTER0_MAX_TICKS + 1); + c1_match_ticks = (c1_current_ticks + c1_increment) % (CY_MCWDT_COUNTER1_MAX_TICKS + 1); + + /* Special case - ticks is multiple of (CY_MCWDT_COUNTER0_MAX_TICKS + 1) */ + if (c0_increment == 0) + { + c0_match_ticks = c0_current_ticks - 1; + c1_match_ticks = c1_match_ticks -1; + } + + mcwdt_interrupt_mask = CY_MCWDT_CTR1; + } + else + { + c0_match_ticks = c0_current_ticks + (uint16_t)ticks; + c1_match_ticks = CY_MCWDT_COUNTER1_MAX_TICKS; + + /* MCWDT has internal delay of about 1.5 LF clock ticks, so this is the minimum + * that we can schedule. + */ + if (ticks < 3) + { + /* Cheating a bit here. */ + c0_match_ticks = c0_current_ticks + 3; + } + + mcwdt_interrupt_mask = CY_MCWDT_CTR0; + } + + if(c1_match_ticks == 0) + { + c1_match_ticks = 1; + } + + if(c0_match_ticks == 0) + { + c0_match_ticks = 1; + } + + Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER0, c0_match_ticks, CY_MCWDT_SETMATCH_NOWAIT_TIME_US); + Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER1, c1_match_ticks, CY_MCWDT_SETMATCH_NOWAIT_TIME_US); + Cy_MCWDT_SetInterruptMask(obj->base, mcwdt_interrupt_mask); + return CY_RSLT_SUCCESS; } uint32_t cyhal_lptimer_read(const cyhal_lptimer_t *obj) { - return Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER0); + return Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER2); } -void cyhal_lptimer_register_irq(cyhal_lptimer_t *obj, cyhal_lptimer_irq_handler_t handler, void *handler_arg) +void cyhal_lptimer_register_callback(cyhal_lptimer_t *obj, cyhal_lptimer_event_callback_t callback, void *callback_arg) { CY_ASSERT_L2(CYHAL_RSC_INVALID != obj->resource.block_num); - cyhal_lptimer_handlers[obj->resource.block_num].handler = NULL; - __DSB(); - __ISB(); - cyhal_lptimer_handlers[obj->resource.block_num].handler_arg = handler_arg; - __DSB(); - __ISB(); - cyhal_lptimer_handlers[obj->resource.block_num].handler = handler; + + uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); + obj->callback_data.callback = (cy_israddress) callback; + obj->callback_data.callback_arg = callback_arg; + cyhal_system_critical_section_exit(savedIntrStatus); } -void cyhal_lptimer_irq_enable(cyhal_lptimer_t *obj, cyhal_lptimer_irq_event_t event, bool enable) +void cyhal_lptimer_enable_event(cyhal_lptimer_t *obj, cyhal_lptimer_event_t event, uint8_t intrPriority, bool enable) { Cy_MCWDT_SetInterruptMask(obj->base, enable ? CY_MCWDT_CTR0 : 0); + + IRQn_Type irqn = (IRQn_Type)(srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); + NVIC_SetPriority(irqn, intrPriority); } void cyhal_lptimer_irq_trigger(cyhal_lptimer_t *obj) { CY_ASSERT_L2(CYHAL_RSC_INVALID != obj->resource.block_num); - IRQn_Type irq = (IRQn_Type)(srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); - NVIC_SetPendingIRQ(irq); + IRQn_Type irqn = (IRQn_Type)(srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); + NVIC_SetPendingIRQ(irqn); } #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_not_implemented.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_not_implemented.c index 9a35b0ff044..bedd38d6ebb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_not_implemented.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_not_implemented.c @@ -3,8 +3,10 @@ * * \brief * This file contains place holder functions for drivers that are not yet -* implemented but are referenced by mbed and cause build failures on some -* toolchains. As the drivers are implemented, these items need to be deleted. +* fully implemented for the target device. Prototype or stub implmentations +* are made available for to prevevent build failures on some toolchains or +* to allow for initial testing. As the drivers are implemented, these items +* will be deleted or moved into the appropriate driver. * ******************************************************************************** * \copyright @@ -24,44 +26,183 @@ * limitations under the License. *******************************************************************************/ -#include "cyhal_adc.h" -#include "cyhal_dac.h" -#include "cyhal_dma.h" +#include "cyhal_interconnect.h" + +#if defined(__cplusplus) +extern "C" +{ +#endif -uint8_t* cyhal_dest_to_mux; -uint8_t* cyhal_mux_dest_index; -uint8_t* cyhal_source_count_per_mux; -cyhal_source_t** cyhal_mux_to_sources; -cyhal_dest_t* cyhal_intra_trigger_source; -cy_rslt_t cyhal_dma_init(cyhal_dma_t *obj, uint8_t priority, cyhal_dma_direction_t direction) +/* Stub definitions for trigger connection items that will be autogenerated. */ + +/* Trigger type for each input ~400b */ +typedef enum { - return CY_RSLT_SUCCESS; -} + SRC0, + SRC1, + SRC2, + MUX_OUT0, +} cyhal_trigger_src; -void cyhal_dma_free(cyhal_dma_t *obj) +/* Trigger type for each output ~100b */ +typedef enum { -} + DEST0, + DEST1, + MUX_IN1, +} cyhal_trigger_dest; + +// Two fake muxes. +// Mux0 +// Inputs: SRC0, SRC1 +// Outputs: DEST0, MUX_IN1 +// Mux1: +// Inputs: SRC2, MUX_OUT0 +// Outputs: DEST1 -cy_rslt_t cyhal_dma_setup_transfer(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg) +/* Maps each cyhal_destination_t to a mux index ~100b */ +const uint8_t cyhal_dest_to_mux[] = { - return CY_RSLT_SUCCESS; -} + 0, // DEST0 + 1, // DEST1 + 0, // MUX_IN1 +}; -cy_rslt_t cyhal_dma_start_transfer(cyhal_dma_t *obj) +/* Maps each cyhal_destination_t to a specific output in its mux ~100b */ +const uint8_t cyhal_mux_dest_index[] = { - return CY_RSLT_SUCCESS; -} + 0, // DEST0 + 0, // DEST1 + 1, // MUX_IN1 +}; + +/* Number of sources for each mux ~30b */ +const uint8_t cyhal_source_count_per_mux[] = {2, 2}; +static const cyhal_source_t cyhal_mux0_sources[] = { SRC0, SRC1, }; // MUX0 +static const cyhal_source_t cyhal_mux1_sources[] = { SRC2, MUX_OUT0, }; // MUX1 +/* Mux index to a table of cyhal_source_t ~2400b (2b * 15muxes * 80sources_per_mux) (could be 1/2 the size if there are less than 255 sources) */ +const cyhal_source_t* cyhal_mux_to_sources[] = { cyhal_mux0_sources, cyhal_mux1_sources }; + +/* Mapping from cyhal_source_t to cyhal_destination_t for intra mux connections ~80b*/ +const cyhal_dest_t cyhal_intra_trigger_source[] = +{ + CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC0 + CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC1, + CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC2, + MUX_IN1 // MUX_OUT0 +}; + + -bool cyhal_dma_busy(cyhal_dma_t *obj) +/* Protototype for interconnect driver's trigger connection API. */ + +/** Trigger type */ +typedef enum { + CY_TRIGGER_LEVEL, //!< Level triggered + CY_TRIGGER_EDGE, //!< Edge triggered + CY_TRIGGER_EITHER,//!< Level or edge triggered +} cyhal_trigger_type_t; + +/** Number of muxes */ +#define MUX_COUNT +/** Mux identiifer the one-to-one triggers */ +#define ONE_TO_ONE_IDENT 0x80 +/** Determines whether a mux is one-to-one */ +#define IS_1TO1(muxId) (ONE_TO_ONE_IDENT == (muxId & ONE_TO_ONE_IDENT)) +#define WRITE_REGISTER(muxIdx, sourceId, destId) /* TODO */ + +/* Maps each cyhal_destination_t to a mux index */ +//extern uint8_t cyhal_dest_to_mux[]; +/* Maps each cyhal_destination_t to a specific output in its mux */ +//extern uint8_t cyhal_mux_dest_index[]; +/* Number of sources for each mux */ +//extern uint8_t cyhal_source_count_per_mux[]; +/* Mux index to a table of cyhal_source_t */ +//extern cyhal_source_t* cyhal_mux_to_sources[]; +/* Mapping from cyhal_source_t to cyhal_destination_t for intra mux connections */ +//extern cyhal_dest_t cyhal_intra_trigger_source[]; + +bool cyhal_has_connection(uint8_t mux, uint8_t outputIdx) +{ + // TODO return false; } -void cyhal_dma_register_irq(cyhal_dma_t *obj, cyhal_dma_irq_handler_t handler, void *handler_arg) +/* + * Connects two digital terminals. The source will be routed to the destination via the trigger routing + * framework in the device. This supports both the trigger mux routing and the 1:1 triggers. As expected, + * a single source can drive multiple destinations, but a destination can only be driven by a single source. + * If the output is already connected, or the connection can not be established an error will be returned. + */ +cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest) { + uint8_t muxIdx = cyhal_dest_to_mux[dest]; + uint8_t destId = dest - cyhal_mux_dest_index[dest]; + uint8_t sourceCount = cyhal_source_count_per_mux[muxIdx]; + + if (cyhal_has_connection(muxIdx, destId)) + { + return CYHAL_CONNECT_RSLT_ALREADY_CONNECTED; + } + + for (uint8_t sourceId = 0; sourceId < sourceCount; sourceId++) + { + cyhal_source_t foundSource = cyhal_mux_to_sources[muxIdx][sourceId]; + if (foundSource == source) + { + if (IS_1TO1(muxIdx) && sourceId != destId) + { + return CYHAL_CONNECT_RSLT_INVALID_TRIGGER_CONNECTION; + } + + WRITE_REGISTER (muxIdx, sourceId, destId); + return CY_RSLT_SUCCESS; + } + else + { + cyhal_dest_t intraDest = cyhal_intra_trigger_source[foundSource]; + if (CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION != intraDest) + { + // This destination can be driven by the output of another mux. + uint8_t upstreamMuxIdx = cyhal_dest_to_mux[intraDest]; + uint8_t intraDestId = intraDest - cyhal_mux_dest_index[intraDest]; + uint8_t upstreamMuxSourceCount = cyhal_source_count_per_mux[upstreamMuxIdx]; + cy_rslt_t result = CYHAL_CONNECT_RSLT_NO_CONNECTION; + + if (cyhal_has_connection(upstreamMuxIdx, intraDestId)) + { + result = CYHAL_CONNECT_RSLT_ALREADY_CONNECTED; + } + + for (uint8_t upstreamSourceId = 0; upstreamSourceId < upstreamMuxSourceCount; upstreamSourceId++) + { + cyhal_source_t upstreamSource = cyhal_mux_to_sources[upstreamMuxIdx][intraDestId]; + if (upstreamSource == source) + { + if (IS_1TO1(upstreamMuxIdx) && sourceId != intraDestId) + { + result = CYHAL_CONNECT_RSLT_INVALID_TRIGGER_CONNECTION; + } + + WRITE_REGISTER (upstreamMuxIdx, sourceId, intraDestId); + result = CY_RSLT_SUCCESS; + break; + } + } + + if (result == CY_RSLT_SUCCESS) + { + WRITE_REGISTER (muxIdx, sourceId, destId); + return result; + } + } + } + } + return CYHAL_CONNECT_RSLT_NO_CONNECTION; } -void cyhal_dma_irq_enable(cyhal_dma_t *obj, cyhal_dma_irq_event_t event, bool enable) -{ +#if defined(__cplusplus) } +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c index e69db127921..1deba28727e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c @@ -24,8 +24,9 @@ *******************************************************************************/ #include -#include "cyhal_pwm.h" +#include "cyhal_pwm_impl.h" #include "cyhal_gpio.h" +#include "cyhal_hwmgr.h" #include "cyhal_interconnect.h" #include "cyhal_utils.h" @@ -35,25 +36,6 @@ extern "C" { #endif -typedef struct { - TCPWM_Type *base; - en_clk_dst_t clock_dst; - uint32_t cnt_width; -} cyhal_internal_pwm_data_t; - -static const cyhal_internal_pwm_data_t cyhal_internal_pwm_data[] = { -#ifdef TCPWM0 - {TCPWM0, PCLK_TCPWM0_CLOCKS0, TCPWM0_CNT_CNT_WIDTH}, -#endif -#ifdef TCPWM1 - {TCPWM1, PCLK_TCPWM1_CLOCKS0, TCPWM1_CNT_CNT_WIDTH}, -#endif -}; -#if CY_IP_MXTCPWM_INSTANCES > 2 -#error PWM driver must be updated to support more TCPWM instances -#endif - -#define CYHAL_NC_PIN_VALUE_GPIO_VALUE ((cyhal_gpio_t)CYHAL_NC_PIN_VALUE) #define CYHAL_TCPWM_MAX_WIDTH 32 static const cyhal_resource_pin_mapping_t* try_alloc_pwm(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pin_map, size_t count) @@ -75,9 +57,10 @@ cy_rslt_t cyhal_pwm_init(cyhal_pwm_t *obj, cyhal_gpio_t pin, const cyhal_clock_d { CY_ASSERT(NULL != obj); + cy_rslt_t result = CY_RSLT_SUCCESS; /* Explicitly marked not allocated resources as invalid to prevent freeing them. */ obj->resource.type = CYHAL_RSC_INVALID; - obj->pin = CYHAL_NC_PIN_VALUE_GPIO_VALUE; + obj->pin = CYHAL_NC_PIN_VALUE; obj->dedicated_clock = false; const cyhal_resource_pin_mapping_t* map = try_alloc_pwm(pin, cyhal_pin_map_tcpwm_line, sizeof(cyhal_pin_map_tcpwm_line) / sizeof(cyhal_resource_pin_mapping_t)); @@ -87,81 +70,82 @@ cy_rslt_t cyhal_pwm_init(cyhal_pwm_t *obj, cyhal_gpio_t pin, const cyhal_clock_d } if (map == NULL) { - return CYHAL_PWM_RSLT_BAD_ARGUMENT; + result = CYHAL_PWM_RSLT_BAD_ARGUMENT; } - obj->resource = *map->inst; - obj->base = cyhal_internal_pwm_data[obj->resource.block_num].base; - en_clk_dst_t pclk = (en_clk_dst_t)(cyhal_internal_pwm_data[obj->resource.block_num].clock_dst + obj->resource.channel_num); + if(CY_RSLT_SUCCESS == result) + { + obj->resource = *map->inst; + obj->base = CYHAL_TCPWM_DATA[obj->resource.block_num].base; + result = cyhal_gpio_init(pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, true); + } - cy_rslt_t result; - if (CY_RSLT_SUCCESS == (result = cyhal_gpio_init(pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, true))) + if (CY_RSLT_SUCCESS == result) { obj->pin = pin; - if (CY_RSLT_SUCCESS == (result = cyhal_connect_pin(map))) + result = cyhal_connect_pin(map); + } + if (CY_RSLT_SUCCESS == result) + { + en_clk_dst_t pclk = (en_clk_dst_t)(CYHAL_TCPWM_DATA[obj->resource.block_num].clock_dst + obj->resource.channel_num); + if (NULL != clk) { - if (NULL != clk) - { - obj->clock_hz = cy_PeriClkFreqHz / (1 + Cy_SysClk_PeriphGetDivider(clk->div_type, clk->div_num)); - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, clk->div_type, clk->div_num)) - result = CYHAL_PWM_RSLT_FAILED_CLOCK; - } - else if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false))) - { - obj->dedicated_clock = true; - uint32_t div = (uint32_t)(1 << (CYHAL_TCPWM_MAX_WIDTH - cyhal_internal_pwm_data[obj->resource.block_num].cnt_width)); - if (0 == div || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num) || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num)) - result = CYHAL_PWM_RSLT_FAILED_CLOCK; - else - { - obj->clock_hz = cy_PeriClkFreqHz / div; - } - } - - if (CY_RSLT_SUCCESS == result && - !cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num)) + obj->clock_hz = cy_PeriClkFreqHz / (1 + Cy_SysClk_PeriphGetDivider(clk->div_type, clk->div_num)); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, clk->div_type, clk->div_num)) + result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT; + } + else if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false))) + { + obj->dedicated_clock = true; + uint32_t div = (uint32_t)(1 << (CYHAL_TCPWM_MAX_WIDTH - CYHAL_TCPWM_DATA[obj->resource.block_num].max_count)); + if (0 == div || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num) || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num)) + result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT; + else { - static const cy_stc_tcpwm_pwm_config_t config = - { - /* .pwmMode = */ CY_TCPWM_PWM_MODE_PWM, - /* .clockPrescaler = */ CY_TCPWM_PWM_PRESCALER_DIVBY_1, - /* .pwmAlignment = */ CY_TCPWM_PWM_LEFT_ALIGN, - /* .deadTimeClocks = */ 0UL, - /* .runMode = */ CY_TCPWM_PWM_CONTINUOUS, - /* .period0 = */ 0UL, - /* .period1 = */ 0UL, - /* .enablePeriodSwap = */ false, - /* .compare0 = */ 0UL, - /* .compare1 = */ 0UL, - /* .enableCompareSwap = */ false, - /* .interruptSources = */ CY_TCPWM_INT_NONE, - /* .invertPWMOut = */ CY_TCPWM_PWM_INVERT_DISABLE, - /* .invertPWMOutN = */ CY_TCPWM_PWM_INVERT_ENABLE, - /* .killMode = */ CY_TCPWM_PWM_STOP_ON_KILL, - /* .swapInputMode = */ CY_TCPWM_INPUT_RISINGEDGE, - /* .swapInput = */ CY_TCPWM_INPUT_0, - /* .reloadInputMode = */ CY_TCPWM_INPUT_RISINGEDGE, - /* .reloadInput = */ CY_TCPWM_INPUT_0, - /* .startInputMode = */ CY_TCPWM_INPUT_RISINGEDGE, - /* .startInput = */ CY_TCPWM_INPUT_0, - /* .killInputMode = */ CY_TCPWM_INPUT_RISINGEDGE, - /* .killInput = */ CY_TCPWM_INPUT_0, - /* .countInputMode = */ CY_TCPWM_INPUT_LEVEL, - /* .countInput = */ CY_TCPWM_INPUT_1 - }; - result = Cy_TCPWM_PWM_Init(obj->base, obj->resource.channel_num, &config); - if (CY_TCPWM_SUCCESS == result) - { - result = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - } + obj->clock_hz = cy_PeriClkFreqHz / div; } } } - if (result == CY_RSLT_SUCCESS) + + if (CY_RSLT_SUCCESS == result) + { + static const cy_stc_tcpwm_pwm_config_t config = + { + .pwmMode = CY_TCPWM_PWM_MODE_PWM, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, + .deadTimeClocks = 0UL, + .runMode = CY_TCPWM_PWM_CONTINUOUS, + .period0 = 0UL, + .period1 = 0UL, + .enablePeriodSwap = false, + .compare0 = 0UL, + .compare1 = 0UL, + .enableCompareSwap = false, + .interruptSources = CY_TCPWM_INT_NONE, + .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = CY_TCPWM_PWM_INVERT_ENABLE, + .killMode = CY_TCPWM_PWM_STOP_ON_KILL, + .swapInputMode = CY_TCPWM_INPUT_RISINGEDGE, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = CY_TCPWM_INPUT_RISINGEDGE, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = CY_TCPWM_INPUT_RISINGEDGE, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = CY_TCPWM_INPUT_RISINGEDGE, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = CY_TCPWM_INPUT_LEVEL, + .countInput = CY_TCPWM_INPUT_1 + }; + result = Cy_TCPWM_PWM_Init(obj->base, obj->resource.channel_num, &config); + } + + if (CY_RSLT_SUCCESS == result) { + cyhal_tcpwm_init_callback_data(&(obj->resource), &(obj->callback_data)); Cy_TCPWM_PWM_Enable(obj->base, obj->resource.channel_num); } else @@ -176,6 +160,9 @@ void cyhal_pwm_free(cyhal_pwm_t *obj) { CY_ASSERT(NULL != obj); + IRQn_Type irqn = (IRQn_Type)(CYHAL_TCPWM_DATA[obj->resource.block_num].isr_offset + obj->resource.channel_num); + NVIC_DisableIRQ(irqn); + if (CYHAL_NC_PIN_VALUE != obj->pin) { cyhal_gpio_free(obj->pin); @@ -185,7 +172,6 @@ void cyhal_pwm_free(cyhal_pwm_t *obj) if (NULL != obj->base) { Cy_TCPWM_PWM_Disable(obj->base, obj->resource.channel_num); - cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); cyhal_hwmgr_free(&(obj->resource)); obj->base = NULL; @@ -203,7 +189,7 @@ void cyhal_pwm_free(cyhal_pwm_t *obj) static cy_rslt_t cyhal_pwm_set_period_and_compare(cyhal_pwm_t *obj, uint32_t period, uint32_t compare) { - if (period < 1 || period > (uint32_t)((1 << cyhal_internal_pwm_data[obj->resource.block_num].cnt_width)) - 1) + if (period < 1 || period > (uint32_t)((1 << CYHAL_TCPWM_DATA[obj->resource.block_num].max_count)) - 1) return CYHAL_PWM_RSLT_BAD_ARGUMENT; if (compare > period) compare = period; @@ -213,20 +199,18 @@ static cy_rslt_t cyhal_pwm_set_period_and_compare(cyhal_pwm_t *obj, uint32_t per return CY_RSLT_SUCCESS; } -cy_rslt_t cyhal_pwm_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us) +cy_rslt_t cyhal_pwm_set_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us) { static const uint32_t US_PER_SEC = 1000000u; - if (NULL == obj) - return CYHAL_PWM_RSLT_BAD_ARGUMENT; + CY_ASSERT(NULL != obj); uint32_t period = (uint32_t)((uint64_t)period_us * obj->clock_hz / US_PER_SEC); uint32_t width = (uint32_t)((uint64_t)pulse_width_us * obj->clock_hz / US_PER_SEC); return cyhal_pwm_set_period_and_compare(obj, period, width); } -cy_rslt_t cyhal_pwm_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz) +cy_rslt_t cyhal_pwm_set_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz) { - if (NULL == obj) - return CYHAL_PWM_RSLT_BAD_ARGUMENT; + CY_ASSERT(NULL != obj); if (duty_cycle < 0.0f || duty_cycle > 100.0f || frequencyhal_hz < 1) return CYHAL_PWM_RSLT_BAD_ARGUMENT; uint32_t period = obj->clock_hz / frequencyhal_hz; @@ -236,16 +220,14 @@ cy_rslt_t cyhal_pwm_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t freq cy_rslt_t cyhal_pwm_start(cyhal_pwm_t *obj) { - if (NULL == obj) - return CYHAL_PWM_RSLT_BAD_ARGUMENT; + CY_ASSERT(NULL != obj); Cy_TCPWM_TriggerReloadOrIndex(obj->base, 1u << obj->resource.channel_num); return CY_RSLT_SUCCESS; } cy_rslt_t cyhal_pwm_stop(cyhal_pwm_t *obj) { - if (NULL == obj) - return CYHAL_PWM_RSLT_BAD_ARGUMENT; + CY_ASSERT(NULL != obj); Cy_TCPWM_TriggerStopOrKill(obj->base, 1u << obj->resource.channel_num); return CY_RSLT_SUCCESS; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c index 246799d8851..cc204b4dcc8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c @@ -30,6 +30,7 @@ #include "cyhal_hwmgr.h" #include "cyhal_gpio.h" #include "cyhal_interconnect.h" +#include "cyhal_system_impl.h" #ifdef CY_IP_MXSMIF @@ -43,9 +44,35 @@ extern "C" { /* in microseconds, timeout for all blocking functions */ #define TIMEOUT_10_MS (10000UL) +#define MAX_DATA_PINS 8 + #define SMIF_MAX_RX_COUNT (65536UL) #define QSPI_DESELECT_DELAY (7UL) +#if (defined(SMIF_CHIP_TOP_DATA8_PRESENT) && (SMIF_CHIP_TOP_DATA8_PRESENT)) || \ + (defined(SMIF0_CHIP_TOP_DATA8_PRESENT) && (SMIF0_CHIP_TOP_DATA8_PRESENT)) + #define DATA8_PRESENT 1 +#else + #define DATA8_PRESENT 0 +#endif +#if (SMIF_CHIP_TOP_SPI_SEL_NR > 1) + #define SPI_SEL1 1 +#else + #define SPI_SEL1 0 +#endif +#if (SMIF_CHIP_TOP_SPI_SEL_NR > 2) + #define SPI_SEL2 1 +#else + #define SPI_SEL2 0 +#endif +#if (SMIF_CHIP_TOP_SPI_SEL_NR > 3) + #define SPI_SEL3 1 +#else + #define SPI_SEL3 0 +#endif + +static cyhal_qspi_t *cyhal_qspi_config_structs[CY_IP_MXSMIF_INSTANCES]; + /* Default QSPI configuration */ static const cy_stc_smif_config_t default_qspi_config = { @@ -64,27 +91,32 @@ SMIF_Type *smif_base_addresses[CY_IP_MXSMIF_INSTANCES] = }; /* List of available QSPI interrupt sources */ -IRQn_Type CY_QSPI_IRQ_N[CY_IP_MXSMIF_INSTANCES] = +IRQn_Type CYHAL_QSPI_IRQ_N[CY_IP_MXSMIF_INSTANCES] = { #ifdef SMIF0 smif_interrupt_IRQn, #endif /* ifdef SMIF0 */ }; -static void cyhal_qspi_0_callback_handler(uint32_t event) __attribute__((unused)); - -/* Callback information struct */ -static struct +static uint8_t cyhal_qspi_get_block_from_irqn(IRQn_Type irqn) { - cyhal_qspi_t *obj; - cyhal_qspi_irq_handler_t handler; - void *irq_arg; -} irq_data_stc[CY_IP_MXSMIF_INSTANCES]; + switch (irqn) + { +#if (CY_CPU_CORTEX_M4) +#ifdef SMIF0 + case smif_interrupt_IRQn: return 0; +#endif /* ifdef SMIF0 */ +#endif /* (CY_CPU_CORTEX_M4) */ + default: + CY_ASSERT(false); // Should never be called with a non-SMIF IRQn + return 0; + } +} /* Translate PDL QSPI interrupt cause into QSPI HAL interrupt cause */ -static cyhal_qspi_irq_event_t cyhal_convert_event_from_pdl(uint32_t pdl_intr_cause) +static cyhal_qspi_event_t cyhal_convert_event_from_pdl(uint32_t pdl_intr_cause) { - cyhal_qspi_irq_event_t intr_cause; + cyhal_qspi_event_t intr_cause; switch (pdl_intr_cause) { @@ -95,62 +127,51 @@ static cyhal_qspi_irq_event_t cyhal_convert_event_from_pdl(uint32_t pdl_intr_cau intr_cause = CYHAL_QSPI_IRQ_RECEIVE_DONE; break; default: - intr_cause = CYHAL_QSPI_IRQ_NONE; + intr_cause = CYHAL_QSPI_EVENT_NONE; } return intr_cause; } +static cyhal_qspi_t *cyhal_qspi_get_irq_obj(void) +{ + IRQn_Type irqn = CYHAL_GET_CURRENT_IRQN(); + uint8_t block = cyhal_qspi_get_block_from_irqn(irqn); + return cyhal_qspi_config_structs[block]; +} + /******************************************************************************* * Dispatcher Interrrupt Service Routine *******************************************************************************/ -static void cyhal_qspi_callback_wrapper_indexed(uint32_t instance_num, uint32_t event) +static void cyhal_qspi_cb_wrapper(uint32_t event) { - if (NULL != irq_data_stc[instance_num].handler) + cyhal_qspi_t *obj = cyhal_qspi_get_irq_obj(); + cyhal_qspi_event_t anded_events = (cyhal_qspi_event_t)(obj->irq_cause & (uint32_t)cyhal_convert_event_from_pdl(event)); + if (anded_events) { - cyhal_qspi_irq_event_t irq_status = cyhal_convert_event_from_pdl(event); - - /* Call registered callbacks here */ - irq_data_stc[instance_num].handler(irq_data_stc[instance_num].irq_arg, irq_status); + cyhal_qspi_event_callback_t callback = (cyhal_qspi_event_callback_t) obj->callback_data.callback; + callback(obj->callback_data.callback_arg, cyhal_convert_event_from_pdl(event)); } } + /******************************************************************************* * (Internal) Interrrupt Service Routines *******************************************************************************/ -/* Handler for SMIF0 */ -static void cyhal_qspi_0_callback_handler(uint32_t event) -{ - cyhal_qspi_callback_wrapper_indexed(0, event); -} - /* Interrupt call, needed for SMIF Async operations */ -static void cyhal_qspi_process_smif_0_intr() +static void cyhal_qspi_irq_handler() { - Cy_SMIF_Interrupt(irq_data_stc[0].obj->base, &(irq_data_stc[0].obj->context)); + cyhal_qspi_t *obj = cyhal_qspi_get_irq_obj(); + Cy_SMIF_Interrupt(obj->base, &(obj->context)); } -/* List of callback handler, takes instance id as idx */ -static void (*cyhal_qspi_callback_dispatcher_table[CY_IP_MXSMIF_INSTANCES])(uint32_t event) = -{ -#if (CY_IP_MXSMIF_INSTANCES > 0) - cyhal_qspi_0_callback_handler, -#endif /* CY_IP_MXSMIF_INSTANCES > 0 */ -}; - -/* List of SMIF service interrupt handler, takes instance id as idx */ -static void (*cyhal_smif_intr_dispatcher_table[CY_IP_MXSMIF_INSTANCES])() = -{ -#if (CY_IP_MXSMIF_INSTANCES > 0) - cyhal_qspi_process_smif_0_intr, -#endif /* CY_IP_MXSMIF_INSTANCES > 0 */ -}; - /******************************************************************************* * (Internal) QSPI Pin Related Functions *******************************************************************************/ +#ifndef __MBED__ + /* Check if pin valid as resource and reserve it */ static cy_rslt_t check_pin_and_reserve(cyhal_gpio_t pin) { @@ -171,49 +192,21 @@ static cy_rslt_t make_pin_reservations(cyhal_qspi_t *obj) { result = check_pin_and_reserve(obj->pin_ssel); } - /* reserve the io0 pin */ - if (result == CY_RSLT_SUCCESS) - { - result = check_pin_and_reserve(obj->pin_io0); - } - /* reserve the io1 pin */ - if ((NC != obj->pin_io1) && (CY_RSLT_SUCCESS == result)) - { - result = check_pin_and_reserve(obj->pin_io1); - } - /* reserve the obj->pin_io2 pin */ - if ((NC != obj->pin_io2) && (CY_RSLT_SUCCESS == result)) - { - result = check_pin_and_reserve(obj->pin_io2); - } - /* reserve the obj->pin_io3 pin */ - if ((NC != obj->pin_io3) && (CY_RSLT_SUCCESS == result)) - { - result = check_pin_and_reserve(obj->pin_io3); - } - /* reserve the obj->pin_io4 pin */ - if ((NC != obj->pin_io4) && (CY_RSLT_SUCCESS == result)) - { - result = check_pin_and_reserve(obj->pin_io4); - } - /* reserve the obj->pin_io5 pin */ - if ((NC != obj->pin_io5) && (CY_RSLT_SUCCESS == result)) - { - result = check_pin_and_reserve(obj->pin_io5); - } - /* reserve the obj->pin_io6 pin */ - if ((NC != obj->pin_io6) && (CY_RSLT_SUCCESS == result)) - { - result = check_pin_and_reserve(obj->pin_io6); - } - /* reserve the obj->pin_io7 pin */ - if ((NC != obj->pin_io7) && (CY_RSLT_SUCCESS == result)) + + /* reserve the io pins */ + for (uint8_t i = 0; (i < MAX_DATA_PINS) && (result == CY_RSLT_SUCCESS); i++) { - result = check_pin_and_reserve(obj->pin_io7); + if (NC != obj->pin_ios[i]) + { + result = check_pin_and_reserve(obj->pin_ios[i]); + } } + return result; } +#endif + /* Free all QSPI pins */ static void free_pin_connections(cyhal_qspi_t *obj) { @@ -227,45 +220,14 @@ static void free_pin_connections(cyhal_qspi_t *obj) cyhal_utils_disconnect_and_free(obj->pin_ssel); obj->pin_ssel = CYHAL_NC_PIN_VALUE; } - if (CYHAL_NC_PIN_VALUE != obj->pin_io0) - { - cyhal_utils_disconnect_and_free(obj->pin_io0); - obj->pin_io0 = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_io1) - { - cyhal_utils_disconnect_and_free(obj->pin_io1); - obj->pin_io1 = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_io2) - { - cyhal_utils_disconnect_and_free(obj->pin_io2); - obj->pin_io2 = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_io3) - { - cyhal_utils_disconnect_and_free(obj->pin_io3); - obj->pin_io3 = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_io4) - { - cyhal_utils_disconnect_and_free(obj->pin_io4); - obj->pin_io4 = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_io5) - { - cyhal_utils_disconnect_and_free(obj->pin_io5); - obj->pin_io5 = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_io6) - { - cyhal_utils_disconnect_and_free(obj->pin_io6); - obj->pin_io6 = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_io7) + + for (uint8_t i = 0; (i < MAX_DATA_PINS); i++) { - cyhal_utils_disconnect_and_free(obj->pin_io7); - obj->pin_io7 = CYHAL_NC_PIN_VALUE; + if (CYHAL_NC_PIN_VALUE != obj->pin_ios[i]) + { + cyhal_utils_disconnect_and_free(obj->pin_ios[i]); + obj->pin_ios[i] = CYHAL_NC_PIN_VALUE; + } } } @@ -308,8 +270,8 @@ static void convert_to_cyhal_cmd_config(const cyhal_qspi_command_t *qspi_command cyhal_cmd_config->command = qspi_command->instruction.value; cyhal_cmd_config->cmdWidth = get_cyhal_bus_width(qspi_command->instruction.bus_width); cyhal_cmd_config->addrWidth = get_cyhal_bus_width(qspi_command->address.bus_width); - cyhal_cmd_config->mode = qspi_command->alt.value; - cyhal_cmd_config->modeWidth = get_cyhal_bus_width(qspi_command->alt.bus_width); + cyhal_cmd_config->mode = qspi_command->mode_bits.value; + cyhal_cmd_config->modeWidth = get_cyhal_bus_width(qspi_command->mode_bits.bus_width); cyhal_cmd_config->dummyCycles = qspi_command->dummy_count; cyhal_cmd_config->dataWidth = get_cyhal_bus_width(qspi_command->data.bus_width); } @@ -325,29 +287,9 @@ static void uint32_to_byte_array(uint32_t value, uint8_t *byteArray, uint32_t st } /* cyhal_qspi_size_t to number bytes */ -static uint32_t get_size(cyhal_qspi_size_t hal_size) +static inline uint32_t get_size(cyhal_qspi_size_t hal_size) { - uint32_t size; - - switch (hal_size) - { - case CYHAL_QSPI_CFG_SIZE_8: - size = 1; - break; - case CYHAL_QSPI_CFG_SIZE_16: - size = 2; - break; - case CYHAL_QSPI_CFG_SIZE_24: - size = 3; - break; - case CYHAL_QSPI_CFG_SIZE_32: - size = 4; - break; - default: - size = 0; - } - - return size; + return ((uint32_t)hal_size >> 3); /* convert bits to bytes */ } /* Sends QSPI command with certain set of data */ @@ -355,29 +297,29 @@ static uint32_t get_size(cyhal_qspi_size_t hal_size) static cy_rslt_t qspi_command_transfer(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, uint32_t addr, bool endOfTransfer) { - /* max address size is 4 bytes and max alt size is 4 bytes */ + /* max address size is 4 bytes and max mode bits size is 4 bytes */ uint8_t cmd_param[8] = {0}; uint32_t start_pos = 0; uint32_t addr_size = 0; - uint32_t alt_size = 0; + uint32_t mode_bits_size = 0; cy_en_smif_txfr_width_t bus_width = CY_SMIF_WIDTH_SINGLE; cy_stc_smif_mem_cmd_t cyhal_cmd_config; cy_rslt_t result = CY_RSLT_SUCCESS; convert_to_cyhal_cmd_config(command, &cyhal_cmd_config); - /* Does not support different bus_width for address and alt. - * bus_width is selected based on what (address or alt) is enabled. - * If both are enabled, bus_width of alt is selected - * It is either possible to support 1 byte alt with different bus_width - * by sending the alt byte as command as done in Cy_SMIF_Memslot_CmdRead() - * in cyhal_smif_memslot.c or support multiple bytes of alt with same bus_width - * as address by passing the alt bytes as cmd_param to Cy_SMIF_TransmitCommand(). + /* Does not support different bus_width for address and mode bits. + * bus_width is selected based on what (address or mode bits) is enabled. + * If both are enabled, bus_width of mode bits is selected + * It is either possible to support 1 byte mode bits with different bus_width + * by sending the mode byte as command as done in Cy_SMIF_Memslot_CmdRead() + * in cyhal_smif_memslot.c or support multiple bytes of mode bits with same bus_width + * as address by passing the mode bytes as cmd_param to Cy_SMIF_TransmitCommand(). * Second approach is implemented here. This restriction is because of the way * PDL API is implemented. */ - if (!command->address.disabled && !command->alt.disabled) + if (!command->address.disabled && !command->mode_bits.disabled) { if (cyhal_cmd_config.addrWidth != cyhal_cmd_config.modeWidth) { @@ -395,16 +337,16 @@ static cy_rslt_t qspi_command_transfer(cyhal_qspi_t *obj, const cyhal_qspi_comma bus_width = cyhal_cmd_config.addrWidth; } - if (!command->alt.disabled) + if (!command->mode_bits.disabled) { - alt_size = get_size(command->alt.size); - uint32_to_byte_array(cyhal_cmd_config.mode, cmd_param, start_pos, alt_size); + mode_bits_size = get_size(command->mode_bits.size); + uint32_to_byte_array(cyhal_cmd_config.mode, cmd_param, start_pos, mode_bits_size); bus_width = cyhal_cmd_config.modeWidth; } uint32_t cmpltTxfr = ((endOfTransfer) ? 1UL : 0UL); result = (cy_rslt_t)Cy_SMIF_TransmitCommand(obj->base, cyhal_cmd_config.command, - cyhal_cmd_config.cmdWidth, cmd_param, (addr_size + alt_size), + cyhal_cmd_config.cmdWidth, cmd_param, (addr_size + mode_bits_size), bus_width, obj->slave_select, cmpltTxfr, &obj->context); } return result; @@ -414,85 +356,62 @@ static cy_rslt_t qspi_command_transfer(cyhal_qspi_t *obj, const cyhal_qspi_comma static cy_rslt_t check_user_pins(cyhal_qspi_t *obj, cyhal_qspi_bus_width_t *max_width) { cy_rslt_t result = CY_RSLT_SUCCESS; - /* Single mode */ - if (NC == obj->pin_io0) + + if (NC == obj->pin_sclk || NC == obj->pin_ssel) { + *max_width = CYHAL_QSPI_CFG_BUS_SINGLE; result = CYHAL_QSPI_RSLT_ERR_PIN; } else { - *max_width = CYHAL_QSPI_CFG_BUS_SINGLE; - } - /* Dual mode */ - if (NC != obj->pin_io1) - { - *max_width = CYHAL_QSPI_CFG_BUS_DUAL; - } - /* Quad Mode */ - if ((NC != obj->pin_io2) && (CY_RSLT_SUCCESS == result)) - { - result = NC != obj->pin_io1 ? CY_RSLT_SUCCESS : CYHAL_QSPI_RSLT_ERR_PIN; - if (CY_RSLT_SUCCESS == result) - { - result = NC != obj->pin_io3 ? CY_RSLT_SUCCESS : CYHAL_QSPI_RSLT_ERR_PIN; - if (CY_RSLT_SUCCESS == result) - { - *max_width = CYHAL_QSPI_CFG_BUS_QUAD; - } - } - } - /* Octo Mode */ - if ((NC != obj->pin_io4) && (CY_RSLT_SUCCESS == result)) - { - result = NC != obj->pin_io1 ? CY_RSLT_SUCCESS : CYHAL_QSPI_RSLT_ERR_PIN; - if (CY_RSLT_SUCCESS == result) +#if DATA8_PRESENT + if (NC != obj->pin_ios[4]) { - result = NC != obj->pin_io2 ? CY_RSLT_SUCCESS : CYHAL_QSPI_RSLT_ERR_PIN; - } - if (CY_RSLT_SUCCESS == result) - { - result = NC != obj->pin_io3 ? CY_RSLT_SUCCESS : CYHAL_QSPI_RSLT_ERR_PIN; + *max_width = CYHAL_QSPI_CFG_BUS_OCTAL; } - if (CY_RSLT_SUCCESS == result) + else +#endif + if (NC != obj->pin_ios[2]) { - result = NC != obj->pin_io5 ? CY_RSLT_SUCCESS : CYHAL_QSPI_RSLT_ERR_PIN; + *max_width = CYHAL_QSPI_CFG_BUS_QUAD; } - if (CY_RSLT_SUCCESS == result) + else if (NC != obj->pin_ios[1]) { - result = NC != obj->pin_io6 ? CY_RSLT_SUCCESS : CYHAL_QSPI_RSLT_ERR_PIN; + *max_width = CYHAL_QSPI_CFG_BUS_DUAL; } - if (CY_RSLT_SUCCESS == result) + else { - result = NC != obj->pin_io7 ? CY_RSLT_SUCCESS : CYHAL_QSPI_RSLT_ERR_PIN; + *max_width = CYHAL_QSPI_CFG_BUS_SINGLE; } - if (CY_RSLT_SUCCESS == result) + + for (uint8_t i = 1; i <= MAX_DATA_PINS; i++) { - *max_width = CYHAL_QSPI_CFG_BUS_OCTAL; + /* Pins with index lower than width must be provided, pins above should be NC */ + if ((NC == obj->pin_ios[i-1]) != (i > *max_width)) + { + result = CYHAL_QSPI_RSLT_ERR_PIN; + } } - - } - if (CY_RSLT_SUCCESS == result) - { - result = NC != obj->pin_sclk ? CY_RSLT_SUCCESS : CYHAL_QSPI_RSLT_ERR_PIN; } - if (CY_RSLT_SUCCESS == result) - { - result = NC != obj->pin_ssel ? CY_RSLT_SUCCESS : CYHAL_QSPI_RSLT_ERR_PIN; - } return result; } /* Based on ssel pin chosen, determines SMIF slave select parameter and pin mapping */ static const cyhal_resource_pin_mapping_t *get_slaveselect(cyhal_gpio_t ssel, cy_en_smif_slave_select_t *slave_select) { +#if SPI_SEL1 || SPI_SEL2 || SPI_SEL3 bool pin_found = false; +#endif const cyhal_resource_pin_mapping_t *pin_mapping = CY_UTILS_GET_RESOURCE(ssel, cyhal_pin_map_smif_spi_select0); if (NULL != pin_mapping) { +#if SPI_SEL1 || SPI_SEL2 || SPI_SEL3 pin_found = true; +#endif *slave_select = CY_SMIF_SLAVE_SELECT_0; } +#if SPI_SEL1 if (!pin_found) { pin_mapping = CY_UTILS_GET_RESOURCE(ssel, cyhal_pin_map_smif_spi_select1); @@ -502,6 +421,8 @@ static const cyhal_resource_pin_mapping_t *get_slaveselect(cyhal_gpio_t ssel, cy *slave_select = CY_SMIF_SLAVE_SELECT_1; } } +#endif +#if SPI_SEL2 if (!pin_found) { pin_mapping = CY_UTILS_GET_RESOURCE(ssel, cyhal_pin_map_smif_spi_select2); @@ -511,6 +432,8 @@ static const cyhal_resource_pin_mapping_t *get_slaveselect(cyhal_gpio_t ssel, cy *slave_select = CY_SMIF_SLAVE_SELECT_2; } } +#endif +#if SPI_SEL3 if (!pin_found) { pin_mapping = CY_UTILS_GET_RESOURCE(ssel, cyhal_pin_map_smif_spi_select3); @@ -520,6 +443,7 @@ static const cyhal_resource_pin_mapping_t *get_slaveselect(cyhal_gpio_t ssel, cy *slave_select = CY_SMIF_SLAVE_SELECT_3; } } +#endif return pin_mapping; } @@ -543,6 +467,7 @@ static const cyhal_resource_pin_mapping_t *get_dataselect(cyhal_gpio_t io0, cy_e *data_select = CY_SMIF_DATA_SEL1; } } +#if DATA8_PRESENT if (!pin_found) { pin_mapping = CY_UTILS_GET_RESOURCE(io0, cyhal_pin_map_smif_spi_data4); @@ -561,6 +486,7 @@ static const cyhal_resource_pin_mapping_t *get_dataselect(cyhal_gpio_t io0, cy_e *data_select = CY_SMIF_DATA_SEL3; } } +#endif return pin_mapping; } @@ -588,14 +514,14 @@ cy_rslt_t cyhal_qspi_init( obj->pin_sclk = sclk; obj->pin_ssel = ssel; - obj->pin_io0 = io0; - obj->pin_io1 = io1; - obj->pin_io2 = io2; - obj->pin_io3 = io3; - obj->pin_io4 = io4; - obj->pin_io5 = io5; - obj->pin_io6 = io6; - obj->pin_io7 = io7; + obj->pin_ios[0] = io0; + obj->pin_ios[1] = io1; + obj->pin_ios[2] = io2; + obj->pin_ios[3] = io3; + obj->pin_ios[4] = io4; + obj->pin_ios[5] = io5; + obj->pin_ios[6] = io6; + obj->pin_ios[7] = io7; cy_rslt_t result = check_user_pins(obj, &max_width); @@ -625,11 +551,10 @@ cy_rslt_t cyhal_qspi_init( { obj->slave_select = slave_select; } - } if (CY_RSLT_SUCCESS == result) { - io0_map = get_dataselect(obj->pin_io0, &data_select); + io0_map = get_dataselect(obj->pin_ios[0], &data_select); if (io0_map == NULL) { result = CYHAL_QSPI_RSLT_ERR_PIN; @@ -638,7 +563,6 @@ cy_rslt_t cyhal_qspi_init( { obj->data_select = data_select; } - } if (CY_RSLT_SUCCESS == result) { @@ -647,7 +571,7 @@ cy_rslt_t cyhal_qspi_init( case CY_SMIF_DATA_SEL0: if (max_width >= CYHAL_QSPI_CFG_BUS_DUAL) { - io1_map = CY_UTILS_GET_RESOURCE(obj->pin_io1, cyhal_pin_map_smif_spi_data1); + io1_map = CY_UTILS_GET_RESOURCE(obj->pin_ios[1], cyhal_pin_map_smif_spi_data1); if (NULL == io1_map) { result = CYHAL_QSPI_RSLT_ERR_PIN; @@ -655,41 +579,42 @@ cy_rslt_t cyhal_qspi_init( } if (max_width >= CYHAL_QSPI_CFG_BUS_QUAD) { - io2_map = CY_UTILS_GET_RESOURCE(obj->pin_io2, cyhal_pin_map_smif_spi_data2); - io3_map = CY_UTILS_GET_RESOURCE(obj->pin_io3, cyhal_pin_map_smif_spi_data3); + io2_map = CY_UTILS_GET_RESOURCE(obj->pin_ios[2], cyhal_pin_map_smif_spi_data2); + io3_map = CY_UTILS_GET_RESOURCE(obj->pin_ios[3], cyhal_pin_map_smif_spi_data3); if ((NULL == io2_map) || (NULL == io3_map)) { result = CYHAL_QSPI_RSLT_ERR_PIN; } } +#if DATA8_PRESENT if (max_width >= CYHAL_QSPI_CFG_BUS_OCTAL) { - io4_map = CY_UTILS_GET_RESOURCE(obj->pin_io4, cyhal_pin_map_smif_spi_data4); - io5_map = CY_UTILS_GET_RESOURCE(obj->pin_io5, cyhal_pin_map_smif_spi_data5); - io6_map = CY_UTILS_GET_RESOURCE(obj->pin_io6, cyhal_pin_map_smif_spi_data6); - io7_map = CY_UTILS_GET_RESOURCE(obj->pin_io7, cyhal_pin_map_smif_spi_data7); + io4_map = CY_UTILS_GET_RESOURCE(obj->pin_ios[4], cyhal_pin_map_smif_spi_data4); + io5_map = CY_UTILS_GET_RESOURCE(obj->pin_ios[5], cyhal_pin_map_smif_spi_data5); + io6_map = CY_UTILS_GET_RESOURCE(obj->pin_ios[6], cyhal_pin_map_smif_spi_data6); + io7_map = CY_UTILS_GET_RESOURCE(obj->pin_ios[7], cyhal_pin_map_smif_spi_data7); if ((NULL == io4_map) || (NULL == io5_map) || (NULL == io6_map) || (NULL == io7_map)) { result = CYHAL_QSPI_RSLT_ERR_PIN; } } break; - +#endif case CY_SMIF_DATA_SEL1: if (max_width >= CYHAL_QSPI_CFG_BUS_DUAL) { - io1_map = CY_UTILS_GET_RESOURCE(obj->pin_io1, cyhal_pin_map_smif_spi_data3); + io1_map = CY_UTILS_GET_RESOURCE(obj->pin_ios[1], cyhal_pin_map_smif_spi_data3); if (NULL == io1_map) { result = CYHAL_QSPI_RSLT_ERR_PIN; } } break; - +#if DATA8_PRESENT case CY_SMIF_DATA_SEL2: if (max_width >= CYHAL_QSPI_CFG_BUS_DUAL) { - io1_map = CY_UTILS_GET_RESOURCE(obj->pin_io1, cyhal_pin_map_smif_spi_data5); + io1_map = CY_UTILS_GET_RESOURCE(obj->pin_ios[1], cyhal_pin_map_smif_spi_data5); if (NULL == io1_map) { result = CYHAL_QSPI_RSLT_ERR_PIN; @@ -697,8 +622,8 @@ cy_rslt_t cyhal_qspi_init( } if (max_width >= CYHAL_QSPI_CFG_BUS_QUAD) { - io2_map = CY_UTILS_GET_RESOURCE(obj->pin_io2, cyhal_pin_map_smif_spi_data6); - io3_map = CY_UTILS_GET_RESOURCE(obj->pin_io3, cyhal_pin_map_smif_spi_data7); + io2_map = CY_UTILS_GET_RESOURCE(obj->pin_ios[2], cyhal_pin_map_smif_spi_data6); + io3_map = CY_UTILS_GET_RESOURCE(obj->pin_ios[3], cyhal_pin_map_smif_spi_data7); if ((NULL == io2_map) || (NULL == io3_map)) { result = CYHAL_QSPI_RSLT_ERR_PIN; @@ -709,14 +634,14 @@ cy_rslt_t cyhal_qspi_init( case CY_SMIF_DATA_SEL3: if (max_width >= CYHAL_QSPI_CFG_BUS_DUAL) { - io1_map = CY_UTILS_GET_RESOURCE(obj->pin_io1, cyhal_pin_map_smif_spi_data7); + io1_map = CY_UTILS_GET_RESOURCE(obj->pin_ios[1], cyhal_pin_map_smif_spi_data7); if (NULL == io1_map) { result = CYHAL_QSPI_RSLT_ERR_PIN; } } break; - +#endif default: result = CYHAL_QSPI_RSLT_ERR_DATA_SEL; } @@ -724,24 +649,18 @@ cy_rslt_t cyhal_qspi_init( /* Check that all pins are belongs to same instance */ if (CY_RSLT_SUCCESS == result) { - if (sclk_map->inst->block_num != ssel_map->inst->block_num) + if (sclk_map->inst->block_num != ssel_map->inst->block_num || + sclk_map->inst->block_num != io0_map->inst->block_num) { result = CYHAL_QSPI_RSLT_ERR_PIN; } } - if (CY_RSLT_SUCCESS == result) + if (CY_RSLT_SUCCESS == result && (max_width >= CYHAL_QSPI_CFG_BUS_DUAL)) { - if (sclk_map->inst->block_num != io0_map->inst->block_num) + if (sclk_map->inst->block_num != io1_map->inst->block_num) { result = CYHAL_QSPI_RSLT_ERR_PIN; } - if ((max_width >= CYHAL_QSPI_CFG_BUS_DUAL) && (CY_RSLT_SUCCESS == result)) - { - if (sclk_map->inst->block_num != io1_map->inst->block_num) - { - result = CYHAL_QSPI_RSLT_ERR_PIN; - } - } } /* Pins io2 and io3 are only available in CY_SMIF_DATA_SEL0 and CY_SMIF_DATA_SEL2 modes */ if ((CY_RSLT_SUCCESS == result) && ((data_select == CY_SMIF_DATA_SEL0) || (data_select == CY_SMIF_DATA_SEL2)) @@ -765,6 +684,9 @@ cy_rslt_t cyhal_qspi_init( } } +#ifndef __MBED__ + // Mbed calls qspi_init multiple times without calling qspi_free to update the QSPI frequency/mode. + // As a result, we won't worry about resource reservation if running through mbed. if (CY_RSLT_SUCCESS == result) { result = make_pin_reservations(obj); @@ -772,14 +694,15 @@ cy_rslt_t cyhal_qspi_init( if (CY_RSLT_SUCCESS == result) { - obj->base = smif_base_addresses[obj->resource.block_num]; result = cyhal_hwmgr_reserve(sclk_map->inst); } +#endif if (CY_RSLT_SUCCESS == result) { obj->resource = *sclk_map->inst; - + obj->base = smif_base_addresses[obj->resource.block_num]; + result = cyhal_connect_pin(sclk_map); if (CY_RSLT_SUCCESS == result) { @@ -822,30 +745,27 @@ cy_rslt_t cyhal_qspi_init( if (CY_RSLT_SUCCESS == result) { - result = cyhal_qspi_frequency(obj, hz); + result = cyhal_qspi_set_frequency(obj, hz); } - bool configured = cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - if ((CY_RSLT_SUCCESS == result) && !configured) + if (CY_RSLT_SUCCESS == result) { - result = (cy_rslt_t)Cy_SMIF_Init(obj->base, &default_qspi_config, TIMEOUT_10_MS, &obj->context); - - Cy_SMIF_SetDataSelect(obj->base, slave_select, data_select); - Cy_SMIF_Enable(obj->base, &obj->context); - result = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); + result = (cy_rslt_t) Cy_SMIF_Init(obj->base, &default_qspi_config, TIMEOUT_10_MS, &obj->context); } if (CY_RSLT_SUCCESS == result) { - irq_data_stc[obj->resource.block_num].obj = obj; - irq_data_stc[obj->resource.block_num].obj->irq_cause = CYHAL_QSPI_IRQ_NONE; - /* default interrupt priority of 7 (lowest possible priority). */ - cy_stc_sysint_t irqCfg = { - .intrSrc = CY_QSPI_IRQ_N[obj->resource.block_num], - .intrPriority = 7u - }; - Cy_SysInt_Init(&irqCfg, cyhal_smif_intr_dispatcher_table[obj->resource.block_num]); - NVIC_EnableIRQ(CY_QSPI_IRQ_N[obj->resource.block_num]); + Cy_SMIF_SetDataSelect(obj->base, slave_select, data_select); + Cy_SMIF_Enable(obj->base, &obj->context); + + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + obj->irq_cause = CYHAL_QSPI_EVENT_NONE; + cyhal_qspi_config_structs[obj->resource.block_num] = obj; + + cy_stc_sysint_t irqCfg = { CYHAL_QSPI_IRQ_N[obj->resource.block_num], CYHAL_ISR_PRIORITY_DEFAULT }; + Cy_SysInt_Init(&irqCfg, cyhal_qspi_irq_handler); + NVIC_EnableIRQ(CYHAL_QSPI_IRQ_N[obj->resource.block_num]); } if (CY_RSLT_SUCCESS != result) @@ -860,18 +780,22 @@ void cyhal_qspi_free(cyhal_qspi_t *obj) { if (CYHAL_RSC_INVALID != obj->resource.type) { + IRQn_Type irqn = CYHAL_QSPI_IRQ_N[obj->resource.block_num]; + NVIC_DisableIRQ(irqn); + if (obj->base != NULL) { Cy_SMIF_DeInit(obj->base); + obj->base = NULL; } - cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); cyhal_hwmgr_free(&(obj->resource)); + obj->resource.type = CYHAL_RSC_INVALID; } free_pin_connections(obj); } -cy_rslt_t cyhal_qspi_frequency(cyhal_qspi_t *obj, uint32_t hz) +cy_rslt_t cyhal_qspi_set_frequency(cyhal_qspi_t *obj, uint32_t hz) { /* TODO after HAL clock management implemented JIRA: BSP-510 */ (void) obj; @@ -911,8 +835,7 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command if (CY_RSLT_SUCCESS == status) { status = (cy_rslt_t)Cy_SMIF_ReceiveDataBlocking(obj->base, (uint8_t *)data, chunk, - get_cyhal_bus_width(command->data.bus_width), - &obj->context); + get_cyhal_bus_width(command->data.bus_width), &obj->context); if (CY_RSLT_SUCCESS != status) { break; @@ -929,9 +852,8 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command cy_rslt_t cyhal_qspi_read_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, void *data, size_t *length) { - cy_rslt_t status = CY_RSLT_SUCCESS; - uint32_t addr = command->address.value; - status = qspi_command_transfer(obj, command, addr, false); + cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false); + if (CY_RSLT_SUCCESS == status) { if (command->dummy_count > 0u) @@ -941,17 +863,8 @@ cy_rslt_t cyhal_qspi_read_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *c if (CY_RSLT_SUCCESS == status) { - cy_smif_event_cb_t callback_dispatcher_ptr; - if (obj->irq_cause & CYHAL_QSPI_IRQ_RECEIVE_DONE) - { - callback_dispatcher_ptr = cyhal_qspi_callback_dispatcher_table[obj->resource.block_num]; - } - else - { - callback_dispatcher_ptr = NULL; - } status = (cy_rslt_t)Cy_SMIF_ReceiveData(obj->base, (uint8_t *)data, (uint32_t)*length, - get_cyhal_bus_width(command->data.bus_width), callback_dispatcher_ptr, &obj->context); + get_cyhal_bus_width(command->data.bus_width), cyhal_qspi_cb_wrapper, &obj->context); } } return status; @@ -972,7 +885,7 @@ cy_rslt_t cyhal_qspi_write(cyhal_qspi_t *obj, const cyhal_qspi_command_t *comman if ((CY_SMIF_SUCCESS == status) && (*length > 0)) { status = (cy_rslt_t)Cy_SMIF_TransmitDataBlocking(obj->base, (uint8_t *)data, *length, - get_cyhal_bus_width(command->data.bus_width), &obj->context); + get_cyhal_bus_width(command->data.bus_width), &obj->context); } } @@ -993,17 +906,8 @@ cy_rslt_t cyhal_qspi_write_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t * if ((CY_SMIF_SUCCESS == status) && (*length > 0)) { - cy_smif_event_cb_t callback_dispatcher_ptr; - if (obj->irq_cause & CYHAL_QSPI_IRQ_TRANSMIT_DONE) - { - callback_dispatcher_ptr = cyhal_qspi_callback_dispatcher_table[obj->resource.block_num]; - } - else - { - callback_dispatcher_ptr = NULL; - } - status = (cy_rslt_t)Cy_SMIF_TransmitData(obj->base, (uint8_t *)data, *length, - get_cyhal_bus_width(command->data.bus_width), callback_dispatcher_ptr, &obj->context); + status = (cy_rslt_t)Cy_SMIF_TransmitData(obj->base, (uint8_t *)data, *length, + get_cyhal_bus_width(command->data.bus_width), cyhal_qspi_cb_wrapper, &obj->context); } } return status; @@ -1038,14 +942,17 @@ cy_rslt_t cyhal_qspi_transfer( return status; } -void cyhal_qspi_register_irq(cyhal_qspi_t *obj, cyhal_qspi_irq_handler_t handler, void *handler_arg) +void cyhal_qspi_register_callback(cyhal_qspi_t *obj, cyhal_qspi_event_callback_t callback, void *callback_arg) { - uint8_t idx = obj->resource.block_num; - irq_data_stc[idx].handler = handler; - irq_data_stc[idx].irq_arg = handler_arg; + uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); + obj->callback_data.callback = (cy_israddress) callback; + obj->callback_data.callback_arg = callback_arg; + cyhal_system_critical_section_exit(savedIntrStatus); + + obj->irq_cause = CYHAL_QSPI_EVENT_NONE; } -void cyhal_qspi_irq_enable(cyhal_qspi_t *obj, cyhal_qspi_irq_event_t event, bool enable) +void cyhal_qspi_enable_event(cyhal_qspi_t *obj, cyhal_qspi_event_t event, uint8_t intrPriority, bool enable) { if (enable) { @@ -1055,6 +962,9 @@ void cyhal_qspi_irq_enable(cyhal_qspi_t *obj, cyhal_qspi_irq_event_t event, bool { obj->irq_cause &= ~event; } + + IRQn_Type irqn = CYHAL_QSPI_IRQ_N[obj->resource.block_num]; + NVIC_SetPriority(irqn, intrPriority); } #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_rtc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_rtc.c index 3e6b76b07af..c0042f70e22 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_rtc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_rtc.c @@ -25,8 +25,9 @@ * limitations under the License. *******************************************************************************/ -#include "cyhal_implementation.h" #include "cy_rtc.h" +#include "cyhal_rtc.h" +#include "cyhal_system.h" #ifdef CY_IP_MXS40SRSS_RTC_INSTANCES @@ -34,13 +35,14 @@ extern "C" { #endif -#define CY_RTC_STATE_UNINITIALIZED 0 -#define CY_RTC_STATE_ENABLED 1 -#define CY_RTC_STATE_TIME_SET 2 -#define CY_RTC_DEFAULT_PRIORITY 5 -#define CY_TM_YEAR_BASE 1900 +#define CYHAL_RTC_STATE_UNINITIALIZED 0 +#define CYHAL_RTC_STATE_ENABLED 1 +#define CYHAL_RTC_STATE_TIME_SET 2 +#define CYHAL_RTC_DEFAULT_PRIORITY 5 +#define CYHAL_RTC_INIT_CENTURY 2000 +#define CYHAL_TM_YEAR_BASE 1900 -// Cy_RTC_DeepSleepCallback does not have a compatible signature +/** Wrapper around the PDL Cy_RTC_DeepSleepCallback to adapt the function signature */ static cy_en_syspm_status_t cyhal_rtc_syspm_callback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode) { return Cy_RTC_DeepSleepCallback(params, mode); @@ -52,12 +54,13 @@ static cy_stc_syspm_callback_t cyhal_rtc_pm_cb = { .type = CY_SYSPM_DEEPSLEEP, .callbackParams = &cyhal_rtc_pm_cb_params, }; -static cyhal_rtc_irq_handler_t cyhal_rtc_user_handler; +static cyhal_rtc_event_callback_t cyhal_rtc_user_handler; static void *cyhal_rtc_handler_arg; #define CYHAL_RTC_INITIAL_CENTURY 1900 static uint16_t cyhal_rtc_century = CYHAL_RTC_INITIAL_CENTURY; -static uint8_t cyhal_rtc_initialized = CY_RTC_STATE_UNINITIALIZED; +static uint8_t cyhal_rtc_initialized = CYHAL_RTC_STATE_UNINITIALIZED; +/** Wrapper around the PDL RTC interrupt handler to adapt the function signature */ static void cyhal_rtc_internal_handler(void) { Cy_RTC_Interrupt(NULL, false); @@ -78,8 +81,9 @@ void Cy_RTC_CenturyInterrupt(void) cy_rslt_t cyhal_rtc_init(cyhal_rtc_t *obj) { + CY_ASSERT(NULL != obj); cy_rslt_t rslt = CY_RSLT_SUCCESS; - if (cyhal_rtc_initialized == CY_RTC_STATE_UNINITIALIZED) + if (cyhal_rtc_initialized == CYHAL_RTC_STATE_UNINITIALIZED) { if (Cy_RTC_IsExternalResetOccurred()) { @@ -95,32 +99,34 @@ cy_rslt_t cyhal_rtc_init(cyhal_rtc_t *obj) else { // Time is already set (possibly after sw reset). Assume century. - cyhal_rtc_century = 2000; + cyhal_rtc_century = CYHAL_RTC_INIT_CENTURY; } Cy_RTC_ClearInterrupt(CY_RTC_INTR_CENTURY); Cy_RTC_SetInterruptMask(CY_RTC_INTR_CENTURY); - static const cy_stc_sysint_t irqCfg = {.intrSrc = srss_interrupt_backup_IRQn, .intrPriority = CY_RTC_DEFAULT_PRIORITY}; + static const cy_stc_sysint_t irqCfg = {.intrSrc = srss_interrupt_backup_IRQn, .intrPriority = CYHAL_RTC_DEFAULT_PRIORITY}; Cy_SysInt_Init(&irqCfg, &cyhal_rtc_internal_handler); - NVIC_EnableIRQ(srss_interrupt_backup_IRQn); Cy_SysPm_RegisterCallback(&cyhal_rtc_pm_cb); - cyhal_rtc_initialized = CY_RTC_STATE_ENABLED; + cyhal_rtc_initialized = CYHAL_RTC_STATE_ENABLED; } + NVIC_EnableIRQ(srss_interrupt_backup_IRQn); return rslt; } void cyhal_rtc_free(cyhal_rtc_t *obj) { + NVIC_DisableIRQ(srss_interrupt_backup_IRQn); + Cy_RTC_SetInterruptMask(CY_RTC_INTR_CENTURY); } bool cyhal_rtc_is_enabled(cyhal_rtc_t *obj) { - return (cyhal_rtc_initialized == CY_RTC_STATE_TIME_SET); + return (cyhal_rtc_initialized == CYHAL_RTC_STATE_TIME_SET); } cy_rslt_t cyhal_rtc_read(cyhal_rtc_t *obj, struct tm *time) { - // The number of days that precede each month of the year, not including Fdb 29 + // The number of days that precede each month of the year, not including Feb 29 static const uint16_t CUMULATIVE_DAYS[] = {0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334}; cy_stc_rtc_config_t dateTime; uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); @@ -132,7 +138,7 @@ cy_rslt_t cyhal_rtc_read(cyhal_rtc_t *obj, struct tm *time) time->tm_hour = dateTime.hour; time->tm_mday = dateTime.date; time->tm_mon = dateTime.month - 1u; - time->tm_year = year - CY_TM_YEAR_BASE; + time->tm_year = year - CYHAL_TM_YEAR_BASE; time->tm_wday = dateTime.dayOfWeek - 1u; time->tm_yday = CUMULATIVE_DAYS[time->tm_mon] + dateTime.date - 1u + ((dateTime.month >= 3 && Cy_RTC_IsLeapYear(year)) ? 1u : 0u); @@ -162,17 +168,17 @@ cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time) uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); rslt = (cy_rslt_t)Cy_RTC_SetDateAndTime(&newtime); if (rslt == CY_RSLT_SUCCESS) - cyhal_rtc_century = time->tm_year - year2digit + CY_TM_YEAR_BASE; + cyhal_rtc_century = time->tm_year - year2digit + CYHAL_TM_YEAR_BASE; cyhal_system_critical_section_exit(savedIntrStatus); ++retry; } while (rslt == CY_RTC_INVALID_STATE && retry < MAX_RETRY); while (CY_RTC_BUSY == Cy_RTC_GetSyncStatus()) { } if (rslt == CY_RSLT_SUCCESS) - cyhal_rtc_initialized = CY_RTC_STATE_TIME_SET; + cyhal_rtc_initialized = CYHAL_RTC_STATE_TIME_SET; return rslt; } -cy_rslt_t cyhal_rtc_alarm(cyhal_rtc_t *obj, const struct tm *time, cyhal_alarm_active_t active) +cy_rslt_t cyhal_rtc_set_alarm(cyhal_rtc_t *obj, const struct tm *time, cyhal_alarm_active_t active) { // Note: the hardware does not support year matching cy_stc_rtc_alarm_t alarm = { @@ -193,15 +199,15 @@ cy_rslt_t cyhal_rtc_alarm(cyhal_rtc_t *obj, const struct tm *time, cyhal_alarm_a return (cy_rslt_t)Cy_RTC_SetAlarmDateAndTime(&alarm, CY_RTC_ALARM_1); } -void cyhal_rtc_register_irq(cyhal_rtc_t *obj, cyhal_rtc_irq_handler_t handler, void *handler_arg) +void cyhal_rtc_register_callback(cyhal_rtc_t *obj, cyhal_rtc_event_callback_t callback, void *callback_arg) { uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); - cyhal_rtc_handler_arg = handler_arg; - cyhal_rtc_user_handler = handler; + cyhal_rtc_handler_arg = callback_arg; + cyhal_rtc_user_handler = callback; cyhal_system_critical_section_exit(savedIntrStatus); } -void cyhal_rtc_irq_enable(cyhal_rtc_t *obj, cyhal_rtc_irq_event_t event, bool enable) +void cyhal_rtc_enable_event(cyhal_rtc_t *obj, cyhal_rtc_event_t event, uint8_t intrPriority, bool enable) { Cy_RTC_ClearInterrupt(CY_RTC_INTR_ALARM1 | CY_RTC_INTR_ALARM2); Cy_RTC_SetInterruptMask((enable ? CY_RTC_INTR_ALARM1 : 0) | CY_RTC_INTR_CENTURY); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c index 1eab234a635..20448a187dc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c @@ -1,9 +1,9 @@ /***************************************************************************//** -* \file cyhal_scb_types.h +* \file cyhal_scb_common.c * * \brief * Provides a struct definitions for configuration resources in the SCB (UART, I2C, SPI). -* +* ******************************************************************************** * \copyright * Copyright 2018-2019 Cypress Semiconductor Corporation @@ -26,7 +26,12 @@ #ifdef CY_IP_MXSCB -CySCB_Type* CY_SCB_BASE_ADDRESSES[CY_IP_MXSCB_INSTANCES] = +#if defined(__cplusplus) +extern "C" +{ +#endif + +CySCB_Type* CYHAL_SCB_BASE_ADDRESSES[CY_IP_MXSCB_INSTANCES] = { #ifdef SCB0 SCB0, @@ -78,7 +83,7 @@ CySCB_Type* CY_SCB_BASE_ADDRESSES[CY_IP_MXSCB_INSTANCES] = #endif }; -IRQn_Type CY_SCB_IRQ_N[CY_IP_MXSCB_INSTANCES] = +IRQn_Type CYHAL_SCB_IRQ_N[CY_IP_MXSCB_INSTANCES] = { #ifdef SCB0 scb_0_interrupt_IRQn, @@ -130,4 +135,84 @@ IRQn_Type CY_SCB_IRQ_N[CY_IP_MXSCB_INSTANCES] = #endif }; +void *cyhal_scb_config_structs[CY_IP_MXSCB_INSTANCES]; + +uint8_t cyhal_scb_get_block_from_irqn(IRQn_Type irqn) { + switch (irqn) + { +#if (CY_CPU_CORTEX_M4) +#if (CY_IP_MXSCB_INSTANCES > 0) + case scb_0_interrupt_IRQn: return 0; +#endif +#if (CY_IP_MXSCB_INSTANCES > 1) + case scb_1_interrupt_IRQn: return 1; +#endif +#if (CY_IP_MXSCB_INSTANCES > 2) + case scb_2_interrupt_IRQn: return 2; +#endif +#if (CY_IP_MXSCB_INSTANCES > 3) + case scb_3_interrupt_IRQn: return 3; +#endif +#if (CY_IP_MXSCB_INSTANCES > 4) + case scb_4_interrupt_IRQn: return 4; +#endif +#if (CY_IP_MXSCB_INSTANCES > 5) + case scb_5_interrupt_IRQn: return 5; +#endif +#if (CY_IP_MXSCB_INSTANCES > 6) + case scb_6_interrupt_IRQn: return 6; +#endif +#if (CY_IP_MXSCB_INSTANCES > 7) + case scb_7_interrupt_IRQn: return 7; +#endif +#if (CY_IP_MXSCB_INSTANCES > 8) + case scb_8_interrupt_IRQn: return 8; +#endif +#if (CY_IP_MXSCB_INSTANCES > 9) + case scb_9_interrupt_IRQn: return 9; +#endif +#if (CY_IP_MXSCB_INSTANCES > 10) + case scb_10_interrupt_IRQn: return 10; +#endif +#if (CY_IP_MXSCB_INSTANCES > 11) + case scb_11_interrupt_IRQn: return 11; +#endif +#if (CY_IP_MXSCB_INSTANCES > 12) + case scb_12_interrupt_IRQn: return 12; +#endif +#if (CY_IP_MXSCB_INSTANCES > 13) + case scb_13_interrupt_IRQn: return 13; +#endif +#if (CY_IP_MXSCB_INSTANCES > 14) + case scb_14_interrupt_IRQn: return 14; +#endif +#if (CY_IP_MXSCB_INSTANCES > 15) + case scb_15_interrupt_IRQn: return 15; +#endif +#if (CY_IP_MXSCB_INSTANCES > 16) + case scb_16_interrupt_IRQn: return 16; +#endif +#if (CY_IP_MXSCB_INSTANCES > 17) + case scb_17_interrupt_IRQn: return 17; +#endif +#if (CY_IP_MXSCB_INSTANCES > 18) + case scb_18_interrupt_IRQn: return 18; +#endif +#if (CY_IP_MXSCB_INSTANCES > 19) + case scb_19_interrupt_IRQn: return 19; +#endif +#if (CY_IP_MXSCB_INSTANCES > 20) +#error "Unhandled scb count" +#endif +#endif /* (CY_CPU_CORTEX_M4) */ + default: + CY_ASSERT(false); // Should never be called with a non-SCB IRQn + return 0; + } +} + +#if defined(__cplusplus) +} +#endif + #endif /* CY_IP_MXSCB */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c index 1875a60e4a7..167bfb14522 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c @@ -32,34 +32,38 @@ #include "cyhal_gpio.h" #include "cyhal_hwmgr.h" #include "cyhal_utils.h" +#include "cyhal_system_impl.h" #include "cyhal_interconnect.h" -#include "cyhal_implementation.h" #ifdef CY_IP_MXSDHC -#define CY_HAL_READ_WRITE_RETRY_CYCLES (100u) /* Number of cycles for read/write operation complete */ -#define CY_HAL_SDHC_RETRY_TIME (1000UL) /* The number loops to make the timeout in msec */ -#define CY_HAL_SDHC_FUJE_TIMEOUT_MS (1000U) /* The Fuje timeout for one block */ -#define CY_HAL_SDHC_READ_WRITE_TIMEOUT_MS (500U) /* The Read/Write timeout for one block */ -#define CY_HAL_SDHC_OPER_CMPLT_US (250U) /* Delay in uS to complete all internal pending operations */ -#define CY_HAL_SDHC_CMD_TIMEOUT_US (5U) /* The Command timeout */ -#define CY_HAL_SDHC_TRANSFER_TIMEOUT (0xCUL) /* The transfer timeout */ -#define CY_HAL_SDHC_EMMC_TRIM_TIMEOUT (100U) /* The EMMC TRIM timeout */ +#if defined(__cplusplus) +extern "C" +{ +#endif + +#define SDHC_IRQ_PRIORITY (3UL) +#define SDHC_RW_RETRY_CYCLES (100u) /* Number of cycles for read/write operation complete */ +#define SDHC_RETRY_TIMES (1000UL) /* The number loops to make the timeout in msec */ +#define SDHC_FUJE_TIMEOUT_MS (1000U) /* The Fuje timeout for one block */ +#define SDHC_RW_TIMEOUT_US (500U) /* The SDHC Read/Write timeout for one block */ +#define SDHC_TRANSFER_TIMEOUT (0xCUL) /* The transfer timeout */ +#define SDHC_EMMC_TRIM_DELAY_MS (100U) /* The EMMC TRIM timeout */ #ifndef SDIO_ENUMERATION_TIMEOUT_MS - #define SDIO_ENUMERATION_TIMEOUT_MS (500) + #define SDIO_ENUMERATION_TIMEOUT_MS (500U) #endif -#define CY_SD_HOST_CLK_400K (400UL * 1000UL) /* 400 kHz. */ -#define SDHC_SDIO_64B_BLOCK (64U) +#define SDIO_RW_TIMEOUT_US (5U) /* The SDIO Read/Write timeout for one block */ +#define SDIO_CMD_CMPLT_DELAY_US (5U) /* The Command complete delay */ +#define SDIO_HOST_CLK_400K (400UL * 1000UL) /* 400 kHz clock frequency */ +#define SDIO_64B_BLOCK (64U) -#define SDHC_IRQ_PRIORITY (3UL) -#define SDIO_IRQ_PRIORITY (3UL) -#define ENABLE_ALL_INTERRUPT_MASK (0x0000FFFFUL) -#define ENABLE_ALL_INTERRUPT_ENABLE (0x0000FFFFUL) -#define DISABLE_ALL_INTERRUPT_MASK (0x0UL) -#define DISABLE_ALL_INTERRUPT_ENABLE (0x0UL) -#define CY_SDIO_BULK_TRANSF_TRIES (50) +#define SDIO_SET_ALL_INTERRUPTS_MASK (0x61FFUL) +#define SDIO_ALL_INTERRUPTS_ENABLE_MASK (0x61FFUL) +#define SDIO_CLEAR_ALL_INTERRUPTS_MASK (0x0UL) +#define SDIO_CLEAR_ALL_INTERRUPTS_ENABLE_MASK (0x0UL) +#define SDIO_TRANSF_TRIES (50U) /* Clock frequency which is connected to SDHC divider */ @@ -67,34 +71,252 @@ #define BIT_MASK( x ) (( 1 << x ) - 1 ) -#define SDIO_PINS_NC ((cyhal_gpio_t) CYHAL_NC_PIN_VALUE) +#define SDIO_PINS_NC ((cyhal_gpio_t) CYHAL_NC_PIN_VALUE) + +/* Macro-function to calculate pin mapping number */ +#define COUNT(pin_mapping) (sizeof(pin_mapping)/sizeof(cyhal_resource_pin_mapping_t)) + + +#if (defined(SDHC_CHIP_TOP_DATA8_PRESENT) && (SDHC_CHIP_TOP_DATA8_PRESENT)) || \ + (defined(SDHC0_CHIP_TOP_DATA8_PRESENT) && (SDHC0_CHIP_TOP_DATA8_PRESENT)) || \ + (defined(SDHC1_CHIP_TOP_DATA8_PRESENT) && (SDHC1_CHIP_TOP_DATA8_PRESENT)) + #define DATA8_PRESENT 1 +#else + #define DATA8_PRESENT 0 +#endif +#if (defined(SDHC_CHIP_TOP_CARD_DETECT_PRESENT) && (SDHC_CHIP_TOP_CARD_DETECT_PRESENT)) || \ + (defined(SDHC0_CHIP_TOP_CARD_DETECT_PRESENT) && (SDHC0_CHIP_TOP_CARD_DETECT_PRESENT)) || \ + (defined(SDHC1_CHIP_TOP_CARD_DETECT_PRESENT) && (SDHC1_CHIP_TOP_CARD_DETECT_PRESENT)) + #define CARD_DETECT_PRESENT 1 +#else + #define CARD_DETECT_PRESENT 0 +#endif +#if (defined(SDHC_CHIP_TOP_CARD_WRITE_PROT_PRESENT) && (SDHC_CHIP_TOP_CARD_WRITE_PROT_PRESENT)) || \ + (defined(SDHC0_CHIP_TOP_CARD_WRITE_PROT_PRESENT) && (SDHC0_CHIP_TOP_CARD_WRITE_PROT_PRESENT)) || \ + (defined(SDHC1_CHIP_TOP_CARD_WRITE_PROT_PRESENT) && (SDHC1_CHIP_TOP_CARD_WRITE_PROT_PRESENT)) + #define CARD_WRITE_PROT_PRESENT 1 +#else + #define CARD_WRITE_PROT_PRESENT 0 +#endif +#if (defined(SDHC_CHIP_TOP_LED_CTRL_PRESENT) && (SDHC_CHIP_TOP_LED_CTRL_PRESENT)) || \ + (defined(SDHC0_CHIP_TOP_LED_CTRL_PRESENT) && (SDHC0_CHIP_TOP_LED_CTRL_PRESENT)) || \ + (defined(SDHC1_CHIP_TOP_LED_CTRL_PRESENT) && (SDHC1_CHIP_TOP_LED_CTRL_PRESENT)) + #define LED_CTRL_PRESENT 1 +#else + #define LED_CTRL_PRESENT 0 +#endif +#if (defined(SDHC_CHIP_TOP_IO_VOLT_SEL_PRESENT) && (SDHC_CHIP_TOP_IO_VOLT_SEL_PRESENT)) || \ + (defined(SDHC0_CHIP_TOP_IO_VOLT_SEL_PRESENT) && (SDHC0_CHIP_TOP_IO_VOLT_SEL_PRESENT)) || \ + (defined(SDHC1_CHIP_TOP_IO_VOLT_SEL_PRESENT) && (SDHC1_CHIP_TOP_IO_VOLT_SEL_PRESENT)) + #define IO_VOLT_SEL_PRESENT 1 +#else + #define IO_VOLT_SEL_PRESENT 0 +#endif +#if (defined(SDHC_CHIP_TOP_CARD_IF_POWER_EN_PRESENT) && (SDHC_CHIP_TOP_CARD_IF_POWER_EN_PRESENT)) || \ + (defined(SDHC0_CHIP_TOP_CARD_IF_POWER_EN_PRESENT) && (SDHC0_CHIP_TOP_CARD_IF_POWER_EN_PRESENT)) || \ + (defined(SDHC1_CHIP_TOP_CARD_IF_POWER_EN_PRESENT) && (SDHC1_CHIP_TOP_CARD_IF_POWER_EN_PRESENT)) + #define CARD_IF_POWER_EN_PRESENT 1 +#else + #define CARD_IF_POWER_EN_PRESENT 0 +#endif +#if (defined(SDHC_CHIP_TOP_CARD_EMMC_RESET_PRESENT) && (SDHC_CHIP_TOP_CARD_EMMC_RESET_PRESENT)) || \ + (defined(SDHC0_CHIP_TOP_CARD_EMMC_RESET_PRESENT) && (SDHC0_CHIP_TOP_CARD_EMMC_RESET_PRESENT)) || \ + (defined(SDHC1_CHIP_TOP_CARD_EMMC_RESET_PRESENT) && (SDHC1_CHIP_TOP_CARD_EMMC_RESET_PRESENT)) + #define CARD_EMMC_RESET_PRESENT 1 +#else + #define CARD_EMMC_RESET_PRESENT 0 +#endif + +/* Mask which indicates interface change */ +#define SDIO_INTERFACE_CHANGE_MASK ((uint32_t) ((uint32_t) CYHAL_SDIO_GOING_DOWN) | ((uint32_t) CYHAL_SDIO_COMING_UP)) + +#if !defined(CYHAL_SDIO_DS_CB_ORDER) + /* The order value for SDIO Deep Sleep callback */ + #define CYHAL_SDIO_DS_CB_ORDER (0U) + #endif /* !defined(CYHAL_SDIO_DS_CB_ORDER) */ /* List of available SDHC instances */ -static SDHC_Type * CY_SDHC_BASE_ADDRESSES[CY_IP_MXSDHC_INSTANCES] = +static SDHC_Type * const CYHAL_SDHC_BASE_ADDRESSES[CY_IP_MXSDHC_INSTANCES] = { #ifdef SDHC0 SDHC0, -#endif /* ifdef SMIF0 */ +#endif /* ifdef SDHC0 */ + #ifdef SDHC1 SDHC1, -#endif /* ifdef SMIF1 */ +#endif /* ifdef SDHC1 */ +}; + +/* List of available SDHC HF clocks */ +static uint8_t const CYHAL_SDHC_HF_CLOCKS[CY_IP_MXSDHC_INSTANCES] = +{ +#ifdef SDHC0 + 4, +#endif /* ifdef SDHC0 */ + +#ifdef SDHC1 + 2, +#endif /* ifdef SDHC1 */ }; + /* List of available SDHC interrupt sources */ -static IRQn_Type CY_SDHC_IRQ_N[CY_IP_MXSDHC_INSTANCES] = +static IRQn_Type const CYHAL_SDHC_IRQ_N[CY_IP_MXSDHC_INSTANCES] = { #ifdef SDHC0 sdhc_0_interrupt_general_IRQn, #endif /* ifdef SDHC0 */ + #ifdef SDHC1 sdhc_1_interrupt_general_IRQn, #endif /* ifdef SDHC1 */ }; +static uint8_t cyhal_sd_get_block_from_irqn(IRQn_Type irqn) +{ + switch (irqn) + { +#if (CY_CPU_CORTEX_M4) + #if (CY_IP_MXSDHC_INSTANCES > 0) + case sdhc_0_interrupt_general_IRQn: return 0; + #endif + + #if (CY_IP_MXSDHC_INSTANCES > 1) + case sdhc_1_interrupt_general_IRQn: return 1; + #endif + + #if (CY_IP_MXSDHC_INSTANCES > 2) + #error "Unhandled SDHC count" + #endif +#endif /* (CY_CPU_CORTEX_M4) */ + default: + CY_ASSERT(false); /* Should never be called with a non-SDHC IRQn */ + return 0; + } +} + +static void *cyhal_sd_config_structs[CY_IP_MXSDHC_INSTANCES]; + +static void release_pin_if_used(cyhal_gpio_t *pin) +{ + if (CYHAL_NC_PIN_VALUE != *pin) + { + cyhal_utils_disconnect_and_free(*pin); + *pin = CYHAL_NC_PIN_VALUE; + } +} + +static cy_rslt_t setup_pin(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pinmap, size_t count, cyhal_gpio_t *objRef) +{ + cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(pin); + cy_rslt_t result = cyhal_hwmgr_reserve(&pin_rsc); + + if (result == CY_RSLT_SUCCESS) + { + const cyhal_resource_pin_mapping_t *map = cyhal_utils_get_resource(pin, pinmap, count); + + if (map == NULL) + { + result = CYHAL_SDHC_RSLT_ERR_PIN; + } + + if (result == CY_RSLT_SUCCESS) + { + result = cyhal_connect_pin(map); + } + + if (result == CY_RSLT_SUCCESS) + { + *objRef = pin; + } + else + { + cyhal_hwmgr_free(&pin_rsc); + } + } + + return result; +} + /* Internal global variable to indicate pending sdio async status */ static bool isTransferInProcess = false; +/* Internal functions */ +static cy_en_sd_host_status_t Cy_SD_Host_PollTransferComplete(SDHC_Type *base, const uint16_t delay); +static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base); +static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency); static cy_en_sd_host_bus_width_t convert_buswidth(uint8_t stopbits); +static cy_en_syspm_status_t cyhal_sdio_syspm_callback(cy_stc_syspm_callback_params_t *params, + cy_en_syspm_callback_mode_t mode); + +/******************************************************************************* +* Deep Sleep Callback Service Routine +*******************************************************************************/ +static cy_en_syspm_status_t cyhal_sdio_syspm_callback(cy_stc_syspm_callback_params_t *params, + cy_en_syspm_callback_mode_t mode) +{ + cy_en_syspm_status_t retVal = CY_SYSPM_FAIL; + cyhal_sdio_t *obj = params->context; + static bool wasCheckReadyExecuted = false; + + cy_stc_syspm_callback_params_t pdl_params = + { + .base = obj->base, + .context = &(obj->context) + }; + + retVal = Cy_SD_Host_DeepSleepCallback(&pdl_params, mode); + + if (retVal == CY_SYSPM_SUCCESS) + { + switch (mode) + { + case CY_SYSPM_CHECK_READY: + { + cyhal_sdio_event_callback_t callback = (cyhal_sdio_event_callback_t) obj->callback_data.callback; + if ((callback != NULL) && (0U != (obj->events & (uint32_t) CYHAL_SDIO_GOING_DOWN))) + { + (void)(callback)(obj->callback_data.callback_arg, CYHAL_SDIO_GOING_DOWN); + } + + wasCheckReadyExecuted = true; + + break; + } + + case CY_SYSPM_BEFORE_TRANSITION: + { + /* Nothing to do in this mode */ + break; + } + + case CY_SYSPM_AFTER_TRANSITION: + case CY_SYSPM_CHECK_FAIL: + { + /* Execute this only if check ready case was executed */ + if (wasCheckReadyExecuted) + { + /* Execute callback to indicate that interface is coming up */ + cyhal_sdio_event_callback_t callback = (cyhal_sdio_event_callback_t) obj->callback_data.callback; + if ((callback != NULL) && (0U != (obj->events & (uint32_t) CYHAL_SDIO_COMING_UP))) + { + (void)(callback)(obj->callback_data.callback_arg, CYHAL_SDIO_COMING_UP); + } + + wasCheckReadyExecuted = false; + } + break; + } + + default: + break; + } + } + + return retVal; +} + + static cy_en_sd_host_bus_width_t convert_buswidth(uint8_t stopbits) { switch (stopbits) @@ -111,7 +333,7 @@ static cy_en_sd_host_bus_width_t convert_buswidth(uint8_t stopbits) } } -static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint32_t frequency); + /******************************************************************************* * Function Name: Cy_SD_Host_SdCardChangeClock ****************************************************************************//** @@ -121,34 +343,42 @@ static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint * \param *base * The SD host registers structure pointer. * +* \param instance_num +* The SD host instance number. +* * \param frequency * The frequency in Hz. * * \return \ref cy_en_sd_host_status_t * *******************************************************************************/ -static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint32_t frequency) +static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency) { cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_INVALID_PARAMETER; - uint32_t clkDiv; - uint32_t clockInput = SDIO_CLK_HF_HZ; - cy_en_sd_host_bus_speed_mode_t busSpeed; + uint32_t clockInput = 0; + + cy_rslt_t get_frequency_result = + cyhal_system_clock_get_frequency(CYHAL_SDHC_HF_CLOCKS[instance_num], &clockInput); - if (NULL != base) + if ((NULL != base) && (get_frequency_result == CY_RSLT_SUCCESS) && (0U != clockInput)) { - clkDiv = (clockInput / frequency) >> 1UL; + /* Update SD Host clock divider */ + uint16_t clkDiv = (uint16_t) ((clockInput / frequency) >> 1UL); + Cy_SD_Host_DisableSdClk(base); - ret = Cy_SD_Host_SetSdClkDiv(base, (uint16_t)clkDiv); + ret = Cy_SD_Host_SetSdClkDiv(base, clkDiv); Cy_SD_Host_EnableSdClk(base); /* Update bus speed mode based on new frequency */ if (ret == CY_SD_HOST_SUCCESS) { - if (clkDiv == 0u) + cy_en_sd_host_bus_speed_mode_t busSpeed; + + if (frequency == CY_SD_HOST_CLK_50M) { busSpeed = CY_SD_HOST_BUS_SPEED_SDR50; } - else if (clkDiv == 1u) + else if (frequency == CY_SD_HOST_CLK_25M) { busSpeed = CY_SD_HOST_BUS_SPEED_SDR25; } @@ -164,7 +394,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint return ret; } -static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base); + /******************************************************************************* * Function Name: Cy_SD_Host_PollCmdComplete ****************************************************************************//** @@ -180,7 +410,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base); static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base) { cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_TIMEOUT; - uint32_t retry = CY_HAL_SDHC_RETRY_TIME; + uint32_t retry = SDHC_RETRY_TIMES; while (retry > 0UL) { @@ -194,14 +424,14 @@ static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base) break; } - Cy_SysLib_DelayUs(CY_HAL_SDHC_CMD_TIMEOUT_US); + Cy_SysLib_DelayUs(SDIO_CMD_CMPLT_DELAY_US); retry--; } return ret; } -static cy_en_sd_host_status_t Cy_SD_Host_PollTransferComplete(SDHC_Type *base); + /******************************************************************************* * Function Name: Cy_SD_Host_PollTransferComplete ****************************************************************************//** @@ -211,18 +441,21 @@ static cy_en_sd_host_status_t Cy_SD_Host_PollTransferComplete(SDHC_Type *base); * \param *base * The SD host registers structure pointer. * +* \param delay +* The delay timeout for one block transfer. +* * \return cy_en_sd_host_status_t * *base checking result. * If the pointer is NULL, returns error. * *******************************************************************************/ -static cy_en_sd_host_status_t Cy_SD_Host_PollTransferComplete(SDHC_Type *base) +static cy_en_sd_host_status_t Cy_SD_Host_PollTransferComplete(SDHC_Type *base, const uint16_t delay) { cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_TIMEOUT; - uint32_t retry = CY_HAL_READ_WRITE_RETRY_CYCLES; + uint32_t retry = SDHC_RW_RETRY_CYCLES; uint32_t status = 0UL; - while ((CY_SD_HOST_ERROR_TIMEOUT == ret) && (retry-- > 0u)) + while ((CY_SD_HOST_ERROR_TIMEOUT == ret) && (retry-- > 0U)) { status = Cy_SD_Host_GetNormalInterruptStatus(base); @@ -236,303 +469,337 @@ static cy_en_sd_host_status_t Cy_SD_Host_PollTransferComplete(SDHC_Type *base) break; } - Cy_SysLib_DelayUs(CY_HAL_SDHC_READ_WRITE_TIMEOUT_MS); + Cy_SysLib_DelayUs(delay); } return ret; } -static cy_rslt_t setup_pin(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pinmap, cyhal_gpio_t *objRef) +static void cyhal_sdhc_irq_handler(void) { - cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(pin); - cy_rslt_t result = cyhal_hwmgr_reserve(&pin_rsc); - if (result == CY_RSLT_SUCCESS) + IRQn_Type irqn = CYHAL_GET_CURRENT_IRQN(); + uint8_t block = cyhal_sd_get_block_from_irqn(irqn); + SDHC_Type *blockAddr = CYHAL_SDHC_BASE_ADDRESSES[block]; + cyhal_sdhc_t *obj = (cyhal_sdhc_t*) cyhal_sd_config_structs[block]; + + uint32_t interruptStatus = Cy_SD_Host_GetNormalInterruptStatus(blockAddr); + uint32_t userInterruptStatus = interruptStatus & obj->irq_cause; + + if (obj->callback_data.callback != NULL) { - const cyhal_resource_pin_mapping_t *map = CY_UTILS_GET_RESOURCE(pin, pinmap); - result = cyhal_connect_pin(map); + cyhal_sdhc_event_callback_t callback = (cyhal_sdhc_event_callback_t) obj->callback_data.callback; + /* Call registered callbacks here */ + (void) (callback) (obj->callback_data.callback_arg, (cyhal_sdhc_event_t) userInterruptStatus); + } - if (result == CY_RSLT_SUCCESS) - { - *objRef = pin; - } - else - { - cyhal_hwmgr_free(&pin_rsc); - } + /* Clear only handled events */ + Cy_SD_Host_ClearNormalInterruptStatus(blockAddr, userInterruptStatus); + + /* To clear SD Card interrupt need to disable SD Card Interrupt Enable bit. + * The SD Card interrupt is enabled in the bulk transfer function later on + * the next data transfer. + */ + if (0U != (interruptStatus & CY_SD_HOST_CARD_INTERRUPT)) + { + uint32_t interruptMask = Cy_SD_Host_GetNormalInterruptEnable(blockAddr); + interruptMask &= (uint32_t) ~CY_SD_HOST_CARD_INTERRUPT; + + /* Disable SD Card interrupt */ + Cy_SD_Host_SetNormalInterruptEnable(blockAddr, interruptMask); } - return result; + } cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, - cyhal_gpio_t cmd, - cyhal_gpio_t clk, - cyhal_gpio_t data0, - cyhal_gpio_t data1, - cyhal_gpio_t data2, - cyhal_gpio_t data3, - cyhal_gpio_t data4, - cyhal_gpio_t data5, - cyhal_gpio_t data6, - cyhal_gpio_t data7, - cyhal_gpio_t cardDetect, - cyhal_gpio_t ioVoltSel, - cyhal_gpio_t cardIfPwrEn, - cyhal_gpio_t cardMechWriteProt, - cyhal_gpio_t ledCtrl, - cyhal_gpio_t cardEmmcReset) + const cyhal_sdhc_config_t *config, + cyhal_gpio_t cmd, + cyhal_gpio_t clk, + cyhal_gpio_t data0, + cyhal_gpio_t data1, + cyhal_gpio_t data2, + cyhal_gpio_t data3, + cyhal_gpio_t data4, + cyhal_gpio_t data5, + cyhal_gpio_t data6, + cyhal_gpio_t data7, + cyhal_gpio_t cardDetect, + cyhal_gpio_t ioVoltSel, + cyhal_gpio_t cardIfPwrEn, + cyhal_gpio_t cardMechWriteProt, + cyhal_gpio_t ledCtrl, + cyhal_gpio_t cardEmmcReset) { CY_ASSERT(NULL != obj); cy_rslt_t result = CY_RSLT_SUCCESS; + + obj->base = NULL; + + obj->pin_clk = CYHAL_NC_PIN_VALUE; + obj->pin_cmd = CYHAL_NC_PIN_VALUE; + obj->pin_data[0] = CYHAL_NC_PIN_VALUE; + obj->pin_data[1] = CYHAL_NC_PIN_VALUE; + obj->pin_data[2] = CYHAL_NC_PIN_VALUE; + obj->pin_data[3] = CYHAL_NC_PIN_VALUE; + obj->pin_data[4] = CYHAL_NC_PIN_VALUE; + obj->pin_data[5] = CYHAL_NC_PIN_VALUE; + obj->pin_data[6] = CYHAL_NC_PIN_VALUE; + obj->pin_data[7] = CYHAL_NC_PIN_VALUE; + obj->pin_cardDetect = CYHAL_NC_PIN_VALUE; + obj->pin_ioVoltSel = CYHAL_NC_PIN_VALUE; + obj->pin_cardIfPwrEn = CYHAL_NC_PIN_VALUE; + obj->pin_cardMechWriteProt = CYHAL_NC_PIN_VALUE; + obj->pin_ledCtrl = CYHAL_NC_PIN_VALUE; + obj->pin_cardEmmcReset = CYHAL_NC_PIN_VALUE; + + cyhal_gpio_t data[8]; + data[0] = data0; + data[1] = data1; + data[2] = data2; + data[3] = data3; + data[4] = data4; + data[5] = data5; + data[6] = data6; + data[7] = data7; /* Reserve SDHC */ const cyhal_resource_pin_mapping_t *map = CY_UTILS_GET_RESOURCE(cmd, cyhal_pin_map_sdhc_card_cmd); - if (NULL != map) - { - obj->resource = *map->inst; - result = cyhal_hwmgr_reserve(&obj->resource); - } - /* Reserve and configure GPIO pins. */ - if (result == CY_RSLT_SUCCESS) + if (NULL == map || NC == data0) { - result = setup_pin(cmd, cyhal_pin_map_sdhc_card_cmd, &(obj->pin_cmd)); + result = CYHAL_SDHC_RSLT_ERR_PIN; } + /* Reserve and configure GPIO pins */ if (result == CY_RSLT_SUCCESS) { - result = setup_pin(clk, cyhal_pin_map_sdhc_clk_card, &(obj->pin_clk)); + result = setup_pin( + cmd, cyhal_pin_map_sdhc_card_cmd, COUNT(cyhal_pin_map_sdhc_card_cmd), &(obj->pin_cmd)); } if (result == CY_RSLT_SUCCESS) { - result = setup_pin(data0, cyhal_pin_map_sdhc_card_dat_3to0, &(obj->pin_data0)); - } - - if ((NC != data1) && (CY_RSLT_SUCCESS == result)) - { - result = setup_pin(data1, cyhal_pin_map_sdhc_card_dat_3to0, &(obj->pin_data1)); - } - - if ((NC != data2) && (CY_RSLT_SUCCESS == result)) - { - result = setup_pin(data2, cyhal_pin_map_sdhc_card_dat_3to0, &(obj->pin_data2)); - } - - if ((NC != data3) && (CY_RSLT_SUCCESS == result)) - { - result = setup_pin(data3, cyhal_pin_map_sdhc_card_dat_3to0, &(obj->pin_data3)); + result = setup_pin( + clk, cyhal_pin_map_sdhc_clk_card, COUNT(cyhal_pin_map_sdhc_clk_card), &(obj->pin_clk)); } - if ((NC != data4) && (CY_RSLT_SUCCESS == result)) + for (uint8_t i = 0; (i < 4) && (CY_RSLT_SUCCESS == result); i++) { - result = setup_pin(data4, cyhal_pin_map_sdhc_card_dat_7to4, &(obj->pin_data4)); - } - - if ((NC != data5) && (CY_RSLT_SUCCESS == result)) - { - result = setup_pin(data5, cyhal_pin_map_sdhc_card_dat_7to4, &(obj->pin_data5)); + if (NC != data[i]) + { + result = setup_pin(data[i], cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data[i])); + } } - if ((NC != data6) && (CY_RSLT_SUCCESS == result)) +#if DATA8_PRESENT + for (uint8_t i = 4; (i < 8) && (CY_RSLT_SUCCESS == result); i++) { - result = setup_pin(data6, cyhal_pin_map_sdhc_card_dat_7to4, &(obj->pin_data6)); + if (NC != data[i]) + { + result = setup_pin(data[i], cyhal_pin_map_sdhc_card_dat_7to4, COUNT(cyhal_pin_map_sdhc_card_dat_7to4), &(obj->pin_data[i])); + } } - - if ((NC != data7) && (CY_RSLT_SUCCESS == result)) +#else + if ((NC != data4 || NC != data5 || NC != data6 || NC != data7) && (CY_RSLT_SUCCESS == result)) { - result = setup_pin(data7, cyhal_pin_map_sdhc_card_dat_7to4, &(obj->pin_data7)); + result = CYHAL_SDHC_RSLT_ERR_PIN; } +#endif if ((NC != cardDetect) && (CY_RSLT_SUCCESS == result)) { - result = setup_pin(cardDetect, cyhal_pin_map_sdhc_card_detect_n, &(obj->pin_cardDetect)); +#if CARD_DETECT_PRESENT + result = setup_pin(cardDetect, cyhal_pin_map_sdhc_card_detect_n, + COUNT(cyhal_pin_map_sdhc_card_detect_n), &(obj->pin_cardDetect)); +#else + result = CYHAL_SDHC_RSLT_ERR_PIN; +#endif } if ((NC != ioVoltSel) && (CY_RSLT_SUCCESS == result)) { - result = setup_pin(ioVoltSel, cyhal_pin_map_sdhc_io_volt_sel, &(obj->pin_ioVoltSel)); +#if IO_VOLT_SEL_PRESENT + result = setup_pin(ioVoltSel, cyhal_pin_map_sdhc_io_volt_sel, + COUNT(cyhal_pin_map_sdhc_io_volt_sel), &(obj->pin_ioVoltSel)); +#else + result = CYHAL_SDHC_RSLT_ERR_PIN; +#endif } if ((NC != cardIfPwrEn) && (CY_RSLT_SUCCESS == result)) { - result = setup_pin(cardIfPwrEn, cyhal_pin_map_sdhc_card_if_pwr_en, &(obj->pin_cardIfPwrEn)); +#if CARD_IF_PWR_EN_PRESENT + result = setup_pin(cardIfPwrEn, cyhal_pin_map_sdhc_card_if_pwr_en, + COUNT(cyhal_pin_map_sdhc_card_if_pwr_en), &(obj->pin_cardIfPwrEn)); +#else + result = CYHAL_SDHC_RSLT_ERR_PIN; +#endif } if ((NC != cardMechWriteProt) && (CY_RSLT_SUCCESS == result)) { - result = setup_pin(cardMechWriteProt, cyhal_pin_map_sdhc_card_mech_write_prot, &(obj->pin_cardMechWriteProt)); +#if CARD_WRITE_PROT_PRESENT + result = setup_pin(cardMechWriteProt, cyhal_pin_map_sdhc_card_mech_write_prot, + COUNT(cyhal_pin_map_sdhc_card_mech_write_prot), &(obj->pin_cardMechWriteProt)); +#else + result = CYHAL_SDHC_RSLT_ERR_PIN; +#endif } if ((NC != ledCtrl) && (CY_RSLT_SUCCESS == result)) { - result = setup_pin(ledCtrl, cyhal_pin_map_sdhc_led_ctrl, &(obj->pin_ledCtrl)); +#if LED_CTRL_PRESENT + result = setup_pin(ledCtrl, cyhal_pin_map_sdhc_led_ctrl, + COUNT(cyhal_pin_map_sdhc_led_ctrl), &(obj->pin_ledCtrl)); +#else + result = CYHAL_SDHC_RSLT_ERR_PIN; +#endif } if ((NC != cardEmmcReset) && (CY_RSLT_SUCCESS == result)) { - result = setup_pin(cardEmmcReset, cyhal_pin_map_sdhc_card_emmc_reset_n, &(obj->pin_cardEmmcReset)); +#if CARD_EMMC_RESET_PRESENT + result = setup_pin(cardEmmcReset, cyhal_pin_map_sdhc_card_emmc_reset_n, + COUNT(cyhal_pin_map_sdhc_card_emmc_reset_n), &(obj->pin_cardEmmcReset)); +#else + result = CYHAL_SDHC_RSLT_ERR_PIN; +#endif } if (CY_RSLT_SUCCESS == result) { - /* Enable the SDHC block. */ - Cy_SD_Host_Enable(obj->base); - - /* Configure SD Host to operate */ - cy_stc_sd_host_init_config_t hostConfig; - hostConfig.dmaType = obj->dmaType; - hostConfig.emmc = obj->emmc; - obj->context.cardType = CY_SD_HOST_NOT_EMMC; - - result = Cy_SD_Host_Init(obj->base, &hostConfig, &obj->context); - } + obj->resource = *map->inst; + result = cyhal_hwmgr_reserve(&obj->resource); - if (result != CY_RSLT_SUCCESS) - { - cyhal_sdhc_free(obj); - } + if (CY_RSLT_SUCCESS == result) + { + obj->base = CYHAL_SDHC_BASE_ADDRESSES[obj->resource.block_num]; - return result; -} + /* Enable the SDHC block */ + Cy_SD_Host_Enable(obj->base); -void cyhal_sdhc_free(cyhal_sdhc_t *obj) -{ - CY_ASSERT(NULL != obj); + /* Do not support eMMC card */ + obj->emmc = config->isEmmc; + obj->dmaType = CY_SD_HOST_DMA_SDMA; - Cy_SD_Host_DeInit(obj->base); + /* Configure SD Host to operate */ + cy_stc_sd_host_init_config_t hostConfig; + hostConfig.dmaType = obj->dmaType; + hostConfig.emmc = obj->emmc; - /* Free pins */ - if (CYHAL_NC_PIN_VALUE != obj->pin_cmd) - { - cyhal_utils_disconnect_and_free(obj->pin_cmd); - obj->pin_cmd = CYHAL_NC_PIN_VALUE; - } + #if LED_CTRL_PRESENT + if (NC != ledCtrl) + { + hostConfig.enableLedControl = true; + } + else + #endif + { + hostConfig.enableLedControl = false; + } - if (CYHAL_NC_PIN_VALUE != obj->pin_clk) - { - cyhal_utils_disconnect_and_free(obj->pin_clk); - obj->pin_clk = CYHAL_NC_PIN_VALUE; - } + obj->context.cardType = CY_SD_HOST_NOT_EMMC; - if (CYHAL_NC_PIN_VALUE != obj->pin_data0) - { - cyhal_utils_disconnect_and_free(obj->pin_data0); - obj->pin_data0 = CYHAL_NC_PIN_VALUE; - } + obj->irq_cause = 0UL; + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + cyhal_sd_config_structs[obj->resource.block_num] = obj; - if (CYHAL_NC_PIN_VALUE != obj->pin_data1) - { - cyhal_utils_disconnect_and_free(obj->pin_data1); - obj->pin_data1 = CYHAL_NC_PIN_VALUE; - } + IRQn_Type irqn = CYHAL_SDHC_IRQ_N[obj->resource.block_num]; + cy_stc_sysint_t irqCfg = { irqn, CYHAL_ISR_PRIORITY_DEFAULT }; + Cy_SysInt_Init(&irqCfg, cyhal_sdhc_irq_handler); + NVIC_EnableIRQ(irqn); + + result = (cy_rslt_t) Cy_SD_Host_Init(obj->base, &hostConfig, &obj->context); + } - if (CYHAL_NC_PIN_VALUE != obj->pin_data2) - { - cyhal_utils_disconnect_and_free(obj->pin_data2); - obj->pin_data2 = CYHAL_NC_PIN_VALUE; + /* Initialize card */ + if (result == CY_RSLT_SUCCESS) + { + cy_stc_sd_host_sd_card_config_t stcSdcardCfg; + cy_en_sd_host_card_capacity_t cardCapacity; + uint32_t rca = 0UL; + cy_en_sd_host_card_type_t cardType = CY_SD_HOST_UNUSABLE; + + /* Initialize the SDIO/SD/eMMC card configuration structure */ + stcSdcardCfg.lowVoltageSignaling = config->lowVoltageSignaling; + stcSdcardCfg.busWidth = convert_buswidth(config->busWidth); + stcSdcardCfg.cardType = &cardType; + stcSdcardCfg.rca = &rca; + stcSdcardCfg.cardCapacity = &cardCapacity; + + /* Initialize the card */ + result = (cy_rslt_t)Cy_SD_Host_InitCard(obj->base, &stcSdcardCfg, &obj->context); + + if (result == CY_RSLT_SUCCESS) + { + /* Update SD Card frequency to be 25 Mhz */ + result = (cy_rslt_t) Cy_SD_Host_SdCardChangeClock(obj->base, obj->resource.block_num, CY_SD_HOST_CLK_25M); + } + } } - if (CYHAL_NC_PIN_VALUE != obj->pin_data3) + if (result != CY_RSLT_SUCCESS) { - cyhal_utils_disconnect_and_free(obj->pin_data3); - obj->pin_data3 = CYHAL_NC_PIN_VALUE; + cyhal_sdhc_free(obj); } - if (CYHAL_NC_PIN_VALUE != obj->pin_data4) - { - cyhal_utils_disconnect_and_free(obj->pin_data4); - obj->pin_data4 = CYHAL_NC_PIN_VALUE; - } + return result; +} - if (CYHAL_NC_PIN_VALUE != obj->pin_data5) - { - cyhal_utils_disconnect_and_free(obj->pin_data5); - obj->pin_data5 = CYHAL_NC_PIN_VALUE; - } +void cyhal_sdhc_free(cyhal_sdhc_t *obj) +{ + CY_ASSERT(NULL != obj); - if (CYHAL_NC_PIN_VALUE != obj->pin_data6) + if ((NULL != obj->base) && (obj->resource.type != CYHAL_RSC_INVALID)) { - cyhal_utils_disconnect_and_free(obj->pin_data6); - obj->pin_data6 = CYHAL_NC_PIN_VALUE; - } + IRQn_Type irqn = CYHAL_SDHC_IRQ_N[obj->resource.block_num]; + NVIC_DisableIRQ(irqn); - if (CYHAL_NC_PIN_VALUE != obj->pin_data7) - { - cyhal_utils_disconnect_and_free(obj->pin_data7); - obj->pin_data6 = CYHAL_NC_PIN_VALUE; + Cy_SD_Host_DeInit(obj->base); + + cyhal_hwmgr_free(&(obj->resource)); + obj->base = NULL; + obj->resource.type = CYHAL_RSC_INVALID; } - if (CYHAL_NC_PIN_VALUE != obj->pin_cardDetect) - { - cyhal_utils_disconnect_and_free(obj->pin_cardDetect); - obj->pin_cardDetect = CYHAL_NC_PIN_VALUE; - } + /* Free pins */ + release_pin_if_used(&obj->pin_cmd); + release_pin_if_used(&obj->pin_clk); - if (CYHAL_NC_PIN_VALUE != obj->pin_ioVoltSel) +#if DATA8_PRESENT + const uint8_t max_idx = 8; +#else + const uint8_t max_idx = 4; +#endif + for (uint8_t i = 0; i < max_idx; i++) { - cyhal_utils_disconnect_and_free(obj->pin_ioVoltSel); - obj->pin_ioVoltSel = CYHAL_NC_PIN_VALUE; + release_pin_if_used(&obj->pin_data[i]); } - if (CYHAL_NC_PIN_VALUE != obj->pin_cardIfPwrEn) - { - cyhal_utils_disconnect_and_free(obj->pin_cardIfPwrEn); - obj->pin_cardIfPwrEn = CYHAL_NC_PIN_VALUE; - } +#if CARD_DETECT_PRESENT + release_pin_if_used(&obj->pin_cardDetect); +#endif - if (CYHAL_NC_PIN_VALUE != obj->pin_cardMechWriteProt) - { - cyhal_utils_disconnect_and_free(obj->pin_cardMechWriteProt); - obj->pin_cardMechWriteProt = CYHAL_NC_PIN_VALUE; - } +#if IO_VOLT_SEL_PRESENT + release_pin_if_used(&obj->pin_ioVoltSel); +#endif - if (CYHAL_NC_PIN_VALUE != obj->pin_ledCtrl) - { - cyhal_utils_disconnect_and_free(obj->pin_ledCtrl); - obj->pin_ledCtrl = CYHAL_NC_PIN_VALUE; - } +#if CARD_IF_PWR_EN_PRESENT + release_pin_if_used(&obj->pin_cardIfPwrEn); +#endif - if (CYHAL_NC_PIN_VALUE != obj->pin_cardEmmcReset) - { - cyhal_utils_disconnect_and_free(obj->pin_cardEmmcReset); - obj->pin_cardEmmcReset = CYHAL_NC_PIN_VALUE; - } +#if CARD_WRITE_PROT_PRESENT + release_pin_if_used(&obj->pin_cardMechWriteProt); +#endif - /* Free SDHC */ - if (CYHAL_RSC_INVALID != obj->resource.type) - { - cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - cyhal_hwmgr_free(&obj->resource); - } -} +#if LED_CTRL_PRESENT + release_pin_if_used(&obj->pin_ledCtrl); +#endif -cy_rslt_t cyhal_sdhc_configure(cyhal_sdhc_t *obj, const cyhal_sdhc_config_t *config) -{ - cy_rslt_t ret = CY_RSLT_SUCCESS; - cy_en_sd_host_status_t driverRet = CY_SD_HOST_SUCCESS; - cy_stc_sd_host_sd_card_config_t stcSdcardCfg; - cy_en_sd_host_card_capacity_t cardCapacity; - uint32_t rca = 0UL; - cy_en_sd_host_card_type_t cardType = CY_SD_HOST_UNUSABLE; - - bool configured = cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - if (!configured) - { - /** Initialize the SDIO/SD/eMMC card configuration structure */ - stcSdcardCfg.lowVoltageSignaling = config->lowVoltageSignaling; - stcSdcardCfg.busWidth = convert_buswidth(config->busWidth); - stcSdcardCfg.cardType = &cardType; - stcSdcardCfg.rca = &rca; - stcSdcardCfg.cardCapacity = &cardCapacity; - - /** Initialize the card */ - driverRet = Cy_SD_Host_InitCard(obj->base, &stcSdcardCfg, &obj->context); - ret = ((CY_SD_HOST_SUCCESS != driverRet) && (ret == CY_RSLT_SUCCESS)) - ? CY_RSLT_TYPE_ERROR - : cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - } - return ret; +#if CARD_EMMC_RESET_PRESENT + release_pin_if_used(&obj->pin_cardEmmcReset); +#endif } cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *data, size_t *length) @@ -547,7 +814,7 @@ cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *da dataConfig.autoCommand = (1UL == (uint32_t)*length) ? CY_SD_HOST_AUTO_CMD_NONE : CY_SD_HOST_AUTO_CMD_AUTO; - dataConfig.dataTimeout = CY_HAL_SDHC_TRANSFER_TIMEOUT; /* The timeout value for the transfer. */ + dataConfig.dataTimeout = SDHC_TRANSFER_TIMEOUT; /* The timeout value for the transfer. */ dataConfig.enReliableWrite = false; /* For EMMC cards enable reliable write. */ dataConfig.enableDma = true; @@ -557,12 +824,23 @@ cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *da { ret = CY_RSLT_TYPE_ERROR; } - - driverRet = Cy_SD_Host_PollTransferComplete(obj->base); - - if (CY_SD_HOST_SUCCESS != driverRet) + else { - ret = CY_RSLT_TYPE_ERROR; + driverRet = Cy_SD_Host_PollTransferComplete(obj->base, SDHC_RW_TIMEOUT_US); + + if (CY_SD_HOST_SUCCESS != driverRet) + { + ret = CY_RSLT_TYPE_ERROR; + } + } + + /* Enable SD Card interrupt because it was disabled in interrupt handler */ + if ((uint32_t) CYHAL_SDHC_CARD_INTERRUPT == ((uint32_t)CYHAL_SDHC_CARD_INTERRUPT & obj->irq_cause)) + { + uint32_t intrStsEn = Cy_SD_Host_GetNormalInterruptEnable(obj->base); + + /* This interrupt is disabled in interrupt handler so need to enable it here */ + Cy_SD_Host_SetNormalInterruptEnable(obj->base, (intrStsEn | CY_SD_HOST_CARD_INTERRUPT)); } return ret; @@ -580,7 +858,7 @@ cy_rslt_t cyhal_sdhc_write(const cyhal_sdhc_t *obj, uint32_t address, const uint dataConfig.autoCommand = (1UL == (uint32_t)*length) ? CY_SD_HOST_AUTO_CMD_NONE : CY_SD_HOST_AUTO_CMD_AUTO; - dataConfig.dataTimeout = CY_HAL_SDHC_TRANSFER_TIMEOUT; /* The timeout value for the transfer. */ + dataConfig.dataTimeout = SDHC_TRANSFER_TIMEOUT; /* The timeout value for the transfer. */ dataConfig.enReliableWrite = false; /* For EMMC cards enable reliable write. */ dataConfig.enableDma = true; @@ -590,12 +868,23 @@ cy_rslt_t cyhal_sdhc_write(const cyhal_sdhc_t *obj, uint32_t address, const uint { ret = CY_RSLT_TYPE_ERROR; } + else + { + driverRet = Cy_SD_Host_PollTransferComplete(obj->base, SDHC_RW_TIMEOUT_US); - driverRet = Cy_SD_Host_PollTransferComplete(obj->base); + if (CY_SD_HOST_SUCCESS != driverRet) + { + ret = CY_RSLT_TYPE_ERROR; + } + } - if (CY_SD_HOST_SUCCESS != driverRet) + /* Enable SD Card interrupt because it was disabled in interrupt handler */ + if ((uint32_t) CYHAL_SDHC_CARD_INTERRUPT == ((uint32_t)CYHAL_SDHC_CARD_INTERRUPT & obj->irq_cause)) { - ret = CY_RSLT_TYPE_ERROR; + uint32_t intrStsEn = Cy_SD_Host_GetNormalInterruptEnable(obj->base); + + /* This interrupt is disabled in interrupt handler so need to enable it here */ + Cy_SD_Host_SetNormalInterruptEnable(obj->base, (intrStsEn | CY_SD_HOST_CARD_INTERRUPT)); } return ret; @@ -606,7 +895,7 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t l cy_rslt_t ret = CY_RSLT_SUCCESS; cy_en_sd_host_status_t driverRet; cy_en_sd_host_erase_type_t eraseType = CY_SD_HOST_ERASE_ERASE; - uint32_t i = CY_HAL_SDHC_RETRY_TIME; + uint32_t i = SDHC_RETRY_TIMES; uint32_t cardStatus; if (obj->emmc) @@ -614,8 +903,7 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t l eraseType = CY_SD_HOST_ERASE_TRIM; } - driverRet = Cy_SD_Host_Erase(obj->base, startAddr, - (startAddr + length), eraseType, &obj->context); + driverRet = Cy_SD_Host_Erase(obj->base, startAddr, (startAddr + length), eraseType, &obj->context); if (CY_SD_HOST_SUCCESS != driverRet) { @@ -644,7 +932,7 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t l break; } - Cy_SysLib_DelayUs(CY_HAL_SDHC_FUJE_TIMEOUT_MS); /* The Fuje timeout for one block. */ + Cy_SysLib_DelayUs(SDHC_FUJE_TIMEOUT_MS); /* The Fuje timeout for one block. */ } if (CY_SD_HOST_SUCCESS != driverRet) @@ -654,7 +942,16 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t l } else { - Cy_SysLib_Delay(CY_HAL_SDHC_EMMC_TRIM_TIMEOUT); + Cy_SysLib_Delay(SDHC_EMMC_TRIM_DELAY_MS); + } + + /* Enable SD Card interrupt because it was disabled in interrupt handler */ + if ((uint32_t) CYHAL_SDHC_CARD_INTERRUPT == ((uint32_t)CYHAL_SDHC_CARD_INTERRUPT & obj->irq_cause)) + { + uint32_t intrStsEn = Cy_SD_Host_GetNormalInterruptEnable(obj->base); + + /* This interrupt is disabled in interrupt handler so need to enable it here */ + Cy_SD_Host_SetNormalInterruptEnable(obj->base, (intrStsEn | CY_SD_HOST_CARD_INTERRUPT)); } return ret; @@ -691,82 +988,93 @@ cy_rslt_t cyhal_sdhc_abort_async(const cyhal_sdhc_t *obj) ret = CY_RSLT_TYPE_ERROR; } - return ret; -} - -void cyhal_sdhc_register_irq(cyhal_sdhc_t *obj, cyhal_sdhc_irq_handler_t handler, void *handler_arg) -{ - IRQn_Type irqn = (obj->base == SDHC1) - ? sdhc_0_interrupt_general_IRQn - : sdhc_1_interrupt_general_IRQn; - - /* Only enable if it's not already enabled */ - if (NVIC_GetEnableIRQ(irqn) == 0) - { - cy_stc_sysint_t irqCfg = {irqn, SDHC_IRQ_PRIORITY}; - - Cy_SysInt_Init(&irqCfg, (cy_israddress)handler); - NVIC_EnableIRQ(irqn); - } - else - { - NVIC_SetPriority(irqn, SDHC_IRQ_PRIORITY); - } + return ret; +} + +void cyhal_sdhc_register_callback(cyhal_sdhc_t *obj, cyhal_sdhc_event_callback_t callback, void *callback_arg) +{ + uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); + obj->callback_data.callback = (cy_israddress) callback; + obj->callback_data.callback_arg = callback_arg; + cyhal_system_critical_section_exit(savedIntrStatus); } -void cyhal_sdhc_irq_enable(cyhal_sdhc_t *obj, cyhal_sdhc_irq_event_t event, bool enable) +void cyhal_sdhc_enable_event(cyhal_sdhc_t *obj, cyhal_sdhc_event_t event, uint8_t intrPriority, bool enable) { + const uint8_t eventCount = 12; + const uint32_t eventMap[12][2] = + { + { (uint32_t)CYHAL_SDHC_CMD_COMPLETE, (uint32_t)CY_SD_HOST_CMD_COMPLETE}, + { (uint32_t)CYHAL_SDHC_XFER_COMPLETE, (uint32_t)CY_SD_HOST_XFER_COMPLETE }, + { (uint32_t)CYHAL_SDHC_BGAP_EVENT, (uint32_t)CY_SD_HOST_BGAP }, + { (uint32_t)CYHAL_SDHC_DMA_INTERRUPT, (uint32_t)CY_SD_HOST_DMA_INTERRUPT }, + { (uint32_t)CYHAL_SDHC_BUF_WR_READY, (uint32_t)CY_SD_HOST_BUF_WR_READY }, + { (uint32_t)CYHAL_SDHC_BUF_RD_READY, (uint32_t)CY_SD_HOST_BUF_RD_READY }, + { (uint32_t)CYHAL_SDHC_CARD_INSERTION, (uint32_t)CY_SD_HOST_CARD_INSERTION }, + { (uint32_t)CYHAL_SDHC_CARD_REMOVAL, (uint32_t)CY_SD_HOST_CARD_REMOVAL }, + { (uint32_t)CYHAL_SDHC_CARD_INTERRUPT, (uint32_t)CY_SD_HOST_CARD_INTERRUPT }, + { (uint32_t)CYHAL_SDHC_FX_EVENT, (uint32_t)CY_SD_HOST_FX_EVENT }, + { (uint32_t)CYHAL_SDHC_CQE_EVENT, (uint32_t)CY_SD_HOST_CQE_EVENT }, + { (uint32_t)CYHAL_SDHC_ERR_INTERRUPT, (uint32_t)CY_SD_HOST_ERR_INTERRUPT }, + }; + uint32_t interruptMask; uint32_t interruptEnable; interruptEnable = Cy_SD_Host_GetNormalInterruptEnable(obj->base); interruptMask = Cy_SD_Host_GetNormalInterruptMask(obj->base); + IRQn_Type irqn = CYHAL_SDHC_IRQ_N[obj->resource.block_num]; + NVIC_SetPriority(irqn, intrPriority); + if(enable == true) { + obj->irq_cause |= event; + /* Enable specific interrupt */ - if(event < CYHAL_SDHC_ERR_INTERRUPT) + if((uint32_t) event < (uint32_t) CYHAL_SDHC_ALL_INTERRUPTS) { - interruptEnable |= (1 << event); - interruptMask |= (1 << event); - } - /* Enable error interrupts */ - else if (event == CYHAL_SDHC_ERR_INTERRUPT) - { - Cy_SD_Host_SetErrorInterruptEnable(obj->base, ENABLE_ALL_INTERRUPT_ENABLE); - Cy_SD_Host_SetErrorInterruptMask(obj->base, ENABLE_ALL_INTERRUPT_MASK); + for (int i = 0; i < eventCount; i++) + { + const uint32_t *map_entry = eventMap[i]; + if ((map_entry[0] & obj->irq_cause) > 0) + { + interruptEnable |= map_entry[1]; + interruptMask |= map_entry[1]; + } + } } /* Enable all interrupts */ - else if (event == CYHAL_SDHC_ALL_INTERRUPTS) + else { - interruptEnable = ENABLE_ALL_INTERRUPT_ENABLE; - interruptMask = ENABLE_ALL_INTERRUPT_MASK; - Cy_SD_Host_SetErrorInterruptEnable(obj->base, ENABLE_ALL_INTERRUPT_ENABLE); - Cy_SD_Host_SetErrorInterruptMask(obj->base, ENABLE_ALL_INTERRUPT_MASK); + interruptEnable = SDIO_ALL_INTERRUPTS_ENABLE_MASK; + interruptMask = SDIO_SET_ALL_INTERRUPTS_MASK; + obj->irq_cause = (uint32_t) CYHAL_SDHC_ALL_INTERRUPTS; } } /* Disable interrupt */ else { - /* Disable specific interrupt */ - if(event < CYHAL_SDHC_ERR_INTERRUPT) - { - interruptEnable &= ~(1 << event); - interruptMask &= ~(1 << event); - } - /* Disable error interrupts */ - else if (event == CYHAL_SDHC_ERR_INTERRUPT) + obj->irq_cause &= ~event; + + if((uint32_t) event < (uint32_t) CYHAL_SDHC_ALL_INTERRUPTS) { - Cy_SD_Host_SetErrorInterruptEnable(obj->base, DISABLE_ALL_INTERRUPT_ENABLE); - Cy_SD_Host_SetErrorInterruptMask(obj->base, DISABLE_ALL_INTERRUPT_MASK); + for (int i = 0; i < eventCount; i++) + { + const uint32_t *map_entry = eventMap[i]; + if ((map_entry[0] & obj->irq_cause) > 0) + { + interruptEnable &= ~map_entry[1]; + interruptMask &= ~map_entry[1]; + } + } } /* Disable all interrupts */ - else if (event == CYHAL_SDHC_ALL_INTERRUPTS) + else { - interruptEnable = DISABLE_ALL_INTERRUPT_ENABLE; - interruptMask = DISABLE_ALL_INTERRUPT_MASK; - Cy_SD_Host_SetErrorInterruptEnable(obj->base, DISABLE_ALL_INTERRUPT_ENABLE); - Cy_SD_Host_SetErrorInterruptMask(obj->base, DISABLE_ALL_INTERRUPT_MASK); + interruptEnable = SDIO_CLEAR_ALL_INTERRUPTS_ENABLE_MASK; + interruptMask = SDIO_CLEAR_ALL_INTERRUPTS_MASK; + obj->irq_cause = 0u; } } @@ -774,179 +1082,133 @@ void cyhal_sdhc_irq_enable(cyhal_sdhc_t *obj, cyhal_sdhc_irq_event_t event, bool Cy_SD_Host_SetNormalInterruptEnable(obj->base, interruptEnable); } -cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3) +static void cyhal_sdio_irq_handler() { - cy_stc_sd_host_init_config_t hostConfig; - cy_rslt_t result; - cy_stc_sd_host_context_t context; - cyhal_resource_inst_t pin_rsc; - - CY_ASSERT(NULL != obj); - - obj->resource.type = CYHAL_RSC_INVALID; - obj->pin_cmd = SDIO_PINS_NC; - obj->pin_clk = SDIO_PINS_NC; - obj->pin_data0 = SDIO_PINS_NC; - obj->pin_data1 = SDIO_PINS_NC; - obj->pin_data2 = SDIO_PINS_NC; - obj->pin_data3 = SDIO_PINS_NC; + IRQn_Type irqn = CYHAL_GET_CURRENT_IRQN(); + uint8_t block = cyhal_sd_get_block_from_irqn(irqn); + SDHC_Type *blockAddr = CYHAL_SDHC_BASE_ADDRESSES[block]; + cyhal_sdio_t *obj = (cyhal_sdio_t*) cyhal_sd_config_structs[block]; - /* Get pins from package */ - const cyhal_resource_pin_mapping_t *cmd_map = CY_UTILS_GET_RESOURCE(cmd, cyhal_pin_map_sdhc_card_cmd); - - const cyhal_resource_pin_mapping_t *clk_map = CY_UTILS_GET_RESOURCE(clk, cyhal_pin_map_sdhc_clk_card); - - const cyhal_resource_pin_mapping_t *data0_map = CY_UTILS_GET_RESOURCE(data0, cyhal_pin_map_sdhc_card_dat_3to0); - const cyhal_resource_pin_mapping_t *data1_map = CY_UTILS_GET_RESOURCE(data1, cyhal_pin_map_sdhc_card_dat_3to0); - const cyhal_resource_pin_mapping_t *data2_map = CY_UTILS_GET_RESOURCE(data2, cyhal_pin_map_sdhc_card_dat_3to0); - const cyhal_resource_pin_mapping_t *data3_map = CY_UTILS_GET_RESOURCE(data3, cyhal_pin_map_sdhc_card_dat_3to0); + uint32_t interruptStatus = Cy_SD_Host_GetNormalInterruptStatus(blockAddr); + uint32_t userInterruptStatus = interruptStatus & obj->irq_cause; - if ((NULL == cmd_map) || (NULL == clk_map) || (NULL == data0_map) || (NULL == data1_map) || (NULL == data2_map) || (NULL == data3_map)) + if (obj->callback_data.callback != NULL && userInterruptStatus > 0) { - return CYHAL_SDIO_RSLT_ERR_BAD_PARAM; + cyhal_sdio_event_callback_t callback = (cyhal_sdio_event_callback_t) obj->callback_data.callback; + /* Call registered callbacks here */ + (void)(callback)(obj->callback_data.callback_arg, (cyhal_sdio_irq_event_t) userInterruptStatus); } - /* Reserve the CMD pin */ - pin_rsc = cyhal_utils_get_gpio_resource(cmd); - result = cyhal_hwmgr_reserve(&pin_rsc); - if (result == CY_RSLT_SUCCESS) - { - obj->pin_cmd = cmd; - } + /* Clear only handled events */ + Cy_SD_Host_ClearNormalInterruptStatus(blockAddr, userInterruptStatus); - /* Reserve the CLK pin */ - if (result == CY_RSLT_SUCCESS) - { - pin_rsc = cyhal_utils_get_gpio_resource(clk); - result = cyhal_hwmgr_reserve(&pin_rsc); - if (result == CY_RSLT_SUCCESS) - { - obj->pin_clk = clk; - } - } - - /* Reserve the DATA0 pin */ - if (result == CY_RSLT_SUCCESS) - { - pin_rsc = cyhal_utils_get_gpio_resource(data0); - result = cyhal_hwmgr_reserve(&pin_rsc); - if (result == CY_RSLT_SUCCESS) - { - obj->pin_data0 = data0; - } - } - - /* Reserve the DATA1 pin */ - if (result == CY_RSLT_SUCCESS) - { - pin_rsc = cyhal_utils_get_gpio_resource(data1); - result = cyhal_hwmgr_reserve(&pin_rsc); - if (result == CY_RSLT_SUCCESS) - { - obj->pin_data1 = data1; - } - } - - /* Reserve the DATA2 pin */ - if (result == CY_RSLT_SUCCESS) + /* To clear SD Card interrupt need to disable SD Card Interrupt Enable bit. + * The SD Card interrupt is enabled in the bulk transfer function later on + * the next data transfer. + */ + if (0U != (obj->irq_cause & CY_SD_HOST_CARD_INTERRUPT)) { - pin_rsc = cyhal_utils_get_gpio_resource(data2); - result = cyhal_hwmgr_reserve(&pin_rsc); - if (result == CY_RSLT_SUCCESS) + if (0U != (interruptStatus & CY_SD_HOST_CARD_INTERRUPT)) { - obj->pin_data2 = data2; - } - } + uint32_t interruptMask = Cy_SD_Host_GetNormalInterruptEnable(blockAddr); + interruptMask &= (uint32_t) ~CY_SD_HOST_CARD_INTERRUPT; - /* Reserve the DATA3 pin */ - if (result == CY_RSLT_SUCCESS) - { - pin_rsc = cyhal_utils_get_gpio_resource(data3); - result = cyhal_hwmgr_reserve(&pin_rsc); - if (result == CY_RSLT_SUCCESS) - { - obj->pin_data3 = data3; + /* Disable SD Card interrupt */ + Cy_SD_Host_SetNormalInterruptEnable(blockAddr, interruptMask); } } +} - if (result == CY_RSLT_SUCCESS) - { - result = cyhal_connect_pin(cmd_map); - } - - if (result == CY_RSLT_SUCCESS) +cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3) +{ + cy_stc_sd_host_init_config_t hostConfig; + cy_rslt_t result; + cy_stc_sd_host_context_t context; + + CY_ASSERT(NULL != obj); + + obj->resource.type = CYHAL_RSC_INVALID; + obj->base = NULL; + + result = setup_pin( + cmd, cyhal_pin_map_sdhc_card_cmd, COUNT(cyhal_pin_map_sdhc_card_cmd), &(obj->pin_cmd)); + + if (CY_RSLT_SUCCESS == result) { - result = cyhal_connect_pin(clk_map); + result = setup_pin( + clk, cyhal_pin_map_sdhc_clk_card, COUNT(cyhal_pin_map_sdhc_clk_card), &(obj->pin_clk)); } - - if (result == CY_RSLT_SUCCESS) + + if (CY_RSLT_SUCCESS == result) { - result = cyhal_connect_pin(data0_map); + result = setup_pin( + data0, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data0)); } - if (result == CY_RSLT_SUCCESS) + if (CY_RSLT_SUCCESS == result) { - result = cyhal_connect_pin(data1_map); + result = setup_pin( + data1, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data1)); } - if (result == CY_RSLT_SUCCESS) + if (CY_RSLT_SUCCESS == result) { - result = cyhal_connect_pin(data2_map); + result = setup_pin( + data2, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data2)); } - if (result == CY_RSLT_SUCCESS) + if (CY_RSLT_SUCCESS == result) { - result = cyhal_connect_pin(data3_map); + result = setup_pin( + data3, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data3)); } - + if (result == CY_RSLT_SUCCESS) { + const cyhal_resource_pin_mapping_t *cmd_map = CY_UTILS_GET_RESOURCE(cmd, cyhal_pin_map_sdhc_card_cmd); cyhal_resource_inst_t sdhc = *cmd_map->inst; result = cyhal_hwmgr_reserve(&sdhc); if (result == CY_RSLT_SUCCESS) { obj->resource = sdhc; - bool configured = cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - if (result == CY_RSLT_SUCCESS && !configured) + + if (result == CY_RSLT_SUCCESS) { - /* Set HF CL to 100MHz */ - /* TODO - uncomment once the function is implemented - uint8_t clk_hf = 0xff; - if (obj->resource.block_num == 0) - { - clk_hf = 4; - } - else if (obj->resource.block_num == 1) - { - clk_hf = 2; - } - else - { - // Do nothing as we have incorrect SDHC instance - } + obj->base = CYHAL_SDHC_BASE_ADDRESSES[obj->resource.block_num]; - if (clk_hf != 0xff) - { - result = cyhal_system_clock_frequency(clk_hf, SDIO_CLK_HF_HZ); - } - */ + /* Enable the SDHC block */ + Cy_SD_Host_Enable(obj->base); - if (result == CY_RSLT_SUCCESS) - { - obj->base = CY_SDHC_BASE_ADDRESSES[obj->resource.block_num]; + hostConfig.dmaType = CY_SD_HOST_DMA_SDMA; + hostConfig.emmc = false; + hostConfig.enableLedControl = false; + context.cardType = CY_SD_HOST_SDIO; - /* Enable the SDHC block */ - Cy_SD_Host_Enable(obj->base); + /* Configure SD Host to operate */ + (void) Cy_SD_Host_Init(obj->base, &hostConfig, &context); - hostConfig.dmaType = CY_SD_HOST_DMA_SDMA; - hostConfig.emmc = false; - hostConfig.enableLedControl = false; - context.cardType = CY_SD_HOST_SDIO; + /* Register SDIO Deep Sleep Callback */ + obj->pm_params.base = obj->base; + obj->pm_params.context = obj; - /* Configure SD Host to operate */ - (void) Cy_SD_Host_Init(obj->base, &hostConfig, &context); + obj->pm_callback.callback = &cyhal_sdio_syspm_callback; + obj->pm_callback.type = CY_SYSPM_DEEPSLEEP; + obj->pm_callback.skipMode = 0; + obj->pm_callback.callbackParams = &(obj->pm_params); + obj->pm_callback.prevItm = NULL; + obj->pm_callback.nextItm = NULL; + if (result == CY_RSLT_SUCCESS) + { + if (!Cy_SysPm_RegisterCallback(&(obj->pm_callback))) + { + result = CY_RSLT_TYPE_ERROR; + } + } + + if (result == CY_RSLT_SUCCESS) + { /* Only enable the SDMA interrupt */ Cy_SD_Host_SetNormalInterruptMask(obj->base, CY_SD_HOST_DMA_INTERRUPT); @@ -954,24 +1216,33 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, Cy_SD_Host_SetErrorInterruptMask(obj->base, 0UL); /* Clear all interrupts */ - Cy_SD_Host_ClearErrorInterruptStatus(obj->base, 0xffff); - Cy_SD_Host_ClearNormalInterruptStatus(obj->base, 0xffff); + Cy_SD_Host_ClearErrorInterruptStatus(obj->base, SDIO_SET_ALL_INTERRUPTS_MASK); + Cy_SD_Host_ClearNormalInterruptStatus(obj->base, SDIO_SET_ALL_INTERRUPTS_MASK); + + obj->irq_cause = 0UL; + obj->events = 0UL; + + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + cyhal_sd_config_structs[obj->resource.block_num] = obj; + + IRQn_Type irqn = CYHAL_SDHC_IRQ_N[obj->resource.block_num]; + cy_stc_sysint_t irqCfg = { irqn, CYHAL_ISR_PRIORITY_DEFAULT }; + Cy_SysInt_Init(&irqCfg, cyhal_sdio_irq_handler); + NVIC_EnableIRQ(irqn); (void)Cy_SD_Host_SetHostBusWidth(obj->base, CY_SD_HOST_BUS_WIDTH_4_BIT); /* Change the host SD clock to 400 kHz */ - (void)Cy_SD_Host_SdCardChangeClock(obj->base, CY_SD_HOST_CLK_400K); - - result = - cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); + (void) Cy_SD_Host_SdCardChangeClock(obj->base, obj->resource.block_num, SDIO_HOST_CLK_400K); - obj->frequencyhal_hz = CY_SD_HOST_CLK_400K; - obj->block_size = SDHC_SDIO_64B_BLOCK; + obj->frequencyhal_hz = SDIO_HOST_CLK_400K; + obj->block_size = SDIO_64B_BLOCK; } } } } - + if (result != CY_RSLT_SUCCESS) { cyhal_sdio_free(obj); @@ -982,79 +1253,53 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, void cyhal_sdio_free(cyhal_sdio_t *obj) { - cy_rslt_t result; CY_ASSERT(NULL != obj); + if ((NULL != obj->base) && (obj->resource.type != CYHAL_RSC_INVALID)) { + IRQn_Type irqn = CYHAL_SDHC_IRQ_N[obj->resource.block_num]; + NVIC_DisableIRQ(irqn); + Cy_SD_Host_DeInit(obj->base); - result = cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - CY_ASSERT(CY_RSLT_SUCCESS == result); - cyhal_hwmgr_free(&(obj->resource)); obj->base = NULL; obj->resource.type = CYHAL_RSC_INVALID; - } - - /* Free pins */ - if (obj->pin_clk != SDIO_PINS_NC) - { - cyhal_utils_disconnect_and_free(obj->pin_clk); - obj->pin_clk = SDIO_PINS_NC; - } - - if (obj->pin_cmd != SDIO_PINS_NC) - { - cyhal_utils_disconnect_and_free(obj->pin_cmd); - obj->pin_cmd = SDIO_PINS_NC; - } - if (obj->pin_data0 != SDIO_PINS_NC) - { - cyhal_utils_disconnect_and_free(obj->pin_data0); - obj->pin_data0 = SDIO_PINS_NC; - } - - if (obj->pin_data1 != SDIO_PINS_NC) - { - cyhal_utils_disconnect_and_free(obj->pin_data1); - obj->pin_data1 = SDIO_PINS_NC; - } - - if (obj->pin_data2 != SDIO_PINS_NC) - { - cyhal_utils_disconnect_and_free(obj->pin_data2); - obj->pin_data2 = SDIO_PINS_NC; + /* Unregister SDIO Deep Sleep Callback */ + (void)Cy_SysPm_UnregisterCallback(&(obj->pm_callback)); } - if (obj->pin_data3 != SDIO_PINS_NC) - { - cyhal_utils_disconnect_and_free(obj->pin_data3); - obj->pin_data3 = SDIO_PINS_NC; - } + /* Free pins */ + release_pin_if_used(&obj->pin_clk); + release_pin_if_used(&obj->pin_cmd); + release_pin_if_used(&obj->pin_data0); + release_pin_if_used(&obj->pin_data1); + release_pin_if_used(&obj->pin_data2); + release_pin_if_used(&obj->pin_data3); } cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config) { cy_en_sd_host_status_t result = CY_SD_HOST_ERROR_TIMEOUT; - + if ((NULL == obj) && (config == NULL)) { return CYHAL_SDIO_RSLT_ERR_BAD_PARAM; } - if (config->frequencyhal_hz != 0) + if (config->frequencyhal_hz != 0U) { - result = Cy_SD_Host_SdCardChangeClock(obj->base, config->frequencyhal_hz); + result = Cy_SD_Host_SdCardChangeClock(obj->base, obj->resource.block_num, config->frequencyhal_hz); obj->frequencyhal_hz = config->frequencyhal_hz; } - if (config->block_size != 0) + if (config->block_size != 0U) { - /* No need to change anything in HW, because it will be overwritten + /* No need to change anything in HW, because it will be overwritten * in cyhal_sdio_bulk_transfer()/cyhal_sdio_transfer_async() functions. - * The HW block size will taken based on obj->block_size, which is + * The HW block size will taken based on obj->block_size, which is * updated here. */ obj->block_size = config->block_size; @@ -1064,7 +1309,7 @@ cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config } /******************************************************************************* -* Note that during this function execution the CY_SD_HOST_CMD_COMPLETE +* Note that during this function execution the CY_SD_HOST_CMD_COMPLETE * interrupt is disabled. *******************************************************************************/ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, \ @@ -1078,7 +1323,7 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio cy_rslt_t ret = CY_RSLT_SUCCESS; cy_en_sd_host_status_t result = CY_SD_HOST_ERROR_TIMEOUT; cy_stc_sd_host_cmd_config_t cmd; - uint32_t retry = 50UL; + uint32_t retry = SDIO_TRANSF_TRIES; uint32_t regIntrSts = Cy_SD_Host_GetNormalInterruptMask(obj->base); /* Clear out the response */ @@ -1102,11 +1347,11 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio * requires more time, but this short version is working quite well and * successfully clears out the error state. */ - Cy_SD_Host_ClearErrorInterruptStatus(obj->base, 0xffffU); + Cy_SD_Host_ClearErrorInterruptStatus(obj->base, SDIO_SET_ALL_INTERRUPTS_MASK); Cy_SD_Host_SoftwareReset(obj->base, CY_SD_HOST_RESET_CMD_LINE); Cy_SD_Host_SoftwareReset(obj->base, CY_SD_HOST_RESET_DATALINE); Cy_SysLib_DelayUs(1); - obj->base->CORE.SW_RST_R = 0x00; + obj->base->CORE.SW_RST_R = 0U; } cmd.commandIndex = (uint32_t)command; @@ -1119,7 +1364,7 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio cmd.cmdType = CY_SD_HOST_CMD_NORMAL; result = Cy_SD_Host_SendCommand(obj->base, &cmd); - + if (CY_SD_HOST_SUCCESS == result) { result = Cy_SD_Host_PollCmdComplete(obj->base); @@ -1141,25 +1386,29 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio /******************************************************************************* -* Note that during this function execution the CY_SD_HOST_CMD_COMPLETE and -* CY_SD_HOST_CMD_COMPLETE interrupts are disabled. +* \note +* During this function execution the CYHAL_SDIO_CMD_COMPLETE and +* CYHAL_SDIO_XFER_COMPLETE events are disabled. +* The CYHAL_SDIO_CMD_COMPLETE and CYHAL_SDIO_XFER_COMPLETE events are enabled +* after the asynchronous transfer is complete and in the condition they were +* enabled in before the transfer operation started. *******************************************************************************/ -cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, - uint32_t argument, const uint32_t* data, +cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, + uint32_t argument, const uint32_t* data, uint16_t length, uint32_t* response) { if (NULL == obj) { return CYHAL_SDIO_RSLT_ERR_BAD_PARAM; } - + cy_rslt_t ret = CY_RSLT_SUCCESS; - uint32_t retry = CY_SDIO_BULK_TRANSF_TRIES; + uint32_t retry = SDIO_TRANSF_TRIES; cy_stc_sd_host_cmd_config_t cmd; cy_stc_sd_host_data_config_t dat; cy_en_sd_host_status_t result = CY_SD_HOST_ERROR_TIMEOUT; - uint32_t regIntrSts = Cy_SD_Host_GetNormalInterruptMask(obj->base);; - + uint32_t regIntrSts = Cy_SD_Host_GetNormalInterruptMask(obj->base); + /* Initialize data constants*/ dat.autoCommand = CY_SD_HOST_AUTO_CMD_NONE; dat.dataTimeout = 0x0dUL; @@ -1178,32 +1427,32 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction while ((CY_SD_HOST_SUCCESS != result) && (retry-- > 0UL)) { /* Add SDIO Error Handling - * SDIO write timeout is expected when doing first write to register + * SDIO write timeout is expected when doing first write to register * after KSO bit disable (as it goes to AOS core). - * This timeout, however, triggers an error state in the hardware. + * This timeout, however, triggers an error state in the hardware. * So, check for the error and then recover from it - * as needed via reset issuance. This is the only time known that + * as needed via reset issuance. This is the only time known that * a write timeout occurs. */ /* First clear out the command complete and transfer complete statuses */ Cy_SD_Host_ClearNormalInterruptStatus(obj->base, (CY_SD_HOST_XFER_COMPLETE | CY_SD_HOST_CMD_COMPLETE)); - /* Check if an error occurred on any previous transactions or reset - * after the first unsuccessful bulk transfer try + /* Check if an error occurred on any previous transactions or reset + * after the first unsuccessful bulk transfer try */ if( (Cy_SD_Host_GetNormalInterruptStatus(obj->base) & CY_SD_HOST_ERR_INTERRUPT) || - (retry < CY_SDIO_BULK_TRANSF_TRIES)) + (retry < SDIO_TRANSF_TRIES)) { /* Reset the block if there was an error. Note a full reset usually - * requires more time, but this short version is working quite well + * requires more time, but this short version is working quite well * and successfully clears out the error state. */ - Cy_SD_Host_ClearErrorInterruptStatus(obj->base, 0xffffU); + Cy_SD_Host_ClearErrorInterruptStatus(obj->base, SDIO_SET_ALL_INTERRUPTS_MASK); Cy_SD_Host_SoftwareReset(obj->base, CY_SD_HOST_RESET_CMD_LINE); Cy_SD_Host_SoftwareReset(obj->base, CY_SD_HOST_RESET_DATALINE); Cy_SysLib_DelayUs(1); - obj->base->CORE.SW_RST_R = 0x00; + obj->base->CORE.SW_RST_R = 0U; } /* Prepare the data transfer register */ @@ -1217,7 +1466,6 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction cmd.cmdType = CY_SD_HOST_CMD_NORMAL; dat.data = (uint32_t*)data; - /* TODO - BSP-542 */ /* Block mode */ if (length >= obj->block_size) { @@ -1232,7 +1480,7 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction } /* Disable XFER Done interrupt */ - Cy_SD_Host_SetNormalInterruptMask(obj->base, (regIntrSts & + Cy_SD_Host_SetNormalInterruptMask(obj->base, (regIntrSts & (uint16_t)~(CY_SD_HOST_XFER_COMPLETE | CY_SD_HOST_CMD_COMPLETE))); (void)Cy_SD_Host_InitDataTransfer(obj->base, &dat); @@ -1244,18 +1492,16 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction if ( CY_SD_HOST_SUCCESS == result ) { - result = Cy_SD_Host_PollTransferComplete(obj->base); + result = Cy_SD_Host_PollTransferComplete(obj->base, SDIO_RW_TIMEOUT_US); } } - - Cy_SysLib_DelayUs(CY_HAL_SDHC_OPER_CMPLT_US); } if (response != NULL ) { (void)Cy_SD_Host_GetResponse(obj->base, response, false); } - + /* Restore interrupts after transition */ Cy_SD_Host_SetNormalInterruptMask(obj->base, regIntrSts); @@ -1267,7 +1513,7 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction if (0u != (CY_SD_HOST_CARD_INTERRUPT & obj->irq_cause)) { uint32_t intrStsEn = Cy_SD_Host_GetNormalInterruptEnable(obj->base); - + /* This interrupt is disabled in interrupt handler so need to enable it here */ Cy_SD_Host_SetNormalInterruptEnable(obj->base, (intrStsEn | CY_SD_HOST_CARD_INTERRUPT)); } @@ -1278,17 +1524,25 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction /******************************************************************************* * -* Asynchronous transfer is implemented on the CY_SD_HOST_CMD_COMPLETE and +* The asynchronous transfer is implemented on the CY_SD_HOST_CMD_COMPLETE and +* CY_SD_HOST_CMD_COMPLETE interrupts. +* The function sets up data and disables the CY_SD_HOST_CMD_COMPLETE and * CY_SD_HOST_CMD_COMPLETE interrupts. -* Function setup data and enables CY_SD_HOST_CMD_COMPLETE and -* CY_SD_HOST_CMD_COMPLETE. After this the cyhal_sdio_is_busy() function returns -* true result to show asynchronous transfer is in progress. -* Once transfer is complete the interrupt is fired. -* After servicing the interrupt the cyhal_sdio_is_busy() function returns -* false to indicate than asynchronous transfer is complete. +* After exiting this function the CYHAL_SDIO_CMD_COMPLETE and +* CYHAL_SDIO_XFER_COMPLETE events are not asserted. +* +* To complete the asynchronous transfer, call cyhal_sdio_is_busy() +* until it returns false. +* The CYHAL_SDIO_CMD_COMPLETE and CYHAL_SDIO_XFER_COMPLETE events are enabled +* after the asynchronous transfer is complete and in the condition they were +* enabled in before the transfer operation started. +* +* \warning +* It is prohibited to enable CYHAL_SDIO_CMD_COMPLETE and +* CYHAL_SDIO_XFER_COMPLETE events during the asynchronous transfer operation. * *******************************************************************************/ -cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, +cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length) { if (NULL == obj) @@ -1297,7 +1551,7 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio } cy_rslt_t ret = CY_RSLT_SUCCESS; - uint32_t retry = CY_SDIO_BULK_TRANSF_TRIES; + uint32_t retry = SDIO_TRANSF_TRIES; cy_stc_sd_host_cmd_config_t cmd; cy_stc_sd_host_data_config_t dat; cy_en_sd_host_status_t result = CY_SD_HOST_ERROR_TIMEOUT; @@ -1314,18 +1568,18 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio while ((CY_SD_HOST_SUCCESS != result) && (retry-- > 0UL)) { /* Check if an error occurred on any previous transactions or reset after the first unsuccessful bulk transfer try */ - if( (Cy_SD_Host_GetNormalInterruptStatus(obj->base) & CY_SD_HOST_ERR_INTERRUPT) || - (retry < CY_SDIO_BULK_TRANSF_TRIES)) + if( (Cy_SD_Host_GetNormalInterruptStatus(obj->base) & CY_SD_HOST_ERR_INTERRUPT) || + (retry < SDIO_TRANSF_TRIES)) { /* Reset the block if there was an error. Note a full reset usually * requires more time, but this short version is working quite well and * successfully clears out the error state. */ - Cy_SD_Host_ClearErrorInterruptStatus(obj->base, 0xffffU); + Cy_SD_Host_ClearErrorInterruptStatus(obj->base, SDIO_SET_ALL_INTERRUPTS_MASK); Cy_SD_Host_SoftwareReset(obj->base, CY_SD_HOST_RESET_CMD_LINE); Cy_SD_Host_SoftwareReset(obj->base, CY_SD_HOST_RESET_DATALINE); - Cy_SysLib_DelayUs(1); - obj->base->CORE.SW_RST_R = 0x00; + Cy_SysLib_DelayUs(1U); + obj->base->CORE.SW_RST_R = 0U; } /* Prepare the data transfer register */ @@ -1354,14 +1608,13 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio dat.numberOfBlock = 1UL; } - /* Enable XFER Done interrupt */ - Cy_SD_Host_SetNormalInterruptMask(obj->base, (intMaskReg | (uint16_t) CY_SD_HOST_XFER_COMPLETE)); - Cy_SD_Host_SetNormalInterruptEnable(obj->base, (intEnableReg | (uint16_t) CY_SD_HOST_XFER_COMPLETE)); + /* Disable XFER Done interrupt */ + Cy_SD_Host_SetNormalInterruptMask(obj->base, (intMaskReg & + (uint16_t)~(CY_SD_HOST_XFER_COMPLETE | CY_SD_HOST_CMD_COMPLETE))); (void)Cy_SD_Host_InitDataTransfer(obj->base, &dat); result = Cy_SD_Host_SendCommand(obj->base, &cmd); - Cy_SysLib_DelayUs(CY_HAL_SDHC_OPER_CMPLT_US); } if (CY_SD_HOST_SUCCESS != result) @@ -1374,7 +1627,7 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio isTransferInProcess = true; } - if (0u != (CY_SD_HOST_CARD_INTERRUPT & obj->irq_cause)) + if (0U != (CY_SD_HOST_CARD_INTERRUPT & obj->irq_cause)) { /* This interrupt is disabled in interrupt handler so need to enable it here */ Cy_SD_Host_SetNormalInterruptEnable(obj->base, (intEnableReg | CY_SD_HOST_CARD_INTERRUPT)); @@ -1385,142 +1638,122 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj) { - return isTransferInProcess; -} - - -cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj) -{ - cy_rslt_t ret = CY_RSLT_SUCCESS; - - /* To abort transition reset dat and cmd lines (software reset) */ - Cy_SD_Host_SoftwareReset(obj->base, CY_SD_HOST_RESET_CMD_LINE); - Cy_SD_Host_SoftwareReset(obj->base, CY_SD_HOST_RESET_DATALINE); - Cy_SysLib_DelayUs(1); - obj->base->CORE.SW_RST_R = 0x00; + static bool isCmdComplete = false; - return ret; -} + if (isTransferInProcess) + { + cy_rslt_t result = CY_RSLT_TYPE_ERROR; -/* Callback array for SDHC SDIO interrupts */ -static cyhal_sdio_irq_handler_t callbacks[CY_IP_MXSDHC_INSTANCES]; -static void *callback_args[CY_IP_MXSDHC_INSTANCES]; -static cyhal_sdio_t *cy_sdio_config_structs[CY_IP_MXSDHC_INSTANCES]; + if (!isCmdComplete) + { + result = Cy_SD_Host_PollCmdComplete(obj->base); + if (CY_SD_HOST_SUCCESS == result) + { + isCmdComplete = true; + } + } -/******************************************************************************* -* Dispatcher Interrupt Service Routine -*******************************************************************************/ + if (isCmdComplete) + { + result = Cy_SD_Host_PollTransferComplete(obj->base, SDIO_RW_TIMEOUT_US); -static void isr_sdio_handler(uint8_t index, SDHC_Type *blockAddr) -{ - uint32_t interruptStatus = Cy_SD_Host_GetNormalInterruptStatus(blockAddr); - - if (callbacks[index] != NULL) - { - /* Call registered callbacks here */ - (void)(callbacks[index])(callback_args[index], (cyhal_sdio_irq_event_t) cy_sdio_config_structs[index]->irq_cause); - } + if (CY_SD_HOST_SUCCESS == result) + { + isTransferInProcess = false; + isCmdComplete = false; - Cy_SD_Host_ClearNormalInterruptStatus(blockAddr, cy_sdio_config_structs[index]->irq_cause); + /* Restore XFER Done interrupt if it was previously enabled */ + if (0U != ((CY_SD_HOST_XFER_COMPLETE | CY_SD_HOST_CMD_COMPLETE) & obj->irq_cause)) + { + uint32_t intrStatus = Cy_SD_Host_GetNormalInterruptMask(obj->base); - /* To clear SD Card interrupt need to disable SD Card Interrupt Enable mask. - * The SD Card interrupt is enabled in the bulk transfer function later on - * the next data transfer. - */ - if (0u != (cy_sdio_config_structs[index]->irq_cause & CY_SD_HOST_CARD_INTERRUPT)) - { - if (0u != (interruptStatus & CY_SD_HOST_CARD_INTERRUPT)) - { - uint32_t interruptMask = Cy_SD_Host_GetNormalInterruptEnable(blockAddr); - interruptMask &= (uint32_t) ~CY_SD_HOST_CARD_INTERRUPT; + if (0U != (CY_SD_HOST_XFER_COMPLETE & obj->irq_cause)) + { + Cy_SD_Host_SetNormalInterruptMask(obj->base, (intrStatus | CY_SD_HOST_XFER_COMPLETE)); + } - /* Disable SD Card interrupt */ - Cy_SD_Host_SetNormalInterruptEnable(blockAddr, interruptMask); + if (0U != (CY_SD_HOST_CMD_COMPLETE & obj->irq_cause)) + { + Cy_SD_Host_SetNormalInterruptMask(obj->base, (intrStatus | CY_SD_HOST_CMD_COMPLETE)); + } + } + } } } - - if (0u != (interruptStatus & CY_SD_HOST_XFER_COMPLETE) && isTransferInProcess) - { - isTransferInProcess = false; - } -} + return isTransferInProcess; +} -/******************************************************************************* -* (Internal) Interrupt Service Routines -*******************************************************************************/ -static void isr_sdio_0_handler(void) __attribute__((unused)); -static void isr_sdio_1_handler(void) __attribute__((unused)); +cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj) +{ + cy_rslt_t ret = CY_RSLT_SUCCESS; -typedef void (*interrupt_dispatcher)(void); + /* To abort transition reset dat and cmd lines (software reset) */ + Cy_SD_Host_SoftwareReset(obj->base, CY_SD_HOST_RESET_CMD_LINE); + Cy_SD_Host_SoftwareReset(obj->base, CY_SD_HOST_RESET_DATALINE); + Cy_SysLib_DelayUs(1U); + obj->base->CORE.SW_RST_R = 0U; -static const interrupt_dispatcher interrupts_dispatcher_table[CY_IP_MXSDHC_INSTANCES] = -{ -#if (CY_IP_MXSDHC_INSTANCES > 0) - isr_sdio_0_handler, -#endif -#if (CY_IP_MXSDHC_INSTANCES > 1) - isr_sdio_1_handler, -#endif -}; + isTransferInProcess = false; -static void isr_sdio_0_handler (void) -{ - isr_sdio_handler(0, SDHC0); + return ret; } -static void isr_sdio_1_handler (void) +void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_event_callback_t callback, void *callback_arg) { - isr_sdio_handler(1, SDHC1); + uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); + obj->callback_data.callback = (cy_israddress) callback; + obj->callback_data.callback_arg = callback_arg; + cyhal_system_critical_section_exit(savedIntrStatus); } -void cyhal_sdio_register_irq(cyhal_sdio_t *obj, cyhal_sdio_irq_handler_t handler, void *handler_arg) +void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, uint8_t intrPriority, bool enable) { - uint8_t index = obj->resource.block_num; - - IRQn_Type irqn = CY_SDHC_IRQ_N[index]; - cy_sdio_config_structs[index] = obj; - callbacks[index] = handler; - callback_args[index] = handler_arg; - - /* Only enable if it's not already enabled */ - if (NVIC_GetEnableIRQ(irqn) == 0) + /* Configure interrupt-based event(s) */ + if (0U != ((uint32_t) event & (uint32_t) CYHAL_SDIO_ALL_INTERRUPTS)) { - cy_stc_sysint_t irqCfg = {irqn, SDIO_IRQ_PRIORITY}; + uint32_t interruptEnable = Cy_SD_Host_GetNormalInterruptEnable(obj->base); + uint32_t interruptMask = Cy_SD_Host_GetNormalInterruptMask(obj->base); - Cy_SysInt_Init(&irqCfg, interrupts_dispatcher_table[index]); - NVIC_EnableIRQ(irqn); - } - else - { - NVIC_SetPriority(irqn, SDIO_IRQ_PRIORITY); - } -} + IRQn_Type irqn = CYHAL_SDHC_IRQ_N[obj->resource.block_num]; + NVIC_SetPriority(irqn, intrPriority); -void cyhal_sdio_irq_enable(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, bool enable) -{ - uint32_t interruptEnable = Cy_SD_Host_GetNormalInterruptEnable(obj->base); - uint32_t interruptMask = Cy_SD_Host_GetNormalInterruptMask(obj->base); + if (enable) + { + interruptEnable |= event; + interruptMask |= event; - if (enable) - { - interruptEnable |= event; - interruptMask |= event; + obj->irq_cause |= event; + } + else + { + interruptEnable &= ~(event); + interruptMask &= ~(event); - obj->irq_cause |= event; - } - else - { - interruptEnable &= ~(event); - interruptMask &= ~(event); + obj->irq_cause &= ~event; + } - obj->irq_cause &= ~event; + Cy_SD_Host_SetNormalInterruptMask(obj->base, interruptMask); + Cy_SD_Host_SetNormalInterruptEnable(obj->base, interruptEnable); } - Cy_SD_Host_SetNormalInterruptMask(obj->base, interruptMask); - Cy_SD_Host_SetNormalInterruptEnable(obj->base, interruptEnable); + /* Configure non-interrupt based event(s) */ + if (0U != ((uint32_t) event & SDIO_INTERFACE_CHANGE_MASK)) + { + if (enable) + { + obj->events |= (uint32_t) event; + } + else + { + obj->events &= (uint32_t) ~((uint32_t) event); + } + } } +#if defined(__cplusplus) +} +#endif #endif /* CY_IP_MXSDHC */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c index c6347358e17..8c878880052 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c @@ -25,14 +25,22 @@ #include #include -#include "cyhal_implementation.h" +#include "cyhal_spi.h" +#include "cyhal_scb_common.h" +#include "cyhal_gpio.h" +#include "cyhal_interconnect.h" +#include "cyhal_system_impl.h" #include "cyhal_hwmgr.h" #ifdef CY_IP_MXSCB +#if defined(__cplusplus) +extern "C" +{ +#endif + #define SPI_DEFAULT_SPEED 100000 #define NUM_SPI_PORTS 8 -#define SPI_DEFAULT_IRQ_PRIORITY 7 #define SPI_OVERSAMPLE_MIN 4 #define SPI_OVERSAMPLE_MAX 16 @@ -49,7 +57,8 @@ #define PENDING_TX_RX 3 /* Default SPI configuration */ -static const cy_stc_scb_spi_config_t default_spi_config = { +static const cy_stc_scb_spi_config_t default_spi_config = +{ .spiMode = CY_SCB_SPI_MASTER, .subMode = CY_SCB_SPI_MOTOROLA, .sclkMode = CY_SCB_SPI_CPHA0_CPOL0, @@ -70,61 +79,15 @@ static const cy_stc_scb_spi_config_t default_spi_config = { .masterSlaveIntEnableMask = 0 }; -static cyhal_spi_irq_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause); - -static cyhal_spi_t *cyhal_spi_config_structs[CY_IP_MXSCB_INSTANCES]; -static cyhal_spi_irq_handler_t cyhal_spi_user_callbacks[CY_IP_MXSCB_INSTANCES]; -static void *cyhal_spi_callback_args[CY_IP_MXSCB_INSTANCES]; - -static void cyhal_spi_0_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_1_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_2_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_3_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_4_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_5_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_6_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_7_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_8_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_9_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_10_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_11_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_12_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_13_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_14_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_15_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_16_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_17_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_18_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_spi_19_cb_wrapper(uint32_t event) __attribute__((unused)); - -static void cyhal_spi_0_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_1_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_2_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_3_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_4_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_5_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_6_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_7_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_8_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_9_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_10_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_11_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_12_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_13_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_14_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_15_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_16_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_17_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_18_irq_handler(void) __attribute__((unused)); -static void cyhal_spi_19_irq_handler(void) __attribute__((unused)); +static cyhal_spi_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause); static cy_rslt_t cyhal_int_spi_frequency(cyhal_spi_t *obj, uint32_t hz, uint8_t *ovr_smpl_val); static void cyhal_set_ssel(cyhal_spi_t *obj); static void cyhal_reset_ssel(cyhal_spi_t *obj); -static cyhal_spi_irq_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause) +static cyhal_spi_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause) { - cyhal_spi_irq_event_t cause; + cyhal_spi_event_t cause; switch (pdl_cause) { case CY_SCB_SPI_TRANSFER_IN_FIFO_EVENT: @@ -142,166 +105,10 @@ static cyhal_spi_irq_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause) } return cause; } -static __INLINE void cyhal_spi_cb_wrapper_indexed(uint32_t event, uint8_t idx) -{ - cyhal_spi_irq_event_t anded_events = (cyhal_spi_irq_event_t)(cyhal_spi_config_structs[idx]->irq_cause & (uint32_t)cyhal_convert_interrupt_cause(event)); - if (anded_events) - { - cyhal_spi_user_callbacks[idx](cyhal_spi_callback_args[idx], anded_events); - } -} -static void cyhal_spi_0_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 0); -} -static void cyhal_spi_1_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 1); -} -static void cyhal_spi_2_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 2); -} -static void cyhal_spi_3_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 3); -} -static void cyhal_spi_4_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 4); -} -static void cyhal_spi_5_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 5); -} -static void cyhal_spi_6_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 6); -} -static void cyhal_spi_7_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 7); -} -static void cyhal_spi_8_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 8); -} -static void cyhal_spi_9_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 9); -} -static void cyhal_spi_10_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 10); -} -static void cyhal_spi_11_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 11); -} -static void cyhal_spi_12_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 12); -} -static void cyhal_spi_13_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 13); -} -static void cyhal_spi_14_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 14); -} -static void cyhal_spi_15_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 15); -} -static void cyhal_spi_16_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 16); -} -static void cyhal_spi_17_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 17); -} -static void cyhal_spi_18_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 18); -} -static void cyhal_spi_19_cb_wrapper(uint32_t event) -{ - cyhal_spi_cb_wrapper_indexed(event, 19); -} -static void (*cyhal_spi_cb_wrapper_table[CY_IP_MXSCB_INSTANCES])(uint32_t event) = +static void cyhal_spi_irq_handler(void) { -#if (CY_IP_MXSCB_INSTANCES > 0) - cyhal_spi_0_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 1) - cyhal_spi_1_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 2) - cyhal_spi_2_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 3) - cyhal_spi_3_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 4) - cyhal_spi_4_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 5) - cyhal_spi_5_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 6) - cyhal_spi_6_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 7) - cyhal_spi_7_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 8) - cyhal_spi_8_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 9) - cyhal_spi_9_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 10) - cyhal_spi_10_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 11) - cyhal_spi_11_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 12) - cyhal_spi_12_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 13) - cyhal_spi_13_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 14) - cyhal_spi_14_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 15) - cyhal_spi_15_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 16) - cyhal_spi_16_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 17) - cyhal_spi_17_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 18) - cyhal_spi_18_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 19) - cyhal_spi_19_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 20) - #error "Unhandled scb count" -#endif -}; - -static void cyhal_spi_interrupts_dispatcher_IRQHandler(uint32_t spi_num) -{ - cyhal_spi_t *obj = cyhal_spi_config_structs[spi_num]; - + cyhal_spi_t *obj = (cyhal_spi_t*) cyhal_scb_get_irq_obj(); if (NULL == obj) { return; @@ -341,163 +148,16 @@ static void cyhal_spi_interrupts_dispatcher_IRQHandler(uint32_t spi_num) } } } -static void cyhal_spi_0_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(0); -} -static void cyhal_spi_1_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(1); -} -static void cyhal_spi_2_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(2); -} -static void cyhal_spi_3_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(3); -} -static void cyhal_spi_4_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(4); -} -static void cyhal_spi_5_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(5); -} -static void cyhal_spi_6_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(6); -} -static void cyhal_spi_7_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(7); -} -static void cyhal_spi_8_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(8); -} -static void cyhal_spi_9_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(9); -} -static void cyhal_spi_10_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(10); -} -static void cyhal_spi_11_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(11); -} -static void cyhal_spi_12_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(12); -} -static void cyhal_spi_13_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(13); -} -static void cyhal_spi_14_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(14); -} -static void cyhal_spi_15_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(15); -} -static void cyhal_spi_16_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(16); -} -static void cyhal_spi_17_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(17); -} -static void cyhal_spi_18_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(18); -} -static void cyhal_spi_19_irq_handler(void) -{ - cyhal_spi_interrupts_dispatcher_IRQHandler(19); -} -static void (*cyhal_spi_interrupts_dispatcher_table[CY_IP_MXSCB_INSTANCES])(void) = -{ -#if (CY_IP_MXSCB_INSTANCES > 0) - cyhal_spi_0_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 1) - cyhal_spi_1_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 2) - cyhal_spi_2_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 3) - cyhal_spi_3_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 4) - cyhal_spi_4_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 5) - cyhal_spi_5_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 6) - cyhal_spi_6_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 7) - cyhal_spi_7_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 8) - cyhal_spi_8_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 9) - cyhal_spi_9_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 10) - cyhal_spi_10_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 11) - cyhal_spi_11_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 12) - cyhal_spi_12_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 13) - cyhal_spi_13_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 14) - cyhal_spi_14_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 15) - cyhal_spi_15_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 16) - cyhal_spi_16_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 17) - cyhal_spi_17_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 18) - cyhal_spi_18_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 19) - cyhal_spi_19_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 20) - #error "Unhandled scb count" -#endif -}; -static void cyhal_spi_install_irq(cyhal_spi_t *obj) +static void cyhal_spi_cb_wrapper(uint32_t event) { - uint8_t idx = obj->resource.block_num; - // default interrupt priority of SPI_DEFAULT_IRQ_PRIORITY (lowest possible priority). - cy_stc_sysint_t irqCfg = {CY_SCB_IRQ_N[idx], SPI_DEFAULT_IRQ_PRIORITY}; - - Cy_SysInt_Init(&irqCfg, cyhal_spi_interrupts_dispatcher_table[idx]); - NVIC_EnableIRQ(CY_SCB_IRQ_N[idx]); - cyhal_spi_config_structs[idx] = obj; - cyhal_spi_config_structs[idx]->irq_cause = CYHAL_SPI_IRQ_NONE; + cyhal_spi_t *obj = (cyhal_spi_t*) cyhal_scb_get_irq_obj(); + cyhal_spi_irq_event_t anded_events = (cyhal_spi_irq_event_t) (obj->irq_cause & (uint32_t) cyhal_convert_interrupt_cause(event)); + if (anded_events) + { + cyhal_spi_event_callback_t callback = (cyhal_spi_event_callback_t) obj->callback_data.callback; + callback(obj->callback_data.callback_arg, anded_events); + } } static cy_en_scb_spi_sclk_mode_t cyhal_convert_mode_sclk(cyhal_spi_mode_t mode) @@ -609,7 +269,7 @@ cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, return CYHAL_SPI_RSLT_ERR_INVALID_PIN; } - cyhal_resource_inst_t spi_inst = *mosi_map->inst; + cyhal_resource_inst_t spi_inst = *sclk_map->inst; if (CY_RSLT_SUCCESS != (result = cyhal_hwmgr_reserve(&spi_inst))) { return result; @@ -622,35 +282,35 @@ cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, { pin_rsc = cyhal_utils_get_gpio_resource(mosi); result = cyhal_hwmgr_reserve(&pin_rsc); - } - if (result == CY_RSLT_SUCCESS) - { - obj->pin_mosi = mosi; + if (result == CY_RSLT_SUCCESS) + { + obj->pin_mosi = mosi; + } } - //reseve the MISO pin + // reserve the MISO pin if ((result == CY_RSLT_SUCCESS) && (NC != miso)) { pin_rsc = cyhal_utils_get_gpio_resource(miso); result = cyhal_hwmgr_reserve(&pin_rsc); - } - if (result == CY_RSLT_SUCCESS) - { - obj->pin_miso = miso; + if (result == CY_RSLT_SUCCESS) + { + obj->pin_miso = miso; + } } - //reseve the SCLK pin + // reserve the SCLK pin if (result == CY_RSLT_SUCCESS) { pin_rsc = cyhal_utils_get_gpio_resource(sclk); result = cyhal_hwmgr_reserve(&pin_rsc); - } - if (result == CY_RSLT_SUCCESS) - { - obj->pin_sclk = sclk; + if (result == CY_RSLT_SUCCESS) + { + obj->pin_sclk = sclk; + } } - //reseve the SSEL pin + // reserve the SSEL pin if ((result == CY_RSLT_SUCCESS) && (NC != ssel)) { if (is_slave) @@ -658,14 +318,19 @@ cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, pin_rsc = cyhal_utils_get_gpio_resource(ssel); result = cyhal_hwmgr_reserve(&pin_rsc); } - } - if (result == CY_RSLT_SUCCESS) - { - obj->is_slave = is_slave; - obj->pin_ssel = ssel; + else + { + result = cyhal_gpio_init(ssel, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, true); + } + + if (result == CY_RSLT_SUCCESS) + { + obj->is_slave = is_slave; + obj->pin_ssel = ssel; + } } - obj->base = CY_SCB_BASE_ADDRESSES[obj->resource.block_num]; + obj->base = CYHAL_SCB_BASE_ADDRESSES[obj->resource.block_num]; if (result == CY_RSLT_SUCCESS) { @@ -713,20 +378,12 @@ cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, { result = cyhal_connect_pin(sclk_map); } - if ((result == CY_RSLT_SUCCESS) && (NC != ssel)) + if ((result == CY_RSLT_SUCCESS) && (NC != ssel) && is_slave) { - if (is_slave) - { - result = cyhal_connect_pin(ssel_map); - } - else - { - result = cyhal_gpio_init(ssel, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, true); - } + result = cyhal_connect_pin(ssel_map); } - bool configured = cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - if (result == CY_RSLT_SUCCESS && !configured) + if (result == CY_RSLT_SUCCESS) { cy_stc_scb_spi_config_t config_structure = default_spi_config; config_structure.spiMode = is_slave == 0 @@ -743,11 +400,16 @@ cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, obj->mode = (uint8_t) mode; obj->oversample_value = ovr_sample_val; Cy_SCB_SPI_Init(obj->base, &config_structure, &(obj->context)); - result = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - cyhal_spi_install_irq(obj); - } - if (result == CY_RSLT_SUCCESS) - { + + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + obj->irq_cause = 0; + cyhal_scb_config_structs[obj->resource.block_num] = obj; + + cy_stc_sysint_t irqCfg = { CYHAL_SCB_IRQ_N[obj->resource.block_num], CYHAL_ISR_PRIORITY_DEFAULT }; + Cy_SysInt_Init(&irqCfg, cyhal_spi_irq_handler); + NVIC_EnableIRQ(CYHAL_SCB_IRQ_N[obj->resource.block_num]); + Cy_SCB_SPI_Enable(obj->base); } else @@ -768,10 +430,9 @@ void cyhal_spi_free(cyhal_spi_t *obj) if (obj->resource.type != CYHAL_RSC_INVALID) { - IRQn_Type irqn = CY_SCB_IRQ_N[obj->resource.block_num]; + IRQn_Type irqn = CYHAL_SCB_IRQ_N[obj->resource.block_num]; NVIC_DisableIRQ(irqn); - cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); cyhal_hwmgr_free(&(obj->resource)); obj->resource.type = CYHAL_RSC_INVALID; } @@ -821,11 +482,7 @@ static inline uint32_t max(uint32_t lhs, uint32_t rhs) static cy_rslt_t cyhal_int_spi_frequency(cyhal_spi_t *obj, uint32_t hz, uint8_t *over_sample_val) { - if (NULL == obj) - { - return CYHAL_SPI_RSLT_BAD_ARGUMENT; - } - + CY_ASSERT(NULL != obj); cy_rslt_t result = CY_RSLT_SUCCESS; uint8_t oversample_value; uint32_t divider_value; @@ -919,7 +576,7 @@ static void cyhal_reset_ssel(cyhal_spi_t *obj) } } -cy_rslt_t cyhal_spi_frequency(cyhal_spi_t *obj, uint32_t hz) +cy_rslt_t cyhal_spi_set_frequency(cyhal_spi_t *obj, uint32_t hz) { cy_rslt_t result = CY_RSLT_SUCCESS; uint8_t ovr_sample_val; @@ -954,9 +611,11 @@ cy_rslt_t cyhal_spi_frequency(cyhal_spi_t *obj, uint32_t hz) return result; } -cy_rslt_t cyhal_spi_read(cyhal_spi_t *obj, uint32_t *value) +cy_rslt_t cyhal_spi_recv(cyhal_spi_t *obj, uint32_t *value) { uint32_t read_value = CY_SCB_SPI_RX_NO_DATA; + const uint32_t fill_in = 0x0000ffffUL; /* PDL Fill in value */ + uint32_t count = 0; if (NULL == obj) { @@ -973,6 +632,28 @@ cy_rslt_t cyhal_spi_read(cyhal_spi_t *obj, uint32_t *value) return CYHAL_SPI_RSLT_INVALID_PIN_API_NOT_SUPPORTED; } + if (!obj->is_slave) + { + cyhal_set_ssel(obj); + + /* Clear FIFOs */ + Cy_SCB_SPI_ClearTxFifo(obj->base); + Cy_SCB_SPI_ClearRxFifo(obj->base); + + while (count == 0) + { + count = Cy_SCB_SPI_Write(obj->base, fill_in); + } + + while (Cy_SCB_SPI_IsTxComplete(obj->base) == false) + { + } + + while ( Cy_SCB_SPI_GetNumInRxFifo(obj->base) == 0 ) + { /* Wait for RX FIFO not empty */ } + cyhal_reset_ssel(obj); + } + while (read_value == CY_SCB_SPI_RX_NO_DATA) { read_value = Cy_SCB_SPI_Read(obj->base); @@ -981,7 +662,7 @@ cy_rslt_t cyhal_spi_read(cyhal_spi_t *obj, uint32_t *value) return CY_RSLT_SUCCESS; } -cy_rslt_t cyhal_spi_write(cyhal_spi_t *obj, uint32_t value) +cy_rslt_t cyhal_spi_send(cyhal_spi_t *obj, uint32_t value) { uint32_t count = 0; uint32_t rx_count = 0; @@ -1004,12 +685,10 @@ cy_rslt_t cyhal_spi_write(cyhal_spi_t *obj, uint32_t value) if (!obj->is_slave) { - rx_count = Cy_SCB_SPI_GetNumInRxFifo(obj->base); - if (rx_count == Cy_SCB_GetFifoSize(obj->base)) - { - (void)Cy_SCB_SPI_Read(obj->base); - } cyhal_set_ssel(obj); + /* Clear FIFOs */ + Cy_SCB_SPI_ClearTxFifo(obj->base); + Cy_SCB_SPI_ClearRxFifo(obj->base); } while (count == 0) @@ -1020,10 +699,12 @@ cy_rslt_t cyhal_spi_write(cyhal_spi_t *obj, uint32_t value) if (!obj->is_slave) { while (Cy_SCB_SPI_IsTxComplete(obj->base) == false) - ; + { + } while (( Cy_SCB_SPI_GetNumInRxFifo(obj->base) == rx_count ) && (rx_count != Cy_SCB_GetFifoSize(obj->base))) { /* Wait for RX FIFO not empty */ } cyhal_reset_ssel(obj); + (void)Cy_SCB_SPI_Read(obj->base); } return result; @@ -1208,24 +889,18 @@ cy_rslt_t cyhal_spi_abort_async(cyhal_spi_t *obj) return CY_RSLT_SUCCESS; } -void cyhal_spi_register_irq(cyhal_spi_t *obj, cyhal_spi_irq_handler_t handler, void *handler_arg) +void cyhal_spi_register_callback(cyhal_spi_t *obj, cyhal_spi_event_callback_t callback, void *callback_arg) { - uint8_t idx = obj->resource.block_num; - cyhal_spi_config_structs[idx] = obj; - cyhal_spi_user_callbacks[idx] = handler; - cyhal_spi_callback_args[idx] = handler_arg; - Cy_SCB_SPI_RegisterCallback(obj->base, cyhal_spi_cb_wrapper_table[idx], &(obj->context)); - if (NVIC_GetEnableIRQ(CY_SCB_IRQ_N[idx]) == 0) - { - // default interrupt priority of SPI_DEFAULT_IRQ_PRIORITY (lowest possible priority). - cy_stc_sysint_t irqCfg = {CY_SCB_IRQ_N[idx], SPI_DEFAULT_IRQ_PRIORITY}; + uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); + obj->callback_data.callback = (cy_israddress) callback; + obj->callback_data.callback_arg = callback_arg; + cyhal_system_critical_section_exit(savedIntrStatus); + Cy_SCB_SPI_RegisterCallback(obj->base, cyhal_spi_cb_wrapper, &(obj->context)); - Cy_SysInt_Init(&irqCfg, cyhal_spi_interrupts_dispatcher_table[idx]); - NVIC_EnableIRQ(CY_SCB_IRQ_N[idx]); - } + obj->irq_cause = 0; } -void cyhal_spi_irq_enable(cyhal_spi_t *obj, cyhal_spi_irq_event_t event, bool enable) +void cyhal_spi_enable_event(cyhal_spi_t *obj, cyhal_spi_event_t event, uint8_t intrPriority, bool enable) { if (enable) { @@ -1235,6 +910,13 @@ void cyhal_spi_irq_enable(cyhal_spi_t *obj, cyhal_spi_irq_event_t event, bool en { obj->irq_cause &= ~event; } + + IRQn_Type irqn = CYHAL_SCB_IRQ_N[obj->resource.block_num]; + NVIC_SetPriority(irqn, intrPriority); } +#if defined(__cplusplus) +} +#endif + #endif /* CY_IP_MXSCB */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_system.c index e52eb691f08..cdd57a5eaee 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_system.c @@ -26,19 +26,25 @@ *******************************************************************************/ #include "cyhal_system.h" +#include "cyhal_hwmgr.h" #ifdef CY_IP_MXS40SRSS +#if defined(__cplusplus) +extern "C" +{ +#endif + #define HZ_PER_MHZ 1000000 -cy_rslt_t cyhal_system_register_callback(cyhal_system_call_back_t *handler) +cy_rslt_t cyhal_system_register_callback(cyhal_system_callback_t *handler) { return Cy_SysPm_RegisterCallback(handler) ? CY_RSLT_SUCCESS : CYHAL_SYSTEM_RSLT_ERROR; } -cy_rslt_t cyhal_system_unregister_callback(cyhal_system_call_back_t const *handler) +cy_rslt_t cyhal_system_unregister_callback(cyhal_system_callback_t const *handler) { return Cy_SysPm_UnregisterCallback(handler) ? CY_RSLT_SUCCESS @@ -115,7 +121,7 @@ cy_rslt_t try_set_hf_divider(uint8_t clock, uint32_t input_freq, uint32_t target divider_found = true; divider = CY_SYSCLK_CLKHF_DIVIDE_BY_8; } - + if (divider_found) { Cy_SysClk_ClkHfSetDivider(clock, divider); @@ -184,7 +190,13 @@ static inline bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf) return (retVal); } -cy_rslt_t cyhal_system_clock_frequency(uint8_t clock, uint32_t frequencyhal_hz) +cy_rslt_t cyhal_system_clock_get_frequency(uint8_t clock, uint32_t *frequency_hz) +{ + *frequency_hz = Cy_SysClk_ClkHfGetFrequency(clock); + return CY_RSLT_SUCCESS; +} + +cy_rslt_t cyhal_system_clock_set_frequency(uint8_t clock, uint32_t frequency_hz) { cy_en_clkhf_in_sources_t path = Cy_SysClk_ClkHfGetSource((uint32_t)clock); cy_en_clkpath_in_sources_t source = Cy_SysClk_ClkPathGetSource((uint32_t)path); @@ -196,8 +208,8 @@ cy_rslt_t cyhal_system_clock_frequency(uint8_t clock, uint32_t frequencyhal_hz) } uint8_t fll_pll_used; uint32_t clkpath_freq = get_clkpath_freq(path, src_freq, &fll_pll_used); - - cy_rslt_t rslt = try_set_hf_divider(clock, clkpath_freq, frequencyhal_hz); + + cy_rslt_t rslt = try_set_hf_divider(clock, clkpath_freq, frequency_hz); if (rslt == CY_RSLT_SUCCESS) { SystemCoreClockUpdate(); @@ -207,11 +219,11 @@ cy_rslt_t cyhal_system_clock_frequency(uint8_t clock, uint32_t frequencyhal_hz) bool enabled = Cy_SysClk_ClkHfIsEnabled(clock); if (enabled && fll_pll_used == 0) { - return try_set_fll(clock, frequencyhal_hz); + return try_set_fll(clock, frequency_hz); } else if (enabled && fll_pll_used <= SRSS_NUM_PLL) { - return try_set_pll(clock, fll_pll_used, frequencyhal_hz); + return try_set_pll(clock, fll_pll_used, frequency_hz); } else { @@ -222,11 +234,11 @@ cy_rslt_t cyhal_system_clock_frequency(uint8_t clock, uint32_t frequencyhal_hz) { if (inst.block_num == 0) { - rslt = try_set_fll(clock, frequencyhal_hz); + rslt = try_set_fll(clock, frequency_hz); } else if (inst.block_num <= SRSS_NUM_PLL) { - rslt = try_set_pll(clock, inst.block_num, frequencyhal_hz); + rslt = try_set_pll(clock, inst.block_num, frequency_hz); } else { @@ -248,7 +260,7 @@ cy_rslt_t cyhal_system_clock_frequency(uint8_t clock, uint32_t frequencyhal_hz) return rslt; } -cy_rslt_t cyhal_system_clock_divider(cyhal_system_clock_t clock, cyhal_system_divider_t divider) +cy_rslt_t cyhal_system_clock_set_divider(cyhal_system_clock_t clock, cyhal_system_divider_t divider) { if (divider < 1 || divider > 0x100) { @@ -280,4 +292,8 @@ cy_rslt_t cyhal_system_clock_divider(cyhal_system_clock_t clock, cyhal_system_di return CY_RSLT_SUCCESS; } +#if defined(__cplusplus) +} +#endif + #endif /* CY_IP_MXS40SRSS */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_tcpwm_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_tcpwm_common.c new file mode 100644 index 00000000000..26e2670f1c9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_tcpwm_common.c @@ -0,0 +1,142 @@ +/***************************************************************************//** +* \file cyhal_tcpwm_common.c +* +* \brief +* Code shared between the Cypress Timer/Counter and PWM. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cyhal_utils.h" +#include "cyhal_system_impl.h" +#include "cyhal_tcpwm_common.h" + +#if defined(CY_IP_MXTCPWM_INSTANCES) + +#if defined(__cplusplus) +extern "C" { +#endif + +const cyhal_tcpwm_data_t CYHAL_TCPWM_DATA[] = { +#if (CY_IP_MXTCPWM_INSTANCES > 0) + {TCPWM0, PCLK_TCPWM0_CLOCKS0, TCPWM0_CNT_CNT_WIDTH, TCPWM0_CNT_NR, 0, tcpwm_0_interrupts_0_IRQn }, +#endif +#if (CY_IP_MXTCPWM_INSTANCES > 1) + {TCPWM1, PCLK_TCPWM1_CLOCKS0, TCPWM1_CNT_CNT_WIDTH, TCPWM1_CNT_NR, TCPWM0_CNT_NR, tcpwm_1_interrupts_0_IRQn }, +#endif +#if (CY_IP_MXTCPWM_INSTANCES > 2) + #warning Unhandled TCPWM instance count +#endif +}; + +#define GET_ARRAY_INDEX(block, channel) (CYHAL_TCPWM_DATA[block].channel_offset + channel) + +#if (CY_IP_MXTCPWM_INSTANCES == 0) +#define TCPWM_CHANNELS (0u) +#elif (CY_IP_MXTCPWM_INSTANCES == 1) +#define TCPWM_CHANNELS (TCPWM0_CNT_NR) +#elif (CY_IP_MXTCPWM_INSTANCES == 2) +#define TCPWM_CHANNELS (TCPWM0_CNT_NR + TCPWM1_CNT_NR) +#else +#warning Unhandled TCPWM instance count +#endif + +/** Callback array for TCPWM interrupts */ +static cyhal_event_callback_data_t *cyhal_tcpwm_callback_data_structs[TCPWM_CHANNELS]; + +void cyhal_tcpwm_init_callback_data(cyhal_resource_inst_t *resource, cyhal_event_callback_data_t *callback_data) +{ + uint8_t index = GET_ARRAY_INDEX(resource->block_num, resource->channel_num); + cyhal_tcpwm_callback_data_structs[index] = callback_data; + callback_data->callback = NULL; + callback_data->callback_arg = NULL; +} + +void cyhal_tcpwm_irq_handler() +{ + IRQn_Type irqn = CYHAL_GET_CURRENT_IRQN(); + uint8_t block, channel = 0; + // Determine TCPWM block and channel from IRQn + for (block = 0; block < CY_IP_MXTCPWM_INSTANCES; block++) + { + if ((irqn >= CYHAL_TCPWM_DATA[block].isr_offset) && (irqn < CYHAL_TCPWM_DATA[block].isr_offset + CYHAL_TCPWM_DATA[block].num_channels)) + { + channel = irqn - CYHAL_TCPWM_DATA[block].isr_offset; + break; + } + else + { + CY_ASSERT(block != CY_IP_MXTCPWM_INSTANCES - 1); // IRQn should always be in one of those ranges + } + } + + TCPWM_Type *blockAddr = CYHAL_TCPWM_DATA[block].base; + uint32_t index = GET_ARRAY_INDEX(block, channel); + + cyhal_event_callback_data_t *callback_data = cyhal_tcpwm_callback_data_structs[index]; + if (callback_data->callback != NULL) + { + cyhal_tcpwm_event_callback_t callback = (cyhal_tcpwm_event_callback_t) callback_data->callback; + /* Call registered callbacks here */ + (void) (callback) (callback_data->callback_arg, Cy_TCPWM_GetInterruptStatus(blockAddr, channel)); + } + + Cy_TCPWM_ClearInterrupt(blockAddr, channel, CY_TCPWM_INT_ON_CC_OR_TC); +} + +/******************************************************************************* +* TCPWM Shared HAL Functions +*******************************************************************************/ + +void cyhal_tcpwm_register_callback(cyhal_resource_inst_t *resource, cy_israddress callback, void *callback_arg) +{ + uint8_t index = GET_ARRAY_INDEX(resource->block_num, resource->channel_num); + uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); + cyhal_tcpwm_callback_data_structs[index]->callback = callback; + cyhal_tcpwm_callback_data_structs[index]->callback_arg = callback_arg; + cyhal_system_critical_section_exit(savedIntrStatus); + + IRQn_Type irqn = (IRQn_Type)(CYHAL_TCPWM_DATA[resource->block_num].isr_offset + resource->channel_num); + /* Only enable if it's not already enabled */ + if (NVIC_GetEnableIRQ(irqn) == 0) + { + cy_stc_sysint_t irqCfg = { irqn, CYHAL_ISR_PRIORITY_DEFAULT }; + Cy_SysInt_Init(&irqCfg, cyhal_tcpwm_irq_handler); + NVIC_EnableIRQ(irqn); + } +} + +void cyhal_tcpwm_enable_event(TCPWM_Type *type, cyhal_resource_inst_t *resource, uint32_t event, uint8_t intrPriority, bool enable) +{ + uint32_t old_mask = Cy_TCPWM_GetInterruptMask(type, resource->channel_num); + if (enable) + { + // Clear any newly enabled events so that old IRQs don't trigger ISRs + Cy_TCPWM_ClearInterrupt(type, resource->channel_num, ~old_mask & event); + } + Cy_TCPWM_SetInterruptMask(type, resource->channel_num, enable ? (old_mask | event) : (old_mask & ~event)); + + IRQn_Type irqn = (IRQn_Type) (CYHAL_TCPWM_DATA[resource->block_num].isr_offset + resource->channel_num); + NVIC_SetPriority(irqn, intrPriority); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* defined(CY_IP_MXTCPWM_INSTANCES) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c index 3d3331a0892..a41baf40972 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c @@ -25,7 +25,7 @@ * limitations under the License. *******************************************************************************/ -#include "cyhal_timer.h" +#include "cyhal_timer_impl.h" #include "cyhal_hwmgr.h" #include "cyhal_gpio.h" @@ -35,44 +35,6 @@ extern "C" { #endif -#define GET_ARRAY_INDEX(block, channel) (cyhal_internal_data[block].channel_offset + channel) - -#if (CY_IP_MXTCPWM_INSTANCES == 0) - #define TCPWM_CHANNELS (0u) -#elif (CY_IP_MXTCPWM_INSTANCES == 1) - #define TCPWM_CHANNELS (TCPWM0_CNT_NR) -#elif (CY_IP_MXTCPWM_INSTANCES == 2) - #define TCPWM_CHANNELS (TCPWM0_CNT_NR + TCPWM1_CNT_NR) -#else - #warning Unhandled TCPWM instance count -#endif - - -/* Callback array for TCPWM interrupts */ -static cyhal_timer_irq_handler_t callbacks[TCPWM_CHANNELS]; -static void *callback_args[TCPWM_CHANNELS]; - -typedef struct { - TCPWM_Type *base; - en_clk_dst_t clock_dst; - uint32_t max_count; - uint8_t channel_offset; - uint8_t isr_offset; -} cyhal_internal_timer_data_t; - -static const cyhal_internal_timer_data_t cyhal_internal_data[] = { -#if (CY_IP_MXTCPWM_INSTANCES > 0) - {TCPWM0, PCLK_TCPWM0_CLOCKS0, (uint32_t)((1ULL << TCPWM0_CNT_CNT_WIDTH) - 1ULL), 0, tcpwm_0_interrupts_0_IRQn }, -#endif -#if (CY_IP_MXTCPWM_INSTANCES > 1) - {TCPWM1, PCLK_TCPWM1_CLOCKS0, (uint32_t)((1ULL << TCPWM1_CNT_CNT_WIDTH) - 1ULL), TCPWM0_CNT_NR, tcpwm_1_interrupts_0_IRQn }, -#endif -#if (CY_IP_MXTCPWM_INSTANCES > 2) - #warning Unhandled TCPWM instance count -#endif -}; - - const cy_stc_tcpwm_counter_config_t default_config = { .period = 32768, @@ -96,553 +58,11 @@ const cy_stc_tcpwm_counter_config_t default_config = .countInput = CY_TCPWM_INPUT_1, }; -/******************************************************************************* -* Dispatcher Interrrupt Service Routine -*******************************************************************************/ - -static void isr_tcpwm_handler(uint8_t block, uint8_t channel) -{ - TCPWM_Type *blockAddr = cyhal_internal_data[block].base; - uint32_t index = GET_ARRAY_INDEX(block, channel); - - if (callbacks[index] != NULL) - { - /* Call registered callbacks here */ - (void)(callbacks[index])(callback_args[index], (cyhal_timer_irq_event_t)Cy_TCPWM_GetInterruptStatus(blockAddr, channel)); - } - Cy_TCPWM_ClearInterrupt(blockAddr, channel, CY_TCPWM_INT_ON_CC_OR_TC); -} - - -/******************************************************************************* -* (Internal) Interrrupt Service Routines -*******************************************************************************/ -static void isr_tcpwm_0_00_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_01_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_02_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_03_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_04_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_05_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_06_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_07_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_08_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_09_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_10_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_11_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_12_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_13_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_14_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_15_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_16_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_17_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_18_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_19_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_20_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_21_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_22_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_23_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_24_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_25_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_26_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_27_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_28_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_29_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_30_handler(void) __attribute__((unused)); -static void isr_tcpwm_0_31_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_00_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_01_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_02_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_03_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_04_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_05_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_06_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_07_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_08_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_09_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_10_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_11_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_12_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_13_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_14_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_15_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_16_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_17_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_18_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_19_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_20_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_21_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_22_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_23_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_24_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_25_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_26_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_27_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_28_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_29_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_30_handler(void) __attribute__((unused)); -static void isr_tcpwm_1_31_handler(void) __attribute__((unused)); - -static void isr_tcpwm_0_00_handler (void) -{ - isr_tcpwm_handler(0, 0); -} -static void isr_tcpwm_0_01_handler (void) -{ - isr_tcpwm_handler(0, 1); -} -static void isr_tcpwm_0_02_handler (void) -{ - isr_tcpwm_handler(0, 2); -} -static void isr_tcpwm_0_03_handler (void) -{ - isr_tcpwm_handler(0, 3); -} -static void isr_tcpwm_0_04_handler (void) -{ - isr_tcpwm_handler(0, 4); -} -static void isr_tcpwm_0_05_handler (void) -{ - isr_tcpwm_handler(0, 5); -} -static void isr_tcpwm_0_06_handler (void) -{ - isr_tcpwm_handler(0, 6); -} -static void isr_tcpwm_0_07_handler (void) -{ - isr_tcpwm_handler(0, 7); -} -static void isr_tcpwm_0_08_handler (void) -{ - isr_tcpwm_handler(0, 8); -} -static void isr_tcpwm_0_09_handler (void) -{ - isr_tcpwm_handler(0, 9); -} -static void isr_tcpwm_0_10_handler (void) -{ - isr_tcpwm_handler(0, 10); -} -static void isr_tcpwm_0_11_handler (void) -{ - isr_tcpwm_handler(0, 11); -} -static void isr_tcpwm_0_12_handler (void) -{ - isr_tcpwm_handler(0, 12); -} -static void isr_tcpwm_0_13_handler (void) -{ - isr_tcpwm_handler(0, 13); -} -static void isr_tcpwm_0_14_handler (void) -{ - isr_tcpwm_handler(0, 14); -} -static void isr_tcpwm_0_15_handler (void) -{ - isr_tcpwm_handler(0, 15); -} -static void isr_tcpwm_0_16_handler (void) -{ - isr_tcpwm_handler(0, 16); -} -static void isr_tcpwm_0_17_handler (void) -{ - isr_tcpwm_handler(0, 17); -} -static void isr_tcpwm_0_18_handler (void) -{ - isr_tcpwm_handler(0, 18); -} -static void isr_tcpwm_0_19_handler (void) -{ - isr_tcpwm_handler(0, 19); -} -static void isr_tcpwm_0_20_handler (void) -{ - isr_tcpwm_handler(0, 20); -} -static void isr_tcpwm_0_21_handler (void) -{ - isr_tcpwm_handler(0, 21); -} -static void isr_tcpwm_0_22_handler (void) -{ - isr_tcpwm_handler(0, 22); -} -static void isr_tcpwm_0_23_handler (void) -{ - isr_tcpwm_handler(0, 23); -} -static void isr_tcpwm_0_24_handler (void) -{ - isr_tcpwm_handler(0, 24); -} -static void isr_tcpwm_0_25_handler (void) -{ - isr_tcpwm_handler(0, 25); -} -static void isr_tcpwm_0_26_handler (void) -{ - isr_tcpwm_handler(0, 26); -} -static void isr_tcpwm_0_27_handler (void) -{ - isr_tcpwm_handler(0, 27); -} -static void isr_tcpwm_0_28_handler (void) -{ - isr_tcpwm_handler(0, 28); -} -static void isr_tcpwm_0_29_handler (void) -{ - isr_tcpwm_handler(0, 29); -} -static void isr_tcpwm_0_30_handler (void) -{ - isr_tcpwm_handler(0, 30); -} -static void isr_tcpwm_0_31_handler (void) -{ - isr_tcpwm_handler(0, 31); -} -static void isr_tcpwm_1_00_handler (void) -{ - isr_tcpwm_handler(1, 0); -} -static void isr_tcpwm_1_01_handler (void) -{ - isr_tcpwm_handler(1, 1); -} -static void isr_tcpwm_1_02_handler (void) -{ - isr_tcpwm_handler(1, 2); -} -static void isr_tcpwm_1_03_handler (void) -{ - isr_tcpwm_handler(1, 3); -} -static void isr_tcpwm_1_04_handler (void) -{ - isr_tcpwm_handler(1, 4); -} -static void isr_tcpwm_1_05_handler (void) -{ - isr_tcpwm_handler(1, 5); -} -static void isr_tcpwm_1_06_handler (void) -{ - isr_tcpwm_handler(1, 6); -} -static void isr_tcpwm_1_07_handler (void) -{ - isr_tcpwm_handler(1, 7); -} -static void isr_tcpwm_1_08_handler (void) -{ - isr_tcpwm_handler(1, 8); -} -static void isr_tcpwm_1_09_handler (void) -{ - isr_tcpwm_handler(1, 9); -} -static void isr_tcpwm_1_10_handler (void) -{ - isr_tcpwm_handler(1, 10); -} -static void isr_tcpwm_1_11_handler (void) -{ - isr_tcpwm_handler(1, 11); -} -static void isr_tcpwm_1_12_handler (void) -{ - isr_tcpwm_handler(1, 12); -} -static void isr_tcpwm_1_13_handler (void) -{ - isr_tcpwm_handler(1, 13); -} -static void isr_tcpwm_1_14_handler (void) -{ - isr_tcpwm_handler(1, 14); -} -static void isr_tcpwm_1_15_handler (void) -{ - isr_tcpwm_handler(1, 15); -} -static void isr_tcpwm_1_16_handler (void) -{ - isr_tcpwm_handler(1, 16); -} -static void isr_tcpwm_1_17_handler (void) -{ - isr_tcpwm_handler(1, 17); -} -static void isr_tcpwm_1_18_handler (void) -{ - isr_tcpwm_handler(1, 18); -} -static void isr_tcpwm_1_19_handler (void) -{ - isr_tcpwm_handler(1, 19); -} -static void isr_tcpwm_1_20_handler (void) -{ - isr_tcpwm_handler(1, 20); -} -static void isr_tcpwm_1_21_handler (void) -{ - isr_tcpwm_handler(1, 21); -} -static void isr_tcpwm_1_22_handler (void) -{ - isr_tcpwm_handler(1, 22); -} -static void isr_tcpwm_1_23_handler (void) -{ - isr_tcpwm_handler(1, 23); -} -static void isr_tcpwm_1_24_handler (void) -{ - isr_tcpwm_handler(1, 24); -} -static void isr_tcpwm_1_25_handler (void) -{ - isr_tcpwm_handler(1, 25); -} -static void isr_tcpwm_1_26_handler (void) -{ - isr_tcpwm_handler(1, 26); -} -static void isr_tcpwm_1_27_handler (void) -{ - isr_tcpwm_handler(1, 27); -} -static void isr_tcpwm_1_28_handler (void) -{ - isr_tcpwm_handler(1, 28); -} -static void isr_tcpwm_1_29_handler (void) -{ - isr_tcpwm_handler(1, 29); -} -static void isr_tcpwm_1_30_handler (void) -{ - isr_tcpwm_handler(1, 30); -} -static void isr_tcpwm_1_31_handler (void) -{ - isr_tcpwm_handler(1, 31); -} - -typedef void (*interrupt_dispatcher)(void); -static const interrupt_dispatcher interrupts_dispatcher_table[TCPWM_CHANNELS] = -{ -#if (TCPWM0_CNT_NR > 0) - isr_tcpwm_0_00_handler, -#endif -#if (TCPWM0_CNT_NR > 1) - isr_tcpwm_0_01_handler, -#endif -#if (TCPWM0_CNT_NR > 2) - isr_tcpwm_0_02_handler, -#endif -#if (TCPWM0_CNT_NR > 3) - isr_tcpwm_0_03_handler, -#endif -#if (TCPWM0_CNT_NR > 4) - isr_tcpwm_0_04_handler, -#endif -#if (TCPWM0_CNT_NR > 5) - isr_tcpwm_0_05_handler, -#endif -#if (TCPWM0_CNT_NR > 6) - isr_tcpwm_0_06_handler, -#endif -#if (TCPWM0_CNT_NR > 7) - isr_tcpwm_0_07_handler, -#endif -#if (TCPWM0_CNT_NR > 8) - isr_tcpwm_0_08_handler, -#endif -#if (TCPWM0_CNT_NR > 9) - isr_tcpwm_0_09_handler, -#endif -#if (TCPWM0_CNT_NR > 10) - isr_tcpwm_0_10_handler, -#endif -#if (TCPWM0_CNT_NR > 11) - isr_tcpwm_0_11_handler, -#endif -#if (TCPWM0_CNT_NR > 12) - isr_tcpwm_0_12_handler, -#endif -#if (TCPWM0_CNT_NR > 13) - isr_tcpwm_0_13_handler, -#endif -#if (TCPWM0_CNT_NR > 14) - isr_tcpwm_0_14_handler, -#endif -#if (TCPWM0_CNT_NR > 15) - isr_tcpwm_0_15_handler, -#endif -#if (TCPWM0_CNT_NR > 16) - isr_tcpwm_0_16_handler, -#endif -#if (TCPWM0_CNT_NR > 17) - isr_tcpwm_0_17_handler, -#endif -#if (TCPWM0_CNT_NR > 18) - isr_tcpwm_0_18_handler, -#endif -#if (TCPWM0_CNT_NR > 19) - isr_tcpwm_0_19_handler, -#endif -#if (TCPWM0_CNT_NR > 20) - isr_tcpwm_0_20_handler, -#endif -#if (TCPWM0_CNT_NR > 21) - isr_tcpwm_0_21_handler, -#endif -#if (TCPWM0_CNT_NR > 22) - isr_tcpwm_0_22_handler, -#endif -#if (TCPWM0_CNT_NR > 23) - isr_tcpwm_0_23_handler, -#endif -#if (TCPWM0_CNT_NR > 24) - isr_tcpwm_0_24_handler, -#endif -#if (TCPWM0_CNT_NR > 25) - isr_tcpwm_0_25_handler, -#endif -#if (TCPWM0_CNT_NR > 26) - isr_tcpwm_0_26_handler, -#endif -#if (TCPWM0_CNT_NR > 27) - isr_tcpwm_0_27_handler, -#endif -#if (TCPWM0_CNT_NR > 28) - isr_tcpwm_0_28_handler, -#endif -#if (TCPWM0_CNT_NR > 29) - isr_tcpwm_0_29_handler, -#endif -#if (TCPWM0_CNT_NR > 30) - isr_tcpwm_0_30_handler, -#endif -#if (TCPWM0_CNT_NR > 31) - isr_tcpwm_0_31_handler, -#endif -#if (TCPWM0_CNT_NR > 32) - #error "Unhandled TCPWM 0 channel count" -#endif -#if (TCPWM1_CNT_NR > 0) - isr_tcpwm_1_00_handler, -#endif -#if (TCPWM1_CNT_NR > 1) - isr_tcpwm_1_01_handler, -#endif -#if (TCPWM1_CNT_NR > 2) - isr_tcpwm_1_02_handler, -#endif -#if (TCPWM1_CNT_NR > 3) - isr_tcpwm_1_03_handler, -#endif -#if (TCPWM1_CNT_NR > 4) - isr_tcpwm_1_04_handler, -#endif -#if (TCPWM1_CNT_NR > 5) - isr_tcpwm_1_05_handler, -#endif -#if (TCPWM1_CNT_NR > 6) - isr_tcpwm_1_06_handler, -#endif -#if (TCPWM1_CNT_NR > 7) - isr_tcpwm_1_07_handler, -#endif -#if (TCPWM1_CNT_NR > 8) - isr_tcpwm_1_08_handler, -#endif -#if (TCPWM1_CNT_NR > 9) - isr_tcpwm_1_09_handler, -#endif -#if (TCPWM1_CNT_NR > 10) - isr_tcpwm_1_10_handler, -#endif -#if (TCPWM1_CNT_NR > 11) - isr_tcpwm_1_11_handler, -#endif -#if (TCPWM1_CNT_NR > 12) - isr_tcpwm_1_12_handler, -#endif -#if (TCPWM1_CNT_NR > 13) - isr_tcpwm_1_13_handler, -#endif -#if (TCPWM1_CNT_NR > 14) - isr_tcpwm_1_14_handler, -#endif -#if (TCPWM1_CNT_NR > 15) - isr_tcpwm_1_15_handler, -#endif -#if (TCPWM1_CNT_NR > 16) - isr_tcpwm_1_16_handler, -#endif -#if (TCPWM1_CNT_NR > 17) - isr_tcpwm_1_17_handler, -#endif -#if (TCPWM1_CNT_NR > 18) - isr_tcpwm_1_18_handler, -#endif -#if (TCPWM1_CNT_NR > 19) - isr_tcpwm_1_19_handler, -#endif -#if (TCPWM1_CNT_NR > 20) - isr_tcpwm_1_20_handler, -#endif -#if (TCPWM1_CNT_NR > 21) - isr_tcpwm_1_21_handler, -#endif -#if (TCPWM1_CNT_NR > 22) - isr_tcpwm_1_22_handler, -#endif -#if (TCPWM1_CNT_NR > 23) - isr_tcpwm_1_23_handler, -#endif -#if (TCPWM1_CNT_NR > 24) - isr_tcpwm_1_24_handler, -#endif -#if (TCPWM1_CNT_NR > 25) - isr_tcpwm_1_25_handler, -#endif -#if (TCPWM1_CNT_NR > 26) - isr_tcpwm_1_26_handler, -#endif -#if (TCPWM1_CNT_NR > 27) - isr_tcpwm_1_27_handler, -#endif -#if (TCPWM1_CNT_NR > 28) - isr_tcpwm_1_28_handler, -#endif -#if (TCPWM1_CNT_NR > 29) - isr_tcpwm_1_29_handler, -#endif -#if (TCPWM1_CNT_NR > 30) - isr_tcpwm_1_30_handler, -#endif -#if (TCPWM1_CNT_NR > 31) - isr_tcpwm_1_31_handler, -#endif -#if (TCPWM1_CNT_NR > 32) - #error "Unhandled TCPWM 1 channel count" -#endif -}; - - +/** Convert timer direction from the HAL enum to the corresponding PDL constant + * + * @param[in] direction The direction, as a HAL enum value + * @return The direction, as a PDL constant + */ static inline uint32_t convert_direction(cyhal_timer_direction_t direction) { switch (direction) @@ -657,7 +77,6 @@ static inline uint32_t convert_direction(cyhal_timer_direction_t direction) return CY_TCPWM_COUNTER_COUNT_UP; } - /******************************************************************************* * Timer HAL Functions *******************************************************************************/ @@ -674,46 +93,43 @@ cy_rslt_t cyhal_timer_init(cyhal_timer_t *obj, cyhal_gpio_t pin, const cyhal_clo if (CY_RSLT_SUCCESS == result) { cyhal_resource_inst_t *timer = &obj->resource; - obj->base = cyhal_internal_data[timer->block_num].base; - en_clk_dst_t pclk = (en_clk_dst_t)(cyhal_internal_data[timer->block_num].clock_dst + timer->channel_num); + obj->base = CYHAL_TCPWM_DATA[timer->block_num].base; + + en_clk_dst_t pclk = (en_clk_dst_t)(CYHAL_TCPWM_DATA[timer->block_num].clock_dst + timer->channel_num); if (NULL != clk) { + obj->clock = *clk; + obj->dedicated_clock = false; obj->clock_hz = cy_PeriClkFreqHz / (1 + Cy_SysClk_PeriphGetDivider(obj->clock.div_type, obj->clock.div_num)); if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, clk->div_type, clk->div_num)) { - result = CYHAL_TIMER_RSLT_ERR_CLOCK; + result = CYHAL_TIMER_RSLT_ERR_CLOCK_INIT; } } else if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false))) { - uint32_t div = cy_PeriClkFreqHz / 1000000u; - if (0 == div || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num) || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num)) + obj->dedicated_clock = true; + result = cyhal_timer_set_frequency(obj, CYHAL_TIMER_DEFAULT_FREQ); + if(CY_RSLT_SUCCESS == result) { - result = CYHAL_TIMER_RSLT_ERR_CLOCK; - } - else - { - obj->clock_hz = cy_PeriClkFreqHz / div; + if(CY_RSLT_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num)) + { + result = CYHAL_TIMER_RSLT_ERR_CLOCK_INIT; + } } } - bool configured = cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - if (CY_RSLT_SUCCESS == result && !configured) + if (CY_RSLT_SUCCESS == result) { result = Cy_TCPWM_Counter_Init(obj->base, obj->resource.channel_num, &default_config); - if (CY_TCPWM_SUCCESS == result) - { - result = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - } } if (result == CY_RSLT_SUCCESS) { + cyhal_tcpwm_init_callback_data(&(obj->resource), &(obj->callback_data)); + Cy_TCPWM_SetInterruptMask(obj->base, obj->resource.channel_num, CY_TCPWM_INT_NONE); Cy_TCPWM_Counter_Enable(obj->base, obj->resource.channel_num); } else @@ -729,15 +145,28 @@ void cyhal_timer_free(cyhal_timer_t *obj) { CY_ASSERT(NULL != obj); + IRQn_Type irqn = (IRQn_Type)(CYHAL_TCPWM_DATA[obj->resource.block_num].isr_offset + obj->resource.channel_num); + NVIC_DisableIRQ(irqn); + if (NULL != obj && NULL != obj->base) { + Cy_TCPWM_Counter_Disable(obj->base, obj->resource.channel_num); + cyhal_hwmgr_free(&obj->resource); - cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); obj->base = NULL; + obj->resource.type = CYHAL_RSC_INVALID; + + if (obj->dedicated_clock) + { + cy_en_sysclk_status_t rslt = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); + CY_ASSERT(CY_SYSCLK_SUCCESS == rslt); + cyhal_hwmgr_free_clock(&(obj->clock)); + obj->dedicated_clock = false; + } } } -cy_rslt_t cyhal_timer_set_config(cyhal_timer_t *obj, const cyhal_timer_cfg_t *cfg) +cy_rslt_t cyhal_timer_configure(cyhal_timer_t *obj, const cyhal_timer_cfg_t *cfg) { cy_rslt_t rslt; if (obj->is_continuous != cfg->is_continuous || @@ -750,9 +179,11 @@ cy_rslt_t cyhal_timer_set_config(cyhal_timer_t *obj, const cyhal_timer_cfg_t *cf config.runMode = cfg->is_continuous ? CY_TCPWM_COUNTER_CONTINUOUS : CY_TCPWM_COUNTER_ONESHOT; config.compareOrCapture = cfg->is_compare ? CY_TCPWM_COUNTER_MODE_COMPARE : CY_TCPWM_COUNTER_MODE_CAPTURE; config.countDirection = convert_direction(cfg->direction); - + // DeInit will clear the interrupt mask; save it now and restore after we re-nit + uint32_t old_mask = Cy_TCPWM_GetInterruptMask(obj->base, obj->resource.channel_num); Cy_TCPWM_Counter_DeInit(obj->base, obj->resource.channel_num, &config); rslt = (cy_rslt_t)Cy_TCPWM_Counter_Init(obj->base, obj->resource.channel_num, &config); + Cy_TCPWM_SetInterruptMask(obj->base, obj->resource.channel_num, old_mask); if (CY_TCPWM_SUCCESS == rslt) { obj->is_continuous = cfg->is_continuous; @@ -774,48 +205,46 @@ cy_rslt_t cyhal_timer_set_config(cyhal_timer_t *obj, const cyhal_timer_cfg_t *cf return rslt; } +cy_rslt_t cyhal_timer_set_frequency(cyhal_timer_t *obj, uint32_t hz) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + if(false == obj->dedicated_clock) + { + result = CYHAL_TIMER_RSLT_ERR_SHARED_CLOCK; + } + + if(CY_RSLT_SUCCESS == result) + { + uint32_t div = cy_PeriClkFreqHz / hz; + if (0 == div || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num)) + { + result = CYHAL_TIMER_RSLT_ERR_CLOCK_INIT; + } + else + { + obj->clock_hz = cy_PeriClkFreqHz / div; + } + } + + return result; +} + cy_rslt_t cyhal_timer_start(cyhal_timer_t *obj) { - if (NULL == obj) - return CYHAL_TIMER_RSLT_ERR_BAD_ARGUMENT; + CY_ASSERT(NULL != obj); Cy_TCPWM_TriggerReloadOrIndex(obj->base, 1u << obj->resource.channel_num); return CY_RSLT_SUCCESS; } cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj) { - if (NULL == obj) - return CYHAL_TIMER_RSLT_ERR_BAD_ARGUMENT; + CY_ASSERT(NULL != obj); Cy_TCPWM_TriggerStopOrKill(obj->base, 1u << obj->resource.channel_num); return CY_RSLT_SUCCESS; } -void cyhal_timer_register_irq(cyhal_timer_t *obj, uint8_t priority, cyhal_timer_irq_handler_t handler, void *handler_arg) -{ - uint8_t index = GET_ARRAY_INDEX(obj->resource.block_num, obj->resource.channel_num); - callbacks[index] = handler; - callback_args[index] = handler_arg; - - IRQn_Type irqn = (IRQn_Type)(cyhal_internal_data[obj->resource.block_num].isr_offset + obj->resource.channel_num); - - /* Only enable if it's not already enabled */ - if (NVIC_GetEnableIRQ(irqn) == 0) - { - cy_stc_sysint_t irqCfg = {irqn, priority}; - Cy_SysInt_Init(&irqCfg, interrupts_dispatcher_table[index]); - NVIC_EnableIRQ(irqn); - } - else - { - NVIC_SetPriority(irqn, priority); - } -} - -void cyhal_timer_irq_enable(cyhal_timer_t *obj, cyhal_timer_irq_event_t event, bool enable) -{ - Cy_TCPWM_SetInterruptMask(obj->base, obj->resource.channel_num, enable ? (uint32_t)event : 0); -} - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_trng.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_trng.c index fb6c28bdff8..c18117eb576 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_trng.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_trng.c @@ -2,8 +2,8 @@ * File Name: cyhal_trng.c * * Description: -* Provides a high level interface for interacting with the Cypress TRNG. This is -* a wrapper around the lower level PDL API. +* Provides a high level interface for interacting with the Cypress True Random +* Number Generator. This is a wrapper around the lower level PDL API. * ******************************************************************************** * \copyright @@ -25,31 +25,35 @@ #include "cyhal_hwmgr.h" #include "cyhal_crypto_common.h" -#include "cy_crypto_core_crc.h" #include "cyhal_trng_impl.h" #if defined(CY_IP_MXCRYPTO) +#if defined(__cplusplus) +extern "C" +{ +#endif + /******************************************************************************* * Functions *******************************************************************************/ cy_rslt_t cyhal_trng_init(cyhal_trng_t *obj) { CY_ASSERT(NULL != obj); - - memset(obj, 0, sizeof(cyhal_trng_t)); - obj->resource.type = CYHAL_RSC_TRNG; - return cyhal_crypto_reserve(&(obj->base), &(obj->resource)); + return cyhal_crypto_reserve(&(obj->base), &(obj->resource), CYHAL_CRYPTO_TRNG); } void cyhal_trng_free(cyhal_trng_t *obj) { - CY_ASSERT(NULL != obj || obj->resource.type != CYHAL_RSC_TRNG); + CY_ASSERT(NULL != obj || obj->resource.type != CYHAL_RSC_CRYPTO); if (obj->resource.type != CYHAL_RSC_INVALID) { - cyhal_crypto_free(obj->base, &(obj->resource)); - obj->resource.type = CYHAL_RSC_INVALID; + cyhal_crypto_free(obj->base, &(obj->resource), CYHAL_CRYPTO_TRNG); } } +#if defined(__cplusplus) +} +#endif + #endif /* defined(CY_IP_MXCRYPTO) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c index 4fee067b176..9bddcaec454 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c @@ -24,10 +24,20 @@ *******************************************************************************/ #include -#include "cyhal_implementation.h" +#include "cyhal_uart.h" +#include "cyhal_scb_common.h" +#include "cyhal_gpio.h" +#include "cyhal_interconnect.h" +#include "cyhal_system_impl.h" +#include "cyhal_hwmgr.h" #ifdef CY_IP_MXSCB +#if defined(__cplusplus) +extern "C" +{ +#endif + #define UART_OVERSAMPLE 12UL #define UART_OVERSAMPLE_MIN 8UL #define UART_OVERSAMPLE_MAX 16UL @@ -67,363 +77,24 @@ static const cy_stc_scb_uart_config_t default_uart_config = { .txFifoIntEnableMask = 0x0UL }; -static cyhal_uart_irq_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause); - -static cyhal_uart_t *cyhal_uart_config_structs[CY_IP_MXSCB_INSTANCES]; -static cyhal_uart_irq_handler_t cyhal_uart_user_callbacks[CY_IP_MXSCB_INSTANCES]; -static void *cyhal_uart_callback_args[CY_IP_MXSCB_INSTANCES]; - -static void cyhal_uart_0_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_1_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_2_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_3_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_4_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_5_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_6_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_7_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_8_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_9_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_10_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_11_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_12_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_13_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_14_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_15_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_16_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_17_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_18_cb_wrapper(uint32_t event) __attribute__((unused)); -static void cyhal_uart_19_cb_wrapper(uint32_t event) __attribute__((unused)); - -static void cyhal_uart_0_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_1_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_2_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_3_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_4_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_5_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_6_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_7_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_8_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_9_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_10_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_11_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_12_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_13_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_14_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_15_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_16_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_17_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_18_irq_handler(void) __attribute__((unused)); -static void cyhal_uart_19_irq_handler(void) __attribute__((unused)); - -static __INLINE void cyhal_uart_cb_wrapper_indexed(uint32_t event, uint8_t idx) -{ - if (NULL != cyhal_uart_user_callbacks[idx]) - { - cyhal_uart_irq_event_t anded_events = (cyhal_uart_irq_event_t)(cyhal_uart_config_structs[idx]->irq_cause & (uint32_t)cyhal_convert_interrupt_cause(event)); - if (anded_events) - { - cyhal_uart_user_callbacks[idx](cyhal_uart_callback_args[idx], anded_events); - } - } -} -static void cyhal_uart_0_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 0); -} -static void cyhal_uart_1_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 1); -} -static void cyhal_uart_2_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 2); -} -static void cyhal_uart_3_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 3); -} -static void cyhal_uart_4_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 4); -} -static void cyhal_uart_5_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 5); -} -static void cyhal_uart_6_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 6); -} -static void cyhal_uart_7_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 7); -} -static void cyhal_uart_8_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 8); -} -static void cyhal_uart_9_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 9); -} -static void cyhal_uart_10_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 10); -} -static void cyhal_uart_11_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 11); -} -static void cyhal_uart_12_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 12); -} -static void cyhal_uart_13_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 13); -} -static void cyhal_uart_14_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 14); -} -static void cyhal_uart_15_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 15); -} -static void cyhal_uart_16_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 16); -} -static void cyhal_uart_17_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 17); -} -static void cyhal_uart_18_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 18); -} -static void cyhal_uart_19_cb_wrapper(uint32_t event) -{ - cyhal_uart_cb_wrapper_indexed(event, 19); -} - -static void (*cyhal_uart_cb_wrapper_table[CY_IP_MXSCB_INSTANCES])(uint32_t event) = -{ -#if (CY_IP_MXSCB_INSTANCES > 0) - cyhal_uart_0_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 1) - cyhal_uart_1_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 2) - cyhal_uart_2_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 3) - cyhal_uart_3_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 4) - cyhal_uart_4_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 5) - cyhal_uart_5_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 6) - cyhal_uart_6_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 7) - cyhal_uart_7_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 8) - cyhal_uart_8_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 9) - cyhal_uart_9_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 10) - cyhal_uart_10_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 11) - cyhal_uart_11_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 12) - cyhal_uart_12_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 13) - cyhal_uart_13_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 14) - cyhal_uart_14_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 15) - cyhal_uart_15_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 16) - cyhal_uart_16_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 17) - cyhal_uart_17_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 18) - cyhal_uart_18_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 19) - cyhal_uart_19_cb_wrapper, -#endif -#if (CY_IP_MXSCB_INSTANCES > 20) - #error "Unhandled scb count" -#endif -}; +static cyhal_uart_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause); -static void cyhal_uart_interrupts_dispatcher_IRQHandler(uint32_t uart_num) +static void cyhal_uart_irq_handler(void) { - Cy_SCB_UART_Interrupt(cyhal_uart_config_structs[uart_num]->base, &(cyhal_uart_config_structs[uart_num]->context)); + cyhal_uart_t *obj = (cyhal_uart_t*) cyhal_scb_get_irq_obj(); + Cy_SCB_UART_Interrupt(obj->base, &(obj->context)); } -static void cyhal_uart_0_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(0); -} -static void cyhal_uart_1_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(1); -} -static void cyhal_uart_2_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(2); -} -static void cyhal_uart_3_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(3); -} -static void cyhal_uart_4_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(4); -} -static void cyhal_uart_5_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(5); -} -static void cyhal_uart_6_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(6); -} -static void cyhal_uart_7_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(7); -} -static void cyhal_uart_8_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(8); -} -static void cyhal_uart_9_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(9); -} -static void cyhal_uart_10_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(10); -} -static void cyhal_uart_11_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(11); -} -static void cyhal_uart_12_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(12); -} -static void cyhal_uart_13_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(13); -} -static void cyhal_uart_14_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(14); -} -static void cyhal_uart_15_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(15); -} -static void cyhal_uart_16_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(16); -} -static void cyhal_uart_17_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(17); -} -static void cyhal_uart_18_irq_handler(void) -{ - cyhal_uart_interrupts_dispatcher_IRQHandler(18); -} -static void cyhal_uart_19_irq_handler(void) + +static void cyhal_uart_cb_wrapper(uint32_t event) { - cyhal_uart_interrupts_dispatcher_IRQHandler(19); + cyhal_uart_t *obj = (cyhal_uart_t*) cyhal_scb_get_irq_obj(); + cyhal_uart_event_t anded_events = (cyhal_uart_event_t)(obj->irq_cause & (uint32_t)cyhal_convert_interrupt_cause(event)); + if (anded_events) + { + cyhal_uart_event_callback_t callback = (cyhal_uart_event_callback_t) obj->callback_data.callback; + callback(obj->callback_data.callback_arg, anded_events); + } } -static void (*cyhal_uart_interrupts_dispatcher_table[CY_IP_MXSCB_INSTANCES])(void) = -{ -#if (CY_IP_MXSCB_INSTANCES > 0) - cyhal_uart_0_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 1) - cyhal_uart_1_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 2) - cyhal_uart_2_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 3) - cyhal_uart_3_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 4) - cyhal_uart_4_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 5) - cyhal_uart_5_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 6) - cyhal_uart_6_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 7) - cyhal_uart_7_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 8) - cyhal_uart_8_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 9) - cyhal_uart_9_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 10) - cyhal_uart_10_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 11) - cyhal_uart_11_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 12) - cyhal_uart_12_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 13) - cyhal_uart_13_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 14) - cyhal_uart_14_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 15) - cyhal_uart_15_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 16) - cyhal_uart_16_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 17) - cyhal_uart_17_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 18) - cyhal_uart_18_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 19) - cyhal_uart_19_irq_handler, -#endif -#if (CY_IP_MXSCB_INSTANCES > 20) - #error "Unhandled scb count" -#endif -}; static cy_en_syspm_status_t cyhal_uart_pm_callback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode) { @@ -551,8 +222,8 @@ cy_rslt_t cyhal_uart_init(cyhal_uart_t *obj, cyhal_gpio_t tx, cyhal_gpio_t rx, c obj->pin_rx = rx; } } - - obj->base = CY_SCB_BASE_ADDRESSES[obj->resource.block_num]; + + obj->base = CYHAL_SCB_BASE_ADDRESSES[obj->resource.block_num]; if (result == CY_RSLT_SUCCESS) { @@ -582,8 +253,7 @@ cy_rslt_t cyhal_uart_init(cyhal_uart_t *obj, cyhal_gpio_t tx, cyhal_gpio_t rx, c result = cyhal_connect_pin(tx_map); } - bool configured = cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - if (result == CY_RSLT_SUCCESS && !configured) + if (result == CY_RSLT_SUCCESS) { obj->config = default_uart_config; @@ -601,7 +271,7 @@ cy_rslt_t cyhal_uart_init(cyhal_uart_t *obj, cyhal_gpio_t tx, cyhal_gpio_t rx, c { Cy_SCB_UART_StartRingBuffer(obj->base, cfg->rx_buffer, cfg->rx_buffer_size, &(obj->context)); } - } + } obj->pm_params.base = obj->base; obj->pm_params.context = obj; @@ -614,18 +284,22 @@ cy_rslt_t cyhal_uart_init(cyhal_uart_t *obj, cyhal_gpio_t tx, cyhal_gpio_t rx, c if (!Cy_SysPm_RegisterCallback(&(obj->pm_callback))) result = CYHAL_UART_RSLT_ERR_PM_CALLBACK; - cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); - } + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + obj->irq_cause = CYHAL_UART_IRQ_NONE; + cyhal_scb_config_structs[obj->resource.block_num] = obj; + + cy_stc_sysint_t irqCfg = { CYHAL_SCB_IRQ_N[obj->resource.block_num], CYHAL_ISR_PRIORITY_DEFAULT }; + Cy_SysInt_Init(&irqCfg, cyhal_uart_irq_handler); + NVIC_EnableIRQ(CYHAL_SCB_IRQ_N[obj->resource.block_num]); - if (result == CY_RSLT_SUCCESS) - { if (obj->is_user_clock) { Cy_SCB_UART_Enable(obj->base); } else { - result = cyhal_uart_baud(obj, CYHAL_UART_DEFAULT_BAUD, NULL); + result = cyhal_uart_set_baud(obj, CYHAL_UART_DEFAULT_BAUD, NULL); } } @@ -640,10 +314,11 @@ void cyhal_uart_free(cyhal_uart_t *obj) { CY_ASSERT(NULL != obj); - if (obj->resource.type != CYHAL_RSC_INVALID) { - cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num); + IRQn_Type irqn = CYHAL_SCB_IRQ_N[obj->resource.block_num]; + NVIC_DisableIRQ(irqn); + cyhal_hwmgr_free(&(obj->resource)); Cy_SysPm_UnregisterCallback(&(obj->pm_callback)); } @@ -685,7 +360,7 @@ static uint32_t cyhal_uart_baud_perdif(uint32_t desired_baud, uint32_t actual_ba { perdif = ((desired_baud * 100) - (actual_baud * 100)) / desired_baud; } - + return perdif; } @@ -716,7 +391,7 @@ static uint8_t cyhal_uart_best_oversample(uint32_t baudrate) return best_oversample; } -cy_rslt_t cyhal_uart_baud(cyhal_uart_t *obj, uint32_t baudrate, uint32_t *actualbaud) +cy_rslt_t cyhal_uart_set_baud(cyhal_uart_t *obj, uint32_t baudrate, uint32_t *actualbaud) { cy_rslt_t status; uint8_t oversample_value; @@ -732,14 +407,14 @@ cy_rslt_t cyhal_uart_baud(cyhal_uart_t *obj, uint32_t baudrate, uint32_t *actual divider = cyhal_divider_value(baudrate * oversample_value, 0); /* Set baud rate */ - if ((obj->clock.div_type == CY_SYSCLK_DIV_16_5_BIT) || (obj->clock.div_type == CY_SYSCLK_DIV_24_5_BIT)) + if ((obj->clock.div_type == CY_SYSCLK_DIV_16_5_BIT) || (obj->clock.div_type == CY_SYSCLK_DIV_24_5_BIT)) { status = (cy_rslt_t) Cy_SysClk_PeriphSetFracDivider(obj->clock.div_type, obj->clock.div_num, divider, 0U); - } - else + } + else { status = (cy_rslt_t) Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, @@ -764,7 +439,7 @@ cy_rslt_t cyhal_uart_baud(cyhal_uart_t *obj, uint32_t baudrate, uint32_t *actual return status; } -cy_rslt_t cyhal_uart_format(cyhal_uart_t *obj, const cyhal_uart_cfg_t *cfg) +cy_rslt_t cyhal_uart_configure(cyhal_uart_t *obj, const cyhal_uart_cfg_t *cfg) { CY_ASSERT(NULL != obj); CY_ASSERT(NULL != cfg); @@ -794,7 +469,7 @@ cy_rslt_t cyhal_uart_getc(cyhal_uart_t *obj, uint8_t *value, uint32_t timeout) else { return CY_RSLT_ERR_CSP_UART_GETC_TIMEOUT; - } + } } read_value = Cy_SCB_UART_Get(obj->base); } @@ -842,21 +517,24 @@ cy_rslt_t cyhal_uart_clear(cyhal_uart_t *obj) cy_rslt_t cyhal_uart_set_flow_control(cyhal_uart_t *obj, cyhal_gpio_t cts, cyhal_gpio_t rts) { - cy_rslt_t result; + cy_rslt_t result = CY_RSLT_SUCCESS; cyhal_resource_inst_t pin_rsc; if (cts != obj->pin_cts) { if (NC == cts) { - result = cyhal_disconnect_pin(cts); - - if (CY_RSLT_SUCCESS == result) + if(obj->pin_cts != NC) { - Cy_SCB_UART_DisableCts(obj->base); + result = cyhal_disconnect_pin(obj->pin_cts); + + if (CY_RSLT_SUCCESS == result) + { + Cy_SCB_UART_DisableCts(obj->base); - pin_rsc = cyhal_utils_get_gpio_resource(cts); - cyhal_hwmgr_free(&pin_rsc); + pin_rsc = cyhal_utils_get_gpio_resource(obj->pin_cts); + cyhal_hwmgr_free(&pin_rsc); + } } } else @@ -888,12 +566,15 @@ cy_rslt_t cyhal_uart_set_flow_control(cyhal_uart_t *obj, cyhal_gpio_t cts, cyhal { if (NC == rts) { - result = cyhal_disconnect_pin(rts); - - if (CY_RSLT_SUCCESS == result) + if(obj->pin_rts != NC) { - pin_rsc = cyhal_utils_get_gpio_resource(rts); - cyhal_hwmgr_free(&pin_rsc); + result = cyhal_disconnect_pin(obj->pin_rts); + + if (CY_RSLT_SUCCESS == result) + { + pin_rsc = cyhal_utils_get_gpio_resource(obj->pin_rts); + cyhal_hwmgr_free(&pin_rsc); + } } } else @@ -923,19 +604,19 @@ cy_rslt_t cyhal_uart_set_flow_control(cyhal_uart_t *obj, cyhal_gpio_t cts, cyhal return CY_RSLT_SUCCESS; } -cy_rslt_t cyhal_uart_tx(cyhal_uart_t *obj, void *tx, size_t *tx_length) +cy_rslt_t cyhal_uart_write(cyhal_uart_t *obj, void *tx, size_t *tx_length) { *tx_length = Cy_SCB_UART_PutArray(obj->base, tx, *tx_length); return CY_RSLT_SUCCESS; } -cy_rslt_t cyhal_uart_rx(cyhal_uart_t *obj, void *rx, size_t *rx_length) +cy_rslt_t cyhal_uart_read(cyhal_uart_t *obj, void *rx, size_t *rx_length) { *rx_length = Cy_SCB_UART_GetArray(obj->base, rx, *rx_length); return CY_RSLT_SUCCESS; } -cy_rslt_t cyhal_uart_tx_async(cyhal_uart_t *obj, void *tx, size_t length) +cy_rslt_t cyhal_uart_write_async(cyhal_uart_t *obj, void *tx, size_t length) { cy_en_scb_uart_status_t uart_status = Cy_SCB_UART_Transmit(obj->base, tx, length, &(obj->context)); return uart_status == CY_SCB_UART_SUCCESS @@ -943,7 +624,7 @@ cy_rslt_t cyhal_uart_tx_async(cyhal_uart_t *obj, void *tx, size_t length) : CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_UART, 0); } -cy_rslt_t cyhal_uart_rx_async(cyhal_uart_t *obj, void *rx, size_t length) +cy_rslt_t cyhal_uart_read_async(cyhal_uart_t *obj, void *rx, size_t length) { cy_en_scb_uart_status_t uart_status = Cy_SCB_UART_Receive(obj->base, rx, length, &(obj->context)); return uart_status == CY_SCB_UART_SUCCESS @@ -961,21 +642,21 @@ bool cyhal_uart_is_rx_active(cyhal_uart_t *obj) return (0UL != (obj->context.rxStatus & CY_SCB_UART_RECEIVE_ACTIVE)); } -cy_rslt_t cyhal_uart_tx_abort(cyhal_uart_t *obj) +cy_rslt_t cyhal_uart_write_abort(cyhal_uart_t *obj) { Cy_SCB_UART_AbortTransmit(obj->base, &(obj->context)); return CY_RSLT_SUCCESS; } -cy_rslt_t cyhal_uart_rx_abort(cyhal_uart_t *obj) +cy_rslt_t cyhal_uart_read_abort(cyhal_uart_t *obj) { Cy_SCB_UART_AbortReceive(obj->base, &(obj->context)); return CY_RSLT_SUCCESS; } -static cyhal_uart_irq_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause) +static cyhal_uart_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause) { - cyhal_uart_irq_event_t cause; + cyhal_uart_event_t cause; switch (pdl_cause) { case CY_SCB_UART_TRANSMIT_IN_FIFO_EVENT: @@ -1009,24 +690,18 @@ static cyhal_uart_irq_event_t cyhal_convert_interrupt_cause(uint32_t pdl_cause) return cause; } -void cyhal_uart_register_irq(cyhal_uart_t *obj, cyhal_uart_irq_handler_t handler, void *handler_arg) +void cyhal_uart_register_callback(cyhal_uart_t *obj, cyhal_uart_event_callback_t callback, void *callback_arg) { - uint8_t idx = obj->resource.block_num; - cyhal_uart_config_structs[idx] = obj; - cyhal_uart_user_callbacks[idx] = handler; - cyhal_uart_callback_args[idx] = handler_arg; - Cy_SCB_UART_RegisterCallback(obj->base, cyhal_uart_cb_wrapper_table[idx], &(obj->context)); - if (NVIC_GetEnableIRQ(CY_SCB_IRQ_N[idx]) == 0) - { - // default interrupt priority of 7 (lowest possible priority). - cy_stc_sysint_t irqCfg = {CY_SCB_IRQ_N[idx], 7u}; + uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); + obj->callback_data.callback = (cy_israddress) callback; + obj->callback_data.callback_arg = callback_arg; + cyhal_system_critical_section_exit(savedIntrStatus); + Cy_SCB_UART_RegisterCallback(obj->base, cyhal_uart_cb_wrapper, &(obj->context)); - Cy_SysInt_Init(&irqCfg, cyhal_uart_interrupts_dispatcher_table[idx]); - NVIC_EnableIRQ(CY_SCB_IRQ_N[idx]); - } + obj->irq_cause = CYHAL_UART_IRQ_NONE; } -void cyhal_uart_irq_enable(cyhal_uart_t *obj, cyhal_uart_irq_event_t event, bool enable) +void cyhal_uart_enable_event(cyhal_uart_t *obj, cyhal_uart_event_t event, uint8_t intrPriority, bool enable) { if (enable) { @@ -1052,6 +727,12 @@ void cyhal_uart_irq_enable(cyhal_uart_t *obj, cyhal_uart_irq_event_t event, bool Cy_SCB_SetTxInterruptMask(obj->base, Cy_SCB_GetTxInterruptMask(obj->base) & ~CY_SCB_UART_TX_EMPTY); } } + + NVIC_SetPriority(CYHAL_SCB_IRQ_N[obj->resource.block_num], intrPriority); } +#if defined(__cplusplus) +} +#endif + #endif /* CY_IP_MXSCB */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c index 62e8ce5046d..833bdf893bf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c @@ -27,13 +27,17 @@ #if defined(CYHAL_UDB_SDIO) +#if defined(__cplusplus) +extern "C" +{ +#endif + #include #include "SDIO_HOST_cfg.h" #include "cyhal_utils.h" #include "cyhal_sdio.h" #include "cyhal_gpio.h" #include "cyhal_interconnect.h" -#include "cyhal_implementation.h" /* Not connected pin define */ #define SDIO_PINS_NC ((cyhal_gpio_t) CYHAL_NC_PIN_VALUE) @@ -52,6 +56,21 @@ /* The 1 byte transition mode define */ #define CY_HAL_SDIO_1B (1u) +/* Mask which indicates interface change */ +#define CYHAL_SDIO_INTERFACE_CHANGE_MASK ((uint32_t) ((uint32_t) CYHAL_SDIO_GOING_DOWN) | ((uint32_t) CYHAL_SDIO_COMING_UP)) + +#if !defined(CYHAL_SDIO_DS_CB_ORDER) + /* The order value for SDIO Deep Sleep callback */ + #define CYHAL_SDIO_DS_CB_ORDER (0u) + #endif /* !defined(CYHAL_SDIO_DS_CB_ORDER) */ + +/* Callback pointers */ +static cyhal_sdio_event_callback_t cyhal_sdio_callback = NULL; +static cyhal_sdio_t *cyhal_sdio_config_struct = NULL; +static void *cyhal_sdio_callback_args = NULL; +static bool deep_sleep_pending = false; +static bool op_pending = false; + /******************************************************************************* * (Internal) Configuration structures for SDIO pins *******************************************************************************/ @@ -106,29 +125,23 @@ const cy_stc_gpio_pin_config_t pin_clk_config = .vohSel = 0UL, }; -/* Callback pointers */ -static cyhal_sdio_irq_handler_t cyhal_sdio_callback = NULL; -static cyhal_sdio_t *cyhal_sdio_config_struct = NULL; -static void *cyhal_sdio_callback_args = NULL; - +/******************************************************************************* +* Internal functions +*******************************************************************************/ +static void cyhal_free_pins(cyhal_sdio_t *obj); /******************************************************************************* * Dispatcher Interrupt Callbacks Service Routine *******************************************************************************/ static void cyhal_sdio_interrupts_dispatcher_IRQHandler(void) { + /* Only CYHAL_SDIO_CARD_INTERRUPT event can be registered and executed */ if ((cyhal_sdio_callback != NULL) && (cyhal_sdio_config_struct->irq_cause != 0U)) { - (void)(cyhal_sdio_callback)(cyhal_sdio_callback_args, (cyhal_sdio_irq_event_t) cyhal_sdio_config_struct->irq_cause); + (void)(cyhal_sdio_callback)(cyhal_sdio_callback_args, CYHAL_SDIO_CARD_INTERRUPT); } } - -/******************************************************************************* -* Internal functions -*******************************************************************************/ -static void cyhal_free_pins(cyhal_sdio_t *obj); - static void cyhal_free_pins(cyhal_sdio_t *obj) { cyhal_gpio_free(obj->pin_clk); @@ -180,8 +193,8 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, { CY_ASSERT(NULL != obj); - /* If something go wrong, any resource not marked as invalid will be freed. - * Explicitly marked not allocated resources as invalid to prevent freeing + /* If something goes wrong, any resource not marked as invalid will be freed. + * We explicitly mark unallocated resources as invalid to prevent freeing * them. * * Before we reserve UDB at all we need try to reserve clock divider, then @@ -326,7 +339,7 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, Cy_GPIO_Pin_Init(CYHAL_GET_PORTADDR(data3), CYHAL_GET_PIN(data3), &pin_data_config); } } - + /* Reserve UDB SDIO */ if (retVal == CY_RSLT_SUCCESS) { @@ -341,18 +354,18 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, obj->resource.block_num = udbRsc.block_num; obj->resource.channel_num = udbRsc.channel_num; - /* Set default interrupt priority of 7 (lowest possible priority) */ - cy_stc_sysint_t irqCfg = {udb_interrupts_0_IRQn, 7}; + /* Set default interrupt priority to default value */ + cy_stc_sysint_t irqCfg = { udb_interrupts_0_IRQn, CYHAL_ISR_PRIORITY_DEFAULT }; Cy_SysInt_Init(&irqCfg, &SDIO_IRQ); NVIC_EnableIRQ(udb_interrupts_0_IRQn); /* Setup write DMA interrupt handler */ - cy_stc_sysint_t irqDma1_1 = {cpuss_interrupts_dw1_1_IRQn, 7}; + cy_stc_sysint_t irqDma1_1 = { cpuss_interrupts_dw1_1_IRQn, CYHAL_ISR_PRIORITY_DEFAULT }; Cy_SysInt_Init(&irqDma1_1, &SDIO_WRITE_DMA_IRQ); NVIC_EnableIRQ(cpuss_interrupts_dw1_1_IRQn); /* Setup read DMA interrupt handler */ - cy_stc_sysint_t irqDma1_3 = {cpuss_interrupts_dw1_3_IRQn, 7}; + cy_stc_sysint_t irqDma1_3 = { cpuss_interrupts_dw1_3_IRQn, CYHAL_ISR_PRIORITY_DEFAULT }; Cy_SysInt_Init(&irqDma1_3, &SDIO_READ_DMA_IRQ); NVIC_EnableIRQ(cpuss_interrupts_dw1_3_IRQn); @@ -376,10 +389,9 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, obj->frequencyhal_hz = CY_HAL_SDIO_DEF_FREQ; obj->block_size = CY_HAL_SDIO_64B; - /* Initialize interrupt cause */ + /* Initialize interrupt cause and events */ obj->irq_cause = 0u; - - retVal = cyhal_hwmgr_set_configured(udbRsc.type, udbRsc.block_num, udbRsc.channel_num); + obj->events = 0u; } } @@ -395,9 +407,14 @@ void cyhal_sdio_free(cyhal_sdio_t *obj) { CY_ASSERT(NULL != obj); + NVIC_DisableIRQ(udb_interrupts_0_IRQn); + NVIC_DisableIRQ(cpuss_interrupts_dw1_1_IRQn); + NVIC_DisableIRQ(cpuss_interrupts_dw1_3_IRQn); + cyhal_free_pins(obj); cyhal_free_clocks(obj); cyhal_free_dmas(obj); + cyhal_hwmgr_free(&(obj->resource)); } cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config) @@ -410,7 +427,7 @@ cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config SDIO_SetSdClkFrequency(config->frequencyhal_hz); obj->frequencyhal_hz = config->frequencyhal_hz; } - + /* Do not change block size if requested value is zero */ if (config->block_size != 0) { @@ -420,7 +437,6 @@ cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config return CY_RSLT_SUCCESS; } - cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t* response) { CY_ASSERT(NULL != obj); @@ -513,9 +529,10 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length) { /* UDB SDIO implementation does not support async transfers */ - + + CY_ASSERT(NULL != obj); /* Just add check to suppress warning about unused arguments */ - if ((NULL == obj) && (data == NULL) && (length == 0) && (argument == 0) && (direction == ((cyhal_transfer_t) 0x3))) + if ((data == NULL) && (length == 0) && (argument == 0) && (direction == ((cyhal_transfer_t) 0x3))) { return CYHAL_SDIO_RSLT_ERR_BAD_PARAM; } @@ -526,7 +543,7 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj) { /* UDB SDIO does not support async transfers */ - return true; + return false; } cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj) @@ -536,14 +553,14 @@ cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj) return CY_RSLT_SUCCESS; } -void cyhal_sdio_register_irq(cyhal_sdio_t *obj, cyhal_sdio_irq_handler_t handler, void *handler_arg) +void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_event_callback_t callback, void *callback_arg) { cyhal_sdio_config_struct = obj; - cyhal_sdio_callback = handler; - cyhal_sdio_callback_args = handler_arg; + cyhal_sdio_callback = callback; + cyhal_sdio_callback_args = callback_arg; } -void cyhal_sdio_irq_enable(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, bool enable) +void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_event_t event, uint8_t intrPriority, bool enable) { /* Only CYHAL_SDIO_CARD_INTERRUPT event can be registered */ if (event == CYHAL_SDIO_CARD_INTERRUPT) @@ -556,7 +573,7 @@ void cyhal_sdio_irq_enable(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, bool { cyhal_sdio_config_struct->irq_cause = event; } - + SDIO_EnableChipInt(); } else @@ -571,6 +588,27 @@ void cyhal_sdio_irq_enable(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, bool SDIO_DisableChipInt(); } } + + /* Enable/disable non-interrupt based event */ + if (0u != ((uint32_t) event & CYHAL_SDIO_INTERFACE_CHANGE_MASK)) + { + if (enable) + { + obj->events |= (uint32_t) event; + } + else + { + obj->events &= (uint32_t) ~((uint32_t) event); + } + + cyhal_sdio_config_struct->events = obj->events; + } + + NVIC_SetPriority(udb_interrupts_0_IRQn, intrPriority); +} + +#if defined(__cplusplus) } +#endif #endif /* defined(CYHAL_UDB_SDIO) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c index 119d813aa6c..7a94f948021 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c @@ -3,8 +3,8 @@ * * \brief * Provides a high level interface for interacting with the Cypress USB Device. -* This interface abstracts out the chip specific details. -* If any chip specific functionality is necessary, or performance is critical +* This interface abstracts out the chip specific details. +* If any chip specific functionality is necessary, or performance is critical * the low level functions can be used directly. * ******************************************************************************** @@ -27,11 +27,17 @@ #include "cyhal_usb_dev.h" #include "cyhal_gpio.h" +#include "cyhal_hwmgr.h" #include "cyhal_interconnect.h" #include "cyhal_utils.h" #if defined(CY_IP_MXUSBFS) +#if defined(__cplusplus) +extern "C" +{ +#endif + /* Interrupt configuration and access */ #define CYHAL_USB_DEV_DEFAULT_IRQ_PRIORITY (3U) @@ -79,7 +85,7 @@ typedef enum CYHAL_USB_DEV_EP8_IDX = 7, /* Callback number for Endpoint 8 completion interrupt */ } cyhal_usb_dev_ep_cb_num_t; -static USBFS_Type* const CYHAL_USB_DEV_BASE_ADDRESSES[CY_IP_MXUSBFS_INSTANCES] = +static USBFS_Type* const CYHAL_USB_DEV_BASE_ADDRESSES[CY_IP_MXUSBFS_INSTANCES] = { #ifdef USBFS0 USBFS0, @@ -108,8 +114,8 @@ static void cyhal_usb_0_dev_bus_reset_callback(USBFS_Type *base, struct cy_stc_u static void cyhal_usb_0_dev_ep0_setup_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext); static void cyhal_usb_0_dev_ep0_in_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext); static void cyhal_usb_0_dev_ep0_out_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext); -static cyhal_usb_dev_event_handler_t cyhal_usb_dev_event_callback_table[CY_IP_MXUSBFS_INSTANCES][CYHAL_USB_DEV_EVENT_NUM]; -static cy_cb_usbfs_dev_drv_callback_t cyhal_usb_dev_drv_event_cb_table[CY_IP_MXUSBFS_INSTANCES][CYHAL_USB_DEV_EVENT_NUM] = +static cyhal_usb_dev_event_callback_t cyhal_usb_dev_event_callback_table[CY_IP_MXUSBFS_INSTANCES][CYHAL_USB_DEV_EVENT_NUM]; +static cy_cb_usbfs_dev_drv_callback_t cyhal_usb_dev_drv_event_cb_table[CY_IP_MXUSBFS_INSTANCES][CYHAL_USB_DEV_EVENT_NUM] = { /* USBFS0 */ { @@ -121,7 +127,7 @@ static cy_cb_usbfs_dev_drv_callback_t cyhal_usb_dev_drv_event_cb_table[CY_IP_MXU }; static void cyhal_usb_0_dev_sof_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext); -static cyhal_usb_dev_sof_handler_t cyhal_usb_dev_sof_user_callback[CY_IP_MXUSBFS_INSTANCES]; +static cyhal_usb_dev_sof_callback_t cyhal_usb_dev_sof_user_callback[CY_IP_MXUSBFS_INSTANCES]; static cy_cb_usbfs_dev_drv_callback_t cyhal_usb_dev_drv_sof_cb_table[CY_IP_MXUSBFS_INSTANCES]= { /* USBFS0 */ @@ -129,7 +135,7 @@ static cy_cb_usbfs_dev_drv_callback_t cyhal_usb_dev_drv_sof_cb_table[CY_IP_MXUSB }; static void cyhal_usb_0_dev_ep_callback(USBFS_Type *base, uint32_t ep_addr, uint32_t errorType, cy_stc_usbfs_dev_drv_context_t *drvContext); -static cyhal_usb_dev_endpoint_handler_t cyhal_usb_dev_ep_handler_table[CY_IP_MXUSBFS_INSTANCES][CYHAL_USB_DEV_EP_EVENT_NUM]; +static cyhal_usb_dev_endpoint_callback_t cyhal_usb_dev_ep_handler_table[CY_IP_MXUSBFS_INSTANCES][CYHAL_USB_DEV_EP_EVENT_NUM]; static cy_cb_usbfs_dev_drv_ep_callback_t cyhal_usb_dev_drv_ep_cb_table[CY_IP_MXUSBFS_INSTANCES] = { /* USBFS0 */ @@ -172,7 +178,7 @@ static void cyhal_usb_0_dev_ep0_out_callback(USBFS_Type *base, struct cy_stc_usb static void cyhal_usb_0_dev_sof_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext) { (void) drvContext; - + if (NULL != cyhal_usb_dev_sof_user_callback[0]) { uint32_t frame_number = Cy_USBFS_Dev_Drv_GetSofNubmer(base); @@ -183,9 +189,9 @@ static void cyhal_usb_0_dev_sof_callback(USBFS_Type *base, struct cy_stc_usbfs_d static void cyhal_usb_0_dev_ep_callback(USBFS_Type *base, uint32_t ep_addr, uint32_t errorType, cy_stc_usbfs_dev_drv_context_t *drvContext) { - (void) base; (void) errorType; (void) drvContext; + (void) base; (void) errorType; (void) drvContext; uint32_t endpoint_idx = CYHAL_USB_DEV_GET_EP_IDX(ep_addr); - cyhal_usb_dev_endpoint_handler_t ep_handler = cyhal_usb_dev_ep_handler_table[0U][endpoint_idx]; + cyhal_usb_dev_endpoint_callback_t ep_handler = cyhal_usb_dev_ep_handler_table[0U][endpoint_idx]; if (NULL != ep_handler) { @@ -198,7 +204,7 @@ static bool cyhal_usb_dev_set_hf_divider(uint32_t clock, uint32_t input_freq, ui { bool divider_found; cy_en_clkhf_dividers_t divider; - + if (target_freq == input_freq) { divider_found = true; @@ -223,7 +229,7 @@ static bool cyhal_usb_dev_set_hf_divider(uint32_t clock, uint32_t input_freq, ui { divider_found = false; } - + if (divider_found) { Cy_SysClk_ClkHfSetDivider(clock, divider); @@ -237,15 +243,15 @@ static cy_rslt_t cyhal_usb_dev_reseve_pll(cyhal_resource_inst_t *rsc) { cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR_CLK_CFG; uint32_t i; - + rsc->type = CYHAL_RSC_CLKPATH; rsc->channel_num = 0U; - + for (i = 1U; i <= SRSS_NUM_PLL; ++i) { /* Set block number to path number that belongs to PLL */ rsc->block_num = i; - + if (CY_RSLT_SUCCESS == cyhal_hwmgr_reserve(rsc)) { result = CY_RSLT_SUCCESS; @@ -265,10 +271,10 @@ static cy_rslt_t cyhal_usb_dev_reseve_pll(cyhal_resource_inst_t *rsc) static cy_rslt_t cyhal_usb_dev_init_pll(uint32_t clock, uint32_t pll, uint32_t target_freq) { cy_stc_pll_config_t cfg; - + Cy_SysClk_PllDisable(pll); Cy_SysClk_ClkHfSetSource(clock, (cy_en_clkhf_in_sources_t)(pll)); - + cfg.inputFreq = CY_SYSCLK_IMO_FREQ; cfg.outputFreq = target_freq; cfg.lfMode = false; @@ -276,18 +282,18 @@ static cy_rslt_t cyhal_usb_dev_init_pll(uint32_t clock, uint32_t pll, uint32_t t Cy_SysClk_ClkPathSetSource(pll, CY_SYSCLK_CLKPATH_IN_IMO); cy_rslt_t result = Cy_SysClk_PllConfigure(pll, &cfg); - + if (result == CY_RSLT_SUCCESS) { /* Wait up to 1 seconds for PLL to lock */ result = Cy_SysClk_PllEnable(pll, 1000000); } - + if (result == CY_RSLT_SUCCESS) { Cy_SysClk_ClkHfSetDivider(clock, CY_SYSCLK_CLKHF_NO_DIVIDE); } - + return result; } @@ -317,12 +323,12 @@ static cy_rslt_t cyhal_usb_dev_hf_clock_setup(cyhal_usb_dev_t *obj) /* Start CLK_HF3 configuration */ Cy_SysClk_ClkHfDisable(clock); - /* Loop through all enabled PLLs and find one that matches requirements: + /* Loop through all enabled PLLs and find one that matches requirements: * sourced from IMO and frequency in multiple of 48MHz. */ for (path = 1U; path <= SRSS_NUM_PLL; ++path) { - if ( Cy_SysClk_PllIsEnabled(path) && + if ( Cy_SysClk_PllIsEnabled(path) && (CY_SYSCLK_CLKPATH_IN_IMO == Cy_SysClk_ClkPathGetSource(path)) ) { /* Get PLL frequency */ @@ -336,7 +342,7 @@ static cy_rslt_t cyhal_usb_dev_hf_clock_setup(cyhal_usb_dev_t *obj) { Cy_SysClk_ClkHfSetSource(clock, (cy_en_clkhf_in_sources_t) path); } - + /* The existing PLL is used, mark to not try clear it */ result = CY_RSLT_SUCCESS; break; @@ -348,19 +354,12 @@ static cy_rslt_t cyhal_usb_dev_hf_clock_setup(cyhal_usb_dev_t *obj) if (CY_RSLT_SUCCESS != result) { result = cyhal_usb_dev_reseve_pll(&(obj->pll_resource)); - + if (CY_RSLT_SUCCESS == result) { /* Sets PLL source IMO and clear CLK_HF3 divider */ result = cyhal_usb_dev_init_pll(clock, obj->pll_resource.block_num, CYHAL_USB_DEV_USB_CLK_HF_FREQ); } - - if (CY_RSLT_SUCCESS == result) - { - result = cyhal_hwmgr_set_configured(obj->pll_resource.type, - obj->pll_resource.block_num, - obj->pll_resource.channel_num); - } } /* End CLK_HF3 configuration */ @@ -378,19 +377,19 @@ static cy_rslt_t cyhal_usb_dev_peri_clock_setup(cyhal_usb_dev_t *obj, const cyha { cy_rslt_t result; cy_en_sysclk_status_t status = CY_SYSCLK_BAD_PARAM; - + if (NULL == clk) { obj->shared_clock = false; - - /* USB bus reset clock must be 100KHz. Usual peri clock frequency is > 26 MHz, which requires 16-bit divider */ + + /* USB bus reset clock must be 100KHz. Usual peri clock frequency is > 26 MHz, which requires 16-bit divider */ result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, true); - + if (CY_RSLT_SUCCESS == result) { /* Get divider to provide 100kHz clock or less */ uint32_t div_value = (cy_PeriClkFreqHz / CYHAL_USB_DEV_BUS_RESET_CLOCK_HZ) - 1U; - + (void) Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); status = Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div_value); (void) Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num); @@ -402,12 +401,12 @@ static cy_rslt_t cyhal_usb_dev_peri_clock_setup(cyhal_usb_dev_t *obj, const cyha obj->shared_clock = true; status = CY_SYSCLK_SUCCESS; } - + if (CY_SYSCLK_SUCCESS == status) { status = Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, obj->clock.div_type, obj->clock.div_num); } - + result = (CY_SYSCLK_SUCCESS == status) ? CY_RSLT_SUCCESS : CYHAL_USB_DEV_RSLT_ERR_CLK_CFG; return result; @@ -416,17 +415,17 @@ static cy_rslt_t cyhal_usb_dev_peri_clock_setup(cyhal_usb_dev_t *obj, const cyha static cy_rslt_t cyhal_usb_dev_pin_setup(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, cyhal_gpio_t dm) { cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR; - + const cyhal_resource_pin_mapping_t *dp_map = CY_UTILS_GET_RESOURCE(dp, cyhal_pin_map_usb_usb_dp_pad); const cyhal_resource_pin_mapping_t *dm_map = CY_UTILS_GET_RESOURCE(dm, cyhal_pin_map_usb_usb_dm_pad); - if((NULL != dp_map) && (NULL != dm_map) && + if((NULL != dp_map) && (NULL != dm_map) && (dp_map->inst->block_num == dm_map->inst->block_num)) { cyhal_resource_inst_t pin_rsc; obj->resource = *dp_map->inst; - + /* reserve DM and DP pins */ pin_rsc = cyhal_utils_get_gpio_resource(dp); result = cyhal_hwmgr_reserve(&pin_rsc); @@ -442,7 +441,7 @@ static cy_rslt_t cyhal_usb_dev_pin_setup(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, obj->pin_dm = dm; result = cyhal_connect_pin(dp_map); } - + if (CY_RSLT_SUCCESS == result) { result = cyhal_connect_pin(dm_map); @@ -455,35 +454,27 @@ static cy_rslt_t cyhal_usb_dev_pin_setup(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, static void cyhal_usb_dev_free_resources(cyhal_usb_dev_t *obj) { /* The object set into the default state in the cyhal_usb_dev_init() */ - + if (CYHAL_RSC_INVALID != obj->resource.type) { - cyhal_hwmgr_set_unconfigured(obj->resource.type, - obj->resource.block_num, - obj->resource.channel_num); - cyhal_hwmgr_free(&(obj->resource)); } - + if (CYHAL_RSC_INVALID != obj->pll_resource.type) { - cyhal_hwmgr_set_unconfigured(obj->pll_resource.type, - obj->pll_resource.block_num, - obj->pll_resource.channel_num); - cyhal_hwmgr_free(&(obj->pll_resource)); } - + if (!obj->shared_clock) - { + { cyhal_hwmgr_free_clock(&(obj->clock)); } - + if (CYHAL_NC_PIN_VALUE != obj->pin_dp) { cyhal_utils_disconnect_and_free(obj->pin_dp); } - + if (CYHAL_NC_PIN_VALUE != obj->pin_dm) { cyhal_utils_disconnect_and_free(obj->pin_dm); @@ -491,11 +482,11 @@ static void cyhal_usb_dev_free_resources(cyhal_usb_dev_t *obj) } cy_rslt_t cyhal_usb_dev_init(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, cyhal_gpio_t dm, const cyhal_clock_divider_t *clk) -{ +{ cy_rslt_t result; - + CY_ASSERT(NULL != obj); - + /* Reset object into the default state to handle resource free */ obj->base = NULL; obj->resource.type = CYHAL_RSC_INVALID; @@ -503,14 +494,14 @@ cy_rslt_t cyhal_usb_dev_init(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, cyhal_gpio_t obj->shared_clock = true; obj->pin_dp = CYHAL_NC_PIN_VALUE; obj->pin_dm = CYHAL_NC_PIN_VALUE; - + result = cyhal_usb_dev_pin_setup(obj, dp, dm); if (CY_RSLT_SUCCESS == result) - { + { /* Configure CLK_HF3 frequency and proper path */ result = cyhal_usb_dev_hf_clock_setup(obj); - + if (CY_RSLT_SUCCESS == result) { /* Configure CLK_PERI divider */ @@ -521,106 +512,78 @@ cy_rslt_t cyhal_usb_dev_init(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, cyhal_gpio_t if (CY_RSLT_SUCCESS == result) { result = cyhal_hwmgr_reserve(&(obj->resource)); - + obj->base = CYHAL_USB_DEV_BASE_ADDRESSES[obj->resource.block_num]; } if (CY_RSLT_SUCCESS == result) { - bool configured = cyhal_hwmgr_is_configured(obj->resource.type, - obj->resource.block_num, - obj->resource.channel_num); - - if (configured) + /* Configure driver */ + static cy_stc_usbfs_dev_drv_config_t default_cfg = { - /* Check driver configuration (CYHAL supports only CPU management mode) */ - if (_FLD2VAL(USBFS_USBDEV_ARB_CFG_DMA_CFG, USBFS_DEV_ARB_CFG(obj->base)) == - CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU) - { - /* Set context to select 16-bit register access read/write API implementation */ - obj->context.useReg16 = false; - } - else - { - result = CYHAL_USB_DEV_RSLT_ERR_BAD_DRV_CFG; - } - } - else + .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, + .dmaConfig[0] = NULL, + .dmaConfig[1] = NULL, + .dmaConfig[2] = NULL, + .dmaConfig[3] = NULL, + .dmaConfig[4] = NULL, + .dmaConfig[5] = NULL, + .dmaConfig[6] = NULL, + .dmaConfig[7] = NULL, + .epBuffer = NULL, + .epBufferSize = 0U, + .intrLevelSel = CYHAL_USB_DEV_IRQ_LVL_DEFAULT, + .enableLpm = false, + .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR + }; + + if (CY_USBFS_DEV_DRV_SUCCESS != Cy_USBFS_Dev_Drv_Init(obj->base, + &default_cfg, + &(obj->context))) { - /* Configure driver */ - static cy_stc_usbfs_dev_drv_config_t default_cfg = - { - .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, - .dmaConfig[0] = NULL, - .dmaConfig[1] = NULL, - .dmaConfig[2] = NULL, - .dmaConfig[3] = NULL, - .dmaConfig[4] = NULL, - .dmaConfig[5] = NULL, - .dmaConfig[6] = NULL, - .dmaConfig[7] = NULL, - .epBuffer = NULL, - .epBufferSize = 0U, - .intrLevelSel = CYHAL_USB_DEV_IRQ_LVL_DEFAULT, - .enableLpm = false, - .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR - }; - - if (CY_USBFS_DEV_DRV_SUCCESS != Cy_USBFS_Dev_Drv_Init(obj->base, - &default_cfg, - &(obj->context))) - { - result = CYHAL_USB_DEV_RSLT_ERR; - } - - if (CY_RSLT_SUCCESS == result) - { - result = cyhal_hwmgr_set_configured(obj->resource.type, - obj->resource.block_num, - obj->resource.channel_num); - } + result = CYHAL_USB_DEV_RSLT_ERR; } } - + if (CY_RSLT_SUCCESS == result) { uint32_t instance = obj->resource.block_num; uint32_t cb_num; - + /* Register service callbacks */ - Cy_USBFS_Dev_Drv_RegisterServiceCallback(obj->base, CY_USB_DEV_BUS_RESET, - cyhal_usb_dev_drv_event_cb_table[instance][CY_USB_DEV_BUS_RESET], + Cy_USBFS_Dev_Drv_RegisterServiceCallback(obj->base, CY_USB_DEV_BUS_RESET, + cyhal_usb_dev_drv_event_cb_table[instance][CY_USB_DEV_BUS_RESET], &(obj->context)); - Cy_USBFS_Dev_Drv_RegisterServiceCallback(obj->base, CY_USB_DEV_EP0_SETUP, - cyhal_usb_dev_drv_event_cb_table[instance][CY_USB_DEV_EP0_SETUP], + Cy_USBFS_Dev_Drv_RegisterServiceCallback(obj->base, CY_USB_DEV_EP0_SETUP, + cyhal_usb_dev_drv_event_cb_table[instance][CY_USB_DEV_EP0_SETUP], &(obj->context)); - Cy_USBFS_Dev_Drv_RegisterServiceCallback(obj->base, CY_USB_DEV_EP0_IN, - cyhal_usb_dev_drv_event_cb_table[instance][CY_USB_DEV_EP0_IN], + Cy_USBFS_Dev_Drv_RegisterServiceCallback(obj->base, CY_USB_DEV_EP0_IN, + cyhal_usb_dev_drv_event_cb_table[instance][CY_USB_DEV_EP0_IN], &(obj->context)); Cy_USBFS_Dev_Drv_RegisterServiceCallback(obj->base, CY_USB_DEV_EP0_OUT, cyhal_usb_dev_drv_event_cb_table[instance][CY_USB_DEV_EP0_OUT], &(obj->context)); /* Register sof callback (it enables sof interrupt, so disable it after registration) */ - Cy_USBFS_Dev_Drv_RegisterSofCallback(obj->base, cyhal_usb_dev_drv_sof_cb_table[instance], + Cy_USBFS_Dev_Drv_RegisterSofCallback(obj->base, cyhal_usb_dev_drv_sof_cb_table[instance], &(obj->context)); cyhal_usb_dev_sof_enable(obj, false); /* Register data endpoint handlers */ for (cb_num = 0; cb_num < CYHAL_USB_DEV_EP_EVENT_NUM; cb_num++) { - Cy_USBFS_Dev_Drv_RegisterEndpointCallback(obj->base, - (cb_num + 1U), - cyhal_usb_dev_drv_ep_cb_table[instance], + Cy_USBFS_Dev_Drv_RegisterEndpointCallback(obj->base, + (cb_num + 1U), + cyhal_usb_dev_drv_ep_cb_table[instance], &(obj->context)); } } - + if (CY_RSLT_SUCCESS != result) { cyhal_usb_dev_free_resources(obj); } - + return result; } @@ -645,13 +608,13 @@ void cyhal_usb_dev_disconnect(cyhal_usb_dev_t *obj) } -void cyhal_usb_dev_configure(cyhal_usb_dev_t *obj) +void cyhal_usb_dev_set_configured(cyhal_usb_dev_t *obj) { Cy_USBFS_Dev_Drv_ConfigDevice(obj->base, &(obj->context)); } -void cyhal_usb_dev_unconfigure(cyhal_usb_dev_t *obj) +void cyhal_usb_dev_set_unconfigured(cyhal_usb_dev_t *obj) { Cy_USBFS_Dev_Drv_UnConfigureDevice(obj->base, &(obj->context)); } @@ -660,7 +623,7 @@ void cyhal_usb_dev_unconfigure(cyhal_usb_dev_t *obj) void cyhal_usb_dev_sof_enable(cyhal_usb_dev_t *obj, bool enable) { uint32_t mask = Cy_USBFS_Dev_Drv_GetSieInterruptMask(obj->base); - + if (enable) { mask |= CY_USBFS_DEV_DRV_INTR_SIE_SOF; @@ -670,7 +633,7 @@ void cyhal_usb_dev_sof_enable(cyhal_usb_dev_t *obj, bool enable) { mask &= ~CY_USBFS_DEV_DRV_INTR_SIE_SOF; } - + Cy_USBFS_Dev_Drv_SetSieInterruptMask(obj->base, mask); } @@ -708,7 +671,7 @@ uint32_t cyhal_usb_dev_ep0_read_result(cyhal_usb_dev_t *obj) uint32_t cyhal_usb_dev_ep0_write(cyhal_usb_dev_t *obj, uint8_t *buffer, uint32_t size) -{ +{ return Cy_USBFS_Dev_Drv_Ep0Write(obj->base, buffer, size, &(obj->context)); } @@ -734,9 +697,9 @@ cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enab ep_config.endpointAddr = (uint8_t) endpoint; ep_config.attributes = (uint8_t) type; ep_config.maxPacketSize = (uint16_t) max_packet; - - if (CY_USBFS_DEV_DRV_SUCCESS == Cy_USBFS_Dev_Drv_AddEndpoint(obj->base, - &ep_config, + + if (CY_USBFS_DEV_DRV_SUCCESS == Cy_USBFS_Dev_Drv_AddEndpoint(obj->base, + &ep_config, &(obj->context))) { result = CY_RSLT_SUCCESS; @@ -750,13 +713,13 @@ cy_rslt_t cyhal_usb_dev_endpoint_remove(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t { cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR; - if (CY_USBFS_DEV_DRV_SUCCESS == Cy_USBFS_Dev_Drv_RemoveEndpoint(obj->base, - endpoint, + if (CY_USBFS_DEV_DRV_SUCCESS == Cy_USBFS_Dev_Drv_RemoveEndpoint(obj->base, + endpoint, &(obj->context))) { result = CY_RSLT_SUCCESS; } - + return result; } @@ -765,13 +728,13 @@ cy_rslt_t cyhal_usb_dev_endpoint_stall(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t { cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR; - if (CY_USBFS_DEV_DRV_SUCCESS == Cy_USBFS_Dev_Drv_StallEndpoint(obj->base, - CYHAL_USB_DEV_GET_EP_NUM(endpoint), + if (CY_USBFS_DEV_DRV_SUCCESS == Cy_USBFS_Dev_Drv_StallEndpoint(obj->base, + CYHAL_USB_DEV_GET_EP_NUM(endpoint), &(obj->context))) { result = CY_RSLT_SUCCESS; } - + return result; } @@ -780,21 +743,21 @@ cy_rslt_t cyhal_usb_dev_endpoint_unstall(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_ { cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR; - if (CY_USBFS_DEV_DRV_SUCCESS == Cy_USBFS_Dev_Drv_UnStallEndpoint(obj->base, - CYHAL_USB_DEV_GET_EP_NUM(endpoint), + if (CY_USBFS_DEV_DRV_SUCCESS == Cy_USBFS_Dev_Drv_UnStallEndpoint(obj->base, + CYHAL_USB_DEV_GET_EP_NUM(endpoint), &(obj->context))) { result = CY_RSLT_SUCCESS; } - + return result; } bool cyhal_usb_dev_endpoint_is_stalled(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint) { - bool is_stalled = (CY_USB_DEV_EP_STALLED == Cy_USBFS_Dev_Drv_GetEndpointState(obj->base, - CYHAL_USB_DEV_GET_EP_NUM(endpoint), + bool is_stalled = (CY_USB_DEV_EP_STALLED == Cy_USBFS_Dev_Drv_GetEndpointState(obj->base, + CYHAL_USB_DEV_GET_EP_NUM(endpoint), &(obj->context))); return is_stalled; @@ -805,7 +768,7 @@ cy_rslt_t cyhal_usb_dev_endpoint_read(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t e { cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR; uint32_t ep_num = CYHAL_USB_DEV_GET_EP_NUM(endpoint); - + /* Check if endpoint is read for a read operation */ cy_en_usb_dev_ep_state_t ep_state; ep_state = Cy_USBFS_Dev_Drv_GetEndpointState(obj->base, ep_num, &(obj->context)); @@ -828,18 +791,18 @@ cy_rslt_t cyhal_usb_dev_endpoint_read_result(cyhal_usb_dev_t *obj, cyhal_usb_dev { cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR; uint32_t ep_num = CYHAL_USB_DEV_GET_EP_NUM(endpoint); - + /* Check if endpoint is read for a read result operation */ if (CY_USB_DEV_EP_COMPLETED == Cy_USBFS_Dev_Drv_GetEndpointState(obj->base, ep_num, &(obj->context))) { cy_en_usbfs_dev_drv_status_t drvStatus; - drvStatus = Cy_USBFS_Dev_Drv_ReadOutEndpoint(obj->base, - ep_num, - obj->rd_data[CYHAL_USB_DEV_GET_EP_IDX(endpoint)], - obj->rd_size[CYHAL_USB_DEV_GET_EP_IDX(endpoint)], - actSize, + drvStatus = Cy_USBFS_Dev_Drv_ReadOutEndpoint(obj->base, + ep_num, + obj->rd_data[CYHAL_USB_DEV_GET_EP_IDX(endpoint)], + obj->rd_size[CYHAL_USB_DEV_GET_EP_IDX(endpoint)], + actSize, &(obj->context)); - + if (drvStatus == CY_USBFS_DEV_DRV_SUCCESS) { result = CY_RSLT_SUCCESS; @@ -854,17 +817,17 @@ cy_rslt_t cyhal_usb_dev_endpoint_write(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t { cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR; uint32_t ep_num = CYHAL_USB_DEV_GET_EP_NUM(endpoint); - + /* Check if endpoint is read for a write operation */ cy_en_usb_dev_ep_state_t ep_state; ep_state = Cy_USBFS_Dev_Drv_GetEndpointState(obj->base, ep_num, &(obj->context)); if ((CY_USB_DEV_EP_IDLE == ep_state) || (CY_USB_DEV_EP_COMPLETED == ep_state)) { cy_en_usbfs_dev_drv_status_t drvStatus; - drvStatus = Cy_USBFS_Dev_Drv_LoadInEndpoint(obj->base, - ep_num, - data, - size, + drvStatus = Cy_USBFS_Dev_Drv_LoadInEndpoint(obj->base, + ep_num, + data, + size, &(obj->context)); if (drvStatus == CY_USBFS_DEV_DRV_SUCCESS) @@ -872,7 +835,7 @@ cy_rslt_t cyhal_usb_dev_endpoint_write(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t result = CY_RSLT_SUCCESS; } } - + return result; } @@ -908,24 +871,24 @@ void cyhal_usb_dev_irq_enable(cyhal_usb_dev_t *obj, bool enable) void cyhal_usb_dev_process_irq(cyhal_usb_dev_t *obj) { - Cy_USBFS_Dev_Drv_Interrupt(obj->base, - Cy_USBFS_Dev_Drv_GetInterruptCauseLo(obj->base), + Cy_USBFS_Dev_Drv_Interrupt(obj->base, + Cy_USBFS_Dev_Drv_GetInterruptCauseLo(obj->base), &(obj->context)); } -cy_rslt_t cyhal_usb_dev_register_irq(cyhal_usb_dev_t *obj, cyhal_usb_dev_irq_handler_t handler) +cy_rslt_t cyhal_usb_dev_register_irq_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_irq_callback_t callback) { cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR; cy_stc_sysint_t config; uint32_t instance = (uint32_t)obj->resource.block_num; - + /* Configure NVIC parameters */ config.intrPriority = CYHAL_USB_DEV_DEFAULT_IRQ_PRIORITY; config.intrSrc = CYHAL_USBDEV_IRQ_N[instance]; - /* Setup interrupt in NVIC to trigger the handler */ - if (CY_SYSINT_SUCCESS == Cy_SysInt_Init(&config, (cy_israddress)handler)) + /* Setup interrupt in NVIC to trigger the callback */ + if (CY_SYSINT_SUCCESS == Cy_SysInt_Init(&config, (cy_israddress)callback)) { result = CY_RSLT_SUCCESS; } @@ -934,30 +897,34 @@ cy_rslt_t cyhal_usb_dev_register_irq(cyhal_usb_dev_t *obj, cyhal_usb_dev_irq_han } -void cyhal_usb_dev_register_event_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_event_t event, cyhal_usb_dev_event_handler_t handler) +void cyhal_usb_dev_register_event_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_event_t event, cyhal_usb_dev_event_callback_t callback) { CY_ASSERT_L1(CYHAL_USB_DEV_IS_EVENT_VALID(event)); uint32_t instance = (uint32_t)obj->resource.block_num; - cyhal_usb_dev_event_callback_table[instance][event] = handler; + cyhal_usb_dev_event_callback_table[instance][event] = callback; } -void cyhal_usb_dev_register_sof_callback( cyhal_usb_dev_t *obj, cyhal_usb_dev_sof_handler_t handler) +void cyhal_usb_dev_register_sof_callback( cyhal_usb_dev_t *obj, cyhal_usb_dev_sof_callback_t callback) { uint32_t instance = (uint32_t)obj->resource.block_num; - cyhal_usb_dev_sof_user_callback[instance] = handler; + cyhal_usb_dev_sof_user_callback[instance] = callback; } -void cyhal_usb_dev_register_endpoint_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, cyhal_usb_dev_endpoint_handler_t handler) +void cyhal_usb_dev_register_endpoint_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, cyhal_usb_dev_endpoint_callback_t callback) { uint32_t endpoint_num = CYHAL_USB_DEV_GET_EP_NUM(endpoint); uint32_t instance = (uint32_t)obj->resource.block_num; CY_ASSERT_L1(CYHAL_USB_DEV_IS_EP_NUM_VALID(endpoint_num)); - cyhal_usb_dev_ep_handler_table[instance][CYHAL_USB_DEV_GET_EP_IDX(endpoint_num)]= handler; + cyhal_usb_dev_ep_handler_table[instance][CYHAL_USB_DEV_GET_EP_IDX(endpoint_num)]= callback; +} + +#if defined(__cplusplus) } +#endif #endif /* CY_IP_MXUSBFS) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_utils.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_utils.c index c66bfbfe414..2492d4952eb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_utils.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_utils.c @@ -27,6 +27,11 @@ #include "cyhal_hwmgr.h" #include "cyhal_interconnect.h" +#if defined(__cplusplus) +extern "C" +{ +#endif + const cyhal_resource_pin_mapping_t *cyhal_utils_get_resource(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t* mappings, size_t count) { for (uint32_t i = 0; i < count; i++) @@ -45,4 +50,8 @@ void cyhal_utils_disconnect_and_free(cyhal_gpio_t pin) CY_ASSERT(CY_RSLT_SUCCESS == rslt); cyhal_resource_inst_t rsc = cyhal_utils_get_gpio_resource(pin); cyhal_hwmgr_free(&rsc); -} \ No newline at end of file +} + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c new file mode 100644 index 00000000000..a372e90c177 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c @@ -0,0 +1,225 @@ +/***************************************************************************//** +* \file cyhal_wdt.c +* +* \brief +* Provides a high level interface for interacting with the Cypress Watchdog Timer. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +* +******************************************************************************** +* \copyright +* Copyright 2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_psoc6_wdt PSoC 6 WDT (Watchdog Timer) +* \ingroup group_hal_psoc6 +* \{ +* The PSoC 6 WDT is only capable of supporting certain timeout ranges below its maximum timeout of 6000ms. +* As a result, any unsupported timeouts given to the HAL WDT are rounded up to the nearest supported value. +* The following table describes the unsupported ranges and the timeout values they are rounded to. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
Range (ms)Rounded Timeout (ms)
3001 - 40004001
1500 - 20002001
750 - 10001001
375 - 500501
188 - 250251
94 - 125126
47 - 6263
24 - 3132
12 - 1516
6 - 78
34
+* \} group_hal_psoc6 +*/ + +#include +#include "cyhal_wdt.h" +#include "cy_wdt.h" +#include "cy_lvd.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +// ((2^16 * 2) + (2^16 - 1)) * .030518 ms +/** Maximum WDT timeout in milliseconds */ +#define CYHAL_WDT_MAX_TIMEOUT_MS 6000 + +/** Maximum number of ignore bits */ +#define CYHAL_WDT_MAX_IGNORE_BITS 12 + +typedef struct { + uint32_t min_period_ms; // Minimum period in milliseconds that can be represented with this many ignored bits + uint32_t round_threshold_ms; // Timeout threshold in milliseconds from which to round up to the minimum period + // uint32_t pre_match_cycles; // The number of clock cycles in the first two full counter cycles (before the match value matters) +} cyhal_wdt_internal_ignore_bits_data_t; + +// ILO Frequency = 32768 Hz +// ILO Period = 1 / 32768 Hz = .030518 ms +// WDT Reset Period (timeout_ms) = .030518 ms * (2 * 2^(16 - ignore_bits) + match) +// ignore_bits range: 0 - 12 +// match range: 0 - (2^(16 - ignore_bits) - 1) +static const cyhal_wdt_internal_ignore_bits_data_t cyhal_wdt_internal_ignore_bits_data[] = { + {4001, 3001}, // 0 bits: min period: 4001ms, max period: 6000ms, round up from 3001+ms + {2001, 1500}, // 1 bit: min period: 2001ms, max period: 3000ms, round up from 1500+ms + {1001, 750}, // 2 bits: min period: 1001ms, max period: 1499ms, round up from 750+ms + {501, 375}, // 3 bits: min period: 501ms, max period: 749ms, round up from 375+ms + {251, 188}, // 4 bits: min period: 251ms, max period: 374ms, round up from 188+ms + {126, 94}, // 5 bits: min period: 126ms, max period: 187ms, round up from 94+ms + {63, 47}, // 6 bits: min period: 63ms, max period: 93ms, round up from 47+ms + {32, 24}, // 7 bits: min period: 32ms, max period: 46ms, round up from 24+ms + {16, 12}, // 8 bits: min period: 16ms, max period: 23ms, round up from 12+ms + {8, 6}, // 9 bits: min period: 8ms, max period: 11ms, round up from 6+ms + {4, 3}, // 10 bits: min period: 4ms, max period: 5ms, round up from 3+ms + {2, 2}, // 11 bits: min period: 2ms, max period: 2ms + {1, 1} // 12 bits: min period: 1ms, max period: 1ms +}; + +static bool cyhal_wdt_initialized = false; +static bool cyhal_wdt_pdl_initialized = false; +static uint32_t cyhal_wdt_initial_timeout_ms = 0; + +static __INLINE uint32_t cyhal_wdt_timeout_to_ignore_bits(uint32_t *timeout_ms) { + for (uint32_t i = 0; i <= CYHAL_WDT_MAX_IGNORE_BITS; i++) + { + if (*timeout_ms >= cyhal_wdt_internal_ignore_bits_data[i].round_threshold_ms) + { + if (*timeout_ms < cyhal_wdt_internal_ignore_bits_data[i].min_period_ms) + *timeout_ms = cyhal_wdt_internal_ignore_bits_data[i].min_period_ms; + return i; + } + } + return CYHAL_WDT_MAX_IGNORE_BITS; // Should never reach this +} + +static __INLINE uint32_t cyhal_wdt_timeout_to_match(uint32_t timeout_ms, uint32_t ignore_bits) +{ + // match = (timeout_ms / .030518 ms) - (2 * 2^(16 - ignore_bits)) + return (uint32_t)(timeout_ms / .030518) - (1UL << (17 - ignore_bits)); +} + +/* Start API implementing */ + +cy_rslt_t cyhal_wdt_init(cyhal_wdt_t *obj, uint32_t timeout_ms) +{ + if (timeout_ms == 0 || timeout_ms > CYHAL_WDT_MAX_TIMEOUT_MS) + { + return CY_RSLT_WDT_INVALID_TIMEOUT; + } + + if (cyhal_wdt_initialized) + { + return CY_RSLT_WDT_ALREADY_INITIALIZED; + } + + cyhal_wdt_initialized = true; + + if (!cyhal_wdt_pdl_initialized) + { + Cy_WDT_Init(); + Cy_WDT_MaskInterrupt(); + + cyhal_wdt_pdl_initialized = true; + } + + cyhal_wdt_stop(obj); + + cyhal_wdt_initial_timeout_ms = timeout_ms; + uint32_t ignore_bits = cyhal_wdt_timeout_to_ignore_bits(&timeout_ms); + Cy_WDT_SetIgnoreBits(ignore_bits); + Cy_WDT_SetMatch(cyhal_wdt_timeout_to_match(timeout_ms, ignore_bits)); + + cyhal_wdt_start(obj); + + return CY_RSLT_SUCCESS; +} + +void cyhal_wdt_free(cyhal_wdt_t *obj) +{ + cyhal_wdt_stop(obj); + + cyhal_wdt_initialized = false; +} + +void cyhal_wdt_kick(cyhal_wdt_t *obj) +{ + Cy_WDT_ClearWatchdog(); +} + +void cyhal_wdt_start(cyhal_wdt_t *obj) +{ + Cy_WDT_Unlock(); + Cy_WDT_Enable(); + Cy_WDT_Lock(); +} + +void cyhal_wdt_stop(cyhal_wdt_t *obj) +{ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); +} + +uint32_t cyhal_wdt_get_timeout_ms(cyhal_wdt_t *obj) +{ + return cyhal_wdt_initial_timeout_ms; +} + +uint32_t cyhal_wdt_get_max_timeout_ms(void) +{ + return CYHAL_WDT_MAX_TIMEOUT_MS; +} + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c index 6b53fef2c73..aba6f0c0983 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -143,6 +143,91 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = { {P7_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_5_BLESS_EXT_PA_TX_CTL_OUT)}, }; +/* Connections for: bless_mxd_act_bpktctl */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_rx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_tx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_txd_rxd */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_act_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_buck_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_clk_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_dig_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_isolate_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_mxd_clk_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_clk */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_data */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_le */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_reset_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_ldo_ol_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_switch_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_xtal_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_dsi_comp0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = { {P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)}, @@ -191,6 +276,11 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4] = { {P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_PADS3)}, }; +/* Connections for: pass_ctdac_voutsw */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: pass_dsi_ctb_cmp0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1] = { {P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_2_PASS_DSI_CTB_CMP0)}, @@ -727,4 +817,14 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[68] = { {P13_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)}, }; +/* Connections for: usb_usb_dm_pad */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: usb_usb_dp_pad */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1] = { + {NC, NULL, 0u}, +}; + #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c index e2459191381..52632bfbe31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE-USB package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -144,6 +144,91 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = { {P7_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_5_BLESS_EXT_PA_TX_CTL_OUT)}, }; +/* Connections for: bless_mxd_act_bpktctl */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_rx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_tx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_txd_rxd */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_act_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_buck_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_clk_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_dig_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_isolate_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_mxd_clk_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_clk */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_data */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_le */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_reset_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_ldo_ol_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_switch_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_xtal_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_dsi_comp0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = { {P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)}, @@ -192,6 +277,11 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4] = { {P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_PADS3)}, }; +/* Connections for: pass_ctdac_voutsw */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: pass_dsi_ctb_cmp0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1] = { {P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_2_PASS_DSI_CTB_CMP0)}, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_ble.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_ble.c index 387e35d2166..d3739e8152e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_ble.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_ble.c @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 116-BGA-BLE package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -145,6 +145,91 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = { {P7_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_5_BLESS_EXT_PA_TX_CTL_OUT)}, }; +/* Connections for: bless_mxd_act_bpktctl */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_rx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_tx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_txd_rxd */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_act_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_buck_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_clk_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_dig_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_isolate_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_mxd_clk_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_clk */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_data */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_le */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_reset_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_ldo_ol_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_switch_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_xtal_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_dsi_comp0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = { {P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)}, @@ -155,6 +240,11 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = { {P8_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_3_LPCOMP_DSI_COMP1)}, }; +/* Connections for: lpcomp_inn_comp0 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_inn_comp1 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = { {P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)}, @@ -761,4 +851,14 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[74] = { {P13_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)}, }; +/* Connections for: usb_usb_dm_pad */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: usb_usb_dp_pad */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1] = { + {NC, NULL, 0u}, +}; + #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_usb.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_usb.c index cd80573c72f..cfbe3be6e61 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_usb.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_usb.c @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 116-BGA-USB package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -146,6 +146,91 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = { {P7_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_5_BLESS_EXT_PA_TX_CTL_OUT)}, }; +/* Connections for: bless_mxd_act_bpktctl */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_rx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_tx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_txd_rxd */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_act_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_buck_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_clk_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_dig_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_isolate_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_mxd_clk_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_clk */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_data */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_le */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_reset_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_ldo_ol_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_switch_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_xtal_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_dsi_comp0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = { {P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)}, @@ -156,6 +241,11 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = { {P8_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_3_LPCOMP_DSI_COMP1)}, }; +/* Connections for: lpcomp_inn_comp0 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_inn_comp1 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = { {P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)}, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga.c index 82ad6c7f035..5c60a3377b7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga.c @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 124-BGA package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -191,6 +191,11 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1] = {P2_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P2_5_BLESS_MXD_DPSLP_ISOLATE_N)}, }; +/* Connections for: bless_mxd_dpslp_mxd_clk_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: bless_mxd_dpslp_rcb_clk */ const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1] = { {P4_0, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P4_0_BLESS_MXD_DPSLP_RCB_CLK)}, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga_sip.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga_sip.c index 4f49bd88846..b054780a44e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga_sip.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga_sip.c @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 124-BGA-SIP package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -146,6 +146,91 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = { {P7_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_5_BLESS_EXT_PA_TX_CTL_OUT)}, }; +/* Connections for: bless_mxd_act_bpktctl */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_rx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_tx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_txd_rxd */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_act_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_buck_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_clk_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_dig_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_isolate_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_mxd_clk_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_clk */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_data */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_le */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_reset_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_ldo_ol_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_switch_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_xtal_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_dsi_comp0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = { {P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)}, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_43_smt.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_43_smt.c index b34927bc866..99139febff6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_43_smt.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_43_smt.c @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 43-SMT package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -118,6 +118,121 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1] = { {P5_2, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_2_AUDIOSS_TX_WS)}, }; +/* Connections for: bless_ext_lna_rx_ctl_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_ext_pa_lna_chip_en_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_ext_pa_tx_ctl_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_bpktctl */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_rx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_tx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_txd_rxd */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_act_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_buck_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_clk_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_dig_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_isolate_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_mxd_clk_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_clk */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_data */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_le */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_reset_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_ldo_ol_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_switch_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_xtal_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: lpcomp_dsi_comp0 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: lpcomp_dsi_comp1 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: lpcomp_inn_comp0 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_inn_comp1 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = { {P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)}, @@ -375,6 +490,71 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[5] = { {P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)}, }; +/* Connections for: smif_spi_clk */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data0 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data1 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data2 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data3 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data4 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data5 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data6 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data7 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_select0 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_select1 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_select2 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_select3 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: tcpwm_line */ const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38] = { {P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, @@ -455,4 +635,14 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[34] = { {P12_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)}, }; +/* Connections for: usb_usb_dm_pad */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: usb_usb_dp_pad */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1] = { + {NC, NULL, 0u}, +}; + #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_68_qfn_ble.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_68_qfn_ble.c index 66721cf96ad..f16ceef0711 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_68_qfn_ble.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_68_qfn_ble.c @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 68-QFN-BLE package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -73,6 +73,51 @@ static const cyhal_resource_inst_t CYHAL_TCPWM_1_8 = { CYHAL_RSC_TCPWM, 1, 8 }; static const cyhal_resource_inst_t CYHAL_TCPWM_1_9 = { CYHAL_RSC_TCPWM, 1, 9 }; /* Pin connections */ +/* Connections for: audioss_clk_i2s_if */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: audioss_pdm_clk */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: audioss_pdm_data */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: audioss_rx_sck */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: audioss_rx_sdi */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: audioss_rx_ws */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: audioss_tx_sck */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: audioss_tx_sdo */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: audioss_tx_ws */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: bless_ext_lna_rx_ctl_out */ const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1] = { {P7_4, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_4_BLESS_EXT_LNA_RX_CTL_OUT)}, @@ -88,16 +133,116 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = { {P7_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_5_BLESS_EXT_PA_TX_CTL_OUT)}, }; +/* Connections for: bless_mxd_act_bpktctl */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_rx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_tx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_txd_rxd */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_act_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_buck_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_clk_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_dig_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_isolate_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_mxd_clk_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_clk */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_data */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_le */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_reset_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_ldo_ol_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_switch_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_xtal_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_dsi_comp0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = { {P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)}, }; +/* Connections for: lpcomp_dsi_comp1 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: lpcomp_inn_comp0 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_inn_comp1 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = { {P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)}, }; +/* Connections for: lpcomp_inp_comp0 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_inp_comp1 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1] = { {P6_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_2_LPCOMP_INP_COMP1)}, @@ -121,6 +266,11 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4] = { {P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_PADS3)}, }; +/* Connections for: pass_ctdac_voutsw */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: pass_dsi_ctb_cmp0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1] = { {P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_2_PASS_DSI_CTB_CMP0)}, @@ -385,6 +535,26 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = { {P11_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_3_SMIF_SPI_DATA3)}, }; +/* Connections for: smif_spi_data4 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data5 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data6 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data7 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: smif_spi_select0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = { {P11_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0)}, @@ -400,6 +570,11 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1] = { {P11_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2)}, }; +/* Connections for: smif_spi_select3 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: tcpwm_line */ const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[40] = { {P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, @@ -486,4 +661,14 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[38] = { {P12_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)}, }; +/* Connections for: usb_usb_dm_pad */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: usb_usb_dp_pad */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1] = { + {NC, NULL, 0u}, +}; + #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_80_wlcsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_80_wlcsp.c index 83a14f8684b..32f8410d03c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_80_wlcsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_80_wlcsp.c @@ -5,7 +5,7 @@ * PSoC6_01 device GPIO HAL header for 80-WLCSP package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -127,6 +127,106 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1] = { {P5_2, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_2_AUDIOSS_TX_WS)}, }; +/* Connections for: bless_ext_lna_rx_ctl_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_ext_pa_lna_chip_en_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_ext_pa_tx_ctl_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_bpktctl */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_rx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_dbus_tx_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_act_txd_rxd */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_act_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_buck_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_clk_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_dig_ldo_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_isolate_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_mxd_clk_out */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_clk */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_data */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_rcb_le */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_reset_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_ldo_ol_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_ret_switch_hv */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: bless_mxd_dpslp_xtal_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_dsi_comp0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = { {P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)}, @@ -177,6 +277,11 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[6] = { {P9_7, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_7_PASS_CTB_PADS7)}, }; +/* Connections for: pass_ctdac_voutsw */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: pass_dsi_ctb_cmp0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1] = { {P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_2_PASS_DSI_CTB_CMP0)}, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_100_wlcsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_100_wlcsp.c index 298faf44b5d..eff52802c56 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_100_wlcsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_100_wlcsp.c @@ -5,7 +5,7 @@ * PSoC6_02 device GPIO HAL header for 100-WLCSP package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_124_bga.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_124_bga.c index 8bfffc03aa3..04c906e0ef6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_124_bga.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_124_bga.c @@ -5,7 +5,7 @@ * PSoC6_02 device GPIO HAL header for 124-BGA package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_128_tqfp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_128_tqfp.c index c4ee97aa0c9..4a0fe2db8d8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_128_tqfp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_128_tqfp.c @@ -5,7 +5,7 @@ * PSoC6_02 device GPIO HAL header for 128-TQFP package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_68_qfn.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_68_qfn.c index 8623569b411..b08ff8ecb63 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_68_qfn.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_68_qfn.c @@ -5,7 +5,7 @@ * PSoC6_02 device GPIO HAL header for 68-QFN package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -133,6 +133,16 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[2] = { {P11_2, &CYHAL_I2S_1, CYHAL_PIN_OUT_FUNCTION(P11_2_AUDIOSS1_TX_WS)}, }; +/* Connections for: lpcomp_dsi_comp0 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: lpcomp_dsi_comp1 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_inn_comp0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1] = { {P5_7, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_7_LPCOMP_INN_COMP0)}, @@ -434,11 +444,21 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4] = { {P2_3, &CYHAL_SDHC_0, CYHAL_PIN_OUT_BUF_FUNCTION(P2_3_SDHC0_CARD_DAT_3TO03)}, }; +/* Connections for: sdhc_card_dat_7to4 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: sdhc_card_detect_n */ const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1] = { {P2_6, &CYHAL_SDHC_0, CYHAL_PIN_IN_FUNCTION(P2_6_SDHC0_CARD_DETECT_N)}, }; +/* Connections for: sdhc_card_emmc_reset_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: sdhc_card_if_pwr_en */ const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2] = { {P3_1, &CYHAL_SDHC_0, CYHAL_PIN_OUT_FUNCTION(P3_1_SDHC0_CARD_IF_PWR_EN)}, @@ -461,6 +481,11 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2] = { {P12_7, &CYHAL_SDHC_1, CYHAL_PIN_OUT_FUNCTION(P12_7_SDHC1_IO_VOLT_SEL)}, }; +/* Connections for: sdhc_led_ctrl */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: smif_spi_clk */ const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = { {P11_7, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_7_SMIF_SPI_CLK)}, @@ -486,6 +511,26 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = { {P11_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_3_SMIF_SPI_DATA3)}, }; +/* Connections for: smif_spi_data4 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data5 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data6 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_data7 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: smif_spi_select0 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = { {P11_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0)}, @@ -501,6 +546,11 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1] = { {P11_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2)}, }; +/* Connections for: smif_spi_select3 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: tcpwm_line */ const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[50] = { {P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_100_tqfp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_100_tqfp.c index 53c6faf8194..b3dd0ba45f0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_100_tqfp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_100_tqfp.c @@ -5,7 +5,7 @@ * PSoC6_03 device GPIO HAL header for 100-TQFP package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -32,7 +32,7 @@ #include "pin_packages/cyhal_psoc6_03_100_tqfp.h" /* Hardware Blocks */ -static const cyhal_resource_inst_t CYHAL_CANFD_0 = { CYHAL_RSC_CANFD, 0, 0 }; +static const cyhal_resource_inst_t CYHAL_CAN_0 = { CYHAL_RSC_CAN, 0, 0 }; static const cyhal_resource_inst_t CYHAL_LPCOMP_0_0 = { CYHAL_RSC_LPCOMP, 0, 0 }; static const cyhal_resource_inst_t CYHAL_ADC_0 = { CYHAL_RSC_ADC, 0, 0 }; static const cyhal_resource_inst_t CYHAL_SCB_0 = { CYHAL_RSC_SCB, 0, 0 }; @@ -59,14 +59,14 @@ static const cyhal_resource_inst_t CYHAL_TCPWM_1_7 = { CYHAL_RSC_TCPWM, 1, 7 }; static const cyhal_resource_inst_t CYHAL_USB_0 = { CYHAL_RSC_USB, 0, 0 }; /* Pin connections */ -/* Connections for: canfd_ttcan_rx */ -const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1] = { - {P5_0, &CYHAL_CANFD_0, CYHAL_PIN_IN_FUNCTION(P5_0_CANFD0_TTCAN_RX0)}, +/* Connections for: can_ttcan_rx */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1] = { + {P5_0, &CYHAL_CAN_0, CYHAL_PIN_IN_FUNCTION(P5_0_CANFD0_TTCAN_RX0)}, }; -/* Connections for: canfd_ttcan_tx */ -const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1] = { - {P5_1, &CYHAL_CANFD_0, CYHAL_PIN_OUT_FUNCTION(P5_1_CANFD0_TTCAN_TX0)}, +/* Connections for: can_ttcan_tx */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1] = { + {P5_1, &CYHAL_CAN_0, CYHAL_PIN_OUT_FUNCTION(P5_1_CANFD0_TTCAN_TX0)}, }; /* Connections for: lpcomp_dsi_comp0 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_49_wlcsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_49_wlcsp.c index 9f67112d734..4cc2c807926 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_49_wlcsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_49_wlcsp.c @@ -5,7 +5,7 @@ * PSoC6_03 device GPIO HAL header for 49-WLCSP package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -32,7 +32,7 @@ #include "pin_packages/cyhal_psoc6_03_49_wlcsp.h" /* Hardware Blocks */ -static const cyhal_resource_inst_t CYHAL_CANFD_0 = { CYHAL_RSC_CANFD, 0, 0 }; +static const cyhal_resource_inst_t CYHAL_CAN_0 = { CYHAL_RSC_CAN, 0, 0 }; static const cyhal_resource_inst_t CYHAL_LPCOMP_0_0 = { CYHAL_RSC_LPCOMP, 0, 0 }; static const cyhal_resource_inst_t CYHAL_ADC_0 = { CYHAL_RSC_ADC, 0, 0 }; static const cyhal_resource_inst_t CYHAL_SCB_0 = { CYHAL_RSC_SCB, 0, 0 }; @@ -56,14 +56,29 @@ static const cyhal_resource_inst_t CYHAL_TCPWM_1_6 = { CYHAL_RSC_TCPWM, 1, 6 }; static const cyhal_resource_inst_t CYHAL_TCPWM_1_7 = { CYHAL_RSC_TCPWM, 1, 7 }; /* Pin connections */ -/* Connections for: canfd_ttcan_rx */ -const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1] = { - {P5_0, &CYHAL_CANFD_0, CYHAL_PIN_IN_FUNCTION(P5_0_CANFD0_TTCAN_RX0)}, +/* Connections for: can_ttcan_rx */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1] = { + {P5_0, &CYHAL_CAN_0, CYHAL_PIN_IN_FUNCTION(P5_0_CANFD0_TTCAN_RX0)}, }; -/* Connections for: canfd_ttcan_tx */ -const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1] = { - {P5_1, &CYHAL_CANFD_0, CYHAL_PIN_OUT_FUNCTION(P5_1_CANFD0_TTCAN_TX0)}, +/* Connections for: can_ttcan_tx */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1] = { + {P5_1, &CYHAL_CAN_0, CYHAL_PIN_OUT_FUNCTION(P5_1_CANFD0_TTCAN_TX0)}, +}; + +/* Connections for: lpcomp_dsi_comp0 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: lpcomp_dsi_comp1 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: lpcomp_inn_comp0 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1] = { + {NC, NULL, 0u}, }; /* Connections for: lpcomp_inn_comp1 */ @@ -71,6 +86,11 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = { {P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)}, }; +/* Connections for: lpcomp_inp_comp0 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: lpcomp_inp_comp1 */ const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1] = { {P6_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_2_LPCOMP_INP_COMP1)}, @@ -285,11 +305,31 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4] = { {P2_3, &CYHAL_SDHC_0, CYHAL_PIN_OUT_BUF_FUNCTION(P2_3_SDHC0_CARD_DAT_3TO03)}, }; +/* Connections for: sdhc_card_detect_n */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: sdhc_card_if_pwr_en */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: sdhc_card_mech_write_prot */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: sdhc_clk_card */ const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1] = { {P2_5, &CYHAL_SDHC_0, CYHAL_PIN_OUT_BUF_FUNCTION(P2_5_SDHC0_CLK_CARD)}, }; +/* Connections for: sdhc_io_volt_sel */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: smif_spi_clk */ const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = { {P11_7, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_7_SMIF_SPI_CLK)}, @@ -320,6 +360,16 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = { {P11_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0)}, }; +/* Connections for: smif_spi_select1 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: smif_spi_select2 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1] = { + {NC, NULL, 0u}, +}; + /* Connections for: tcpwm_line */ const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38] = { {P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, @@ -402,4 +452,14 @@ const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[36] = { {P11_7, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P11_7_TCPWM1_LINE_COMPL5)}, }; +/* Connections for: usb_usb_dm_pad */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: usb_usb_dp_pad */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1] = { + {NC, NULL, 0u}, +}; + #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_68_qfn.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_68_qfn.c index a75ca0a5097..f9ff30a847e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_68_qfn.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_68_qfn.c @@ -5,7 +5,7 @@ * PSoC6_03 device GPIO HAL header for 68-QFN package * * \note -* Generator version: 1.4.7107.26790 +* Generator version: 1.4.7153.30079 * ******************************************************************************** * \copyright @@ -32,7 +32,7 @@ #include "pin_packages/cyhal_psoc6_03_68_qfn.h" /* Hardware Blocks */ -static const cyhal_resource_inst_t CYHAL_CANFD_0 = { CYHAL_RSC_CANFD, 0, 0 }; +static const cyhal_resource_inst_t CYHAL_CAN_0 = { CYHAL_RSC_CAN, 0, 0 }; static const cyhal_resource_inst_t CYHAL_LPCOMP_0_0 = { CYHAL_RSC_LPCOMP, 0, 0 }; static const cyhal_resource_inst_t CYHAL_ADC_0 = { CYHAL_RSC_ADC, 0, 0 }; static const cyhal_resource_inst_t CYHAL_SCB_0 = { CYHAL_RSC_SCB, 0, 0 }; @@ -59,14 +59,24 @@ static const cyhal_resource_inst_t CYHAL_TCPWM_1_7 = { CYHAL_RSC_TCPWM, 1, 7 }; static const cyhal_resource_inst_t CYHAL_USB_0 = { CYHAL_RSC_USB, 0, 0 }; /* Pin connections */ -/* Connections for: canfd_ttcan_rx */ -const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1] = { - {P5_0, &CYHAL_CANFD_0, CYHAL_PIN_IN_FUNCTION(P5_0_CANFD0_TTCAN_RX0)}, +/* Connections for: can_ttcan_rx */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1] = { + {P5_0, &CYHAL_CAN_0, CYHAL_PIN_IN_FUNCTION(P5_0_CANFD0_TTCAN_RX0)}, }; -/* Connections for: canfd_ttcan_tx */ -const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1] = { - {P5_1, &CYHAL_CANFD_0, CYHAL_PIN_OUT_FUNCTION(P5_1_CANFD0_TTCAN_TX0)}, +/* Connections for: can_ttcan_tx */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1] = { + {P5_1, &CYHAL_CAN_0, CYHAL_PIN_OUT_FUNCTION(P5_1_CANFD0_TTCAN_TX0)}, +}; + +/* Connections for: lpcomp_dsi_comp0 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = { + {NC, NULL, 0u}, +}; + +/* Connections for: lpcomp_dsi_comp1 */ +const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = { + {NC, NULL, 0u}, }; /* Connections for: lpcomp_inn_comp0 */ From 459666f8f21f94b678cc15926bdcc18eb33d950c Mon Sep 17 00:00:00 2001 From: Ryan Morse Date: Tue, 27 Aug 2019 00:42:20 +0100 Subject: [PATCH 2/4] Fixed issue in QSPI when there aren't 8 pins --- .../TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c index cc204b4dcc8..238bf1a3e2f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c @@ -598,8 +598,8 @@ cy_rslt_t cyhal_qspi_init( result = CYHAL_QSPI_RSLT_ERR_PIN; } } - break; #endif + break; case CY_SMIF_DATA_SEL1: if (max_width >= CYHAL_QSPI_CFG_BUS_DUAL) { From 8ad377add305119bb15d78d314f3e67936a63c94 Mon Sep 17 00:00:00 2001 From: Shuopeng Deng Date: Mon, 26 Aug 2019 10:47:06 -0700 Subject: [PATCH 3/4] Fix I2C handling of 1 byte external memory address --- .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c | 30 ++++++++++++++++--- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c index f696bd0b67c..4b979bb47bd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c @@ -400,8 +400,19 @@ cy_rslt_t cyhal_i2c_slave_config_read_buff(cyhal_i2c_t *obj, uint8_t *data, uint cy_rslt_t cyhal_i2c_master_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, const uint8_t *data, uint16_t size, uint32_t timeout) { uint8_t mem_addr_buf[2]; - mem_addr_buf[0] = (uint8_t)(mem_addr >> 8); - mem_addr_buf[1] = (uint8_t)mem_addr; + if (mem_addr_size == 1) + { + mem_addr_buf[0] = (uint8_t)mem_addr; + } + else if (mem_addr_size == 2) + { + mem_addr_buf[0] = (uint8_t)(mem_addr >> 8); + mem_addr_buf[1] = (uint8_t)mem_addr; + } + else + { + return CYHAL_I2C_RSLT_ERR_INVALID_ADDRESS_SIZE; + } cy_rslt_t status = cyhal_i2c_master_write(obj, address, mem_addr_buf, mem_addr_size, timeout, false); @@ -427,8 +438,19 @@ cy_rslt_t cyhal_i2c_master_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_ cy_rslt_t cyhal_i2c_master_mem_read(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, uint8_t *data, uint16_t size, uint32_t timeout) { uint8_t mem_addr_buf[2]; - mem_addr_buf[0] = (uint8_t)(mem_addr >> 8); - mem_addr_buf[1] = (uint8_t)mem_addr; + if (mem_addr_size == 1) + { + mem_addr_buf[0] = (uint8_t)mem_addr; + } + else if (mem_addr_size == 2) + { + mem_addr_buf[0] = (uint8_t)(mem_addr >> 8); + mem_addr_buf[1] = (uint8_t)mem_addr; + } + else + { + return CYHAL_I2C_RSLT_ERR_INVALID_ADDRESS_SIZE; + } cy_rslt_t status = cyhal_i2c_master_write(obj, address, mem_addr_buf, mem_addr_size, timeout, false); if (status == CY_RSLT_SUCCESS) From 5c899a3350a2dae5447dfd63f7086ee85ef245ff Mon Sep 17 00:00:00 2001 From: Ryan Morse Date: Tue, 27 Aug 2019 12:52:10 -0700 Subject: [PATCH 4/4] Bug fixes to interrupt/event handling in SDHC HAL --- .../psoc6csp/hal/include/cyhal_sdhc.h | 46 ++--- .../psoc6csp/hal/src/cyhal_sdhc.c | 172 ++++++++++++------ 2 files changed, 137 insertions(+), 81 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h index c1e400d44b7..51d1a3b5b21 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h @@ -76,23 +76,23 @@ typedef enum /** SDHC interrupt triggers */ typedef enum { - CYHAL_SDHC_CMD_COMPLETE, //!> Command Complete - CYHAL_SDHC_XFER_COMPLETE, //!> Host read/write transfer is complete - CYHAL_SDHC_BGAP_EVENT, //!> This bit is set when both read/write transaction is stopped - CYHAL_SDHC_DMA_INTERRUPT, //!> Host controller detects an SDMA Buffer Boundary during transfer - CYHAL_SDHC_BUF_WR_READY, //!> This bit is set if the Buffer Write Enable changes from 0 to 1 - CYHAL_SDHC_BUF_RD_READY, //!> This bit is set if the Buffer Read Enable changes from 0 to 1 - CYHAL_SDHC_CARD_INSERTION, //!> This bit is set if the Card Inserted in the Present State - CYHAL_SDHC_CARD_REMOVAL, //!> This bit is set if the Card Inserted in the Present State - CYHAL_SDHC_CARD_INTERRUPT, //!> The synchronized value of the DAT[1] interrupt input for SD mode - CYHAL_SDHC_INT_A, - CYHAL_SDHC_INT_B, - CYHAL_SDHC_INT_C, - CYHAL_SDHC_RE_TUNE_EVENT, //!> This bit is set if the Re-Tuning Request changes from 0 to 1 - CYHAL_SDHC_FX_EVENT, //!> This status is set when R[14] of response register is set to 1 - CYHAL_SDHC_CQE_EVENT, //!> This status is set if Command Queuing/Crypto event has occurred - CYHAL_SDHC_ERR_INTERRUPT, //!> If any of the bits in the Error Interrupt Status register are set - CYHAL_SDHC_ALL_INTERRUPTS, //!> Is used to enable/disable all interrupts + CYHAL_SDHC_CMD_COMPLETE = 0x0001, //!> Command Complete + CYHAL_SDHC_XFER_COMPLETE = 0x0002, //!> Host read/write transfer is complete + CYHAL_SDHC_BGAP_EVENT = 0x0004, //!> This bit is set when both read/write transaction is stopped at the block gap + CYHAL_SDHC_DMA_INTERRUPT = 0x0008, //!> Host controller detects an SDMA Buffer Boundary during transfer + CYHAL_SDHC_BUF_WR_READY = 0x0010, //!> This bit is set if the Buffer Write Enable changes from 0 to 1 + CYHAL_SDHC_BUF_RD_READY = 0x0020, //!> This bit is set if the Buffer Read Enable changes from 0 to 1 + CYHAL_SDHC_CARD_INSERTION = 0x0040, //!> This bit is set if the Card Inserted in the Present State register changes from 0 to 1. + CYHAL_SDHC_CARD_REMOVAL = 0x0080, //!> This bit is set if the Card Inserted in the Present State register changes from 1 to 0. + CYHAL_SDHC_CARD_INTERRUPT = 0x0100, //!> The synchronized value of the DAT[1] interrupt input for SD mode + CYHAL_SDHC_INT_A = 0x0200, + CYHAL_SDHC_INT_B = 0x0400, + CYHAL_SDHC_INT_C = 0x0800, + CYHAL_SDHC_RE_TUNE_EVENT = 0x1000, //!> This bit is set if the Re-Tuning Request changes from 0 to 1 + CYHAL_SDHC_FX_EVENT = 0x2000, //!> This status is set when R[14] of response register is set to 1 + CYHAL_SDHC_CQE_EVENT = 0x4000, //!> This status is set if Command Queuing/Crypto event has occurred + CYHAL_SDHC_ERR_INTERRUPT = 0x8000, //!> If any of the bits in the Error Interrupt Status register are set + CYHAL_SDHC_ALL_INTERRUPTS = 0xFFFF, //!> Is used to enable/disable all interrupts } cyhal_sdhc_event_t; /** \} group_hal_sdhc_enums */ @@ -121,7 +121,7 @@ typedef struct { bool enableLedControl; //!< Drive one IO to indicate when the card is being accessed bool lowVoltageSignaling; //!< Whether 1.8V signaling is supported - bool isEmmc; //!< true if eMMC card, other way false + bool isEmmc; //!< true if eMMC card, otherwise false uint8_t busWidth; //!< The desired bus width } cyhal_sdhc_config_t; @@ -186,7 +186,7 @@ void cyhal_sdhc_free(cyhal_sdhc_t *obj); * @param[in] obj The SDHC object * @param[in] address The address to read data from * @param[out] data Pointer to the byte-array of data to read from the device - * @param[in,out] length Number of bytes to read, updated with the number actually read + * @param[in,out] length Number of 512 byte blocks to read, updated with the number actually read * @return The status of the read request */ cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *data, size_t *length); @@ -196,7 +196,7 @@ cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *da * @param[in] obj The SDHC object * @param[in] address The address to write data to * @param[in] data Pointer to the byte-array of data to write to the device - * @param[in,out] length Number of bytes to read, updated with the number actually read + * @param[in,out] length Number of 512 byte blocks to write, updated with the number actually written * @return The status of the write request */ cy_rslt_t cyhal_sdhc_write(const cyhal_sdhc_t *obj, uint32_t address, const uint8_t *data, size_t *length); @@ -205,7 +205,7 @@ cy_rslt_t cyhal_sdhc_write(const cyhal_sdhc_t *obj, uint32_t address, const uint * * @param[in] obj The SDHC object * @param[in] startAddr Is the address of the first byte to erase - * @param[in] length The number of bytes (starting at startAddr) to erase + * @param[in] length Number of 512 byte blocks (starting at startAddr) to erase * @return The status of the erase request */ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t length); @@ -215,7 +215,7 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t l * @param[in] obj The SDHC object that holds the transfer information * @param[in] address The address to read data from * @param[out] data The receive buffer - * @param[in,out] length Number of bytes to read, updated with the number actually read + * @param[in,out] length Number of 512 byte blocks to read, updated with the number actually read * @return The status of the read_async request */ cy_rslt_t cyhal_sdhc_read_async(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *data, size_t *length); @@ -225,7 +225,7 @@ cy_rslt_t cyhal_sdhc_read_async(const cyhal_sdhc_t *obj, uint32_t address, uint8 * @param[in] obj The SDHC object that holds the transfer information * @param[in] address The address to write data to * @param[in] data The transmit buffer - * @param[in,out] length Number of bytes to read, updated with the number actually read + * @param[in,out] length The number of 512 byte blocks to write, updated with the number actually written * @return The status of the write_async request */ cy_rslt_t cyhal_sdhc_write_async(const cyhal_sdhc_t *obj, uint32_t address, const uint8_t *data, size_t *length); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c index 167bfb14522..b3bc8c5ad97 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c @@ -135,6 +135,15 @@ extern "C" #define CYHAL_SDIO_DS_CB_ORDER (0U) #endif /* !defined(CYHAL_SDIO_DS_CB_ORDER) */ +/* Defines for mapping sdhc events on interrupts */ +#define SDHC_EVENTS_NUM (12U) +#define SDHC_EVENTS_MAP_NUM (2U) + +#define SDHC_EVENT (0U) +#define SDHC_ISR (1U) + + + /* List of available SDHC instances */ static SDHC_Type * const CYHAL_SDHC_BASE_ADDRESSES[CY_IP_MXSDHC_INSTANCES] = { @@ -197,6 +206,24 @@ static uint8_t cyhal_sd_get_block_from_irqn(IRQn_Type irqn) static void *cyhal_sd_config_structs[CY_IP_MXSDHC_INSTANCES]; + +/* Structure to map SDHC events on SDHC interrupts */ +const uint32_t eventMap[SDHC_EVENTS_NUM][SDHC_EVENTS_MAP_NUM] = +{ + { (uint32_t)CYHAL_SDHC_CMD_COMPLETE, (uint32_t)CY_SD_HOST_CMD_COMPLETE}, + { (uint32_t)CYHAL_SDHC_XFER_COMPLETE, (uint32_t)CY_SD_HOST_XFER_COMPLETE }, + { (uint32_t)CYHAL_SDHC_BGAP_EVENT, (uint32_t)CY_SD_HOST_BGAP }, + { (uint32_t)CYHAL_SDHC_DMA_INTERRUPT, (uint32_t)CY_SD_HOST_DMA_INTERRUPT }, + { (uint32_t)CYHAL_SDHC_BUF_WR_READY, (uint32_t)CY_SD_HOST_BUF_WR_READY }, + { (uint32_t)CYHAL_SDHC_BUF_RD_READY, (uint32_t)CY_SD_HOST_BUF_RD_READY }, + { (uint32_t)CYHAL_SDHC_CARD_INSERTION, (uint32_t)CY_SD_HOST_CARD_INSERTION }, + { (uint32_t)CYHAL_SDHC_CARD_REMOVAL, (uint32_t)CY_SD_HOST_CARD_REMOVAL }, + { (uint32_t)CYHAL_SDHC_CARD_INTERRUPT, (uint32_t)CY_SD_HOST_CARD_INTERRUPT }, + { (uint32_t)CYHAL_SDHC_FX_EVENT, (uint32_t)CY_SD_HOST_FX_EVENT }, + { (uint32_t)CYHAL_SDHC_CQE_EVENT, (uint32_t)CY_SD_HOST_CQE_EVENT }, + { (uint32_t)CYHAL_SDHC_ERR_INTERRUPT, (uint32_t)CY_SD_HOST_ERR_INTERRUPT }, +}; + static void release_pin_if_used(cyhal_gpio_t *pin) { if (CYHAL_NC_PIN_VALUE != *pin) @@ -248,6 +275,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint static cy_en_sd_host_bus_width_t convert_buswidth(uint8_t stopbits); static cy_en_syspm_status_t cyhal_sdio_syspm_callback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode); +static cyhal_sdhc_event_t get_event_from_isr(uint32_t asserted_interrupt); /******************************************************************************* * Deep Sleep Callback Service Routine @@ -484,21 +512,20 @@ static void cyhal_sdhc_irq_handler(void) uint32_t interruptStatus = Cy_SD_Host_GetNormalInterruptStatus(blockAddr); uint32_t userInterruptStatus = interruptStatus & obj->irq_cause; + cyhal_sdhc_event_t user_events = get_event_from_isr(userInterruptStatus); if (obj->callback_data.callback != NULL) { cyhal_sdhc_event_callback_t callback = (cyhal_sdhc_event_callback_t) obj->callback_data.callback; + /* Call registered callbacks here */ - (void) (callback) (obj->callback_data.callback_arg, (cyhal_sdhc_event_t) userInterruptStatus); + (void) (callback) (obj->callback_data.callback_arg, user_events); } /* Clear only handled events */ - Cy_SD_Host_ClearNormalInterruptStatus(blockAddr, userInterruptStatus); + Cy_SD_Host_ClearNormalInterruptStatus(blockAddr, interruptStatus); - /* To clear SD Card interrupt need to disable SD Card Interrupt Enable bit. - * The SD Card interrupt is enabled in the bulk transfer function later on - * the next data transfer. - */ + /* To clear SD Card interrupt need to disable SD Card Interrupt Enable bit */ if (0U != (interruptStatus & CY_SD_HOST_CARD_INTERRUPT)) { uint32_t interruptMask = Cy_SD_Host_GetNormalInterruptEnable(blockAddr); @@ -507,7 +534,26 @@ static void cyhal_sdhc_irq_handler(void) /* Disable SD Card interrupt */ Cy_SD_Host_SetNormalInterruptEnable(blockAddr, interruptMask); } +} +static cyhal_sdhc_event_t get_event_from_isr(uint32_t asserted_interrupt) +{ + cyhal_sdhc_event_t anded_events = (cyhal_sdhc_event_t) 0U; + + for (uint8_t i = 0; i < SDHC_EVENTS_NUM; i++) + { + const uint32_t *map_entry = eventMap[i]; + + /* Anded events should be handled in user callback function as only + * there exist the knowledge of enabled events + */ + if ((asserted_interrupt & map_entry[SDHC_ISR]) != 0) + { + anded_events |= map_entry[SDHC_EVENT]; + } + } + + return anded_events; } cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, @@ -680,7 +726,7 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, /* Do not support eMMC card */ obj->emmc = config->isEmmc; - obj->dmaType = CY_SD_HOST_DMA_SDMA; + obj->dmaType = CY_SD_HOST_DMA_ADMA2; /* Configure SD Host to operate */ cy_stc_sd_host_init_config_t hostConfig; @@ -807,6 +853,7 @@ cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *da cy_rslt_t ret = CY_RSLT_SUCCESS; cy_en_sd_host_status_t driverRet; cy_stc_sd_host_write_read_config_t dataConfig; + uint32_t regIntrSts = Cy_SD_Host_GetNormalInterruptMask(obj->base); dataConfig.data = (uint32_t*)data; /* The pointer to data. */ dataConfig.address = address; /* The address to write/read data on the card or eMMC. */ @@ -818,6 +865,12 @@ cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *da dataConfig.enReliableWrite = false; /* For EMMC cards enable reliable write. */ dataConfig.enableDma = true; + /* First clear out the transfer and command complete statuses */ + Cy_SD_Host_ClearNormalInterruptStatus(obj->base, (CY_SD_HOST_XFER_COMPLETE | CY_SD_HOST_CMD_COMPLETE)); + + /* Disable CMD Done interrupt, will be enabled after transition is complete */ + Cy_SD_Host_SetNormalInterruptMask(obj->base, (regIntrSts & (uint32_t)~(CY_SD_HOST_XFER_COMPLETE | CY_SD_HOST_CMD_COMPLETE))); + driverRet = Cy_SD_Host_Read(obj->base, &dataConfig, &obj->context); if (CY_SD_HOST_SUCCESS != driverRet) @@ -834,8 +887,11 @@ cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *da } } + /* Restore interrupts after transition */ + Cy_SD_Host_SetNormalInterruptMask(obj->base, regIntrSts); + /* Enable SD Card interrupt because it was disabled in interrupt handler */ - if ((uint32_t) CYHAL_SDHC_CARD_INTERRUPT == ((uint32_t)CYHAL_SDHC_CARD_INTERRUPT & obj->irq_cause)) + if (0U != (obj->irq_cause & CY_SD_HOST_CARD_INTERRUPT)) { uint32_t intrStsEn = Cy_SD_Host_GetNormalInterruptEnable(obj->base); @@ -851,6 +907,7 @@ cy_rslt_t cyhal_sdhc_write(const cyhal_sdhc_t *obj, uint32_t address, const uint cy_rslt_t ret = CY_RSLT_SUCCESS; cy_en_sd_host_status_t driverRet; cy_stc_sd_host_write_read_config_t dataConfig; + uint32_t regIntrSts = Cy_SD_Host_GetNormalInterruptMask(obj->base); dataConfig.data = (uint32_t*)data; /* The pointer to data. */ dataConfig.address = address; /* The address to write/read data on the card or eMMC. */ @@ -862,6 +919,12 @@ cy_rslt_t cyhal_sdhc_write(const cyhal_sdhc_t *obj, uint32_t address, const uint dataConfig.enReliableWrite = false; /* For EMMC cards enable reliable write. */ dataConfig.enableDma = true; + /* First clear out the transfer and command complete statuses */ + Cy_SD_Host_ClearNormalInterruptStatus(obj->base, (CY_SD_HOST_XFER_COMPLETE | CY_SD_HOST_CMD_COMPLETE)); + + /* Disable CMD Done interrupt, will be enabled after transition is complete */ + Cy_SD_Host_SetNormalInterruptMask(obj->base, (regIntrSts & (uint32_t)~(CY_SD_HOST_XFER_COMPLETE | CY_SD_HOST_CMD_COMPLETE))); + driverRet = Cy_SD_Host_Write(obj->base, &dataConfig, &obj->context); if (CY_SD_HOST_SUCCESS != driverRet) @@ -878,8 +941,11 @@ cy_rslt_t cyhal_sdhc_write(const cyhal_sdhc_t *obj, uint32_t address, const uint } } + /* Restore interrupts after transition */ + Cy_SD_Host_SetNormalInterruptMask(obj->base, regIntrSts); + /* Enable SD Card interrupt because it was disabled in interrupt handler */ - if ((uint32_t) CYHAL_SDHC_CARD_INTERRUPT == ((uint32_t)CYHAL_SDHC_CARD_INTERRUPT & obj->irq_cause)) + if (0U != (obj->irq_cause & CY_SD_HOST_CARD_INTERRUPT)) { uint32_t intrStsEn = Cy_SD_Host_GetNormalInterruptEnable(obj->base); @@ -897,20 +963,29 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t l cy_en_sd_host_erase_type_t eraseType = CY_SD_HOST_ERASE_ERASE; uint32_t i = SDHC_RETRY_TIMES; uint32_t cardStatus; + uint32_t regIntrSts = Cy_SD_Host_GetNormalInterruptMask(obj->base); if (obj->emmc) { eraseType = CY_SD_HOST_ERASE_TRIM; } + /* First clear out the transfer and command complete statuses */ + Cy_SD_Host_ClearNormalInterruptStatus(obj->base, (CY_SD_HOST_XFER_COMPLETE | CY_SD_HOST_CMD_COMPLETE)); + + /* Disable CMD Done interrupt, will be enabled after transition is complete */ + Cy_SD_Host_SetNormalInterruptMask(obj->base, (regIntrSts & (uint32_t)~(CY_SD_HOST_XFER_COMPLETE | CY_SD_HOST_CMD_COMPLETE))); + driverRet = Cy_SD_Host_Erase(obj->base, startAddr, (startAddr + length), eraseType, &obj->context); if (CY_SD_HOST_SUCCESS != driverRet) { ret = CY_RSLT_TYPE_ERROR; } - - driverRet = Cy_SD_Host_PollCmdComplete(obj->base); + else + { + driverRet = Cy_SD_Host_PollCmdComplete(obj->base); + } if (CY_SD_HOST_SUCCESS != driverRet) { @@ -945,8 +1020,11 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t l Cy_SysLib_Delay(SDHC_EMMC_TRIM_DELAY_MS); } + /* Restore interrupts after transition */ + Cy_SD_Host_SetNormalInterruptMask(obj->base, regIntrSts); + /* Enable SD Card interrupt because it was disabled in interrupt handler */ - if ((uint32_t) CYHAL_SDHC_CARD_INTERRUPT == ((uint32_t)CYHAL_SDHC_CARD_INTERRUPT & obj->irq_cause)) + if (0U != (obj->irq_cause & CY_SD_HOST_CARD_INTERRUPT)) { uint32_t intrStsEn = Cy_SD_Host_GetNormalInterruptEnable(obj->base); @@ -1001,85 +1079,63 @@ void cyhal_sdhc_register_callback(cyhal_sdhc_t *obj, cyhal_sdhc_event_callback_t void cyhal_sdhc_enable_event(cyhal_sdhc_t *obj, cyhal_sdhc_event_t event, uint8_t intrPriority, bool enable) { - const uint8_t eventCount = 12; - const uint32_t eventMap[12][2] = - { - { (uint32_t)CYHAL_SDHC_CMD_COMPLETE, (uint32_t)CY_SD_HOST_CMD_COMPLETE}, - { (uint32_t)CYHAL_SDHC_XFER_COMPLETE, (uint32_t)CY_SD_HOST_XFER_COMPLETE }, - { (uint32_t)CYHAL_SDHC_BGAP_EVENT, (uint32_t)CY_SD_HOST_BGAP }, - { (uint32_t)CYHAL_SDHC_DMA_INTERRUPT, (uint32_t)CY_SD_HOST_DMA_INTERRUPT }, - { (uint32_t)CYHAL_SDHC_BUF_WR_READY, (uint32_t)CY_SD_HOST_BUF_WR_READY }, - { (uint32_t)CYHAL_SDHC_BUF_RD_READY, (uint32_t)CY_SD_HOST_BUF_RD_READY }, - { (uint32_t)CYHAL_SDHC_CARD_INSERTION, (uint32_t)CY_SD_HOST_CARD_INSERTION }, - { (uint32_t)CYHAL_SDHC_CARD_REMOVAL, (uint32_t)CY_SD_HOST_CARD_REMOVAL }, - { (uint32_t)CYHAL_SDHC_CARD_INTERRUPT, (uint32_t)CY_SD_HOST_CARD_INTERRUPT }, - { (uint32_t)CYHAL_SDHC_FX_EVENT, (uint32_t)CY_SD_HOST_FX_EVENT }, - { (uint32_t)CYHAL_SDHC_CQE_EVENT, (uint32_t)CY_SD_HOST_CQE_EVENT }, - { (uint32_t)CYHAL_SDHC_ERR_INTERRUPT, (uint32_t)CY_SD_HOST_ERR_INTERRUPT }, - }; - - uint32_t interruptMask; - uint32_t interruptEnable; - - interruptEnable = Cy_SD_Host_GetNormalInterruptEnable(obj->base); - interruptMask = Cy_SD_Host_GetNormalInterruptMask(obj->base); + uint32_t interruptMask = Cy_SD_Host_GetNormalInterruptMask(obj->base); IRQn_Type irqn = CYHAL_SDHC_IRQ_N[obj->resource.block_num]; NVIC_SetPriority(irqn, intrPriority); if(enable == true) { - obj->irq_cause |= event; - /* Enable specific interrupt */ if((uint32_t) event < (uint32_t) CYHAL_SDHC_ALL_INTERRUPTS) { - for (int i = 0; i < eventCount; i++) + obj->irq_cause |= event; + uint32_t event_count = SDHC_EVENTS_NUM; + uint8_t i; + + for (i = 0; i < event_count; i++) { const uint32_t *map_entry = eventMap[i]; - if ((map_entry[0] & obj->irq_cause) > 0) + if ((map_entry[SDHC_EVENT] & obj->irq_cause) != 0) { - interruptEnable |= map_entry[1]; - interruptMask |= map_entry[1]; + interruptMask |= map_entry[SDHC_ISR]; } } } /* Enable all interrupts */ else { - interruptEnable = SDIO_ALL_INTERRUPTS_ENABLE_MASK; - interruptMask = SDIO_SET_ALL_INTERRUPTS_MASK; - obj->irq_cause = (uint32_t) CYHAL_SDHC_ALL_INTERRUPTS; + interruptMask = SDIO_SET_ALL_INTERRUPTS_MASK; + obj->irq_cause = SDIO_SET_ALL_INTERRUPTS_MASK; } } /* Disable interrupt */ else { - obj->irq_cause &= ~event; - if((uint32_t) event < (uint32_t) CYHAL_SDHC_ALL_INTERRUPTS) { - for (int i = 0; i < eventCount; i++) + obj->irq_cause &= ~event; + uint32_t event_count = SDHC_EVENTS_NUM; + uint8_t i; + + for (i = 0; i < event_count; i++) { const uint32_t *map_entry = eventMap[i]; - if ((map_entry[0] & obj->irq_cause) > 0) + if ((map_entry[SDHC_EVENT] & obj->irq_cause) != 0) { - interruptEnable &= ~map_entry[1]; - interruptMask &= ~map_entry[1]; + interruptMask &= ~map_entry[SDHC_ISR]; } } } /* Disable all interrupts */ else { - interruptEnable = SDIO_CLEAR_ALL_INTERRUPTS_ENABLE_MASK; interruptMask = SDIO_CLEAR_ALL_INTERRUPTS_MASK; - obj->irq_cause = 0u; + obj->irq_cause = SDIO_CLEAR_ALL_INTERRUPTS_MASK; } } Cy_SD_Host_SetNormalInterruptMask(obj->base, interruptMask); - Cy_SD_Host_SetNormalInterruptEnable(obj->base, interruptEnable); } static void cyhal_sdio_irq_handler() @@ -1129,6 +1185,12 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, obj->resource.type = CYHAL_RSC_INVALID; obj->base = NULL; + obj->pin_cmd = CYHAL_NC_PIN_VALUE; + obj->pin_clk = CYHAL_NC_PIN_VALUE; + obj->pin_data0 = CYHAL_NC_PIN_VALUE; + obj->pin_data1 = CYHAL_NC_PIN_VALUE; + obj->pin_data2 = CYHAL_NC_PIN_VALUE; + obj->pin_data3 = CYHAL_NC_PIN_VALUE; result = setup_pin( cmd, cyhal_pin_map_sdhc_card_cmd, COUNT(cyhal_pin_map_sdhc_card_cmd), &(obj->pin_cmd)); @@ -1713,7 +1775,6 @@ void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, ui /* Configure interrupt-based event(s) */ if (0U != ((uint32_t) event & (uint32_t) CYHAL_SDIO_ALL_INTERRUPTS)) { - uint32_t interruptEnable = Cy_SD_Host_GetNormalInterruptEnable(obj->base); uint32_t interruptMask = Cy_SD_Host_GetNormalInterruptMask(obj->base); IRQn_Type irqn = CYHAL_SDHC_IRQ_N[obj->resource.block_num]; @@ -1721,21 +1782,16 @@ void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, ui if (enable) { - interruptEnable |= event; interruptMask |= event; - obj->irq_cause |= event; } else { - interruptEnable &= ~(event); interruptMask &= ~(event); - obj->irq_cause &= ~event; } Cy_SD_Host_SetNormalInterruptMask(obj->base, interruptMask); - Cy_SD_Host_SetNormalInterruptEnable(obj->base, interruptEnable); } /* Configure non-interrupt based event(s) */