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Update PSoC 6 BSP Targets #11323

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Update PSoC 6 BSP Targets #11323

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1171a6f
Enable SDIO DeepSleep Callback
Aug 23, 2019
567293a
Initialize timer for us_ticker at startup
Aug 20, 2019
2c5ed79
Move BSP design.modus/GenSrc into its own component
Jul 12, 2019
6669f3c
Move nested targets up one level
Jul 12, 2019
2cd3e1e
Update board hardware configuration
Aug 23, 2019
d9bb4f0
Update device startup code and linker scripts
Aug 23, 2019
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8 changes: 4 additions & 4 deletions features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -422,13 +422,13 @@ class HCIDriver : public cordio::CordioHCIDriver {

ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver() {
static ble::vendor::cypress_ble::CyH4TransportDriver transport_driver(
/* TX */ CY_BT_UART_TX, /* RX */ CY_BT_UART_RX,
/* cts */ CY_BT_UART_CTS, /* rts */ CY_BT_UART_RTS, 115200,
CY_BT_PIN_HOST_WAKE, CY_BT_PIN_DEVICE_WAKE
/* TX */ CYBSP_BT_UART_TX, /* RX */ CYBSP_BT_UART_RX,
/* cts */ CYBSP_BT_UART_CTS, /* rts */ CYBSP_BT_UART_RTS, 115200,
CYBSP_BT_HOST_WAKE, CYBSP_BT_DEVICE_WAKE
);
static ble::vendor::cypress::HCIDriver hci_driver(
transport_driver,
/* bt_power */ CY_BT_PIN_POWER
/* bt_power */ CYBSP_BT_POWER
);
return hci_driver;
}
78 changes: 76 additions & 2 deletions targets/TARGET_Cypress/TARGET_PSOC6/PinNamesTypes.h
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Expand Up @@ -19,14 +19,83 @@
#ifndef MBED_PINNAMESTYPES_H
#define MBED_PINNAMESTYPES_H

#include "cmsis.h"
#include "cyhal_gpio.h"
#include "cybsp_types.h"

// Pin Modes
#define PullNone CYHAL_GPIO_DRIVE_STRONG
#define PullDefault CYHAL_GPIO_DRIVE_ANALOG
#define PullDefault CYHAL_GPIO_DRIVE_NONE
#define PullDown CYHAL_GPIO_DRIVE_PULLDOWN
#define PullUp CYHAL_GPIO_DRIVE_PULLUP

// Arduino Headers
#ifdef CYBSP_A0
#define A0 CYBSP_A0
#endif
#ifdef CYBSP_A1
#define A1 CYBSP_A1
#endif
#ifdef CYBSP_A2
#define A2 CYBSP_A2
#endif
#ifdef CYBSP_A3
#define A3 CYBSP_A3
#endif
#ifdef CYBSP_A4
#define A4 CYBSP_A4
#endif
#ifdef CYBSP_A5
#define A5 CYBSP_A5
#endif
#ifdef CYBSP_D0
#define D0 CYBSP_D0
#endif
#ifdef CYBSP_D1
#define D1 CYBSP_D1
#endif
#ifdef CYBSP_D2
#define D2 CYBSP_D2
#endif
#ifdef CYBSP_D3
#define D3 CYBSP_D3
#endif
#ifdef CYBSP_D4
#define D4 CYBSP_D4
#endif
#ifdef CYBSP_D5
#define D5 CYBSP_D5
#endif
#ifdef CYBSP_D6
#define D6 CYBSP_D6
#endif
#ifdef CYBSP_D7
#define D7 CYBSP_D7
#endif
#ifdef CYBSP_D8
#define D8 CYBSP_D8
#endif
#ifdef CYBSP_D9
#define D9 CYBSP_D9
#endif
#ifdef CYBSP_D10
#define D10 CYBSP_D10
#endif
#ifdef CYBSP_D11
#define D11 CYBSP_D11
#endif
#ifdef CYBSP_D12
#define D12 CYBSP_D12
#endif
#ifdef CYBSP_D13
#define D13 CYBSP_D13
#endif
#ifdef CYBSP_D14
#define D14 CYBSP_D14
#endif
#ifdef CYBSP_D15
#define D15 CYBSP_D15
#endif

#ifdef __cplusplus
extern "C" {
#endif
Expand All @@ -37,6 +106,11 @@ typedef enum {
} PinDirection;

typedef cyhal_gpio_drive_mode_t PinMode;
typedef cyhal_gpio_t PinName;
static inline PinName cyhal_gpio_to_rtos(cyhal_gpio_t pin)
{
return pin;
}

#ifdef __cplusplus
}
Expand Down
0 ...8CKIT_062S2_43012/GeneratedSource/cycfg.c → ..._BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
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0 ...8CKIT_062S2_43012/GeneratedSource/cycfg.h → ..._BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
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21 changes: 2 additions & 19 deletions ..._062_4343W/GeneratedSource/cycfg_clocks.c → ...IGN_MODUS/GeneratedSource/cycfg.timestamp
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/*******************************************************************************
* File Name: cycfg_clocks.c
* File Name: cycfg.timestamp
*
* Description:
* Clock configuration
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
*
********************************************************************************
Expand All @@ -22,20 +22,3 @@
* limitations under the License.
********************************************************************************/

#include "cycfg_clocks.h"


void init_cycfg_clocks(void)
{
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);

Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);

Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 35U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
}
38 changes: 34 additions & 4 deletions ...62S2_43012/GeneratedSource/cycfg_clocks.c → ...SIGN_MODUS/GeneratedSource/cycfg_clocks.c
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Expand Up @@ -24,22 +24,52 @@

#include "cycfg_clocks.h"

#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_BT_UART_CLK_DIV_HW,
.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)


void init_cycfg_clocks(void)
{
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 51U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);

Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)

Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)

Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 5U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
}
16 changes: 13 additions & 3 deletions ...62S2_43012/GeneratedSource/cycfg_clocks.h → ...SIGN_MODUS/GeneratedSource/cycfg_clocks.h
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Expand Up @@ -27,14 +27,14 @@

#include "cycfg_notices.h"
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)

#if defined(__cplusplus)
extern "C" {
#endif

#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U
#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_BT_UART_CLK_DIV_NUM 1U
Expand All @@ -45,6 +45,16 @@ extern "C" {
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U

#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)

void init_cycfg_clocks(void);

#if defined(__cplusplus)
Expand Down
0 ...2S2_43012/GeneratedSource/cycfg_notices.h → ...IGN_MODUS/GeneratedSource/cycfg_notices.h
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103 changes: 57 additions & 46 deletions ...43012/GeneratedSource/cycfg_peripherals.c → ...MODUS/GeneratedSource/cycfg_peripherals.c
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Expand Up @@ -56,6 +56,14 @@ const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
Expand All @@ -64,58 +72,29 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
.smartCardRetryOnNack = false,
.irdaInvertRx = false,
.irdaEnableLowPowerReceiver = false,
.oversample = 12,
.enableMsbFirst = false,
.dataWidth = 9UL,
.parity = CY_SCB_UART_PARITY_NONE,
.stopBits = CY_SCB_UART_STOP_BITS_1,
.enableInputFilter = false,
.breakWidth = 11UL,
.dropOnFrameError = false,
.dropOnParityError = false,
.receiverAddress = 0x0UL,
.receiverAddressMask = 0x0UL,
.acceptAddrInFifo = false,
.enableCts = true,
.ctsPolarity = CY_SCB_UART_ACTIVE_HIGH,
.rtsRxFifoLevel = 63,
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rxFifoTriggerLevel = 63UL,
.rxFifoIntEnableMask = 0UL,
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity = CY_SD_HOST_SDSC;
cy_en_sd_host_card_type_t CYBSP_RADIO_cardType = CY_SD_HOST_NOT_EMMC;
uint32_t CYBSP_RADIO_rca = 0u;
const cy_stc_sd_host_init_config_t CYBSP_RADIO_config =
{
.emmc = false,
.dmaType = CY_SD_HOST_DMA_SDMA,
.enableLedControl = false,
};
cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg =
{
.lowVoltageSignaling = false,
.busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT,
.cardType = &CYBSP_RADIO_cardType,
.rca = &CYBSP_RADIO_rca,
.cardCapacity = &CYBSP_RADIO_cardCapacity,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_obj =
{
.type = CYHAL_RSC_SMIF,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_mcwdt_config_t CYBSP_MCWDT_config =
{
.c0Match = 32768U,
Expand All @@ -129,6 +108,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_MCWDT_obj =
{
.type = CYHAL_RSC_LPTIMER,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
Expand All @@ -141,15 +128,39 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
.month = CY_RTC_JANUARY,
.year = 0U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_RTC_obj =
{
.type = CYHAL_RSC_RTC,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)


void init_cycfg_peripherals(void)
{
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);

Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_16_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
#endif //defined (CY_USING_HAL)

Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
#endif //defined (CY_USING_HAL)

#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
#endif //defined (CY_USING_HAL)

#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_MCWDT_obj);
#endif //defined (CY_USING_HAL)

Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
#endif //defined (CY_USING_HAL)
}
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