diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp
index 8ae3b0b037a..e852298d213 100644
--- a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp
+++ b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp
@@ -422,13 +422,13 @@ class HCIDriver : public cordio::CordioHCIDriver {
 
 ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver() {
     static ble::vendor::cypress_ble::CyH4TransportDriver transport_driver(
-        /* TX */ CY_BT_UART_TX, /* RX */ CY_BT_UART_RX,
-        /* cts */ CY_BT_UART_CTS, /* rts */ CY_BT_UART_RTS, 115200,
-		CY_BT_PIN_HOST_WAKE, CY_BT_PIN_DEVICE_WAKE
+        /* TX */ CYBSP_BT_UART_TX, /* RX */ CYBSP_BT_UART_RX,
+        /* cts */ CYBSP_BT_UART_CTS, /* rts */ CYBSP_BT_UART_RTS, 115200,
+		CYBSP_BT_HOST_WAKE, CYBSP_BT_DEVICE_WAKE
     );
     static ble::vendor::cypress::HCIDriver hci_driver(
         transport_driver,
-        /* bt_power */ CY_BT_PIN_POWER
+        /* bt_power */ CYBSP_BT_POWER
     );
     return hci_driver;
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/PinNamesTypes.h b/targets/TARGET_Cypress/TARGET_PSOC6/PinNamesTypes.h
index 315ff7ce460..548c47eda77 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/PinNamesTypes.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/PinNamesTypes.h
@@ -19,14 +19,83 @@
 #ifndef MBED_PINNAMESTYPES_H
 #define MBED_PINNAMESTYPES_H
 
-#include "cmsis.h"
 #include "cyhal_gpio.h"
+#include "cybsp_types.h"
 
+// Pin Modes
 #define PullNone CYHAL_GPIO_DRIVE_STRONG
-#define PullDefault CYHAL_GPIO_DRIVE_ANALOG
+#define PullDefault CYHAL_GPIO_DRIVE_NONE
 #define PullDown CYHAL_GPIO_DRIVE_PULLDOWN
 #define PullUp CYHAL_GPIO_DRIVE_PULLUP
 
+// Arduino Headers
+#ifdef CYBSP_A0
+#define A0 CYBSP_A0
+#endif
+#ifdef CYBSP_A1
+#define A1 CYBSP_A1
+#endif
+#ifdef CYBSP_A2
+#define A2 CYBSP_A2
+#endif
+#ifdef CYBSP_A3
+#define A3 CYBSP_A3
+#endif
+#ifdef CYBSP_A4
+#define A4 CYBSP_A4
+#endif
+#ifdef CYBSP_A5
+#define A5 CYBSP_A5
+#endif
+#ifdef CYBSP_D0
+#define D0 CYBSP_D0
+#endif
+#ifdef CYBSP_D1
+#define D1 CYBSP_D1
+#endif
+#ifdef CYBSP_D2
+#define D2 CYBSP_D2
+#endif
+#ifdef CYBSP_D3
+#define D3 CYBSP_D3
+#endif
+#ifdef CYBSP_D4
+#define D4 CYBSP_D4
+#endif
+#ifdef CYBSP_D5
+#define D5 CYBSP_D5
+#endif
+#ifdef CYBSP_D6
+#define D6 CYBSP_D6
+#endif
+#ifdef CYBSP_D7
+#define D7 CYBSP_D7
+#endif
+#ifdef CYBSP_D8
+#define D8 CYBSP_D8
+#endif
+#ifdef CYBSP_D9
+#define D9 CYBSP_D9
+#endif
+#ifdef CYBSP_D10
+#define D10 CYBSP_D10
+#endif
+#ifdef CYBSP_D11
+#define D11 CYBSP_D11
+#endif
+#ifdef CYBSP_D12
+#define D12 CYBSP_D12
+#endif
+#ifdef CYBSP_D13
+#define D13 CYBSP_D13
+#endif
+#ifdef CYBSP_D14
+#define D14 CYBSP_D14
+#endif
+#ifdef CYBSP_D15
+#define D15 CYBSP_D15
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -37,6 +106,11 @@ typedef enum {
 } PinDirection;
 
 typedef cyhal_gpio_drive_mode_t PinMode;
+typedef cyhal_gpio_t PinName;
+static inline PinName cyhal_gpio_to_rtos(cyhal_gpio_t pin)
+{
+    return pin;
+}
 
 #ifdef __cplusplus
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
similarity index 60%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
index 42e905fca4d..6911b5befd4 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
@@ -1,8 +1,8 @@
 /*******************************************************************************
-* File Name: cycfg_clocks.c
+* File Name: cycfg.timestamp
 *
 * Description:
-* Clock configuration
+* Sentinel file for determining if generated source is up to date.
 * This file was automatically generated and should not be modified.
 * 
 ********************************************************************************
@@ -22,20 +22,3 @@
 * limitations under the License.
 ********************************************************************************/
 
-#include "cycfg_clocks.h"
-
-
-void init_cycfg_clocks(void)
-{
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 35U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
-}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
similarity index 61%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
index c2a2e7fce0e..33ad3de755e 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
@@ -24,22 +24,52 @@
 
 #include "cycfg_clocks.h"
 
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_BT_UART_CLK_DIV_HW,
+		.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+
 
 void init_cycfg_clocks(void)
 {
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 51U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
-
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 5U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
similarity index 78%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
index 8fe28073847..2ba0f1937b7 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
@@ -27,14 +27,14 @@
 
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 
 #if defined(__cplusplus)
 extern "C" {
 #endif
 
-#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
-#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U
 #define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
 #define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
 #define CYBSP_BT_UART_CLK_DIV_NUM 1U
@@ -45,6 +45,16 @@ extern "C" {
 #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+
 void init_cycfg_clocks(void);
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_notices.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
similarity index 69%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
index c58abf46e9f..c26f522b065 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
@@ -56,6 +56,14 @@ const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
 	.txFifoTriggerLevel = 63UL,
 	.txFifoIntEnableMask = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = 
 {
 	.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
@@ -64,51 +72,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
 	.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
 	.enableWakeFromSleep = false,
 };
-const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = 
-{
-	.uartMode = CY_SCB_UART_STANDARD,
-	.enableMutliProcessorMode = false,
-	.smartCardRetryOnNack = false,
-	.irdaInvertRx = false,
-	.irdaEnableLowPowerReceiver = false,
-	.oversample = 12,
-	.enableMsbFirst = false,
-	.dataWidth = 9UL,
-	.parity = CY_SCB_UART_PARITY_NONE,
-	.stopBits = CY_SCB_UART_STOP_BITS_1,
-	.enableInputFilter = false,
-	.breakWidth = 11UL,
-	.dropOnFrameError = false,
-	.dropOnParityError = false,
-	.receiverAddress = 0x0UL,
-	.receiverAddressMask = 0x0UL,
-	.acceptAddrInFifo = false,
-	.enableCts = true,
-	.ctsPolarity = CY_SCB_UART_ACTIVE_HIGH,
-	.rtsRxFifoLevel = 63,
-	.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rxFifoTriggerLevel = 63UL,
-	.rxFifoIntEnableMask = 0UL,
-	.txFifoTriggerLevel = 63UL,
-	.txFifoIntEnableMask = 0UL,
-};
-cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity = CY_SD_HOST_SDSC;
-cy_en_sd_host_card_type_t CYBSP_RADIO_cardType = CY_SD_HOST_NOT_EMMC;
-uint32_t CYBSP_RADIO_rca = 0u;
-const cy_stc_sd_host_init_config_t CYBSP_RADIO_config = 
-{
-	.emmc = false,
-	.dmaType = CY_SD_HOST_DMA_SDMA,
-	.enableLedControl = false,
-};
-cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg = 
-{
-	.lowVoltageSignaling = false,
-	.busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT,
-	.cardType = &CYBSP_RADIO_cardType,
-	.rca = &CYBSP_RADIO_rca,
-	.cardCapacity = &CYBSP_RADIO_cardCapacity,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_smif_config_t CYBSP_QSPI_config = 
 {
 	.mode = (uint32_t)CY_SMIF_NORMAL,
@@ -116,6 +87,14 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
 	.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
 	.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_obj = 
+	{
+		.type = CYHAL_RSC_SMIF,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_mcwdt_config_t CYBSP_MCWDT_config = 
 {
 	.c0Match = 32768U,
@@ -129,6 +108,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT_config =
 	.c0c1Cascade = true,
 	.c1c2Cascade = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_MCWDT_obj = 
+	{
+		.type = CYHAL_RSC_LPTIMER,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_rtc_config_t CYBSP_RTC_config = 
 {
 	.sec = 0U,
@@ -141,6 +128,14 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
 	.month = CY_RTC_JANUARY,
 	.year = 0U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_RTC_obj = 
+	{
+		.type = CYHAL_RSC_RTC,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_peripherals(void)
@@ -148,8 +143,24 @@ void init_cycfg_peripherals(void)
 	Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_16_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_MCWDT_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
similarity index 79%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
index ffdd990d9fe..deff2270e58 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
@@ -29,9 +29,12 @@
 #include "cy_sysclk.h"
 #include "cy_csd.h"
 #include "cy_scb_uart.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_scb_ezi2c.h"
-#include "cy_sd_host.h"
 #include "cy_smif.h"
+#include "cycfg_qspi_memslot.h"
 #include "cy_mcwdt.h"
 #include "cy_rtc.h"
 
@@ -39,7 +42,7 @@
 extern "C" {
 #endif
 
-#define CYBSP_CAPSENSE_ENABLED 1U
+#define CYBSP_CSD_ENABLED 1U
 #define CY_CAPSENSE_CORE 4u
 #define CY_CAPSENSE_CPU_CLK 144000000u
 #define CY_CAPSENSE_PERI_CLK 72000000u
@@ -49,10 +52,10 @@ extern "C" {
 #define Cmod_PORT GPIO_PRT7
 #define CintA_PORT GPIO_PRT7
 #define CintB_PORT GPIO_PRT7
-#define Button0_Rx0_PORT GPIO_PRT8
-#define Button0_Tx_PORT GPIO_PRT1
-#define Button1_Rx0_PORT GPIO_PRT8
-#define Button1_Tx_PORT GPIO_PRT1
+#define Button0_Rx0_PORT GPIO_PRT1
+#define Button0_Tx_PORT GPIO_PRT8
+#define Button1_Rx0_PORT GPIO_PRT1
+#define Button1_Tx_PORT GPIO_PRT8
 #define LinearSlider0_Sns0_PORT GPIO_PRT8
 #define LinearSlider0_Sns1_PORT GPIO_PRT8
 #define LinearSlider0_Sns2_PORT GPIO_PRT8
@@ -61,10 +64,10 @@ extern "C" {
 #define Cmod_PIN 7u
 #define CintA_PIN 1u
 #define CintB_PIN 2u
-#define Button0_Rx0_PIN 1u
-#define Button0_Tx_PIN 0u
-#define Button1_Rx0_PIN 2u
-#define Button1_Tx_PIN 0u
+#define Button0_Rx0_PIN 0u
+#define Button0_Tx_PIN 1u
+#define Button1_Rx0_PIN 0u
+#define Button1_Tx_PIN 2u
 #define LinearSlider0_Sns0_PIN 3u
 #define LinearSlider0_Sns1_PIN 4u
 #define LinearSlider0_Sns2_PIN 5u
@@ -73,20 +76,14 @@ extern "C" {
 #define Cmod_PORT_NUM 7u
 #define CintA_PORT_NUM 7u
 #define CintB_PORT_NUM 7u
-#define CYBSP_CAPSENSE_HW CSD0
-#define CYBSP_CAPSENSE_IRQ csd_interrupt_IRQn
+#define CYBSP_CSD_HW CSD0
+#define CYBSP_CSD_IRQ csd_interrupt_IRQn
 #define CYBSP_BT_UART_ENABLED 1U
 #define CYBSP_BT_UART_HW SCB2
 #define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
 #define CYBSP_CSD_COMM_ENABLED 1U
 #define CYBSP_CSD_COMM_HW SCB3
 #define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
-#define CYBSP_DEBUG_UART_ENABLED 1U
-#define CYBSP_DEBUG_UART_HW SCB5
-#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
-#define CYBSP_RADIO_ENABLED 1U
-#define CYBSP_RADIO_HW SDHC0
-#define CYBSP_RADIO_IRQ sdhc_0_interrupt_general_IRQn
 #define CYBSP_QSPI_ENABLED 1U
 #define CYBSP_QSPI_HW SMIF0
 #define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@@ -119,16 +116,25 @@ extern "C" {
 
 extern cy_stc_csd_context_t cy_csd_0_context;
 extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
-extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
-extern cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity;
-extern cy_en_sd_host_card_type_t CYBSP_RADIO_cardType;
-extern uint32_t CYBSP_RADIO_rca;
-extern const cy_stc_sd_host_init_config_t CYBSP_RADIO_config;
-extern cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_mcwdt_config_t CYBSP_MCWDT_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_MCWDT_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_rtc_config_t CYBSP_RTC_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_RTC_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_peripherals(void);
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
similarity index 58%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_pins.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
index b9069ac8d5f..a9c142e508c 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
@@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_IN_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_IN_PORT_NUM,
+		.channel_num = CYBSP_WCO_IN_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = 
 {
 	.outVal = 1,
@@ -56,54 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_SW2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_PULLUP,
-	.hsiom = CYBSP_SW2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_G_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED5_RGB_G_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED9_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED9_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_OUT_PORT_NUM,
+		.channel_num = CYBSP_WCO_OUT_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config = 
 {
 	.outVal = 1,
@@ -120,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SS0_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SS0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config = 
 {
 	.outVal = 1,
@@ -136,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_DATA3_PORT_NUM,
+		.channel_num = CYBSP_QSPI_DATA3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config = 
 {
 	.outVal = 1,
@@ -152,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_DATA2_PORT_NUM,
+		.channel_num = CYBSP_QSPI_DATA2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config = 
 {
 	.outVal = 1,
@@ -168,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_DATA1_PORT_NUM,
+		.channel_num = CYBSP_QSPI_DATA1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config = 
 {
 	.outVal = 1,
@@ -184,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_DATA0_PORT_NUM,
+		.channel_num = CYBSP_QSPI_DATA0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config = 
 {
 	.outVal = 1,
@@ -200,155 +208,19 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CSD_TX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_R_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED5_RGB_R_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SW4_config = 
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SPI_CLOCK_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SPI_CLOCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = 
 {
 	.outVal = 1,
 	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_SW4_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED8_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED8_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT0_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_SDHC0_DAT0_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT1_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_SDHC0_DAT1_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_SDHC0_DAT2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT3_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_SDHC0_DAT3_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CMD_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_SDHC0_CMD_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CLK_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_SDHC0_CLK_HSIOM,
+	.hsiom = CYBSP_CSD_RX_HSIOM,
 	.intEdge = CY_GPIO_INTR_DISABLE,
 	.intMask = 0UL,
 	.vtrip = CY_GPIO_VTRIP_CMOS,
@@ -360,6 +232,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CLK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_RX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_RX_PORT_NUM,
+		.channel_num = CYBSP_CSD_RX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = 
 {
 	.outVal = 1,
@@ -376,6 +256,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_RX_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_RX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = 
 {
 	.outVal = 1,
@@ -392,6 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_TX_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_TX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = 
 {
 	.outVal = 1,
@@ -408,6 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_RTS_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_RTS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = 
 {
 	.outVal = 1,
@@ -424,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_CTS_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_CTS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config = 
 {
 	.outVal = 1,
@@ -440,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_POWER_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_POWER_PORT_NUM,
+		.channel_num = CYBSP_BT_POWER_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = 
 {
 	.outVal = 0,
@@ -456,6 +376,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
+		.channel_num = CYBSP_BT_HOST_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config = 
 {
 	.outVal = 0,
@@ -472,70 +400,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_HIGHZ,
-	.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RTS_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_DEBUG_UART_RTS_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_CTS_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_HIGHZ,
-	.hsiom = CYBSP_DEBUG_UART_CTS_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM,
+		.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = 
 {
 	.outVal = 1,
@@ -552,6 +424,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SCL_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = 
 {
 	.outVal = 1,
@@ -568,6 +448,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SDA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWO_config = 
 {
 	.outVal = 1,
@@ -584,6 +472,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWO_PORT_NUM,
+		.channel_num = CYBSP_SWO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = 
 {
 	.outVal = 1,
@@ -600,6 +496,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDIO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDIO_PORT_NUM,
+		.channel_num = CYBSP_SWDIO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = 
 {
 	.outVal = 1,
@@ -616,6 +520,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDCK_PORT_NUM,
+		.channel_num = CYBSP_SWDCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINA_config = 
 {
 	.outVal = 1,
@@ -632,6 +544,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINA_PORT_NUM,
+		.channel_num = CYBSP_CINA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINB_config = 
 {
 	.outVal = 1,
@@ -648,22 +568,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_B_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED5_RGB_B_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINB_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINB_PORT_NUM,
+		.channel_num = CYBSP_CINB_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = 
 {
 	.outVal = 1,
@@ -680,6 +592,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CMOD_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CMOD_PORT_NUM,
+		.channel_num = CYBSP_CMOD_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = 
 {
 	.outVal = 1,
@@ -696,6 +616,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN0_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = 
 {
 	.outVal = 1,
@@ -712,6 +640,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN1_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = 
 {
 	.outVal = 1,
@@ -728,6 +664,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD0_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = 
 {
 	.outVal = 1,
@@ -744,6 +688,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD1_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = 
 {
 	.outVal = 1,
@@ -760,6 +712,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD2_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = 
 {
 	.outVal = 1,
@@ -776,6 +736,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD3_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = 
 {
 	.outVal = 1,
@@ -792,92 +760,159 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD4_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD4_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_pins(void)
 {
 	Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SW2_PORT, CYBSP_SW2_PIN, &CYBSP_SW2_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED5_RGB_G_PORT, CYBSP_LED5_RGB_G_PIN, &CYBSP_LED5_RGB_G_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED9_PORT, CYBSP_LED9_PIN, &CYBSP_LED9_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SS0_PORT, CYBSP_QSPI_SS0_PIN, &CYBSP_QSPI_SS0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SS0_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA3_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA2_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA1_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA0_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SPI_CLOCK_PORT, CYBSP_QSPI_SPI_CLOCK_PIN, &CYBSP_QSPI_SPI_CLOCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SPI_CLOCK_obj);
+#endif //defined (CY_USING_HAL)
 
-
-	Cy_GPIO_Pin_Init(CYBSP_LED5_RGB_R_PORT, CYBSP_LED5_RGB_R_PIN, &CYBSP_LED5_RGB_R_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SW4_PORT, CYBSP_SW4_PIN, &CYBSP_SW4_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED8_PORT, CYBSP_LED8_PIN, &CYBSP_LED8_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT0_PORT, CYBSP_SDHC0_DAT0_PIN, &CYBSP_SDHC0_DAT0_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT1_PORT, CYBSP_SDHC0_DAT1_PIN, &CYBSP_SDHC0_DAT1_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT2_PORT, CYBSP_SDHC0_DAT2_PIN, &CYBSP_SDHC0_DAT2_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT3_PORT, CYBSP_SDHC0_DAT3_PIN, &CYBSP_SDHC0_DAT3_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SDHC0_CMD_PORT, CYBSP_SDHC0_CMD_PIN, &CYBSP_SDHC0_CMD_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SDHC0_CLK_PORT, CYBSP_SDHC0_CLK_PIN, &CYBSP_SDHC0_CLK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RTS_PORT, CYBSP_DEBUG_UART_RTS_PIN, &CYBSP_DEBUG_UART_RTS_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_CTS_PORT, CYBSP_DEBUG_UART_CTS_PIN, &CYBSP_DEBUG_UART_CTS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_GPIO_Pin_Init(CYBSP_LED5_RGB_B_PORT, CYBSP_LED5_RGB_B_PIN, &CYBSP_LED5_RGB_B_config);
-
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
new file mode 100644
index 00000000000..ce11bc34279
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
@@ -0,0 +1,916 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cycfg_notices.h"
+#include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cycfg_routing.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PORT_NUM 0U
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_0_HSIOM
+	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PORT_NUM 0U
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_1_HSIOM
+	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SS0_ENABLED 1U
+#define CYBSP_QSPI_SS0_PORT GPIO_PRT11
+#define CYBSP_QSPI_SS0_PORT_NUM 11U
+#define CYBSP_QSPI_SS0_PIN 2U
+#define CYBSP_QSPI_SS0_NUM 2U
+#define CYBSP_QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SS0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_2_HSIOM
+	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
+#define CYBSP_QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS0_HAL_PORT_PIN P11_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS0_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_DATA3_ENABLED 1U
+#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA3_PORT_NUM 11U
+#define CYBSP_QSPI_DATA3_PIN 3U
+#define CYBSP_QSPI_DATA3_NUM 3U
+#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_3_HSIOM
+	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
+#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA3_HAL_PORT_PIN P11_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_DATA2_ENABLED 1U
+#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA2_PORT_NUM 11U
+#define CYBSP_QSPI_DATA2_PIN 4U
+#define CYBSP_QSPI_DATA2_NUM 4U
+#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_4_HSIOM
+	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
+#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA2_HAL_PORT_PIN P11_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_DATA1_ENABLED 1U
+#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA1_PORT_NUM 11U
+#define CYBSP_QSPI_DATA1_PIN 5U
+#define CYBSP_QSPI_DATA1_NUM 5U
+#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_5_HSIOM
+	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
+#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA1_HAL_PORT_PIN P11_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_DATA0_ENABLED 1U
+#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA0_PORT_NUM 11U
+#define CYBSP_QSPI_DATA0_PIN 6U
+#define CYBSP_QSPI_DATA0_NUM 6U
+#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_6_HSIOM
+	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
+#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA0_HAL_PORT_PIN P11_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SPI_CLOCK_ENABLED 1U
+#define CYBSP_QSPI_SPI_CLOCK_PORT GPIO_PRT11
+#define CYBSP_QSPI_SPI_CLOCK_PORT_NUM 11U
+#define CYBSP_QSPI_SPI_CLOCK_PIN 7U
+#define CYBSP_QSPI_SPI_CLOCK_NUM 7U
+#define CYBSP_QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_7_HSIOM
+	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define CYBSP_QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SPI_CLOCK_HAL_PORT_PIN P11_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SPI_CLOCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SPI_CLOCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SPI_CLOCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_RX_ENABLED 1U
+#define CYBSP_CSD_RX_PORT GPIO_PRT1
+#define CYBSP_CSD_RX_PORT_NUM 1U
+#define CYBSP_CSD_RX_PIN 0U
+#define CYBSP_CSD_RX_NUM 0U
+#define CYBSP_CSD_RX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_0_HSIOM
+	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_RX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CSD_RX_IRQ ioss_interrupts_gpio_1_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_RX_HAL_PORT_PIN P1_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_RX_ENABLED 1U
+#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RX_PORT_NUM 3U
+#define CYBSP_BT_UART_RX_PIN 0U
+#define CYBSP_BT_UART_RX_NUM 0U
+#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_0_HSIOM
+	#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
+#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_TX_ENABLED 1U
+#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_TX_PORT_NUM 3U
+#define CYBSP_BT_UART_TX_PIN 1U
+#define CYBSP_BT_UART_TX_NUM 1U
+#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_1_HSIOM
+	#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
+#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_RTS_ENABLED 1U
+#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RTS_PORT_NUM 3U
+#define CYBSP_BT_UART_RTS_PIN 2U
+#define CYBSP_BT_UART_RTS_NUM 2U
+#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_2_HSIOM
+	#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
+#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_CTS_ENABLED 1U
+#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_CTS_PORT_NUM 3U
+#define CYBSP_BT_UART_CTS_PIN 3U
+#define CYBSP_BT_UART_CTS_NUM 3U
+#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_3_HSIOM
+	#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
+#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_POWER_ENABLED 1U
+#define CYBSP_BT_POWER_PORT GPIO_PRT3
+#define CYBSP_BT_POWER_PORT_NUM 3U
+#define CYBSP_BT_POWER_PIN 4U
+#define CYBSP_BT_POWER_NUM 4U
+#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
+#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_4_HSIOM
+	#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
+#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_PORT_PIN P3_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_HOST_WAKE_ENABLED 1U
+#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
+#define CYBSP_BT_HOST_WAKE_PORT_NUM 3U
+#define CYBSP_BT_HOST_WAKE_PIN 5U
+#define CYBSP_BT_HOST_WAKE_NUM 5U
+#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_3_pin_5_HSIOM
+	#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
+#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P3_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
+#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
+#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 4U
+#define CYBSP_BT_DEVICE_WAKE_PIN 0U
+#define CYBSP_BT_DEVICE_WAKE_NUM 0U
+#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_4_pin_0_HSIOM
+	#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
+#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P4_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SCL_ENABLED 1U
+#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SCL_PORT_NUM 6U
+#define CYBSP_EZI2C_SCL_PIN 0U
+#define CYBSP_EZI2C_SCL_NUM 0U
+#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_0_HSIOM
+	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
+#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SDA_ENABLED 1U
+#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SDA_PORT_NUM 6U
+#define CYBSP_EZI2C_SDA_PIN 1U
+#define CYBSP_EZI2C_SDA_NUM 1U
+#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_1_HSIOM
+	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
+#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PORT_NUM 6U
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_4_HSIOM
+	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_PORT_PIN P6_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PORT_NUM 6U
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_6_HSIOM
+	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDCK_ENABLED 1U
+#define CYBSP_SWDCK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PORT_NUM 6U
+#define CYBSP_SWDCK_PIN 7U
+#define CYBSP_SWDCK_NUM 7U
+#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_7_HSIOM
+	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINA_ENABLED 1U
+#define CYBSP_CINA_PORT GPIO_PRT7
+#define CYBSP_CINA_PORT_NUM 7U
+#define CYBSP_CINA_PIN 1U
+#define CYBSP_CINA_NUM 1U
+#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_1_HSIOM
+	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_PORT_PIN P7_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINB_ENABLED 1U
+#define CYBSP_CINB_PORT GPIO_PRT7
+#define CYBSP_CINB_PORT_NUM 7U
+#define CYBSP_CINB_PIN 2U
+#define CYBSP_CINB_NUM 2U
+#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINB_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_2_HSIOM
+	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_PORT_PIN P7_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PORT_NUM 7U
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_7_HSIOM
+	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_PORT_PIN P7_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN0_PORT_NUM 8U
+#define CYBSP_CSD_BTN0_PIN 1U
+#define CYBSP_CSD_BTN0_NUM 1U
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_1_HSIOM
+	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN1_PORT_NUM 8U
+#define CYBSP_CSD_BTN1_PIN 2U
+#define CYBSP_CSD_BTN1_NUM 2U
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_2_HSIOM
+	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD0_PORT_NUM 8U
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_3_HSIOM
+	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD1_PORT_NUM 8U
+#define CYBSP_CSD_SLD1_PIN 4U
+#define CYBSP_CSD_SLD1_NUM 4U
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_4_HSIOM
+	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD2_PORT_NUM 8U
+#define CYBSP_CSD_SLD2_PIN 5U
+#define CYBSP_CSD_SLD2_NUM 5U
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_5_HSIOM
+	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD3_PORT_NUM 8U
+#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_6_HSIOM
+	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD4_PORT_NUM 8U
+#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_7_HSIOM
+	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINB_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
similarity index 82%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_qspi_memslot.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
index 0d3609cfc2f..c4e5bcf916f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_qspi_memslot.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
@@ -24,10 +24,10 @@
 
 #include "cycfg_qspi_memslot.h"
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xEBU,
+    .command = 0xECU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x06U,
@@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x04U,
@@ -78,10 +78,10 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xD8U,
+    .command = 0xDCU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x60U,
@@ -114,10 +114,10 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x38U,
+    .command = 0x34U,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x35U,
@@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x05U,
@@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x01U,
@@ -186,52 +186,52 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Specifies the number of address bytes used by the memory slave device. */
-    .numOfAddrBytes = 0x03U,
+    .numOfAddrBytes = 0x04U,
     /* The size of the memory. */
     .memSize = 0x04000000U,
     /* Specifies the Read command. */
-    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd,
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
     /* Specifies the Write Enable command. */
-    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd,
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
     /* Specifies the Write Disable command. */
-    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd,
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
     /* Specifies the Erase command. */
-    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd,
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
     /* Specifies the sector size of each erase. */
     .eraseSize = 0x00040000U,
     /* Specifies the Chip Erase command. */
-    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd,
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
     /* Specifies the Program command. */
-    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd,
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
     /* Specifies the page size for programming. */
     .programSize = 0x00000200U,
     /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
     /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
     /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
     /* The mask for the status register. */
     .stsRegBusyMask = 0x01U,
     /* The mask for the status register. */
     .stsRegQuadEnableMask = 0x02U,
     /* The max time for the erase type-1 cycle-time in ms. */
-    .eraseTime = 520U,
+    .eraseTime = 2600U,
     /* The max time for the chip-erase cycle-time in ms. */
-    .chipEraseTime = 134000U,
+    .chipEraseTime = 460000U,
     /* The max time for the page-program cycle-time in us. */
-    .programTime = 340U
+    .programTime = 1300U
 };
 
-const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Determines the slot number where the memory device is placed. */
     .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
     /* Flags. */
-    .flags = CY_SMIF_FLAG_WR_EN,
+    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
     /* The data-line selection options for a slave device. */
     .dataSelect = CY_SMIF_DATA_SEL0,
     /* The base address the memory slave is mapped to in the PSoC memory map.
@@ -239,16 +239,16 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
     .baseAddress = 0x18000000U,
     /* The size allocated in the PSoC memory map, for the memory slave device.
     The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
-    .memMappedSize = 0x10000U,
+    .memMappedSize = 0x4000000U,
     /* If this memory device is one of the devices in the dual quad SPI configuration.
     Valid when the memory mapped mode is enabled. */
     .dualQuadSlots = 0,
     /* The configuration of the device. */
-    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
-   &S25FL512S_SlaveSlot_0
+   &S25FL512SX4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_block_config_t smifBlockConfig =
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
similarity index 60%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_qspi_memslot.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
index 846f62c018a..32f9b49b2e6 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_qspi_memslot.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
@@ -28,19 +28,19 @@
 
 #define CY_SMIF_DEVICE_NUM 1
 
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
-
-extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
-
-extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
+
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
+
+extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
 extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
 
 extern const cy_stc_smif_block_config_t smifBlockConfig;
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_routing.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
similarity index 79%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_routing.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
index d69bf20d16f..58fcac0f12d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_routing.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
@@ -41,20 +41,10 @@ void init_cycfg_routing(void);
 #define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
 #define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
 #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_2_pin_0_HSIOM P2_0_SDHC0_CARD_DAT_3TO00
-#define ioss_0_port_2_pin_1_HSIOM P2_1_SDHC0_CARD_DAT_3TO01
-#define ioss_0_port_2_pin_2_HSIOM P2_2_SDHC0_CARD_DAT_3TO02
-#define ioss_0_port_2_pin_3_HSIOM P2_3_SDHC0_CARD_DAT_3TO03
-#define ioss_0_port_2_pin_4_HSIOM P2_4_SDHC0_CARD_CMD
-#define ioss_0_port_2_pin_5_HSIOM P2_5_SDHC0_CLK_CARD
 #define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
 #define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
 #define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
 #define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
-#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
-#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
-#define ioss_0_port_5_pin_2_HSIOM P5_2_SCB5_UART_RTS
-#define ioss_0_port_5_pin_3_HSIOM P5_3_SCB5_UART_CTS
 #define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
 #define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
 #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
@@ -62,10 +52,10 @@ void init_cycfg_routing(void);
 #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
 #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
new file mode 100644
index 00000000000..a8562c420e8
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
@@ -0,0 +1,570 @@
+/*******************************************************************************
+* File Name: cycfg_system.c
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_system.h"
+
+#define CY_CFG_SYSCLK_ECO_ERROR 1
+#define CY_CFG_SYSCLK_ALTHF_ERROR 2
+#define CY_CFG_SYSCLK_PLL_ERROR 3
+#define CY_CFG_SYSCLK_FLL_ERROR 4
+#define CY_CFG_SYSCLK_WCO_ERROR 5
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
+#define CY_CFG_SYSCLK_FLL_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 144UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
+#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
+#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH2
+#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_ILO_ENABLED 1
+#define CY_CFG_SYSCLK_IMO_ENABLED 1
+#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
+#define CY_CFG_SYSCLK_PLL0_ENABLED 1
+#define CY_CFG_SYSCLK_PLL1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
+#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
+#define CY_CFG_SYSCLK_WCO_ENABLED 1
+#define CY_CFG_PWR_ENABLED 1
+#define CY_CFG_PWR_INIT 1
+#define CY_CFG_PWR_USING_PMIC 0
+#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
+#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
+#define CY_CFG_PWR_USING_ULP 0
+
+static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = 
+{
+	.fllMult = 500U,
+	.refDiv = 20U,
+	.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
+	.enableOutputDiv = true,
+	.lockTolerance = 10U,
+	.igain = 9U,
+	.pgain = 5U,
+	.settlingCount = 8U,
+	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
+	.cco_Freq = 355U,
+};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 1U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = 
+{
+	.feedbackDiv = 36,
+	.referenceDiv = 1,
+	.outputDiv = 2,
+	.lfMode = false,
+	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = 
+{
+	.feedbackDiv = 30,
+	.referenceDiv = 1,
+	.outputDiv = 5,
+	.lfMode = false,
+	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
+
+__WEAK void cycfg_ClockStartupError(uint32_t error)
+{
+    (void)error; /* Suppress the compiler warning */
+    while(1);
+}
+__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
+{
+    Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
+}
+__STATIC_INLINE void Cy_SysClk_ClkBakInit()
+{
+    Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
+}
+__STATIC_INLINE void Cy_SysClk_ClkFastInit()
+{
+    Cy_SysClk_ClkFastSetDivider(0U);
+}
+__STATIC_INLINE void Cy_SysClk_FllInit()
+{
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+    }
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+    }
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
+{
+    Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
+}
+__STATIC_INLINE void Cy_SysClk_IloInit()
+{
+    /* The WDT is unlocked in the default startup code */
+    Cy_SysClk_IloEnable();
+    Cy_SysClk_IloHibernateOn(true);
+}
+__STATIC_INLINE void Cy_SysClk_ClkLfInit()
+{
+    /* The WDT is unlocked in the default startup code */
+    Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
+{
+    Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
+{
+    Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
+{
+    Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
+{
+    Cy_SysClk_ClkPeriSetDivider(1U);
+}
+__STATIC_INLINE void Cy_SysClk_Pll0Init()
+{
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+}
+__STATIC_INLINE void Cy_SysClk_Pll1Init()
+{
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+}
+__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
+{
+    Cy_SysClk_ClkSlowSetDivider(0U);
+}
+__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
+{
+    Cy_SysClk_ClkTimerDisable();
+     Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
+    Cy_SysClk_ClkTimerSetDivider(0U);
+    Cy_SysClk_ClkTimerEnable();
+}
+__STATIC_INLINE void Cy_SysClk_WcoInit()
+{
+    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
+    }
+}
+__STATIC_INLINE void init_cycfg_power(void)
+{
+     /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
+     #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
+     if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
+     {
+         Cy_SysLib_ResetBackupDomain();
+         Cy_SysClk_IloDisable();
+         Cy_SysClk_IloInit();
+     }
+     #else /* Dedicated Supply */
+     Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
+     #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+
+     /* Configure core regulator */
+     #if CY_CFG_PWR_USING_LDO
+     Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
+     Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
+     #else
+     Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
+     #endif /* CY_CFG_PWR_USING_LDO */
+     /* Configure PMIC */
+     Cy_SysPm_UnlockPmic();
+     #if CY_CFG_PWR_USING_PMIC
+     Cy_SysPm_PmicEnableOutput();
+     #else
+     Cy_SysPm_PmicDisableOutput();
+     #endif /* CY_CFG_PWR_USING_PMIC */
+}
+
+
+void init_cycfg_system(void)
+{
+	/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
+	Cy_SysLib_SetWaitStates(false, 150UL);
+	#ifdef CY_CFG_PWR_ENABLED
+	    #ifdef CY_CFG_PWR_INIT
+	    init_cycfg_power();
+	    #else
+	    #warning Power system will not be configured. Update power personality to v1.20 or later.
+	    #endif /* CY_CFG_PWR_INIT */
+	#endif /* CY_CFG_PWR_ENABLED */
+	
+	/* Reset the core clock path to default and disable all the FLLs/PLLs */
+	Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+	Cy_SysClk_ClkFastSetDivider(0U);
+	Cy_SysClk_ClkPeriSetDivider(1U);
+	Cy_SysClk_ClkSlowSetDivider(0U);
+	for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
+	{
+	    (void)Cy_SysClk_PllDisable(pll);
+	}
+	Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
+	
+	if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
+	    (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
+	{
+	    Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+	}
+	
+	Cy_SysClk_FllDisable();
+	Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
+	Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
+	#ifdef CY_IP_MXBLESS
+	(void)Cy_BLE_EcoReset();
+	#endif
+	
+	
+	/* Enable all source clocks */
+	#ifdef CY_CFG_SYSCLK_PILO_ENABLED
+	Cy_SysClk_PiloInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_WCO_ENABLED
+	Cy_SysClk_WcoInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+	Cy_SysClk_ClkLfInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
+	Cy_SysClk_AltHfInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_ECO_ENABLED
+	Cy_SysClk_EcoInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+	Cy_SysClk_ExtClkInit();
+	#endif
+	
+	/* Configure CPU clock dividers */
+	#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
+	Cy_SysClk_ClkFastInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
+	Cy_SysClk_ClkPeriInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
+	Cy_SysClk_ClkSlowInit();
+	#endif
+	
+	#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
+	    /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
+	    Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
+	    Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+	#else
+	    #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+	        Cy_SysClk_ClkPath1Init();
+	    #endif
+	#endif
+	
+	/* Configure Path Clocks */
+	#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+	Cy_SysClk_ClkPath0Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
+	Cy_SysClk_ClkPath2Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
+	Cy_SysClk_ClkPath3Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
+	Cy_SysClk_ClkPath4Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
+	Cy_SysClk_ClkPath5Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
+	Cy_SysClk_ClkPath6Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
+	Cy_SysClk_ClkPath7Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
+	Cy_SysClk_ClkPath8Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
+	Cy_SysClk_ClkPath9Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
+	Cy_SysClk_ClkPath10Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
+	Cy_SysClk_ClkPath11Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
+	Cy_SysClk_ClkPath12Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
+	Cy_SysClk_ClkPath13Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
+	Cy_SysClk_ClkPath14Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
+	Cy_SysClk_ClkPath15Init();
+	#endif
+	
+	/* Configure and enable FLL */
+	#ifdef CY_CFG_SYSCLK_FLL_ENABLED
+	Cy_SysClk_FllInit();
+	#endif
+	
+	Cy_SysClk_ClkHf0Init();
+	
+	#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
+	    #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+	        /* Apply the ClkPath1 user setting */
+	        Cy_SysClk_ClkPath1Init();
+	    #endif
+	#endif
+	
+	/* Configure and enable PLLs */
+	#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
+	Cy_SysClk_Pll0Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
+	Cy_SysClk_Pll1Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
+	Cy_SysClk_Pll2Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
+	Cy_SysClk_Pll3Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
+	Cy_SysClk_Pll4Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
+	Cy_SysClk_Pll5Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
+	Cy_SysClk_Pll6Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
+	Cy_SysClk_Pll7Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
+	Cy_SysClk_Pll8Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
+	Cy_SysClk_Pll9Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
+	Cy_SysClk_Pll10Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
+	Cy_SysClk_Pll11Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
+	Cy_SysClk_Pll12Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
+	Cy_SysClk_Pll13Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
+	Cy_SysClk_Pll14Init();
+	#endif
+	
+	/* Configure HF clocks */
+	#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
+	Cy_SysClk_ClkHf1Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
+	Cy_SysClk_ClkHf2Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
+	Cy_SysClk_ClkHf3Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
+	Cy_SysClk_ClkHf4Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
+	Cy_SysClk_ClkHf5Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
+	Cy_SysClk_ClkHf6Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
+	Cy_SysClk_ClkHf7Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
+	Cy_SysClk_ClkHf8Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
+	Cy_SysClk_ClkHf9Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
+	Cy_SysClk_ClkHf10Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
+	Cy_SysClk_ClkHf11Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
+	Cy_SysClk_ClkHf12Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
+	Cy_SysClk_ClkHf13Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
+	Cy_SysClk_ClkHf14Init();
+	#endif
+	#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
+	Cy_SysClk_ClkHf15Init();
+	#endif
+	
+	/* Configure miscellaneous clocks */
+	#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
+	Cy_SysClk_ClkTimerInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+	Cy_SysClk_ClkAltSysTickInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
+	Cy_SysClk_ClkPumpInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
+	Cy_SysClk_ClkBakInit();
+	#endif
+	
+	/* Configure default enabled clocks */
+	#ifdef CY_CFG_SYSCLK_ILO_ENABLED
+	Cy_SysClk_IloInit();
+	#else
+	Cy_SysClk_IloDisable();
+	#endif
+	
+	#ifndef CY_CFG_SYSCLK_IMO_ENABLED
+	#error the IMO must be enabled for proper chip operation
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_MFO_ENABLED
+	Cy_SysClk_MfoInit();
+	#endif
+	
+	#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
+	Cy_SysClk_ClkMfInit();
+	#endif
+	
+	/* Set accurate flash wait states */
+	#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
+	Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
+	#endif
+	
+	/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
+	SystemCoreClockUpdate();
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
similarity index 82%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
index 644e36fccc9..d72cc4107aa 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
@@ -28,6 +28,9 @@
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
 #include "cy_systick.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_gpio.h"
 #include "cy_syspm.h"
 
@@ -43,23 +46,22 @@ extern "C" {
 #define srss_0_clock_0_fll_0_ENABLED 1U
 #define srss_0_clock_0_hfclk_0_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF0 0UL
-#define srss_0_clock_0_hfclk_1_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF1 1UL
 #define srss_0_clock_0_hfclk_2_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF2 2UL
 #define srss_0_clock_0_hfclk_3_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF3 3UL
+#define srss_0_clock_0_hfclk_4_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF4 4UL
 #define srss_0_clock_0_ilo_0_ENABLED 1U
 #define srss_0_clock_0_imo_0_ENABLED 1U
 #define srss_0_clock_0_lfclk_0_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000
 #define srss_0_clock_0_pathmux_0_ENABLED 1U
 #define srss_0_clock_0_pathmux_1_ENABLED 1U
 #define srss_0_clock_0_pathmux_2_ENABLED 1U
-#define srss_0_clock_0_pathmux_3_ENABLED 1U
-#define srss_0_clock_0_pathmux_4_ENABLED 1U
 #define srss_0_clock_0_periclk_0_ENABLED 1U
 #define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_pll_1_ENABLED 1U
 #define srss_0_clock_0_slowclk_0_ENABLED 1U
 #define srss_0_clock_0_timerclk_0_ENABLED 1U
 #define srss_0_clock_0_wco_0_ENABLED 1U
@@ -80,6 +82,16 @@ extern "C" {
 #define CY_CFG_PWR_VDDIO0_MV 3300
 #define CY_CFG_PWR_VDDIO1_MV 3300
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+
 void init_cycfg_system(void);
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
new file mode 100644
index 00000000000..5557ddecddf
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
@@ -0,0 +1,4 @@
+set SMIF_BANKS {
+  0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+}
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
new file mode 100644
index 00000000000..6080a67de62
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
@@ -0,0 +1,402 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by CapSense Configurator 2.0.0 build 531-->
+<Configuration app="Capsense" major="2" minor="0">
+    <GeneralProperties>
+        <Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="REGULAR_IIR_RC_N" value="128"/>
+        <Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="PROX_IIR_RC_N" value="128"/>
+        <Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="REGULAR_IIR_BL_N" value="1"/>
+        <Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="PROX_IIR_BL_N" value="1"/>
+        <Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="MULTI_FREQ_SCAN_EN" value="false"/>
+        <Property id="SENSOR_AUTO_RESET_EN" value="false"/>
+        <Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
+        <Property id="VREF_SOURCE" value="SRSS"/>
+        <Property id="IREF_SOURCE" value="SRSS"/>
+        <Property id="PROX_TOUCH_COEFF" value="300"/>
+        <Property id="NUM_CENTROIDS" value="1"/>
+    </GeneralProperties>
+    <CsdProperties>
+        <Property id="CSD_AUTOTUNE" value="HWTH"/>
+        <Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
+        <Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
+        <Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
+        <Property id="CSD_IDAC_MIN" value="20"/>
+        <Property id="CSD_IDAC_COMP_EN" value="true"/>
+        <Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
+        <Property id="CSD_VREF_CUSTOM" value="false"/>
+        <Property id="CSD_VREF" value="1219"/>
+        <Property id="CSD_SHIELD_EN" value="false"/>
+        <Property id="CSD_SHIELD_TANK_EN" value="false"/>
+        <Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
+        <Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
+        <Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_FINE_INIT_TIME" value="10"/>
+        <Property id="CSD_CALIBRATION_ERROR" value="10"/>
+        <Property id="CSD_R_CONST" value="1000"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsdProperties>
+    <CsxProperties>
+        <Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSX_MAX_FINGERS" value="3"/>
+        <Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
+        <Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
+        <Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_FINE_INIT_TIME" value="10"/>
+        <Property id="CSX_CALIBRATION_ERROR" value="20"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsxProperties>
+    <Widgets>
+        <Widget id="Button0" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="Button1" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="LinearSlider0" type="LINEAR_SLIDER">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Sns0" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns1" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns2" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns3" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns4" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+    </Widgets>
+</Configuration>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
new file mode 100644
index 00000000000..6df618b3a8d
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
+<Configuration app="QSPI" major="2" minor="0">
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <PartNumber>S25FL512S-4byteaddr</PartNumber>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x4000000</Size>
+            <EndAddress>0x1BFFFFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</Configuration>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus
similarity index 70%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/design.modus
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus
index dade5c7a457..75cb3b72acb 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/design.modus
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus
@@ -8,7 +8,7 @@
                     <Param id="dbgMode" value="SWD"/>
                     <Param id="traceEnable" value="false"/>
                 </Block>
-                <Block location="csd[0].csd[0]" alias="CYBSP_CAPSENSE" template="mxs40csd" version="2.0">
+                <Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
                     <Param id="CapSenseEnable" value="true"/>
                     <Param id="CapSenseCore" value="4"/>
                     <Param id="SensorCount" value="12"/>
@@ -64,36 +64,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[0].pin[4]" alias="CYBSP_SW2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[0].pin[5]" alias="CYBSP_LED5_RGB_G" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[11].pin[1]" alias="CYBSP_LED9" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS0" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
                     <Param id="initialState" value="1"/>
@@ -154,27 +124,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[1].pin[1]" alias="CYBSP_LED5_RGB_R" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[1].pin[4]" alias="CYBSP_SW4" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_RX" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -184,76 +134,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[1].pin[5]" alias="CYBSP_LED8" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[0]" alias="CYBSP_SDHC0_DAT0" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[1]" alias="CYBSP_SDHC0_DAT1" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[2]" alias="CYBSP_SDHC0_DAT2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[3]" alias="CYBSP_SDHC0_DAT3" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[4]" alias="CYBSP_SDHC0_CMD" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[5]" alias="CYBSP_SDHC0_CLK" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[3].pin[0]" alias="CYBSP_BT_UART_RX" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
                     <Param id="initialState" value="1"/>
@@ -324,46 +204,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[5].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[2]" alias="CYBSP_DEBUG_UART_RTS" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[3]" alias="CYBSP_DEBUG_UART_CTS" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
                     <Param id="initialState" value="1"/>
@@ -434,16 +274,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[7].pin[3]" alias="CYBSP_LED5_RGB_B" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[7].pin[7]" alias="CYBSP_CMOD" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
@@ -524,11 +354,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="peri[0].div_16[0]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="52"/>
-                    <Param id="fracDivider" value="0"/>
-                    <Param id="startOnReset" value="true"/>
-                </Block>
                 <Block location="peri[0].div_16[1]" alias="CYBSP_BT_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
                     <Param id="intDivider" value="78"/>
                     <Param id="fracDivider" value="0"/>
@@ -598,59 +423,6 @@
                     <Param id="EnableWakeup" value="false"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
-                    <Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
-                    <Param id="IrdaLowPower" value="false"/>
-                    <Param id="BaudRate" value="115200"/>
-                    <Param id="Oversample" value="12"/>
-                    <Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
-                    <Param id="DataWidth" value="9"/>
-                    <Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
-                    <Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
-                    <Param id="EnableInputFilter" value="false"/>
-                    <Param id="EnableTxEn" value="false"/>
-                    <Param id="FlowControl" value="true"/>
-                    <Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_HIGH"/>
-                    <Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
-                    <Param id="RtsTriggerLevel" value="63"/>
-                    <Param id="RxTriggerLevel" value="63"/>
-                    <Param id="TxTriggerLevel" value="63"/>
-                    <Param id="MultiProc" value="false"/>
-                    <Param id="MpRxAddress" value="0"/>
-                    <Param id="MpRxAddressMask" value="255"/>
-                    <Param id="MpRxAcceptAddress" value="false"/>
-                    <Param id="DropOnFrameErr" value="false"/>
-                    <Param id="DropOnParityErr" value="false"/>
-                    <Param id="BreakSignalBits" value="11"/>
-                    <Param id="SmCardRetryOnNack" value="false"/>
-                    <Param id="IrdaPolarity" value="NON_INVERTING"/>
-                    <Param id="inFlash" value="true"/>
-                    <Param id="ApiMode" value="HIGH_LEVEL"/>
-                    <Param id="IntrRxNotEmpty" value="false"/>
-                    <Param id="IntrRxFull" value="false"/>
-                    <Param id="IntrRxOverflow" value="false"/>
-                    <Param id="IntrRxUnderflow" value="false"/>
-                    <Param id="IntrRxFrameErr" value="false"/>
-                    <Param id="IntrRxParityErr" value="false"/>
-                    <Param id="IntrRxBreakDetected" value="false"/>
-                    <Param id="IntrRxTrigger" value="false"/>
-                    <Param id="IntrTxUartDone" value="false"/>
-                    <Param id="IntrTxUartLostArb" value="false"/>
-                    <Param id="IntrTxUartNack" value="false"/>
-                    <Param id="IntrTxEmpty" value="false"/>
-                    <Param id="IntrTxNotFull" value="false"/>
-                    <Param id="IntrTxOverflow" value="false"/>
-                    <Param id="IntrTxUnderflow" value="false"/>
-                    <Param id="IntrTxTrigger" value="false"/>
-                </Block>
-                <Block location="sdhc[0]" alias="CYBSP_RADIO" template="mxs40sdhost" version="1.0">
-                    <Param id="cardType" value="nonEmmc"/>
-                    <Param id="dmaType" value="CY_SD_HOST_DMA_SDMA"/>
-                    <Param id="enableLedControl" value="false"/>
-                    <Param id="busWidth" value="CY_SD_HOST_BUS_WIDTH_4_BIT"/>
-                    <Param id="lowVoltageSignaling" value="false"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
                     <Param id="configurator" value="0"/>
                     <Param id="isrAlignment" value="false"/>
@@ -683,6 +455,10 @@
                     <Param id="sourceClockNumber" value="0"/>
                     <Param id="divider" value="2"/>
                 </Block>
+                <Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="2"/>
+                    <Param id="divider" value="1"/>
+                </Block>
                 <Block location="srss[0].clock[0].hfclk[4]" alias="" template="mxs40hfclk" version="1.1">
                     <Param id="sourceClockNumber" value="0"/>
                     <Param id="divider" value="1"/>
@@ -702,6 +478,9 @@
                 <Block location="srss[0].clock[0].pathmux[1]" alias="" template="mxs40pathmux" version="1.0">
                     <Param id="sourceClock" value="imo"/>
                 </Block>
+                <Block location="srss[0].clock[0].pathmux[2]" alias="" template="mxs40pathmux" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                </Block>
                 <Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
                     <Param id="divider" value="2"/>
                 </Block>
@@ -711,6 +490,12 @@
                     <Param id="desiredFrequency" value="144.000"/>
                     <Param id="optimization" value="MinPower"/>
                 </Block>
+                <Block location="srss[0].clock[0].pll[1]" alias="" template="mxs40pll" version="1.0">
+                    <Param id="lowFrequencyMode" value="false"/>
+                    <Param id="configuration" value="auto"/>
+                    <Param id="desiredFrequency" value="48.000"/>
+                    <Param id="optimization" value="MinPower"/>
+                </Block>
                 <Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
                     <Param id="divider" value="1"/>
                 </Block>
@@ -739,6 +524,22 @@
                     <Param id="CascadeC1C2" value="false"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
+                <Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
+                    <Param id="pwrEstimator" value="0"/>
+                    <Param id="pwrMode" value="LDO_1_1"/>
+                    <Param id="actPwrMode" value="LP"/>
+                    <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
+                    <Param id="pmicEnable" value="false"/>
+                    <Param id="backupSrc" value="VDDD"/>
+                    <Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
+                    <Param id="deepsleepLatency" value="0"/>
+                    <Param id="vddaMv" value="3300"/>
+                    <Param id="vdddMv" value="3300"/>
+                    <Param id="vBackupMv" value="3300"/>
+                    <Param id="vddNsMv" value="3300"/>
+                    <Param id="vddio0Mv" value="3300"/>
+                    <Param id="vddio1Mv" value="3300"/>
+                </Block>
                 <Block location="srss[0].rtc[0]" alias="CYBSP_RTC" template="mxs40rtc" version="1.1">
                     <Param id="format" value="0"/>
                     <Param id="dst" value="false"/>
@@ -790,30 +591,6 @@
                     <Port name="ioss[0].port[0].pin[1].analog[0]"/>
                     <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
                 </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[0].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[1].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[1]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[2].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[2]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[3].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[3]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[4].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_cmd[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[5].digital_out[0]"/>
-                    <Port name="sdhc[0].clk_card[0]"/>
-                </Net>
                 <Net>
                     <Port name="ioss[0].port[3].pin[0].digital_inout[0]"/>
                     <Port name="scb[2].uart_rx[0]"/>
@@ -830,22 +607,6 @@
                     <Port name="ioss[0].port[3].pin[3].digital_in[0]"/>
                     <Port name="scb[2].uart_cts[0]"/>
                 </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
-                    <Port name="scb[5].uart_rx[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
-                    <Port name="scb[5].uart_tx[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[2].digital_out[0]"/>
-                    <Port name="scb[5].uart_rts[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[3].digital_in[0]"/>
-                    <Port name="scb[5].uart_cts[0]"/>
-                </Net>
                 <Net>
                     <Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
                     <Port name="scb[3].i2c_scl[0]"/>
@@ -878,10 +639,6 @@
                     <Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
                     <Port name="smif[0].spi_clk[0]"/>
                 </Net>
-                <Net>
-                    <Port name="peri[0].div_16[0].clk[0]"/>
-                    <Port name="scb[5].clock[0]"/>
-                </Net>
                 <Net>
                     <Port name="peri[0].div_16[1].clk[0]"/>
                     <Port name="scb[2].clock[0]"/>
@@ -890,10 +647,6 @@
                     <Port name="peri[0].div_8[1].clk[0]"/>
                     <Port name="scb[3].clock[0]"/>
                 </Net>
-                <Net>
-                    <Port name="sdhc[0].clk_hf[0]"/>
-                    <Port name="srss[0].clock[0].hfclk[4].root_clk[0]"/>
-                </Net>
                 <Net>
                     <Port name="smif[0].clk_hf[0]"/>
                     <Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
@@ -912,6 +665,9 @@
                     <Arm>
                         <Port name="ioss[0].port[7].pin[2].analog[0]"/>
                     </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
+                    </Arm>
                     <Arm>
                         <Port name="ioss[0].port[8].pin[1].analog[0]"/>
                     </Arm>
@@ -921,9 +677,6 @@
                     <Arm>
                         <Port name="ioss[0].port[8].pin[2].analog[0]"/>
                     </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
-                    </Arm>
                     <Arm>
                         <Port name="ioss[0].port[8].pin[3].analog[0]"/>
                     </Arm>
@@ -942,6 +695,10 @@
                 </Mux>
             </Netlist>
         </Device>
+        <Device mpn="CYW43012WKWBG">
+            <BlockConfig/>
+            <Netlist/>
+        </Device>
     </Devices>
     <Libraries>
         <Library name="bt_sdk" version="1.1"/>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_pins.h
deleted file mode 100644
index af252206f02..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_pins.h
+++ /dev/null
@@ -1,621 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.h
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PINS_H)
-#define CYCFG_PINS_H
-
-#include "cycfg_notices.h"
-#include "cy_gpio.h"
-#include "cycfg_routing.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_WCO_IN_ENABLED 1U
-#define CYBSP_WCO_IN_PORT GPIO_PRT0
-#define CYBSP_WCO_IN_PIN 0U
-#define CYBSP_WCO_IN_NUM 0U
-#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_0_HSIOM
-	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_WCO_OUT_ENABLED 1U
-#define CYBSP_WCO_OUT_PORT GPIO_PRT0
-#define CYBSP_WCO_OUT_PIN 1U
-#define CYBSP_WCO_OUT_NUM 1U
-#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_1_HSIOM
-	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_SW2_ENABLED 1U
-#define CYBSP_SW2_PORT GPIO_PRT0
-#define CYBSP_SW2_PIN 4U
-#define CYBSP_SW2_NUM 4U
-#define CYBSP_SW2_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SW2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_4_HSIOM
-	#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SW2_HSIOM ioss_0_port_0_pin_4_HSIOM
-#define CYBSP_SW2_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_LED5_RGB_G_ENABLED 1U
-#define CYBSP_LED5_RGB_G_PORT GPIO_PRT0
-#define CYBSP_LED5_RGB_G_PIN 5U
-#define CYBSP_LED5_RGB_G_NUM 5U
-#define CYBSP_LED5_RGB_G_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED5_RGB_G_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_5_HSIOM
-	#define ioss_0_port_0_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED5_RGB_G_HSIOM ioss_0_port_0_pin_5_HSIOM
-#define CYBSP_LED5_RGB_G_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_LED9_ENABLED 1U
-#define CYBSP_LED9_PORT GPIO_PRT11
-#define CYBSP_LED9_PIN 1U
-#define CYBSP_LED9_NUM 1U
-#define CYBSP_LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED9_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_1_HSIOM
-	#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED9_HSIOM ioss_0_port_11_pin_1_HSIOM
-#define CYBSP_LED9_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SS0_ENABLED 1U
-#define CYBSP_QSPI_SS0_PORT GPIO_PRT11
-#define CYBSP_QSPI_SS0_PIN 2U
-#define CYBSP_QSPI_SS0_NUM 2U
-#define CYBSP_QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SS0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_2_HSIOM
-	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
-#define CYBSP_QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_DATA3_ENABLED 1U
-#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11
-#define CYBSP_QSPI_DATA3_PIN 3U
-#define CYBSP_QSPI_DATA3_NUM 3U
-#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_3_HSIOM
-	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
-#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_DATA2_ENABLED 1U
-#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11
-#define CYBSP_QSPI_DATA2_PIN 4U
-#define CYBSP_QSPI_DATA2_NUM 4U
-#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_4_HSIOM
-	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
-#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_DATA1_ENABLED 1U
-#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11
-#define CYBSP_QSPI_DATA1_PIN 5U
-#define CYBSP_QSPI_DATA1_NUM 5U
-#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_5_HSIOM
-	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
-#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_DATA0_ENABLED 1U
-#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11
-#define CYBSP_QSPI_DATA0_PIN 6U
-#define CYBSP_QSPI_DATA0_NUM 6U
-#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_6_HSIOM
-	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
-#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SPI_CLOCK_ENABLED 1U
-#define CYBSP_QSPI_SPI_CLOCK_PORT GPIO_PRT11
-#define CYBSP_QSPI_SPI_CLOCK_PIN 7U
-#define CYBSP_QSPI_SPI_CLOCK_NUM 7U
-#define CYBSP_QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_7_HSIOM
-	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
-#define CYBSP_QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_CSD_TX_ENABLED 1U
-#define CYBSP_CSD_TX_PORT GPIO_PRT1
-#define CYBSP_CSD_TX_PIN 0U
-#define CYBSP_CSD_TX_NUM 0U
-#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_0_HSIOM
-	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_LED5_RGB_R_ENABLED 1U
-#define CYBSP_LED5_RGB_R_PORT GPIO_PRT1
-#define CYBSP_LED5_RGB_R_PIN 1U
-#define CYBSP_LED5_RGB_R_NUM 1U
-#define CYBSP_LED5_RGB_R_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED5_RGB_R_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_1_HSIOM
-	#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED5_RGB_R_HSIOM ioss_0_port_1_pin_1_HSIOM
-#define CYBSP_LED5_RGB_R_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_SW4_ENABLED 1U
-#define CYBSP_SW4_PORT GPIO_PRT1
-#define CYBSP_SW4_PIN 4U
-#define CYBSP_SW4_NUM 4U
-#define CYBSP_SW4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_SW4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_4_HSIOM
-	#define ioss_0_port_1_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SW4_HSIOM ioss_0_port_1_pin_4_HSIOM
-#define CYBSP_SW4_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_LED8_ENABLED 1U
-#define CYBSP_LED8_PORT GPIO_PRT1
-#define CYBSP_LED8_PIN 5U
-#define CYBSP_LED8_NUM 5U
-#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED8_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_5_HSIOM
-	#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
-#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_SDHC0_DAT0_ENABLED 1U
-#define CYBSP_SDHC0_DAT0_PORT GPIO_PRT2
-#define CYBSP_SDHC0_DAT0_PIN 0U
-#define CYBSP_SDHC0_DAT0_NUM 0U
-#define CYBSP_SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_SDHC0_DAT0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_0_HSIOM
-	#define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM
-#define CYBSP_SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_SDHC0_DAT1_ENABLED 1U
-#define CYBSP_SDHC0_DAT1_PORT GPIO_PRT2
-#define CYBSP_SDHC0_DAT1_PIN 1U
-#define CYBSP_SDHC0_DAT1_NUM 1U
-#define CYBSP_SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_SDHC0_DAT1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_1_HSIOM
-	#define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM
-#define CYBSP_SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_SDHC0_DAT2_ENABLED 1U
-#define CYBSP_SDHC0_DAT2_PORT GPIO_PRT2
-#define CYBSP_SDHC0_DAT2_PIN 2U
-#define CYBSP_SDHC0_DAT2_NUM 2U
-#define CYBSP_SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_SDHC0_DAT2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_2_HSIOM
-	#define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM
-#define CYBSP_SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_SDHC0_DAT3_ENABLED 1U
-#define CYBSP_SDHC0_DAT3_PORT GPIO_PRT2
-#define CYBSP_SDHC0_DAT3_PIN 3U
-#define CYBSP_SDHC0_DAT3_NUM 3U
-#define CYBSP_SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_SDHC0_DAT3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_3_HSIOM
-	#define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM
-#define CYBSP_SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_SDHC0_CMD_ENABLED 1U
-#define CYBSP_SDHC0_CMD_PORT GPIO_PRT2
-#define CYBSP_SDHC0_CMD_PIN 4U
-#define CYBSP_SDHC0_CMD_NUM 4U
-#define CYBSP_SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_SDHC0_CMD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_4_HSIOM
-	#define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
-#define CYBSP_SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_SDHC0_CLK_ENABLED 1U
-#define CYBSP_SDHC0_CLK_PORT GPIO_PRT2
-#define CYBSP_SDHC0_CLK_PIN 5U
-#define CYBSP_SDHC0_CLK_NUM 5U
-#define CYBSP_SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_SDHC0_CLK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_5_HSIOM
-	#define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
-#define CYBSP_SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_BT_UART_RX_ENABLED 1U
-#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
-#define CYBSP_BT_UART_RX_PIN 0U
-#define CYBSP_BT_UART_RX_NUM 0U
-#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_0_HSIOM
-	#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
-#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_TX_ENABLED 1U
-#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
-#define CYBSP_BT_UART_TX_PIN 1U
-#define CYBSP_BT_UART_TX_NUM 1U
-#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_1_HSIOM
-	#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
-#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_RTS_ENABLED 1U
-#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
-#define CYBSP_BT_UART_RTS_PIN 2U
-#define CYBSP_BT_UART_RTS_NUM 2U
-#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_2_HSIOM
-	#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
-#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_CTS_ENABLED 1U
-#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
-#define CYBSP_BT_UART_CTS_PIN 3U
-#define CYBSP_BT_UART_CTS_NUM 3U
-#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_3_HSIOM
-	#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
-#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_POWER_ENABLED 1U
-#define CYBSP_BT_POWER_PORT GPIO_PRT3
-#define CYBSP_BT_POWER_PIN 4U
-#define CYBSP_BT_POWER_NUM 4U
-#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
-#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_4_HSIOM
-	#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
-#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_HOST_WAKE_ENABLED 1U
-#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
-#define CYBSP_BT_HOST_WAKE_PIN 5U
-#define CYBSP_BT_HOST_WAKE_NUM 5U
-#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_3_pin_5_HSIOM
-	#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
-#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
-#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
-#define CYBSP_BT_DEVICE_WAKE_PIN 0U
-#define CYBSP_BT_DEVICE_WAKE_NUM 0U
-#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_4_pin_0_HSIOM
-	#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
-#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
-#define CYBSP_DEBUG_UART_RX_ENABLED 1U
-#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_RX_PIN 0U
-#define CYBSP_DEBUG_UART_RX_NUM 0U
-#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_0_HSIOM
-	#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
-#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_DEBUG_UART_TX_ENABLED 1U
-#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_TX_PIN 1U
-#define CYBSP_DEBUG_UART_TX_NUM 1U
-#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_1_HSIOM
-	#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
-#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_DEBUG_UART_RTS_ENABLED 1U
-#define CYBSP_DEBUG_UART_RTS_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_RTS_PIN 2U
-#define CYBSP_DEBUG_UART_RTS_NUM 2U
-#define CYBSP_DEBUG_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_DEBUG_UART_RTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_2_HSIOM
-	#define ioss_0_port_5_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_RTS_HSIOM ioss_0_port_5_pin_2_HSIOM
-#define CYBSP_DEBUG_UART_RTS_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_DEBUG_UART_CTS_ENABLED 1U
-#define CYBSP_DEBUG_UART_CTS_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_CTS_PIN 3U
-#define CYBSP_DEBUG_UART_CTS_NUM 3U
-#define CYBSP_DEBUG_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_DEBUG_UART_CTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_3_HSIOM
-	#define ioss_0_port_5_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_CTS_HSIOM ioss_0_port_5_pin_3_HSIOM
-#define CYBSP_DEBUG_UART_CTS_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_EZI2C_SCL_ENABLED 1U
-#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SCL_PIN 0U
-#define CYBSP_EZI2C_SCL_NUM 0U
-#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_0_HSIOM
-	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
-#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_EZI2C_SDA_ENABLED 1U
-#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SDA_PIN 1U
-#define CYBSP_EZI2C_SDA_NUM 1U
-#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_1_HSIOM
-	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
-#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWO_ENABLED 1U
-#define CYBSP_SWO_PORT GPIO_PRT6
-#define CYBSP_SWO_PIN 4U
-#define CYBSP_SWO_NUM 4U
-#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_SWO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_4_HSIOM
-	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDIO_ENABLED 1U
-#define CYBSP_SWDIO_PORT GPIO_PRT6
-#define CYBSP_SWDIO_PIN 6U
-#define CYBSP_SWDIO_NUM 6U
-#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SWDIO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_6_HSIOM
-	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDCK_ENABLED 1U
-#define CYBSP_SWDCK_PORT GPIO_PRT6
-#define CYBSP_SWDCK_PIN 7U
-#define CYBSP_SWDCK_NUM 7U
-#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define CYBSP_SWDCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_7_HSIOM
-	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_CINA_ENABLED 1U
-#define CYBSP_CINA_PORT GPIO_PRT7
-#define CYBSP_CINA_PIN 1U
-#define CYBSP_CINA_NUM 1U
-#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_1_HSIOM
-	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
-#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CINB_ENABLED 1U
-#define CYBSP_CINB_PORT GPIO_PRT7
-#define CYBSP_CINB_PIN 2U
-#define CYBSP_CINB_NUM 2U
-#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINB_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_2_HSIOM
-	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
-#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_LED5_RGB_B_ENABLED 1U
-#define CYBSP_LED5_RGB_B_PORT GPIO_PRT7
-#define CYBSP_LED5_RGB_B_PIN 3U
-#define CYBSP_LED5_RGB_B_NUM 3U
-#define CYBSP_LED5_RGB_B_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED5_RGB_B_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_3_HSIOM
-	#define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED5_RGB_B_HSIOM ioss_0_port_7_pin_3_HSIOM
-#define CYBSP_LED5_RGB_B_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CMOD_ENABLED 1U
-#define CYBSP_CMOD_PORT GPIO_PRT7
-#define CYBSP_CMOD_PIN 7U
-#define CYBSP_CMOD_NUM 7U
-#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CMOD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_7_HSIOM
-	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
-#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CSD_BTN0_ENABLED 1U
-#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN0_PIN 1U
-#define CYBSP_CSD_BTN0_NUM 1U
-#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_1_HSIOM
-	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_BTN1_ENABLED 1U
-#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN1_PIN 2U
-#define CYBSP_CSD_BTN1_NUM 2U
-#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_2_HSIOM
-	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
-#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD0_ENABLED 1U
-#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD0_PIN 3U
-#define CYBSP_CSD_SLD0_NUM 3U
-#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_3_HSIOM
-	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD1_ENABLED 1U
-#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD1_PIN 4U
-#define CYBSP_CSD_SLD1_NUM 4U
-#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_4_HSIOM
-	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
-#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD2_ENABLED 1U
-#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD2_PIN 5U
-#define CYBSP_CSD_SLD2_NUM 5U
-#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_5_HSIOM
-	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
-#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD3_ENABLED 1U
-#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD3_PIN 6U
-#define CYBSP_CSD_SLD3_NUM 6U
-#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_6_HSIOM
-	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
-#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD4_ENABLED 1U
-#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD4_PIN 7U
-#define CYBSP_CSD_SLD4_NUM 7U
-#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_7_HSIOM
-	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
-#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
-
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SW2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_G_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED9_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_R_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SW4_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CMD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CLK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_CTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_B_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
-
-void init_cycfg_pins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PINS_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.c
deleted file mode 100644
index d2a75240e61..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_system.c
-*
-* Description:
-* System configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_system.h"
-
-#define CY_CFG_SYSCLK_ECO_ERROR 1
-#define CY_CFG_SYSCLK_ALTHF_ERROR 2
-#define CY_CFG_SYSCLK_PLL_ERROR 3
-#define CY_CFG_SYSCLK_FLL_ERROR 4
-#define CY_CFG_SYSCLK_WCO_ERROR 5
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
-#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
-#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
-#define CY_CFG_SYSCLK_FLL_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 144UL
-#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
-#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
-#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
-#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_ILO_ENABLED 1
-#define CY_CFG_SYSCLK_IMO_ENABLED 1
-#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
-#define CY_CFG_SYSCLK_PLL0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
-#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
-#define CY_CFG_SYSCLK_WCO_ENABLED 1
-
-static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = 
-{
-	.fllMult = 500U,
-	.refDiv = 20U,
-	.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
-	.enableOutputDiv = true,
-	.lockTolerance = 10U,
-	.igain = 9U,
-	.pgain = 5U,
-	.settlingCount = 8U,
-	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
-	.cco_Freq = 355U,
-};
-static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = 
-{
-	.feedbackDiv = 36,
-	.referenceDiv = 1,
-	.outputDiv = 2,
-	.lfMode = false,
-	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
-};
-
-__WEAK void cycfg_ClockStartupError(uint32_t error)
-{
-    (void)error; /* Suppress the compiler warning */
-    while(1);
-}
-__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
-{
-    Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
-}
-__STATIC_INLINE void Cy_SysClk_ClkBakInit()
-{
-    Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
-}
-__STATIC_INLINE void Cy_SysClk_ClkFastInit()
-{
-    Cy_SysClk_ClkFastSetDivider(0U);
-}
-__STATIC_INLINE void Cy_SysClk_FllInit()
-{
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
-    }
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
-    }
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
-{
-    Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
-{
-    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
-    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
-{
-    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
-    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
-}
-__STATIC_INLINE void Cy_SysClk_IloInit()
-{
-    /* The WDT is unlocked in the default startup code */
-    Cy_SysClk_IloEnable();
-    Cy_SysClk_IloHibernateOn(true);
-}
-__STATIC_INLINE void Cy_SysClk_ClkLfInit()
-{
-    /* The WDT is unlocked in the default startup code */
-    Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
-{
-    Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
-{
-    Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
-{
-    Cy_SysClk_ClkPeriSetDivider(1U);
-}
-__STATIC_INLINE void Cy_SysClk_Pll0Init()
-{
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
-    }
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
-    }
-}
-__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
-{
-    Cy_SysClk_ClkSlowSetDivider(0U);
-}
-__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
-{
-    Cy_SysClk_ClkTimerDisable();
-     Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
-    Cy_SysClk_ClkTimerSetDivider(0U);
-    Cy_SysClk_ClkTimerEnable();
-}
-__STATIC_INLINE void Cy_SysClk_WcoInit()
-{
-    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
-    }
-}
-
-
-void init_cycfg_system(void)
-{
-	/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
-	Cy_SysLib_SetWaitStates(false, 150UL);
-	#ifdef CY_CFG_PWR_ENABLED
-	    #ifdef CY_CFG_PWR_INIT
-	    init_cycfg_power();
-	    #else
-	    #warning Power system will not be configured. Update power personality to v1.20 or later.
-	    #endif /* CY_CFG_PWR_INIT */
-	#endif /* CY_CFG_PWR_ENABLED */
-	
-	/* Reset the core clock path to default and disable all the FLLs/PLLs */
-	Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
-	Cy_SysClk_ClkFastSetDivider(0U);
-	Cy_SysClk_ClkPeriSetDivider(1U);
-	Cy_SysClk_ClkSlowSetDivider(0U);
-	for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
-	{
-	    (void)Cy_SysClk_PllDisable(pll);
-	}
-	Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
-	
-	if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
-	    (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
-	{
-	    Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
-	}
-	
-	Cy_SysClk_FllDisable();
-	Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
-	Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
-	#ifdef CY_IP_MXBLESS
-	(void)Cy_BLE_EcoReset();
-	#endif
-	
-	
-	/* Enable all source clocks */
-	#ifdef CY_CFG_SYSCLK_PILO_ENABLED
-	Cy_SysClk_PiloInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_WCO_ENABLED
-	Cy_SysClk_WcoInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
-	Cy_SysClk_ClkLfInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
-	Cy_SysClk_AltHfInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_ECO_ENABLED
-	Cy_SysClk_EcoInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
-	Cy_SysClk_ExtClkInit();
-	#endif
-	
-	/* Configure CPU clock dividers */
-	#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
-	Cy_SysClk_ClkFastInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
-	Cy_SysClk_ClkPeriInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
-	Cy_SysClk_ClkSlowInit();
-	#endif
-	
-	#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
-	    /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
-	    Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
-	    Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
-	#else
-	    #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
-	        Cy_SysClk_ClkPath1Init();
-	    #endif
-	#endif
-	
-	/* Configure Path Clocks */
-	#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
-	Cy_SysClk_ClkPath0Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
-	Cy_SysClk_ClkPath2Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
-	Cy_SysClk_ClkPath3Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
-	Cy_SysClk_ClkPath4Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
-	Cy_SysClk_ClkPath5Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
-	Cy_SysClk_ClkPath6Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
-	Cy_SysClk_ClkPath7Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
-	Cy_SysClk_ClkPath8Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
-	Cy_SysClk_ClkPath9Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
-	Cy_SysClk_ClkPath10Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
-	Cy_SysClk_ClkPath11Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
-	Cy_SysClk_ClkPath12Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
-	Cy_SysClk_ClkPath13Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
-	Cy_SysClk_ClkPath14Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
-	Cy_SysClk_ClkPath15Init();
-	#endif
-	
-	/* Configure and enable FLL */
-	#ifdef CY_CFG_SYSCLK_FLL_ENABLED
-	Cy_SysClk_FllInit();
-	#endif
-	
-	Cy_SysClk_ClkHf0Init();
-	
-	#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
-	    #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
-	        /* Apply the ClkPath1 user setting */
-	        Cy_SysClk_ClkPath1Init();
-	    #endif
-	#endif
-	
-	/* Configure and enable PLLs */
-	#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
-	Cy_SysClk_Pll0Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
-	Cy_SysClk_Pll1Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
-	Cy_SysClk_Pll2Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
-	Cy_SysClk_Pll3Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
-	Cy_SysClk_Pll4Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
-	Cy_SysClk_Pll5Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
-	Cy_SysClk_Pll6Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
-	Cy_SysClk_Pll7Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
-	Cy_SysClk_Pll8Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
-	Cy_SysClk_Pll9Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
-	Cy_SysClk_Pll10Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
-	Cy_SysClk_Pll11Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
-	Cy_SysClk_Pll12Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
-	Cy_SysClk_Pll13Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
-	Cy_SysClk_Pll14Init();
-	#endif
-	
-	/* Configure HF clocks */
-	#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
-	Cy_SysClk_ClkHf1Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
-	Cy_SysClk_ClkHf2Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
-	Cy_SysClk_ClkHf3Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
-	Cy_SysClk_ClkHf4Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
-	Cy_SysClk_ClkHf5Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
-	Cy_SysClk_ClkHf6Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
-	Cy_SysClk_ClkHf7Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
-	Cy_SysClk_ClkHf8Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
-	Cy_SysClk_ClkHf9Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
-	Cy_SysClk_ClkHf10Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
-	Cy_SysClk_ClkHf11Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
-	Cy_SysClk_ClkHf12Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
-	Cy_SysClk_ClkHf13Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
-	Cy_SysClk_ClkHf14Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
-	Cy_SysClk_ClkHf15Init();
-	#endif
-	
-	/* Configure miscellaneous clocks */
-	#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
-	Cy_SysClk_ClkTimerInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
-	Cy_SysClk_ClkAltSysTickInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
-	Cy_SysClk_ClkPumpInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
-	Cy_SysClk_ClkBakInit();
-	#endif
-	
-	/* Configure default enabled clocks */
-	#ifdef CY_CFG_SYSCLK_ILO_ENABLED
-	Cy_SysClk_IloInit();
-	#else
-	Cy_SysClk_IloDisable();
-	#endif
-	
-	#ifndef CY_CFG_SYSCLK_IMO_ENABLED
-	#error the IMO must be enabled for proper chip operation
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_MFO_ENABLED
-	Cy_SysClk_MfoInit();
-	#endif
-	
-	#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
-	Cy_SysClk_ClkMfInit();
-	#endif
-	
-	/* Set accurate flash wait states */
-	#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
-	Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
-	#endif
-	
-	/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
-	SystemCoreClockUpdate();
-}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.h
deleted file mode 100644
index 92f9d43bc52..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/cycfg_system.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_system.h
-*
-* Description:
-* System configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_SYSTEM_H)
-#define CYCFG_SYSTEM_H
-
-#include "cycfg_notices.h"
-#include "cy_sysclk.h"
-#include "cy_systick.h"
-#include "cy_gpio.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define cpuss_0_dap_0_ENABLED 1U
-#define srss_0_clock_0_ENABLED 1U
-#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
-#define srss_0_clock_0_bakclk_0_ENABLED 1U
-#define srss_0_clock_0_fastclk_0_ENABLED 1U
-#define srss_0_clock_0_fll_0_ENABLED 1U
-#define srss_0_clock_0_hfclk_0_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF0 0UL
-#define srss_0_clock_0_hfclk_2_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF2 2UL
-#define srss_0_clock_0_hfclk_4_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF4 4UL
-#define srss_0_clock_0_ilo_0_ENABLED 1U
-#define srss_0_clock_0_imo_0_ENABLED 1U
-#define srss_0_clock_0_lfclk_0_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000
-#define srss_0_clock_0_pathmux_0_ENABLED 1U
-#define srss_0_clock_0_pathmux_1_ENABLED 1U
-#define srss_0_clock_0_periclk_0_ENABLED 1U
-#define srss_0_clock_0_pll_0_ENABLED 1U
-#define srss_0_clock_0_slowclk_0_ENABLED 1U
-#define srss_0_clock_0_timerclk_0_ENABLED 1U
-#define srss_0_clock_0_wco_0_ENABLED 1U
-
-void init_cycfg_system(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_SYSTEM_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/qspi_config.cfg
deleted file mode 100644
index a561643dcf1..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/GeneratedSource/qspi_config.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-set SMIF_BANKS {
-}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/PinNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/PinNames.h
index f35b123cc29..5e3e9245173 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/PinNames.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/PinNames.h
@@ -20,39 +20,8 @@
 #ifndef MBED_PINNAMES_H
 #define MBED_PINNAMES_H
 
-#include "cmsis.h"
 #include "PinNamesTypes.h"
-#include "PortNames.h"
 #include "cyhal_pin_package.h"
-#include "cyhal_utils.h"
-
-typedef cyhal_gpio_t PinName;
-
-// Arduino connector namings
-#define A0 P10_0
-#define A1 P10_1
-#define A2 P10_2
-#define A3 P10_3
-#define A4 P10_4
-#define A5 P10_5
-
-#define D0 P5_0
-#define D1 P5_1
-#define D2 P5_2
-#define D3 P5_3
-#define D4 P5_4
-#define D5 P5_5
-#define D6 P5_6
-#define D7 P0_2
-#define D8 P13_0
-#define D9 P13_1
-#define D10 P12_3
-#define D11 P12_0
-#define D12 P12_1
-#define D13 P12_2
-#define D14 P6_1
-#define D15 P6_0
-
 
 // Generic signal names
 
@@ -64,46 +33,23 @@ typedef cyhal_gpio_t PinName;
 #define UART_RTS P5_2
 #define UART_CTS P5_3
 
-#define SPI_MOSI P12_0
-#define SPI_MISO P12_1
-#define SPI_CLK P12_2
-#define SPI_CS P12_4
-
-#define UART_RX P5_0
-#define UART_TX P5_1
-#define UART_RTS P5_2
-#define UART_CTS P5_3
-
-#define BT_UART_RX P3_0
-#define BT_UART_TX P3_1
-#define BT_UART_CTS P3_3
-#define BT_UART_RTS P3_2
+#define LED1 P1_1
+#define LED2 P0_5
+#define LED3 P7_3
+#define LED4 P1_5
+#define LED5 P11_1
+#define LED_RED LED1
+#define LED_GREEN LED2
+#define LED_BLUE LED3
 
-#define BT_PIN_POWER P3_4
-#define BT_PIN_HOST_WAKE P3_5
-#define BT_PIN_DEVICE_WAKE P4_0
 // Reset pin unavailable
-
 #define SWITCH2 P0_4
-#define LED1 P13_7
-#define LED2 NC
-#define LED3 NC
-#define LED4 NC
-#define LED_RED LED1
-
+#define SWITCH4 P1_4
 #define USER_BUTTON SWITCH2
 #define BUTTON1 USER_BUTTON
+#define BUTTON2 SWITCH4
 
-#define PDM_DATA P10_5
-#define PDM_CLK P10_4
-#define THERM_OUT_1 P10_1
-#define THERM_OUT_2 P10_2
-#define THERM_OUT THERM_OUT_1
-#define THERM_VDD P10_3
-#define THERM_GND P10_0
-
-#define CARD_DETECT_1 P13_5
-#define CARD_DETECT_2 P12_1
+#define CARD_DETECT_1 P13_7
 #define CARD_DETECT CARD_DETECT_1
 #define SD_CMD P12_4
 #define SD_CLK P12_5
@@ -132,23 +78,7 @@ typedef cyhal_gpio_t PinName;
 #define STDIO_UART_CTS UART_CTS
 #define STDIO_UART_RTS UART_RTS
 
-#define CY_STDIO_UART_RX STDIO_UART_RX
-#define CY_STDIO_UART_TX STDIO_UART_TX
-#define CY_STDIO_UART_CTS STDIO_UART_CTS
-#define CY_STDIO_UART_RTS STDIO_UART_RTS
-
-#define CY_BT_UART_RX BT_UART_RX
-#define CY_BT_UART_TX BT_UART_TX
-#define CY_BT_UART_CTS BT_UART_CTS
-#define CY_BT_UART_RTS BT_UART_RTS
-
-#define CY_BT_PIN_POWER BT_PIN_POWER
-#define CY_BT_PIN_HOST_WAKE BT_PIN_HOST_WAKE
-#define CY_BT_PIN_DEVICE_WAKE BT_PIN_DEVICE_WAKE
-
 #define USBTX UART_TX
 #define USBRX UART_RX
 
-#define CY_WIFI_HOST_WAKE P2_7
-
 #endif
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h
index 395e75bd254..cfec04a1e25 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h
@@ -23,14 +23,6 @@
 * limitations under the License.
 *******************************************************************************/
 
-/**
-* \addtogroup group_bsp_cy8ckit_062s2_43012 CY8CKIT-062S2-43012
-* \ingroup group_bsp
-* \{
-* \defgroup group_bsp_cy8ckit_062s2_43012_macros Macros
-* \defgroup group_bsp_cy8ckit_062s2_43012_enums Enumerated Types
-*/
-
 #pragma once
 
 #include "cyhal.h"
@@ -39,9 +31,8 @@
 extern "C" {
 #endif
 
-
 /**
-* \addtogroup group_bsp_cy8ckit_062s2_43012_macros
+* \addtogroup group_bsp_pins Pin Mappings
 * \{
 */
 
@@ -98,18 +89,25 @@ extern "C" {
 #define CYBSP_WCO_OUT          P0_1
 
 /** Pin: WIFI SDIO D0 */
+/* Corresponds to: ioss[0].port[2].pin[0], sdhc[0] */
 #define CYBSP_WIFI_SDIO_D0     P2_0
 /** Pin: WIFI SDIO D1 */
+/* Corresponds to: ioss[0].port[2].pin[1], sdhc[0] */
 #define CYBSP_WIFI_SDIO_D1     P2_1
 /** Pin: WIFI SDIO D2 */
+/* Corresponds to: ioss[0].port[2].pin[2], sdhc[0] */
 #define CYBSP_WIFI_SDIO_D2     P2_2
 /** Pin: WIFI SDIO D3 */
+/* Corresponds to: ioss[0].port[2].pin[3], sdhc[0] */
 #define CYBSP_WIFI_SDIO_D3     P2_3
 /** Pin: WIFI SDIO CMD */
+/* Corresponds to: ioss[0].port[2].pin[4], sdhc[0] */
 #define CYBSP_WIFI_SDIO_CMD    P2_4
 /** Pin: WIFI SDIO CLK */
+/* Corresponds to: ioss[0].port[2].pin[5], sdhc[0] */
 #define CYBSP_WIFI_SDIO_CLK    P2_5
 /** Pin: WIFI ON */
+/* Corresponds to: ioss[0].port[2].pin[6], sdhc[0] */
 #define CYBSP_WIFI_WL_REG_ON   P2_6
 /** Pin: WIFI Host Wakeup */
 #define CYBSP_WIFI_HOST_WAKE   P4_1
@@ -125,17 +123,21 @@ extern "C" {
 /** Pin: BT Power */
 #define CYBSP_BT_POWER         P3_4
 /** Pin: BT Host Wakeup */
-#define CYBSP_BT_HOST_WAKE     P3_5
+#define CYBSP_BT_HOST_WAKE     P4_0
 /** Pin: BT Device Wakeup */
-#define CYBSP_BT_DEVICE_WAKE   P4_0
+#define CYBSP_BT_DEVICE_WAKE   P3_5
 
 /** Pin: UART RX */
+/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
 #define CYBSP_DEBUG_UART_RX    P5_0
 /** Pin: UART TX */
+/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
 #define CYBSP_DEBUG_UART_TX    P5_1
 /** Pin: UART RX */
+/* Corresponds to: ioss[0].port[5].pin[2], scb[5] */
 #define CYBSP_DEBUG_UART_RTS   P5_2
 /** Pin: UART TX */
+/* Corresponds to: ioss[0].port[5].pin[3], scb[5] */
 #define CYBSP_DEBUG_UART_CTS   P5_3
 
 /** Pin: I2C SCL */
@@ -150,8 +152,8 @@ extern "C" {
 /** Pin: SWDCK */
 #define CYBSP_SWDCK            P6_7
 
-/** Pin: CapSesnse TX */
-#define CYBSP_CSD_TX           P1_0
+/** Pin: CapSesnse RX */
+#define CYBSP_CSD_RX           P1_0
 /** Pin: CapSesnse CINA */
 #define CYBSP_CINA             P7_1
 /** Pin: CapSesnse CINB */
@@ -218,10 +220,10 @@ extern "C" {
 #define SW4                    P1_4
 
 
-/** \} group_bsp_cy8ckit_062s2_43012_macros */
+/** \} group_bsp_cy8ckit_pins */
 
 /**
-* \addtogroup group_bsp_cy8ckit_062s2_43012_enums
+* \addtogroup group_bsp_enums Enumerated Types
 * \{
 */
 
@@ -247,10 +249,15 @@ typedef enum
     CYBSP_LED_RGB_GREEN = LED5_RGB_G,
     CYBSP_LED_RGB_BLUE = LED5_RGB_B,
 
+    /* Corresponds to: ioss[0].port[11].pin[1] */
     CYBSP_USER_LED1 = LED9_R,
+    /* Corresponds to: ioss[0].port[1].pin[5] */
     CYBSP_USER_LED2 = LED8_O,
+    /* Corresponds to: ioss[0].port[1].pin[1] */
     CYBSP_USER_LED3 = CYBSP_LED_RGB_RED,
+    /* Corresponds to: ioss[0].port[0].pin[5] */
     CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN,
+    /* Corresponds to: ioss[0].port[7].pin[3] */
     CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE,
     CYBSP_USER_LED = CYBSP_USER_LED1,
 } cybsp_led_t;
@@ -259,16 +266,16 @@ typedef enum
 /** Enum defining the different user buttons available on the board. */
 typedef enum
 {
+    /* Corresponds to: ioss[0].port[0].pin[4] */
     CYBSP_USER_BTN1 = SW2,
+    /* Corresponds to: ioss[0].port[1].pin[4] */
     CYBSP_USER_BTN2 = SW4,
     CYBSP_USER_BTN = CYBSP_USER_BTN1,
 } cybsp_btn_t;
 
 
-/** \} group_bsp_cy8ckit_062s2_43012_enums */
+/** \} group_bsp_enums */
 
 #if defined(__cplusplus)
 }
 #endif
-
-/** \} group_bsp_cy8ckit_062s2_43012 */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
new file mode 100644
index 00000000000..6911b5befd4
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
@@ -0,0 +1,24 @@
+/*******************************************************************************
+* File Name: cycfg.timestamp
+*
+* Description:
+* Sentinel file for determining if generated source is up to date.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
similarity index 67%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
index 8494d2bc110..134bf0857b6 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
@@ -24,18 +24,37 @@
 
 #include "cycfg_clocks.h"
 
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+
 
 void init_cycfg_clocks(void)
 {
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
 	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
similarity index 82%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
index 34da2e34d96..e3b24b9d0e7 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
@@ -27,6 +27,9 @@
 
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 
 #if defined(__cplusplus)
 extern "C" {
@@ -38,9 +41,13 @@ extern "C" {
 #define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
-#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
+
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_clocks(void);
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_notices.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
similarity index 62%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
index d8a12803e74..e6887747f62 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
@@ -24,6 +24,14 @@
 
 #include "cycfg_peripherals.h"
 
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BLE_obj = 
+	{
+		.type = CYHAL_RSC_BLESS,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 cy_stc_csd_context_t cy_csd_0_context = 
 {
 	.lockKey = CY_CSD_NONE_KEY,
@@ -36,34 +44,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
 	.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
 	.enableWakeFromSleep = false,
 };
-const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = 
-{
-	.uartMode = CY_SCB_UART_STANDARD,
-	.enableMutliProcessorMode = false,
-	.smartCardRetryOnNack = false,
-	.irdaInvertRx = false,
-	.irdaEnableLowPowerReceiver = false,
-	.oversample = 8,
-	.enableMsbFirst = false,
-	.dataWidth = 8UL,
-	.parity = CY_SCB_UART_PARITY_NONE,
-	.stopBits = CY_SCB_UART_STOP_BITS_1,
-	.enableInputFilter = false,
-	.breakWidth = 11UL,
-	.dropOnFrameError = false,
-	.dropOnParityError = false,
-	.receiverAddress = 0x0UL,
-	.receiverAddressMask = 0x0UL,
-	.acceptAddrInFifo = false,
-	.enableCts = false,
-	.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rtsRxFifoLevel = 0UL,
-	.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rxFifoTriggerLevel = 63UL,
-	.rxFifoIntEnableMask = 0UL,
-	.txFifoTriggerLevel = 63UL,
-	.txFifoIntEnableMask = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_smif_config_t CYBSP_QSPI_config = 
 {
 	.mode = (uint32_t)CY_SMIF_NORMAL,
@@ -71,6 +59,14 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
 	.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
 	.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_obj = 
+	{
+		.type = CYHAL_RSC_SMIF,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config = 
 {
 	.c0Match = 32768U,
@@ -84,6 +80,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
 	.c0c1Cascade = true,
 	.c1c2Cascade = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_MCWDT0_obj = 
+	{
+		.type = CYHAL_RSC_LPTIMER,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_rtc_config_t CYBSP_RTC_config = 
 {
 	.sec = 0U,
@@ -96,13 +100,38 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
 	.month = CY_RTC_JANUARY,
 	.year = 0U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_RTC_obj = 
+	{
+		.type = CYHAL_RSC_RTC,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_peripherals(void)
 {
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BLE_obj);
+#endif //defined (CY_USING_HAL)
+
 	Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
similarity index 86%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
index 7ae726a3245..5663a80077f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
@@ -26,11 +26,14 @@
 #define CYCFG_PERIPHERALS_H
 
 #include "cycfg_notices.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_sysclk.h"
 #include "cy_csd.h"
 #include "cy_scb_ezi2c.h"
-#include "cy_scb_uart.h"
 #include "cy_smif.h"
+#include "cycfg_qspi_memslot.h"
 #include "cy_mcwdt.h"
 #include "cy_rtc.h"
 
@@ -85,9 +88,6 @@ extern "C" {
 #define CYBSP_CSD_COMM_ENABLED 1U
 #define CYBSP_CSD_COMM_HW SCB3
 #define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
-#define CYBSP_DEBUG_UART_ENABLED 1U
-#define CYBSP_DEBUG_UART_HW SCB5
-#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
 #define CYBSP_QSPI_ENABLED 1U
 #define CYBSP_QSPI_HW SMIF0
 #define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@@ -118,12 +118,26 @@ extern "C" {
 #define CYBSP_RTC_10_YEAR_OFFSET (4U)
 #define CYBSP_RTC_YEAR_OFFSET (0U)
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BLE_obj;
+#endif //defined (CY_USING_HAL)
 extern cy_stc_csd_context_t cy_csd_0_context;
 extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
-extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_rtc_config_t CYBSP_RTC_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_RTC_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_peripherals(void);
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
similarity index 59%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
index a24b4926748..f38baebd1e0 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
@@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_IN_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_IN_PORT_NUM,
+		.channel_num = CYBSP_WCO_IN_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = 
 {
 	.outVal = 1,
@@ -56,54 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_RED_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_BTN2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_PULLUP,
-	.hsiom = CYBSP_BTN2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_BLUE_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_OUT_PORT_NUM,
+		.channel_num = CYBSP_WCO_OUT_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = 
 {
 	.outVal = 1,
@@ -120,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SS_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = 
 {
 	.outVal = 1,
@@ -136,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D3_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = 
 {
 	.outVal = 1,
@@ -152,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D2_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = 
 {
 	.outVal = 1,
@@ -168,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D1_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = 
 {
 	.outVal = 1,
@@ -184,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D0_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = 
 {
 	.outVal = 1,
@@ -200,22 +208,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED9_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED9_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SCK_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = 
 {
 	.outVal = 1,
@@ -232,70 +232,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_GREEN_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED8_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED8_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_HIGHZ,
-	.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_TX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_TX_PORT_NUM,
+		.channel_num = CYBSP_CSD_TX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = 
 {
 	.outVal = 1,
@@ -312,6 +256,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SCL_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = 
 {
 	.outVal = 1,
@@ -328,6 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SDA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWO_config = 
 {
 	.outVal = 1,
@@ -344,6 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWO_PORT_NUM,
+		.channel_num = CYBSP_SWO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = 
 {
 	.outVal = 1,
@@ -360,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDIO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDIO_PORT_NUM,
+		.channel_num = CYBSP_SWDIO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = 
 {
 	.outVal = 1,
@@ -376,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDCK_PORT_NUM,
+		.channel_num = CYBSP_SWDCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINA_config = 
 {
 	.outVal = 1,
@@ -392,6 +376,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINA_PORT_NUM,
+		.channel_num = CYBSP_CINA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINB_config = 
 {
 	.outVal = 1,
@@ -408,6 +400,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINB_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINB_PORT_NUM,
+		.channel_num = CYBSP_CINB_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = 
 {
 	.outVal = 1,
@@ -424,6 +424,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CMOD_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CMOD_PORT_NUM,
+		.channel_num = CYBSP_CMOD_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = 
 {
 	.outVal = 1,
@@ -440,6 +448,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN0_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = 
 {
 	.outVal = 1,
@@ -456,6 +472,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN1_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = 
 {
 	.outVal = 1,
@@ -472,6 +496,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD0_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = 
 {
 	.outVal = 1,
@@ -488,6 +520,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD1_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = 
 {
 	.outVal = 1,
@@ -504,6 +544,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD2_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = 
 {
 	.outVal = 1,
@@ -520,6 +568,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD3_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = 
 {
 	.outVal = 1,
@@ -536,60 +592,124 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD4_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD4_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_pins(void)
 {
 	Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_BTN2_PORT, CYBSP_BTN2_PIN, &CYBSP_BTN2_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_BLUE_PORT, CYBSP_LED_BLUE_PIN, &CYBSP_LED_BLUE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_GPIO_Pin_Init(CYBSP_LED9_PORT, CYBSP_LED9_PIN, &CYBSP_LED9_config);
-
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_GREEN_PORT, CYBSP_LED_GREEN_PIN, &CYBSP_LED_GREEN_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED8_PORT, CYBSP_LED8_PIN, &CYBSP_LED8_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
new file mode 100644
index 00000000000..b693883d48a
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
@@ -0,0 +1,720 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cycfg_notices.h"
+#include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cycfg_routing.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PORT_NUM 0U
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_0_HSIOM
+	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PORT_NUM 0U
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_1_HSIOM
+	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SS_ENABLED 1U
+#define CYBSP_QSPI_SS_PORT GPIO_PRT11
+#define CYBSP_QSPI_SS_PORT_NUM 11U
+#define CYBSP_QSPI_SS_PIN 2U
+#define CYBSP_QSPI_SS_NUM 2U
+#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_2_HSIOM
+	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
+#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D3_ENABLED 1U
+#define CYBSP_QSPI_D3_PORT GPIO_PRT11
+#define CYBSP_QSPI_D3_PORT_NUM 11U
+#define CYBSP_QSPI_D3_PIN 3U
+#define CYBSP_QSPI_D3_NUM 3U
+#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_3_HSIOM
+	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
+#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D2_ENABLED 1U
+#define CYBSP_QSPI_D2_PORT GPIO_PRT11
+#define CYBSP_QSPI_D2_PORT_NUM 11U
+#define CYBSP_QSPI_D2_PIN 4U
+#define CYBSP_QSPI_D2_NUM 4U
+#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_4_HSIOM
+	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
+#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D1_ENABLED 1U
+#define CYBSP_QSPI_D1_PORT GPIO_PRT11
+#define CYBSP_QSPI_D1_PORT_NUM 11U
+#define CYBSP_QSPI_D1_PIN 5U
+#define CYBSP_QSPI_D1_NUM 5U
+#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_5_HSIOM
+	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
+#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D0_ENABLED 1U
+#define CYBSP_QSPI_D0_PORT GPIO_PRT11
+#define CYBSP_QSPI_D0_PORT_NUM 11U
+#define CYBSP_QSPI_D0_PIN 6U
+#define CYBSP_QSPI_D0_NUM 6U
+#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_6_HSIOM
+	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
+#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SCK_ENABLED 1U
+#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
+#define CYBSP_QSPI_SCK_PORT_NUM 11U
+#define CYBSP_QSPI_SCK_PIN 7U
+#define CYBSP_QSPI_SCK_NUM 7U
+#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_7_HSIOM
+	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_TX_ENABLED 1U
+#define CYBSP_CSD_TX_PORT GPIO_PRT1
+#define CYBSP_CSD_TX_PORT_NUM 1U
+#define CYBSP_CSD_TX_PIN 0U
+#define CYBSP_CSD_TX_NUM 0U
+#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_0_HSIOM
+	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_PORT_PIN P1_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SCL_ENABLED 1U
+#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SCL_PORT_NUM 6U
+#define CYBSP_EZI2C_SCL_PIN 0U
+#define CYBSP_EZI2C_SCL_NUM 0U
+#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_0_HSIOM
+	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
+#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SDA_ENABLED 1U
+#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SDA_PORT_NUM 6U
+#define CYBSP_EZI2C_SDA_PIN 1U
+#define CYBSP_EZI2C_SDA_NUM 1U
+#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_1_HSIOM
+	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
+#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PORT_NUM 6U
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_4_HSIOM
+	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_PORT_PIN P6_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PORT_NUM 6U
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_6_HSIOM
+	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDCK_ENABLED 1U
+#define CYBSP_SWDCK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PORT_NUM 6U
+#define CYBSP_SWDCK_PIN 7U
+#define CYBSP_SWDCK_NUM 7U
+#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_7_HSIOM
+	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINA_ENABLED 1U
+#define CYBSP_CINA_PORT GPIO_PRT7
+#define CYBSP_CINA_PORT_NUM 7U
+#define CYBSP_CINA_PIN 1U
+#define CYBSP_CINA_NUM 1U
+#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_1_HSIOM
+	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_PORT_PIN P7_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINB_ENABLED 1U
+#define CYBSP_CINB_PORT GPIO_PRT7
+#define CYBSP_CINB_PORT_NUM 7U
+#define CYBSP_CINB_PIN 2U
+#define CYBSP_CINB_NUM 2U
+#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINB_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_2_HSIOM
+	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_PORT_PIN P7_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PORT_NUM 7U
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_7_HSIOM
+	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_PORT_PIN P7_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN0_PORT_NUM 8U
+#define CYBSP_CSD_BTN0_PIN 1U
+#define CYBSP_CSD_BTN0_NUM 1U
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_1_HSIOM
+	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN1_PORT_NUM 8U
+#define CYBSP_CSD_BTN1_PIN 2U
+#define CYBSP_CSD_BTN1_NUM 2U
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_2_HSIOM
+	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD0_PORT_NUM 8U
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_3_HSIOM
+	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD1_PORT_NUM 8U
+#define CYBSP_CSD_SLD1_PIN 4U
+#define CYBSP_CSD_SLD1_NUM 4U
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_4_HSIOM
+	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD2_PORT_NUM 8U
+#define CYBSP_CSD_SLD2_PIN 5U
+#define CYBSP_CSD_SLD2_NUM 5U
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_5_HSIOM
+	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD3_PORT_NUM 8U
+#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_6_HSIOM
+	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD4_PORT_NUM 8U
+#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_7_HSIOM
+	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINB_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
similarity index 81%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
index 12487034d72..c4e5bcf916f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
@@ -24,10 +24,10 @@
 
 #include "cycfg_qspi_memslot.h"
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xEBU,
+    .command = 0xECU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -42,7 +42,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x06U,
@@ -60,7 +60,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x04U,
@@ -78,10 +78,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xD8U,
+    .command = 0xDCU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -96,7 +96,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x60U,
@@ -114,10 +114,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x38U,
+    .command = 0x34U,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -132,7 +132,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x35U,
@@ -150,7 +150,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x05U,
@@ -168,7 +168,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x01U,
@@ -186,52 +186,52 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Specifies the number of address bytes used by the memory slave device. */
-    .numOfAddrBytes = 0x03U,
+    .numOfAddrBytes = 0x04U,
     /* The size of the memory. */
     .memSize = 0x04000000U,
     /* Specifies the Read command. */
-    .readCmd = &S25FL512S_SlaveSlot_0_readCmd,
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
     /* Specifies the Write Enable command. */
-    .writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
     /* Specifies the Write Disable command. */
-    .writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
     /* Specifies the Erase command. */
-    .eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
     /* Specifies the sector size of each erase. */
     .eraseSize = 0x00040000U,
     /* Specifies the Chip Erase command. */
-    .chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
     /* Specifies the Program command. */
-    .programCmd = &S25FL512S_SlaveSlot_0_programCmd,
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
     /* Specifies the page size for programming. */
     .programSize = 0x00000200U,
     /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
     /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
     /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
     /* The mask for the status register. */
     .stsRegBusyMask = 0x01U,
     /* The mask for the status register. */
     .stsRegQuadEnableMask = 0x02U,
     /* The max time for the erase type-1 cycle-time in ms. */
-    .eraseTime = 520U,
+    .eraseTime = 2600U,
     /* The max time for the chip-erase cycle-time in ms. */
-    .chipEraseTime = 134000U,
+    .chipEraseTime = 460000U,
     /* The max time for the page-program cycle-time in us. */
-    .programTime = 340U
+    .programTime = 1300U
 };
 
-const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Determines the slot number where the memory device is placed. */
     .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
     /* Flags. */
-    .flags = CY_SMIF_FLAG_WR_EN,
+    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
     /* The data-line selection options for a slave device. */
     .dataSelect = CY_SMIF_DATA_SEL0,
     /* The base address the memory slave is mapped to in the PSoC memory map.
@@ -239,16 +239,16 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
     .baseAddress = 0x18000000U,
     /* The size allocated in the PSoC memory map, for the memory slave device.
     The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
-    .memMappedSize = 0x10000U,
+    .memMappedSize = 0x4000000U,
     /* If this memory device is one of the devices in the dual quad SPI configuration.
     Valid when the memory mapped mode is enabled. */
     .dualQuadSlots = 0,
     /* The configuration of the device. */
-    .deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
 };
 
-const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
-   &S25FL512S_SlaveSlot_0
+const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
+   &S25FL512SX4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_block_config_t smifBlockConfig =
@@ -262,3 +262,4 @@ const cy_stc_smif_block_config_t smifBlockConfig =
     /* The version of the SMIF driver. */
     .minorVersion = CY_SMIF_DRV_VERSION_MINOR
 };
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
similarity index 57%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
index 1f4fb5dfcae..32f9b49b2e6 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
@@ -28,22 +28,23 @@
 
 #define CY_SMIF_DEVICE_NUM 1
 
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
 
-extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
 
-extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
-extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
+extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
 
 extern const cy_stc_smif_block_config_t smifBlockConfig;
 
 
 #endif /*CY_SMIF_MEMCONFIG_H*/
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
similarity index 88%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
index 8c2b9d40761..13d936a1348 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
@@ -40,9 +40,7 @@ void init_cycfg_routing(void);
 #define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
 #define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
 #define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
-#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
-#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
+#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
 #define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
 #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
@@ -50,11 +48,11 @@ void init_cycfg_routing(void);
 #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
 #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
similarity index 90%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
index f736a831427..7bdb3db9750 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
@@ -83,6 +83,46 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
 	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
 	.cco_Freq = 355U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 1U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 4U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = 
 {
 	.feedbackDiv = 30,
@@ -523,4 +563,24 @@ void init_cycfg_system(void)
 	
 	/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
 	SystemCoreClockUpdate();
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
similarity index 81%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
index eb91736fba5..75bd41f224f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
@@ -29,6 +29,9 @@
 #include "cy_sysclk.h"
 #include "cy_ble_clk.h"
 #include "cy_systick.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_gpio.h"
 #include "cy_syspm.h"
 
@@ -81,6 +84,22 @@ extern "C" {
 #define CY_CFG_PWR_VDDIO0_MV 3300
 #define CY_CFG_PWR_VDDIO1_MV 3300
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+#endif //defined (CY_USING_HAL)
+
 void init_cycfg_system(void);
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
new file mode 100644
index 00000000000..5557ddecddf
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
@@ -0,0 +1,4 @@
+set SMIF_BANKS {
+  0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+}
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
new file mode 100644
index 00000000000..43d6108110e
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
@@ -0,0 +1,409 @@
+<?xml version="1.0"?>
+<Configuration major="2" minor="0">
+    <!--
+       File Name: cycfg_capsense.cycapsense 
+
+       Description: 
+       CapSense middleware configuration 
+       This file should not be modified. It was automatically generated by 
+       CapSense Configurator 2.0.0 build 351 
+-->
+    <GeneralProperties>
+        <Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="REGULAR_IIR_RC_N" value="128"/>
+        <Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="PROX_IIR_RC_N" value="128"/>
+        <Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="REGULAR_IIR_BL_N" value="1"/>
+        <Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="PROX_IIR_BL_N" value="1"/>
+        <Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="MULTI_FREQ_SCAN_EN" value="false"/>
+        <Property id="SENSOR_AUTO_RESET_EN" value="false"/>
+        <Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
+        <Property id="VREF_SOURCE" value="SRSS"/>
+        <Property id="IREF_SOURCE" value="SRSS"/>
+        <Property id="PROX_TOUCH_COEFF" value="300"/>
+        <Property id="NUM_CENTROIDS" value="1"/>
+    </GeneralProperties>
+    <CsdProperties>
+        <Property id="CSD_AUTOTUNE" value="HWTH"/>
+        <Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
+        <Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
+        <Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
+        <Property id="CSD_IDAC_MIN" value="20"/>
+        <Property id="CSD_IDAC_COMP_EN" value="true"/>
+        <Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
+        <Property id="CSD_VREF_CUSTOM" value="false"/>
+        <Property id="CSD_VREF" value="1219"/>
+        <Property id="CSD_SHIELD_EN" value="false"/>
+        <Property id="CSD_SHIELD_TANK_EN" value="false"/>
+        <Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
+        <Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
+        <Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_FINE_INIT_TIME" value="10"/>
+        <Property id="CSD_CALIBRATION_ERROR" value="10"/>
+        <Property id="CSD_R_CONST" value="1000"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsdProperties>
+    <CsxProperties>
+        <Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSX_MAX_FINGERS" value="3"/>
+        <Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
+        <Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
+        <Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_FINE_INIT_TIME" value="10"/>
+        <Property id="CSX_CALIBRATION_ERROR" value="20"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsxProperties>
+    <Widgets>
+        <Widget id="Button0" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="Button1" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="LinearSlider0" type="LINEAR_SLIDER">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Sns0" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns1" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns2" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns3" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns4" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+    </Widgets>
+</Configuration>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
new file mode 100644
index 00000000000..3c5fbe94fb8
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
+<Configuration app="QSPI" major="2" minor="0">
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <PartNumber>S25FL512S-4byteaddr</PartNumber>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x4000000</Size>
+            <EndAddress>0x1BFFFFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</Configuration>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus
new file mode 100755
index 00000000000..29698a4c275
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus
@@ -0,0 +1,567 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
+    <ToolInfo version="1.0.0"/>
+    <Devices>
+        <Device mpn="CY8C6347BZI-BLD53">
+            <BlockConfig>
+                <Block location="bless[0]" alias="CYBSP_BLE" template="mxs40ble" version="1.1">
+                    <Param id="BleSharing" value="0"/>
+                    <Param id="ExtPaLnaEnable" value="false"/>
+                </Block>
+                <Block location="cpuss[0].dap[0]" alias="" template="mxs40dap" version="1.0">
+                    <Param id="dbgMode" value="SWD"/>
+                    <Param id="traceEnable" value="false"/>
+                </Block>
+                <Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
+                    <Param id="CapSenseEnable" value="true"/>
+                    <Param id="CapSenseCore" value="4"/>
+                    <Param id="SensorCount" value="12"/>
+                    <Param id="CapacitorCount" value="3"/>
+                    <Param id="SensorName0" value="Cmod"/>
+                    <Param id="SensorName1" value="CintA"/>
+                    <Param id="SensorName2" value="CintB"/>
+                    <Param id="SensorName3" value="Button0_Rx0"/>
+                    <Param id="SensorName4" value="Button0_Tx"/>
+                    <Param id="SensorName5" value="Button1_Rx0"/>
+                    <Param id="SensorName6" value="Button1_Tx"/>
+                    <Param id="SensorName7" value="LinearSlider0_Sns0"/>
+                    <Param id="SensorName8" value="LinearSlider0_Sns1"/>
+                    <Param id="SensorName9" value="LinearSlider0_Sns2"/>
+                    <Param id="SensorName10" value="LinearSlider0_Sns3"/>
+                    <Param id="SensorName11" value="LinearSlider0_Sns4"/>
+                    <Param id="CapSenseConfigurator" value="0"/>
+                    <Param id="CapSenseTuner" value="0"/>
+                    <Param id="CsdAdcEnable" value="false"/>
+                    <Param id="numChannels" value="1"/>
+                    <Param id="resolution" value="CY_CSDADC_RESOLUTION_10BIT"/>
+                    <Param id="range" value="CY_CSDADC_RANGE_VDDA"/>
+                    <Param id="acqTime" value="10"/>
+                    <Param id="autoCalibrInterval" value="30"/>
+                    <Param id="vref" value="-1"/>
+                    <Param id="operClkDivider" value="1"/>
+                    <Param id="azTime" value="5"/>
+                    <Param id="csdInitTime" value="25"/>
+                    <Param id="inFlash" value="true"/>
+                    <Param id="CsdIdacEnable" value="false"/>
+                    <Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
+                    <Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
+                    <Param id="csdIdacInitTime" value="25"/>
+                    <Param id="idacInFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[0].pin[0]" alias="CYBSP_WCO_IN" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[0].pin[1]" alias="CYBSP_WCO_OUT" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[3]" alias="CYBSP_QSPI_D3" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[4]" alias="CYBSP_QSPI_D2" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[5]" alias="CYBSP_QSPI_D1" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[6]" alias="CYBSP_QSPI_D0" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[7]" alias="CYBSP_QSPI_SCK" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[1]" alias="CYBSP_EZI2C_SDA" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[4]" alias="CYBSP_SWO" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[6]" alias="CYBSP_SWDIO" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[7]" alias="CYBSP_SWDCK" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[7].pin[1]" alias="CYBSP_CINA" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[7].pin[2]" alias="CYBSP_CINB" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[7].pin[7]" alias="CYBSP_CMOD" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[1]" alias="CYBSP_CSD_BTN0" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[2]" alias="CYBSP_CSD_BTN1" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[3]" alias="CYBSP_CSD_SLD0" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[4]" alias="CYBSP_CSD_SLD1" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[5]" alias="CYBSP_CSD_SLD2" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[6]" alias="CYBSP_CSD_SLD3" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="ioss[0].port[8].pin[7]" alias="CYBSP_CSD_SLD4" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="1"/>
+                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                    <Param id="sioOutputBuffer" value="true"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="peri[0].div_8[0]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="256"/>
+                    <Param id="fracDivider" value="0"/>
+                    <Param id="startOnReset" value="true"/>
+                </Block>
+                <Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="8"/>
+                    <Param id="fracDivider" value="0"/>
+                    <Param id="startOnReset" value="true"/>
+                </Block>
+                <Block location="scb[3]" alias="CYBSP_CSD_COMM" template="mxs40ezi2c" version="1.0">
+                    <Param id="DataRate" value="100"/>
+                    <Param id="NumOfAddr" value="CY_SCB_EZI2C_ONE_ADDRESS"/>
+                    <Param id="SlaveAddress1" value="8"/>
+                    <Param id="SlaveAddress2" value="9"/>
+                    <Param id="SubAddrSize" value="CY_SCB_EZI2C_SUB_ADDR16_BITS"/>
+                    <Param id="EnableWakeup" value="false"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
+                    <Param id="configurator" value="0"/>
+                    <Param id="isrAlignment" value="false"/>
+                    <Param id="isrUnderflow" value="false"/>
+                    <Param id="isrCmdOverflow" value="false"/>
+                    <Param id="isrDataOverflow" value="false"/>
+                    <Param id="rxTriggerLevel" value="0"/>
+                    <Param id="txTriggerLevel" value="0"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="srss[0].clock[0]" alias="" template="mxs40sysclocks" version="1.2"/>
+                <Block location="srss[0].clock[0].altsystickclk[0]" alias="" template="mxs40altsystick" version="1.0">
+                    <Param id="sourceClock" value="lfclk"/>
+                </Block>
+                <Block location="srss[0].clock[0].bakclk[0]" alias="" template="mxs40bakclk" version="1.0">
+                    <Param id="sourceClock" value="wco"/>
+                </Block>
+                <Block location="srss[0].clock[0].fastclk[0]" alias="" template="mxs40fastclk" version="1.0">
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].fll[0]" alias="" template="mxs40fll" version="1.0">
+                    <Param id="configuration" value="auto"/>
+                    <Param id="desiredFrequency" value="100.000"/>
+                </Block>
+                <Block location="srss[0].clock[0].hfclk[0]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="0"/>
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].hfclk[1]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="1"/>
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].hfclk[2]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="0"/>
+                    <Param id="divider" value="2"/>
+                </Block>
+                <Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="1"/>
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].ilo[0]" alias="" template="mxs40ilo" version="1.0">
+                    <Param id="hibernate" value="true"/>
+                </Block>
+                <Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
+                    <Param id="trim" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
+                    <Param id="sourceClock" value="wco"/>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[0]" alias="" template="mxs40pathmux" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[1]" alias="" template="mxs40pathmux" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[2]" alias="" template="mxs40pathmux" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[3]" alias="" template="mxs40pathmux" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[4]" alias="" template="mxs40pathmux" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                </Block>
+                <Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].pll[0]" alias="" template="mxs40pll" version="1.0">
+                    <Param id="lowFrequencyMode" value="false"/>
+                    <Param id="configuration" value="auto"/>
+                    <Param id="desiredFrequency" value="48.000"/>
+                    <Param id="optimization" value="MinPower"/>
+                </Block>
+                <Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].timerclk[0]" alias="" template="mxs40timerclk" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                    <Param id="timerDivider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].wco[0]" alias="" template="mxs40wco" version="1.0">
+                    <Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
+                    <Param id="clockLostDetection" value="false"/>
+                    <Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
+                    <Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
+                    <Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
+                    <Param id="accuracyPpm" value="150"/>
+                </Block>
+                <Block location="srss[0].mcwdt[0]" alias="CYBSP_MCWDT0" template="mxs40mcwdt" version="1.0">
+                    <Param id="C0ClearOnMatch" value="FREE_RUNNING"/>
+                    <Param id="C0Match" value="32768"/>
+                    <Param id="C0Mode" value="CY_MCWDT_MODE_NONE"/>
+                    <Param id="C1ClearOnMatch" value="FREE_RUNNING"/>
+                    <Param id="C1Match" value="32768"/>
+                    <Param id="C1Mode" value="CY_MCWDT_MODE_NONE"/>
+                    <Param id="C2Mode" value="CY_MCWDT_MODE_NONE"/>
+                    <Param id="C2Period" value="16"/>
+                    <Param id="CascadeC0C1" value="true"/>
+                    <Param id="CascadeC1C2" value="false"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
+                    <Param id="pwrEstimator" value="0"/>
+                    <Param id="pwrMode" value="LDO_1_1"/>
+                    <Param id="actPwrMode" value="LP"/>
+                    <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
+                    <Param id="pmicEnable" value="false"/>
+                    <Param id="backupSrc" value="VDDD"/>
+                    <Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
+                    <Param id="deepsleepLatency" value="0"/>
+                    <Param id="vddaMv" value="3300"/>
+                    <Param id="vdddMv" value="3300"/>
+                    <Param id="vBackupMv" value="3300"/>
+                    <Param id="vddNsMv" value="3300"/>
+                    <Param id="vddio0Mv" value="3300"/>
+                    <Param id="vddio1Mv" value="3300"/>
+                </Block>
+                <Block location="srss[0].rtc[0]" alias="CYBSP_RTC" template="mxs40rtc" version="1.1">
+                    <Param id="format" value="0"/>
+                    <Param id="dst" value="false"/>
+                    <Param id="dstFormat" value="CY_RTC_DST_RELATIVE"/>
+                    <Param id="sec" value="0"/>
+                    <Param id="min" value="0"/>
+                    <Param id="hrFormat" value="CY_RTC_24_HOURS"/>
+                    <Param id="hr" value="12"/>
+                    <Param id="amPmPeriodOfDay" value="CY_RTC_AM"/>
+                    <Param id="dayOfTheWeek" value="CY_RTC_SUNDAY"/>
+                    <Param id="dayOfTheMonth" value="1"/>
+                    <Param id="month" value="CY_RTC_JANUARY"/>
+                    <Param id="year" value="0"/>
+                    <Param id="dstStartMonth" value="CY_RTC_MARCH"/>
+                    <Param id="dstStartDay" value="22"/>
+                    <Param id="dstStartWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
+                    <Param id="dstStartDayOfWeek" value="CY_RTC_SUNDAY"/>
+                    <Param id="dstStartHour" value="0"/>
+                    <Param id="dstStopMonth" value="CY_RTC_OCTOBER"/>
+                    <Param id="dstStopDay" value="22"/>
+                    <Param id="dstStopWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
+                    <Param id="dstStopDayOfWeek" value="CY_RTC_SUNDAY"/>
+                    <Param id="dstStopHour" value="0"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+            </BlockConfig>
+            <Netlist>
+                <Net>
+                    <Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
+                    <Port name="ioss[0].port[6].pin[7].digital_in[0]"/>
+                </Net>
+                <Net>
+                    <Port name="cpuss[0].dap[0].swj_swdio_tms[0]"/>
+                    <Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
+                </Net>
+                <Net>
+                    <Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
+                    <Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
+                </Net>
+                <Net>
+                    <Port name="csd[0].csd[0].clock[0]"/>
+                    <Port name="peri[0].div_8[0].clk[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[0].pin[0].analog[0]"/>
+                    <Port name="srss[0].clock[0].wco[0].wco_in[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[0].pin[1].analog[0]"/>
+                    <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
+                    <Port name="scb[3].i2c_scl[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[6].pin[1].digital_inout[0]"/>
+                    <Port name="scb[3].i2c_sda[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[11].pin[2].digital_out[0]"/>
+                    <Port name="smif[0].spi_select0[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[11].pin[3].digital_out[0]"/>
+                    <Port name="smif[0].spi_data3[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[11].pin[4].digital_out[0]"/>
+                    <Port name="smif[0].spi_data2[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[11].pin[5].digital_out[0]"/>
+                    <Port name="smif[0].spi_data1[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[11].pin[6].digital_out[0]"/>
+                    <Port name="smif[0].spi_data0[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
+                    <Port name="smif[0].spi_clk[0]"/>
+                </Net>
+                <Net>
+                    <Port name="peri[0].div_8[1].clk[0]"/>
+                    <Port name="scb[3].clock[0]"/>
+                </Net>
+                <Net>
+                    <Port name="smif[0].clk_hf[0]"/>
+                    <Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
+                </Net>
+                <Net>
+                    <Port name="smif[0].clk_if[0]"/>
+                    <Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
+                </Net>
+                <Mux name="sense" location="csd[0].csd[0]">
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[7].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[1].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[2].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[1].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[2].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[3].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[4].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[5].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[6].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[7].analog[0]"/>
+                    </Arm>
+                </Mux>
+            </Netlist>
+        </Device>
+    </Devices>
+    <Libraries>
+        <Library name="psoc6sw" version="1.2"/>
+    </Libraries>
+    <ConfiguratorData/>
+</Design>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h
deleted file mode 100644
index af4127be860..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h
+++ /dev/null
@@ -1,429 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.h
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PINS_H)
-#define CYCFG_PINS_H
-
-#include "cycfg_notices.h"
-#include "cy_gpio.h"
-#include "cycfg_routing.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_WCO_IN_ENABLED 1U
-#define CYBSP_WCO_IN_PORT GPIO_PRT0
-#define CYBSP_WCO_IN_PIN 0U
-#define CYBSP_WCO_IN_NUM 0U
-#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_0_HSIOM
-	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_WCO_OUT_ENABLED 1U
-#define CYBSP_WCO_OUT_PORT GPIO_PRT0
-#define CYBSP_WCO_OUT_PIN 1U
-#define CYBSP_WCO_OUT_NUM 1U
-#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_1_HSIOM
-	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_LED_RED_ENABLED 1U
-#define CYBSP_LED_RED_PORT GPIO_PRT0
-#define CYBSP_LED_RED_PIN 3U
-#define CYBSP_LED_RED_NUM 3U
-#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_RED_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_3_HSIOM
-	#define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
-#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_BTN2_ENABLED 1U
-#define CYBSP_BTN2_PORT GPIO_PRT0
-#define CYBSP_BTN2_PIN 4U
-#define CYBSP_BTN2_NUM 4U
-#define CYBSP_BTN2_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_BTN2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_4_HSIOM
-	#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BTN2_HSIOM ioss_0_port_0_pin_4_HSIOM
-#define CYBSP_BTN2_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_LED_BLUE_ENABLED 1U
-#define CYBSP_LED_BLUE_PORT GPIO_PRT11
-#define CYBSP_LED_BLUE_PIN 1U
-#define CYBSP_LED_BLUE_NUM 1U
-#define CYBSP_LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_BLUE_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_1_HSIOM
-	#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
-#define CYBSP_LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SS_ENABLED 1U
-#define CYBSP_QSPI_SS_PORT GPIO_PRT11
-#define CYBSP_QSPI_SS_PIN 2U
-#define CYBSP_QSPI_SS_NUM 2U
-#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_2_HSIOM
-	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
-#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D3_ENABLED 1U
-#define CYBSP_QSPI_D3_PORT GPIO_PRT11
-#define CYBSP_QSPI_D3_PIN 3U
-#define CYBSP_QSPI_D3_NUM 3U
-#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_3_HSIOM
-	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
-#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D2_ENABLED 1U
-#define CYBSP_QSPI_D2_PORT GPIO_PRT11
-#define CYBSP_QSPI_D2_PIN 4U
-#define CYBSP_QSPI_D2_NUM 4U
-#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_4_HSIOM
-	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
-#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D1_ENABLED 1U
-#define CYBSP_QSPI_D1_PORT GPIO_PRT11
-#define CYBSP_QSPI_D1_PIN 5U
-#define CYBSP_QSPI_D1_NUM 5U
-#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_5_HSIOM
-	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
-#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D0_ENABLED 1U
-#define CYBSP_QSPI_D0_PORT GPIO_PRT11
-#define CYBSP_QSPI_D0_PIN 6U
-#define CYBSP_QSPI_D0_NUM 6U
-#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_6_HSIOM
-	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
-#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SCK_ENABLED 1U
-#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
-#define CYBSP_QSPI_SCK_PIN 7U
-#define CYBSP_QSPI_SCK_NUM 7U
-#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_7_HSIOM
-	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
-#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_LED9_ENABLED 1U
-#define CYBSP_LED9_PORT GPIO_PRT13
-#define CYBSP_LED9_PIN 7U
-#define CYBSP_LED9_NUM 7U
-#define CYBSP_LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED9_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_13_pin_7_HSIOM
-	#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
-#define CYBSP_LED9_IRQ ioss_interrupts_gpio_13_IRQn
-#define CYBSP_CSD_TX_ENABLED 1U
-#define CYBSP_CSD_TX_PORT GPIO_PRT1
-#define CYBSP_CSD_TX_PIN 0U
-#define CYBSP_CSD_TX_NUM 0U
-#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_0_HSIOM
-	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_LED_GREEN_ENABLED 1U
-#define CYBSP_LED_GREEN_PORT GPIO_PRT1
-#define CYBSP_LED_GREEN_PIN 1U
-#define CYBSP_LED_GREEN_NUM 1U
-#define CYBSP_LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_GREEN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_1_HSIOM
-	#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
-#define CYBSP_LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_LED8_ENABLED 1U
-#define CYBSP_LED8_PORT GPIO_PRT1
-#define CYBSP_LED8_PIN 5U
-#define CYBSP_LED8_NUM 5U
-#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED8_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_5_HSIOM
-	#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
-#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_DEBUG_UART_RX_ENABLED 1U
-#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_RX_PIN 0U
-#define CYBSP_DEBUG_UART_RX_NUM 0U
-#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_0_HSIOM
-	#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
-#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_DEBUG_UART_TX_ENABLED 1U
-#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_TX_PIN 1U
-#define CYBSP_DEBUG_UART_TX_NUM 1U
-#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_1_HSIOM
-	#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
-#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_EZI2C_SCL_ENABLED 1U
-#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SCL_PIN 0U
-#define CYBSP_EZI2C_SCL_NUM 0U
-#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_0_HSIOM
-	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
-#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_EZI2C_SDA_ENABLED 1U
-#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SDA_PIN 1U
-#define CYBSP_EZI2C_SDA_NUM 1U
-#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_1_HSIOM
-	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
-#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWO_ENABLED 1U
-#define CYBSP_SWO_PORT GPIO_PRT6
-#define CYBSP_SWO_PIN 4U
-#define CYBSP_SWO_NUM 4U
-#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_SWO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_4_HSIOM
-	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDIO_ENABLED 1U
-#define CYBSP_SWDIO_PORT GPIO_PRT6
-#define CYBSP_SWDIO_PIN 6U
-#define CYBSP_SWDIO_NUM 6U
-#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SWDIO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_6_HSIOM
-	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDCK_ENABLED 1U
-#define CYBSP_SWDCK_PORT GPIO_PRT6
-#define CYBSP_SWDCK_PIN 7U
-#define CYBSP_SWDCK_NUM 7U
-#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define CYBSP_SWDCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_7_HSIOM
-	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_CINA_ENABLED 1U
-#define CYBSP_CINA_PORT GPIO_PRT7
-#define CYBSP_CINA_PIN 1U
-#define CYBSP_CINA_NUM 1U
-#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_1_HSIOM
-	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
-#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CINB_ENABLED 1U
-#define CYBSP_CINB_PORT GPIO_PRT7
-#define CYBSP_CINB_PIN 2U
-#define CYBSP_CINB_NUM 2U
-#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINB_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_2_HSIOM
-	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
-#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CMOD_ENABLED 1U
-#define CYBSP_CMOD_PORT GPIO_PRT7
-#define CYBSP_CMOD_PIN 7U
-#define CYBSP_CMOD_NUM 7U
-#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CMOD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_7_HSIOM
-	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
-#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CSD_BTN0_ENABLED 1U
-#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN0_PIN 1U
-#define CYBSP_CSD_BTN0_NUM 1U
-#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_1_HSIOM
-	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_BTN1_ENABLED 1U
-#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN1_PIN 2U
-#define CYBSP_CSD_BTN1_NUM 2U
-#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_2_HSIOM
-	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
-#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD0_ENABLED 1U
-#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD0_PIN 3U
-#define CYBSP_CSD_SLD0_NUM 3U
-#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_3_HSIOM
-	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD1_ENABLED 1U
-#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD1_PIN 4U
-#define CYBSP_CSD_SLD1_NUM 4U
-#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_4_HSIOM
-	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
-#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD2_ENABLED 1U
-#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD2_PIN 5U
-#define CYBSP_CSD_SLD2_NUM 5U
-#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_5_HSIOM
-	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
-#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD3_ENABLED 1U
-#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD3_PIN 6U
-#define CYBSP_CSD_SLD3_NUM 6U
-#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_6_HSIOM
-	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
-#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD4_ENABLED 1U
-#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD4_PIN 7U
-#define CYBSP_CSD_SLD4_NUM 7U
-#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_7_HSIOM
-	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
-#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
-
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BTN2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED9_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
-
-void init_cycfg_pins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PINS_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/qspi_config.cfg
deleted file mode 100644
index a561643dcf1..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/qspi_config.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-set SMIF_BANKS {
-}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PeripheralPins.c
index 85d61a4553f..01abc764dc2 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PeripheralPins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PeripheralPins.c
@@ -91,7 +91,9 @@ const PinMap PinMap_I2C_SCL[] = {
     {P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
     {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
     {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
+    {P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
     {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
+    {P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
     {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
     {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
     {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
@@ -106,7 +108,9 @@ const PinMap PinMap_I2C_SDA[] = {
     {P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
     {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
     {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
+    {P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
     {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
+    {P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
     {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
     {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
     {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
@@ -125,7 +129,9 @@ const PinMap PinMap_SPI_MOSI[] = {
     {P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
     {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
     {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
+    {P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
     {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
+    {P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
     {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
     {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
     {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
@@ -140,7 +146,9 @@ const PinMap PinMap_SPI_MISO[] = {
     {P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
     {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
     {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
+    {P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
     {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
+    {P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
     {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
     {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
     {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
@@ -155,9 +163,10 @@ const PinMap PinMap_SPI_SCLK[] = {
     {P1_2, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)},
     {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
     {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
+    {P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
     {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
+    {P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
     {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
-
     {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
     {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
     {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
@@ -170,7 +179,9 @@ const PinMap PinMap_SPI_SSEL[] = {
     {P1_3, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
     {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
     {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
+    {P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
     {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
+    {P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
     {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
     {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
     {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
@@ -360,7 +371,6 @@ const PinMap PinMap_ADC[] = {
 #if DEVICE_ANALOGOUT
 const PinMap PinMap_DAC[] = {
     {P9_6,  DAC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
-    {P10_5, DAC_0, CY_GPIO_CFG_CREATE(HSIOM_SEL_AMUXA, CY_GPIO_DM_ANALOG)},  // CTDAC connects to the P10_5 pin through the AMUXA bus
     {NC,    NC,     0}
 };
 #endif // DEVICE_ANALOGIN
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PinNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PinNames.h
index ef0b9b3e496..cf2f3e25deb 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PinNames.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PinNames.h
@@ -20,38 +20,8 @@
 #ifndef MBED_PINNAMES_H
 #define MBED_PINNAMES_H
 
-#include "cmsis.h"
 #include "PinNamesTypes.h"
-#include "PortNames.h"
 #include "cyhal_pin_package.h"
-#include "cyhal_utils.h"
-
-typedef cyhal_gpio_t PinName;
-
-// Arduino connector namings
-#define A0 P10_0
-#define A1 P10_1
-#define A2 P10_2
-#define A3 P10_3
-#define A4 P10_4
-#define A5 P10_5
-
-#define D0 P5_0
-#define D1 P5_1
-#define D2 P5_2
-#define D3 P5_3
-#define D4 P5_4
-#define D5 P5_5
-#define D6 P5_6
-#define D7 P0_2
-#define D8 P13_0
-#define D9 P13_1
-#define D10 P12_3
-#define D11 P12_0
-#define D12 P12_1
-#define D13 P12_2
-#define D14 P6_1
-#define D15 P6_0
 
 // Generic signal names
 
@@ -68,17 +38,16 @@ typedef cyhal_gpio_t PinName;
 #define UART_RTS P5_2
 #define UART_CTS P5_3
 
-#define SWITCH2 P0_4
 #define LED1 P0_3
 #define LED2 P1_1
 #define LED3 P11_1
 #define LED4 P1_5
 #define LED5 P13_7
-
 #define LED_RED LED1
 #define LED_BLUE LED3
 #define LED_GREEN LED2
 
+#define SWITCH2 P0_4
 #define USER_BUTTON SWITCH2
 #define BUTTON1 USER_BUTTON
 
@@ -102,11 +71,6 @@ typedef cyhal_gpio_t PinName;
 #define STDIO_UART_CTS UART_CTS
 #define STDIO_UART_RTS UART_RTS
 
-#define CY_STDIO_UART_RX STDIO_UART_RX
-#define CY_STDIO_UART_TX STDIO_UART_TX
-#define CY_STDIO_UART_CTS STDIO_UART_CTS
-#define CY_STDIO_UART_RTS STDIO_UART_RTS
-
 #define USBTX UART_TX
 #define USBRX UART_RX
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h
old mode 100644
new mode 100755
index 6669595f2b8..bbf71f770f9
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h
@@ -23,27 +23,65 @@
 * limitations under the License.
 *******************************************************************************/
 
-/**
-* \addtogroup group_bsp_cy8ckit_062_ble CY8CKIT-062-BLE
-* \ingroup group_bsp
-* \{
-* \defgroup group_bsp_cy8ckit_062_ble_macros Macros
-* \defgroup group_bsp_cy8ckit_062_ble_enums Enumerated Types
-*/
-
 #pragma once
 
-#include "cyhal.h"
+#include "cyhal_pin_package.h"
 
 #if defined(__cplusplus)
 extern "C" {
 #endif
 
 /**
-* \addtogroup group_bsp_cy8ckit_062_ble_macros
+* \addtogroup group_bsp_pins Pin Mappings
 * \{
 */
 
+// Arduino connector namings
+/** Arduino A0 */
+#define CYBSP_A0 P10_0
+/** Arduino A1 */
+#define CYBSP_A1 P10_1
+/** Arduino A2 */
+#define CYBSP_A2 P10_2
+/** Arduino A3 */
+#define CYBSP_A3 P10_3
+/** Arduino A4 */
+#define CYBSP_A4 P10_4
+/** Arduino A5 */
+#define CYBSP_A5 P10_5
+/** Arduino D0 */
+#define CYBSP_D0 P5_0
+/** Arduino D1 */
+#define CYBSP_D1 P5_1
+/** Arduino D2 */
+#define CYBSP_D2 P5_2
+/** Arduino D3 */
+#define CYBSP_D3 P5_3
+/** Arduino D4 */
+#define CYBSP_D4 P5_4
+/** Arduino D5 */
+#define CYBSP_D5 P5_5
+/** Arduino D6 */
+#define CYBSP_D6 P5_6
+/** Arduino D7 */
+#define CYBSP_D7 P0_2
+/** Arduino D8 */
+#define CYBSP_D8 P13_0
+/** Arduino D9 */
+#define CYBSP_D9 P13_1
+/** Arduino D10 */
+#define CYBSP_D10 P12_3
+/** Arduino D11 */
+#define CYBSP_D11 P12_0
+/** Arduino D12 */
+#define CYBSP_D12 P12_1
+/** Arduino D13 */
+#define CYBSP_D13 P12_2
+/** Arduino D14 */
+#define CYBSP_D14 P6_1
+/** Arduino D15 */
+#define CYBSP_D15 P6_0
+
 // Generic signal names
 /** Pin: WCO input */
 #define CYBSP_WCO_IN           P0_0
@@ -51,8 +89,10 @@ extern "C" {
 #define CYBSP_WCO_OUT          P0_1
 
 /** Pin: UART RX */
+/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
 #define CYBSP_DEBUG_UART_RX    P5_0
 /** Pin: UART TX */
+/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
 #define CYBSP_DEBUG_UART_TX    P5_1
 
 /** Pin: I2C SCL */
@@ -103,25 +143,25 @@ extern "C" {
 /** Pin: QUAD SPI SCK */
 #define CYBSP_QSPI_SCK         P11_7
 
-/** \} group_bsp_cy8ckit_062_ble_macros */
+/** \} group_bsp_pins */
 
 /**
-* \addtogroup group_bsp_cy8ckit_062_ble_enums
+* \addtogroup group_bsp_enums Enumerated Types
 * \{
 */
 
 /** Enum defining the different states for the LED. */
 typedef enum
 {
-	CYBSP_LED_STATE_ON        	= 0,
-	CYBSP_LED_STATE_OFF        	= 1,
+    CYBSP_LED_STATE_ON          = 0,
+    CYBSP_LED_STATE_OFF         = 1,
 } cybsp_led_state_t;
 
 /** Enum defining the different states for a button. */
 typedef enum
 {
-	CYBSP_BTN_PRESSED  	      	= 0,
-	CYBSP_BTN_OFF	          	= 1,
+    CYBSP_BTN_PRESSED           = 0,
+    CYBSP_BTN_OFF               = 1,
 } cybsp_btn_state_t;
 
 /** Enum defining the different LED pins on the board. */
@@ -133,10 +173,15 @@ typedef enum
     CYBSP_LED_RGB_GREEN = P1_1,
     CYBSP_LED_RGB_BLUE = P11_1,
 
+    /* Corresponds to: ioss[0].port[1].pin[5] */
     CYBSP_USER_LED1 = CYBSP_LED8,
+    /* Corresponds to: ioss[0].port[13].pin[7] */
     CYBSP_USER_LED2 = CYBSP_LED9,
+    /* Corresponds to: ioss[0].port[0].pin[3] */
     CYBSP_USER_LED3 = CYBSP_LED_RGB_RED,
+    /* Corresponds to: ioss[0].port[1].pin[1] */
     CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN,
+    /* Corresponds to: ioss[0].port[11].pin[1] */
     CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE,
     CYBSP_USER_LED = CYBSP_USER_LED1,
 } cybsp_led_t;
@@ -146,14 +191,13 @@ typedef enum
 {
     CYBSP_SW2 = P0_4,
 
+    /* Corresponds to: ioss[0].port[0].pin[4] */
     CYBSP_USER_BTN1 = CYBSP_SW2,
     CYBSP_USER_BTN = CYBSP_USER_BTN1,
 } cybsp_btn_t;
 
-/** \} group_bsp_cy8ckit_062_ble_enums */
+/** \} group_bsp_enums */
 
 #if defined(__cplusplus)
 }
 #endif
-
-/** \} group_bsp_cy8ckit_062_ble */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
index a23e6e13f61..a0ab034d41c 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
@@ -3,7 +3,7 @@
 ; to pass a scatter file through a C preprocessor.
 
 ;*******************************************************************************
-;* \file cy8c6xx7_cm4_dual.scat
+;* \file cy8c6xx7_cm4_dual.sct
 ;* \version 2.50
 ;*
 ;* Linker file for the ARMCC.
@@ -173,7 +173,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
     RW_RAM_DATA +0
     {
         * (.cy_ramfunc)
-        .ANY (+RW, +ZI)
+        * (+RW, +ZI)
     }
 
     ; Place variables in the section that should not be initialized during the
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
similarity index 98%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
index cb430a41643..cda6d4025b1 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
@@ -28,6 +28,7 @@ void init_cycfg_all(void)
 {
 	init_cycfg_system();
 	init_cycfg_clocks();
+	init_cycfg_dmas();
 	init_cycfg_routing();
 	init_cycfg_peripherals();
 	init_cycfg_pins();
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
new file mode 100644
index 00000000000..6911b5befd4
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
@@ -0,0 +1,24 @@
+/*******************************************************************************
+* File Name: cycfg.timestamp
+*
+* Description:
+* Sentinel file for determining if generated source is up to date.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
new file mode 100644
index 00000000000..151484a1da7
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
@@ -0,0 +1,105 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.c
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_clocks.h"
+
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_USB_CLK_DIV_HW,
+		.channel_num = CYBSP_USB_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_SDIO_DIV_HW,
+		.channel_num = CYBSP_SDIO_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t peri_0_div_8_4_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = peri_0_div_8_4_HW,
+		.channel_num = peri_0_div_8_4_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_clocks(void)
+{
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SDIO_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&peri_0_div_8_4_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
similarity index 69%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
index c2703466b25..516b0c3730d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
@@ -27,6 +27,9 @@
 
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 
 #if defined(__cplusplus)
 extern "C" {
@@ -41,12 +44,28 @@ extern "C" {
 #define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
-#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
 #define CYBSP_CSD_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_CLK_DIV_NUM 3U
+#define peri_0_div_8_4_ENABLED 1U
+#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT
+#define peri_0_div_8_4_NUM 4U
+
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t peri_0_div_8_4_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_clocks(void);
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
similarity index 78%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
index a8e9de3e069..8d869195513 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
@@ -62,6 +62,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig =
 	.enable = false,
 	.bufferable = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj = 
+	{
+		.type = CYHAL_RSC_DMA,
+		.block_num = 0U,
+		.channel_num = cpuss_0_dw0_0_chan_0_CHANNEL,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config = 
 {
 	.retrigger = CY_DMA_RETRIG_16CYC,
@@ -100,6 +108,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig =
 	.enable = false,
 	.bufferable = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj = 
+	{
+		.type = CYHAL_RSC_DMA,
+		.block_num = 0U,
+		.channel_num = cpuss_0_dw0_0_chan_1_CHANNEL,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config = 
 {
 	.retrigger = CY_DMA_RETRIG_4CYC,
@@ -138,6 +154,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig =
 	.enable = false,
 	.bufferable = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj = 
+	{
+		.type = CYHAL_RSC_DMA,
+		.block_num = 1U,
+		.channel_num = cpuss_0_dw1_0_chan_1_CHANNEL,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config = 
 {
 	.retrigger = CY_DMA_RETRIG_IM,
@@ -176,4 +200,31 @@ const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig =
 	.enable = false,
 	.bufferable = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj = 
+	{
+		.type = CYHAL_RSC_DMA,
+		.block_num = 1U,
+		.channel_num = cpuss_0_dw1_0_chan_3_CHANNEL,
+	};
+#endif //defined (CY_USING_HAL)
 
+
+void init_cycfg_dmas(void)
+{
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
similarity index 78%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
index 69a805e9598..d6c0d6587db 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
@@ -27,6 +27,9 @@
 
 #include "cycfg_notices.h"
 #include "cy_dma.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 
 #if defined(__cplusplus)
 extern "C" {
@@ -34,34 +37,47 @@ extern "C" {
 
 #define cpuss_0_dw0_0_chan_0_ENABLED 1U
 #define cpuss_0_dw0_0_chan_0_HW DW0
-#define cpuss_0_dw0_0_chan_0_CHANNEL 0
+#define cpuss_0_dw0_0_chan_0_CHANNEL 0U
 #define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
 #define cpuss_0_dw0_0_chan_1_ENABLED 1U
 #define cpuss_0_dw0_0_chan_1_HW DW0
-#define cpuss_0_dw0_0_chan_1_CHANNEL 1
+#define cpuss_0_dw0_0_chan_1_CHANNEL 1U
 #define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
 #define cpuss_0_dw1_0_chan_1_ENABLED 1U
 #define cpuss_0_dw1_0_chan_1_HW DW1
-#define cpuss_0_dw1_0_chan_1_CHANNEL 1
+#define cpuss_0_dw1_0_chan_1_CHANNEL 1U
 #define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
 #define cpuss_0_dw1_0_chan_3_ENABLED 1U
 #define cpuss_0_dw1_0_chan_3_HW DW1
-#define cpuss_0_dw1_0_chan_3_CHANNEL 3
+#define cpuss_0_dw1_0_chan_3_CHANNEL 3U
 #define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
 
 extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config;
 extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0;
 extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config;
 extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0;
 extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config;
 extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0;
 extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config;
 extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0;
 extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj;
+#endif //defined (CY_USING_HAL)
 
+void init_cycfg_dmas(void);
 
 #if defined(__cplusplus)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_notices.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
similarity index 72%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
index 73f7af2d873..9aeb651afb5 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
@@ -70,6 +70,14 @@ const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
 	.txFifoTriggerLevel = 63UL,
 	.txFifoIntEnableMask = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = 
 {
 	.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
@@ -78,34 +86,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
 	.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
 	.enableWakeFromSleep = false,
 };
-const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = 
-{
-	.uartMode = CY_SCB_UART_STANDARD,
-	.enableMutliProcessorMode = false,
-	.smartCardRetryOnNack = false,
-	.irdaInvertRx = false,
-	.irdaEnableLowPowerReceiver = false,
-	.oversample = 8,
-	.enableMsbFirst = false,
-	.dataWidth = 8UL,
-	.parity = CY_SCB_UART_PARITY_NONE,
-	.stopBits = CY_SCB_UART_STOP_BITS_1,
-	.enableInputFilter = false,
-	.breakWidth = 11UL,
-	.dropOnFrameError = false,
-	.dropOnParityError = false,
-	.receiverAddress = 0x0UL,
-	.receiverAddressMask = 0x0UL,
-	.acceptAddrInFifo = false,
-	.enableCts = false,
-	.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rtsRxFifoLevel = 0UL,
-	.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rxFifoTriggerLevel = 63UL,
-	.rxFifoIntEnableMask = 0UL,
-	.txFifoTriggerLevel = 63UL,
-	.txFifoIntEnableMask = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_smif_config_t CYBSP_QSPI_config = 
 {
 	.mode = (uint32_t)CY_SMIF_NORMAL,
@@ -113,6 +101,14 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
 	.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
 	.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_obj = 
+	{
+		.type = CYHAL_RSC_SMIF,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config = 
 {
 	.c0Match = 32768U,
@@ -126,6 +122,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
 	.c0c1Cascade = true,
 	.c1c2Cascade = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_MCWDT0_obj = 
+	{
+		.type = CYHAL_RSC_LPTIMER,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_rtc_config_t CYBSP_RTC_config = 
 {
 	.sec = 0U,
@@ -138,6 +142,14 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
 	.month = CY_RTC_JANUARY,
 	.year = 0U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_RTC_obj = 
+	{
+		.type = CYHAL_RSC_RTC,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = 
 {
 	.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
@@ -155,19 +167,44 @@ const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
 	.enableLpm = false,
 	.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USBUART_obj = 
+	{
+		.type = CYHAL_RSC_USB,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_peripherals(void)
 {
 	Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
+	Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
similarity index 85%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
index 8f732170440..106b3ad7a05 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
@@ -29,8 +29,12 @@
 #include "cy_sysclk.h"
 #include "cy_csd.h"
 #include "cy_scb_uart.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_scb_ezi2c.h"
 #include "cy_smif.h"
+#include "cycfg_qspi_memslot.h"
 #include "cy_mcwdt.h"
 #include "cy_rtc.h"
 #include "cy_usbfs_dev_drv.h"
@@ -81,9 +85,6 @@ extern "C" {
 #define CYBSP_CSD_COMM_ENABLED 1U
 #define CYBSP_CSD_COMM_HW SCB3
 #define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
-#define CYBSP_DEBUG_UART_ENABLED 1U
-#define CYBSP_DEBUG_UART_HW SCB5
-#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
 #define CYBSP_QSPI_ENABLED 1U
 #define CYBSP_QSPI_HW SMIF0
 #define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@@ -113,7 +114,6 @@ extern "C" {
 #define CYBSP_RTC_100_YEAR_OFFSET (8U)
 #define CYBSP_RTC_10_YEAR_OFFSET (4U)
 #define CYBSP_RTC_YEAR_OFFSET (0U)
-#define CYBSP_SDIO_ENABLED 1U
 #define CYBSP_USBUART_ENABLED 1U
 #define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
 #define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
@@ -126,12 +126,29 @@ extern "C" {
 
 extern cy_stc_csd_context_t cy_csd_0_context;
 extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
-extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_rtc_config_t CYBSP_RTC_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_RTC_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_peripherals(void);
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
similarity index 58%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
index 69bf22b3b4d..ca1cca68968 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
@@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_IN_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_IN_PORT_NUM,
+		.channel_num = CYBSP_WCO_IN_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = 
 {
 	.outVal = 1,
@@ -56,54 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_RED_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_BTN2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_PULLUP,
-	.hsiom = CYBSP_BTN2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_BLUE_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_OUT_PORT_NUM,
+		.channel_num = CYBSP_WCO_OUT_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = 
 {
 	.outVal = 1,
@@ -120,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SS_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = 
 {
 	.outVal = 1,
@@ -136,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D3_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = 
 {
 	.outVal = 1,
@@ -152,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D2_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = 
 {
 	.outVal = 1,
@@ -168,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D1_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = 
 {
 	.outVal = 1,
@@ -184,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D0_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = 
 {
 	.outVal = 1,
@@ -200,22 +208,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED9_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED9_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SCK_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config = 
 {
 	.outVal = 1,
@@ -232,6 +232,14 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t ioss_0_port_14_pin_0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = ioss_0_port_14_pin_0_PORT_NUM,
+		.channel_num = ioss_0_port_14_pin_0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config = 
 {
 	.outVal = 1,
@@ -248,6 +256,14 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t ioss_0_port_14_pin_1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = ioss_0_port_14_pin_1_PORT_NUM,
+		.channel_num = ioss_0_port_14_pin_1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = 
 {
 	.outVal = 1,
@@ -264,150 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_GREEN_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_LED8_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED8_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_D0_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_D1_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_D2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_D3_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_CMD_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_WIFI_SDIO_CLK_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config = 
-{
-	.outVal = 0,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_WIFI_WL_REG_ON_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_TX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_TX_PORT_NUM,
+		.channel_num = CYBSP_CSD_TX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config = 
 {
 	.outVal = 0,
@@ -424,6 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM,
+		.channel_num = CYBSP_WIFI_HOST_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = 
 {
 	.outVal = 1,
@@ -440,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_RX_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_RX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = 
 {
 	.outVal = 1,
@@ -456,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_TX_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_TX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = 
 {
 	.outVal = 1,
@@ -472,6 +376,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_RTS_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_RTS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = 
 {
 	.outVal = 1,
@@ -488,6 +400,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_CTS_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_CTS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config = 
 {
 	.outVal = 1,
@@ -504,6 +424,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_POWER_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_POWER_PORT_NUM,
+		.channel_num = CYBSP_BT_POWER_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = 
 {
 	.outVal = 0,
@@ -520,6 +448,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
+		.channel_num = CYBSP_BT_HOST_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config = 
 {
 	.outVal = 0,
@@ -536,38 +472,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_HIGHZ,
-	.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM,
+		.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = 
 {
 	.outVal = 1,
@@ -584,6 +496,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SCL_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = 
 {
 	.outVal = 1,
@@ -600,6 +520,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SDA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWO_config = 
 {
 	.outVal = 1,
@@ -616,6 +544,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWO_PORT_NUM,
+		.channel_num = CYBSP_SWO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = 
 {
 	.outVal = 1,
@@ -632,6 +568,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDIO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDIO_PORT_NUM,
+		.channel_num = CYBSP_SWDIO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = 
 {
 	.outVal = 1,
@@ -648,6 +592,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDCK_PORT_NUM,
+		.channel_num = CYBSP_SWDCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINA_config = 
 {
 	.outVal = 1,
@@ -664,6 +616,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINA_PORT_NUM,
+		.channel_num = CYBSP_CINA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINB_config = 
 {
 	.outVal = 1,
@@ -680,6 +640,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINB_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINB_PORT_NUM,
+		.channel_num = CYBSP_CINB_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = 
 {
 	.outVal = 1,
@@ -696,6 +664,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CMOD_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CMOD_PORT_NUM,
+		.channel_num = CYBSP_CMOD_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = 
 {
 	.outVal = 1,
@@ -712,6 +688,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN0_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = 
 {
 	.outVal = 1,
@@ -728,6 +712,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN1_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = 
 {
 	.outVal = 1,
@@ -744,6 +736,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD0_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = 
 {
 	.outVal = 1,
@@ -760,6 +760,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD1_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = 
 {
 	.outVal = 1,
@@ -776,6 +784,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD2_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = 
 {
 	.outVal = 1,
@@ -792,6 +808,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD3_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = 
 {
 	.outVal = 1,
@@ -808,94 +832,174 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD4_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD4_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_pins(void)
 {
 	Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_BTN2_PORT, CYBSP_BTN2_PIN, &CYBSP_BTN2_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_BLUE_PORT, CYBSP_LED_BLUE_PIN, &CYBSP_LED_BLUE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED9_PORT, CYBSP_LED9_PIN, &CYBSP_LED9_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(ioss_0_port_14_pin_0_PORT, ioss_0_port_14_pin_0_PIN, &ioss_0_port_14_pin_0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&ioss_0_port_14_pin_0_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(ioss_0_port_14_pin_1_PORT, ioss_0_port_14_pin_1_PIN, &ioss_0_port_14_pin_1_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&ioss_0_port_14_pin_1_obj);
+#endif //defined (CY_USING_HAL)
 
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_GREEN_PORT, CYBSP_LED_GREEN_PIN, &CYBSP_LED_GREEN_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED8_PORT, CYBSP_LED8_PIN, &CYBSP_LED8_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D0_PORT, CYBSP_WIFI_SDIO_D0_PIN, &CYBSP_WIFI_SDIO_D0_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D1_PORT, CYBSP_WIFI_SDIO_D1_PIN, &CYBSP_WIFI_SDIO_D1_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D2_PORT, CYBSP_WIFI_SDIO_D2_PIN, &CYBSP_WIFI_SDIO_D2_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D3_PORT, CYBSP_WIFI_SDIO_D3_PIN, &CYBSP_WIFI_SDIO_D3_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CMD_PORT, CYBSP_WIFI_SDIO_CMD_PIN, &CYBSP_WIFI_SDIO_CMD_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CLK_PORT, CYBSP_WIFI_SDIO_CLK_PIN, &CYBSP_WIFI_SDIO_CLK_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_WL_REG_ON_PORT, CYBSP_WIFI_WL_REG_ON_PIN, &CYBSP_WIFI_WL_REG_ON_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
new file mode 100644
index 00000000000..9bf6916e7ba
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
@@ -0,0 +1,998 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cycfg_notices.h"
+#include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cycfg_routing.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PORT_NUM 0U
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_0_HSIOM
+	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PORT_NUM 0U
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_1_HSIOM
+	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SS_ENABLED 1U
+#define CYBSP_QSPI_SS_PORT GPIO_PRT11
+#define CYBSP_QSPI_SS_PORT_NUM 11U
+#define CYBSP_QSPI_SS_PIN 2U
+#define CYBSP_QSPI_SS_NUM 2U
+#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_2_HSIOM
+	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
+#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D3_ENABLED 1U
+#define CYBSP_QSPI_D3_PORT GPIO_PRT11
+#define CYBSP_QSPI_D3_PORT_NUM 11U
+#define CYBSP_QSPI_D3_PIN 3U
+#define CYBSP_QSPI_D3_NUM 3U
+#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_3_HSIOM
+	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
+#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D2_ENABLED 1U
+#define CYBSP_QSPI_D2_PORT GPIO_PRT11
+#define CYBSP_QSPI_D2_PORT_NUM 11U
+#define CYBSP_QSPI_D2_PIN 4U
+#define CYBSP_QSPI_D2_NUM 4U
+#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_4_HSIOM
+	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
+#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D1_ENABLED 1U
+#define CYBSP_QSPI_D1_PORT GPIO_PRT11
+#define CYBSP_QSPI_D1_PORT_NUM 11U
+#define CYBSP_QSPI_D1_PIN 5U
+#define CYBSP_QSPI_D1_NUM 5U
+#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_5_HSIOM
+	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
+#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D0_ENABLED 1U
+#define CYBSP_QSPI_D0_PORT GPIO_PRT11
+#define CYBSP_QSPI_D0_PORT_NUM 11U
+#define CYBSP_QSPI_D0_PIN 6U
+#define CYBSP_QSPI_D0_NUM 6U
+#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_6_HSIOM
+	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
+#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SCK_ENABLED 1U
+#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
+#define CYBSP_QSPI_SCK_PORT_NUM 11U
+#define CYBSP_QSPI_SCK_PIN 7U
+#define CYBSP_QSPI_SCK_NUM 7U
+#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_7_HSIOM
+	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define ioss_0_port_14_pin_0_ENABLED 1U
+#define ioss_0_port_14_pin_0_PORT GPIO_PRT14
+#define ioss_0_port_14_pin_0_PORT_NUM 14U
+#define ioss_0_port_14_pin_0_PIN 0U
+#define ioss_0_port_14_pin_0_NUM 0U
+#define ioss_0_port_14_pin_0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define ioss_0_port_14_pin_0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_14_pin_0_HSIOM
+	#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_0_HAL_PORT_PIN P14_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define ioss_0_port_14_pin_1_ENABLED 1U
+#define ioss_0_port_14_pin_1_PORT GPIO_PRT14
+#define ioss_0_port_14_pin_1_PORT_NUM 14U
+#define ioss_0_port_14_pin_1_PIN 1U
+#define ioss_0_port_14_pin_1_NUM 1U
+#define ioss_0_port_14_pin_1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define ioss_0_port_14_pin_1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_14_pin_1_HSIOM
+	#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_1_HAL_PORT_PIN P14_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define ioss_0_port_14_pin_1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_TX_ENABLED 1U
+#define CYBSP_CSD_TX_PORT GPIO_PRT1
+#define CYBSP_CSD_TX_PORT_NUM 1U
+#define CYBSP_CSD_TX_PIN 0U
+#define CYBSP_CSD_TX_NUM 0U
+#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_0_HSIOM
+	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_PORT_PIN P1_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
+#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2
+#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 2U
+#define CYBSP_WIFI_HOST_WAKE_PIN 7U
+#define CYBSP_WIFI_HOST_WAKE_NUM 7U
+#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_2_pin_7_HSIOM
+	#define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM
+#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P2_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_RX_ENABLED 1U
+#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RX_PORT_NUM 3U
+#define CYBSP_BT_UART_RX_PIN 0U
+#define CYBSP_BT_UART_RX_NUM 0U
+#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_0_HSIOM
+	#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
+#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_TX_ENABLED 1U
+#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_TX_PORT_NUM 3U
+#define CYBSP_BT_UART_TX_PIN 1U
+#define CYBSP_BT_UART_TX_NUM 1U
+#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_1_HSIOM
+	#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
+#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_RTS_ENABLED 1U
+#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RTS_PORT_NUM 3U
+#define CYBSP_BT_UART_RTS_PIN 2U
+#define CYBSP_BT_UART_RTS_NUM 2U
+#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_2_HSIOM
+	#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
+#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_CTS_ENABLED 1U
+#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_CTS_PORT_NUM 3U
+#define CYBSP_BT_UART_CTS_PIN 3U
+#define CYBSP_BT_UART_CTS_NUM 3U
+#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_3_HSIOM
+	#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
+#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_POWER_ENABLED 1U
+#define CYBSP_BT_POWER_PORT GPIO_PRT3
+#define CYBSP_BT_POWER_PORT_NUM 3U
+#define CYBSP_BT_POWER_PIN 4U
+#define CYBSP_BT_POWER_NUM 4U
+#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
+#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_4_HSIOM
+	#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
+#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_PORT_PIN P3_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_HOST_WAKE_ENABLED 1U
+#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
+#define CYBSP_BT_HOST_WAKE_PORT_NUM 3U
+#define CYBSP_BT_HOST_WAKE_PIN 5U
+#define CYBSP_BT_HOST_WAKE_NUM 5U
+#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_3_pin_5_HSIOM
+	#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
+#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P3_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
+#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
+#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 4U
+#define CYBSP_BT_DEVICE_WAKE_PIN 0U
+#define CYBSP_BT_DEVICE_WAKE_NUM 0U
+#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_4_pin_0_HSIOM
+	#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
+#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P4_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SCL_ENABLED 1U
+#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SCL_PORT_NUM 6U
+#define CYBSP_EZI2C_SCL_PIN 0U
+#define CYBSP_EZI2C_SCL_NUM 0U
+#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_0_HSIOM
+	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
+#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SDA_ENABLED 1U
+#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SDA_PORT_NUM 6U
+#define CYBSP_EZI2C_SDA_PIN 1U
+#define CYBSP_EZI2C_SDA_NUM 1U
+#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_1_HSIOM
+	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
+#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PORT_NUM 6U
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_4_HSIOM
+	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_PORT_PIN P6_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PORT_NUM 6U
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_6_HSIOM
+	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDCK_ENABLED 1U
+#define CYBSP_SWDCK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PORT_NUM 6U
+#define CYBSP_SWDCK_PIN 7U
+#define CYBSP_SWDCK_NUM 7U
+#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_7_HSIOM
+	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINA_ENABLED 1U
+#define CYBSP_CINA_PORT GPIO_PRT7
+#define CYBSP_CINA_PORT_NUM 7U
+#define CYBSP_CINA_PIN 1U
+#define CYBSP_CINA_NUM 1U
+#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_1_HSIOM
+	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_PORT_PIN P7_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINB_ENABLED 1U
+#define CYBSP_CINB_PORT GPIO_PRT7
+#define CYBSP_CINB_PORT_NUM 7U
+#define CYBSP_CINB_PIN 2U
+#define CYBSP_CINB_NUM 2U
+#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINB_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_2_HSIOM
+	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_PORT_PIN P7_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PORT_NUM 7U
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_7_HSIOM
+	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_PORT_PIN P7_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN0_PORT_NUM 8U
+#define CYBSP_CSD_BTN0_PIN 1U
+#define CYBSP_CSD_BTN0_NUM 1U
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_1_HSIOM
+	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN1_PORT_NUM 8U
+#define CYBSP_CSD_BTN1_PIN 2U
+#define CYBSP_CSD_BTN1_NUM 2U
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_2_HSIOM
+	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD0_PORT_NUM 8U
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_3_HSIOM
+	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD1_PORT_NUM 8U
+#define CYBSP_CSD_SLD1_PIN 4U
+#define CYBSP_CSD_SLD1_NUM 4U
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_4_HSIOM
+	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD2_PORT_NUM 8U
+#define CYBSP_CSD_SLD2_PIN 5U
+#define CYBSP_CSD_SLD2_NUM 5U
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_5_HSIOM
+	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD3_PORT_NUM 8U
+#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_6_HSIOM
+	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD4_PORT_NUM 8U
+#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_7_HSIOM
+	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t ioss_0_port_14_pin_0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t ioss_0_port_14_pin_1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINB_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
similarity index 81%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
index 12487034d72..c4e5bcf916f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
@@ -24,10 +24,10 @@
 
 #include "cycfg_qspi_memslot.h"
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xEBU,
+    .command = 0xECU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -42,7 +42,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x06U,
@@ -60,7 +60,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x04U,
@@ -78,10 +78,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xD8U,
+    .command = 0xDCU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -96,7 +96,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x60U,
@@ -114,10 +114,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x38U,
+    .command = 0x34U,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -132,7 +132,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x35U,
@@ -150,7 +150,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x05U,
@@ -168,7 +168,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x01U,
@@ -186,52 +186,52 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Specifies the number of address bytes used by the memory slave device. */
-    .numOfAddrBytes = 0x03U,
+    .numOfAddrBytes = 0x04U,
     /* The size of the memory. */
     .memSize = 0x04000000U,
     /* Specifies the Read command. */
-    .readCmd = &S25FL512S_SlaveSlot_0_readCmd,
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
     /* Specifies the Write Enable command. */
-    .writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
     /* Specifies the Write Disable command. */
-    .writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
     /* Specifies the Erase command. */
-    .eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
     /* Specifies the sector size of each erase. */
     .eraseSize = 0x00040000U,
     /* Specifies the Chip Erase command. */
-    .chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
     /* Specifies the Program command. */
-    .programCmd = &S25FL512S_SlaveSlot_0_programCmd,
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
     /* Specifies the page size for programming. */
     .programSize = 0x00000200U,
     /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
     /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
     /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
     /* The mask for the status register. */
     .stsRegBusyMask = 0x01U,
     /* The mask for the status register. */
     .stsRegQuadEnableMask = 0x02U,
     /* The max time for the erase type-1 cycle-time in ms. */
-    .eraseTime = 520U,
+    .eraseTime = 2600U,
     /* The max time for the chip-erase cycle-time in ms. */
-    .chipEraseTime = 134000U,
+    .chipEraseTime = 460000U,
     /* The max time for the page-program cycle-time in us. */
-    .programTime = 340U
+    .programTime = 1300U
 };
 
-const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Determines the slot number where the memory device is placed. */
     .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
     /* Flags. */
-    .flags = CY_SMIF_FLAG_WR_EN,
+    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
     /* The data-line selection options for a slave device. */
     .dataSelect = CY_SMIF_DATA_SEL0,
     /* The base address the memory slave is mapped to in the PSoC memory map.
@@ -239,16 +239,16 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
     .baseAddress = 0x18000000U,
     /* The size allocated in the PSoC memory map, for the memory slave device.
     The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
-    .memMappedSize = 0x10000U,
+    .memMappedSize = 0x4000000U,
     /* If this memory device is one of the devices in the dual quad SPI configuration.
     Valid when the memory mapped mode is enabled. */
     .dualQuadSlots = 0,
     /* The configuration of the device. */
-    .deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
 };
 
-const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
-   &S25FL512S_SlaveSlot_0
+const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
+   &S25FL512SX4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_block_config_t smifBlockConfig =
@@ -262,3 +262,4 @@ const cy_stc_smif_block_config_t smifBlockConfig =
     /* The version of the SMIF driver. */
     .minorVersion = CY_SMIF_DRV_VERSION_MINOR
 };
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
similarity index 57%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
index 7217969c325..32f9b49b2e6 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
@@ -28,22 +28,23 @@
 
 #define CY_SMIF_DEVICE_NUM 1
 
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeEnCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeDisCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_eraseCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_chipEraseCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_programCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegQeCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegWipCmd;
-extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
 
-extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25HL512T_SlaveSlot_0;
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
 
-extern const cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_0;
-extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
+extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
 
 extern const cy_stc_smif_block_config_t smifBlockConfig;
 
 
 #endif /*CY_SMIF_MEMCONFIG_H*/
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
similarity index 64%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
index 31a37742141..a1dadb2d0b0 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
@@ -24,22 +24,10 @@
 
 #include "cycfg_routing.h"
 
-#include "cy_trigmux.h"
-
-#include "stdbool.h"
-
 #include "cy_device_headers.h"
 
 void init_cycfg_routing(void)
 {
-	Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT44, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT1, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
 	HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
 		HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
 		HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
similarity index 77%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
index 17ec9db2365..368bd8797f4 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
@@ -40,34 +40,28 @@ void init_cycfg_routing(void);
 #define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
 #define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
 #define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
+#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD
+#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD
 #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_2_pin_0_HSIOM P2_0_SDHC0_CARD_DAT_3TO00
-#define ioss_0_port_2_pin_1_HSIOM P2_1_SDHC0_CARD_DAT_3TO01
-#define ioss_0_port_2_pin_2_HSIOM P2_2_SDHC0_CARD_DAT_3TO02
-#define ioss_0_port_2_pin_3_HSIOM P2_3_SDHC0_CARD_DAT_3TO03
-#define ioss_0_port_2_pin_4_HSIOM P2_4_SDHC0_CARD_CMD
-#define ioss_0_port_2_pin_5_HSIOM P2_5_SDHC0_CLK_CARD
 #define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
 #define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
 #define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
 #define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
-#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
-#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
 #define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
 #define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
 #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
 #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
 #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
 #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
 
 #if defined(__cplusplus)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
similarity index 90%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
index 9f12369c1a1..4f68fad8d9c 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
@@ -83,6 +83,46 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
 	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
 	.cco_Freq = 355U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 1U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 4U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = 
 {
 	.feedbackDiv = 30,
@@ -523,4 +563,24 @@ void init_cycfg_system(void)
 	
 	/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
 	SystemCoreClockUpdate();
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
new file mode 100644
index 00000000000..139dff5bdec
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
@@ -0,0 +1,109 @@
+/*******************************************************************************
+* File Name: cycfg_system.h
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_SYSTEM_H)
+#define CYCFG_SYSTEM_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_systick.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cy_gpio.h"
+#include "cy_syspm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define cpuss_0_dap_0_ENABLED 1U
+#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
+#define srss_0_clock_0_bakclk_0_ENABLED 1U
+#define srss_0_clock_0_fastclk_0_ENABLED 1U
+#define srss_0_clock_0_fll_0_ENABLED 1U
+#define srss_0_clock_0_hfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF0 0UL
+#define srss_0_clock_0_hfclk_1_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF1 1UL
+#define srss_0_clock_0_hfclk_2_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF2 2UL
+#define srss_0_clock_0_hfclk_3_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF3 3UL
+#define srss_0_clock_0_ilo_0_ENABLED 1U
+#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_lfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define srss_0_clock_0_pathmux_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_1_ENABLED 1U
+#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_pathmux_4_ENABLED 1U
+#define srss_0_clock_0_periclk_0_ENABLED 1U
+#define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_slowclk_0_ENABLED 1U
+#define srss_0_clock_0_timerclk_0_ENABLED 1U
+#define srss_0_clock_0_wco_0_ENABLED 1U
+#define srss_0_power_0_ENABLED 1U
+#define CY_CFG_PWR_MODE_LP 0x01UL
+#define CY_CFG_PWR_MODE_ULP 0x02UL
+#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
+#define CY_CFG_PWR_MODE_SLEEP 0x08UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
+#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
+#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
+#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VBACKUP_MV 3300
+#define CY_CFG_PWR_VDD_NS_MV 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
+
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_system(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_SYSTEM_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
new file mode 100644
index 00000000000..5557ddecddf
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
@@ -0,0 +1,4 @@
+set SMIF_BANKS {
+  0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+}
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
new file mode 100644
index 00000000000..13cf564a5a6
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
@@ -0,0 +1,409 @@
+<?xml version="1.0"?>
+<Configuration major="2" minor="0">
+    <!--
+       File Name: cycfg_capsense.cycapsense 
+
+       Description: 
+       CapSense middleware configuration 
+       This file should not be modified. It was automatically generated by 
+       CapSense Configurator 2.0.0 build 185 
+-->
+    <GeneralProperties>
+        <Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="REGULAR_IIR_RC_N" value="128"/>
+        <Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="PROX_IIR_RC_N" value="128"/>
+        <Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="REGULAR_IIR_BL_N" value="1"/>
+        <Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="PROX_IIR_BL_N" value="1"/>
+        <Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="MULTI_FREQ_SCAN_EN" value="false"/>
+        <Property id="SENSOR_AUTO_RESET_EN" value="false"/>
+        <Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
+        <Property id="VREF_SOURCE" value="SRSS"/>
+        <Property id="IREF_SOURCE" value="SRSS"/>
+        <Property id="PROX_TOUCH_COEFF" value="300"/>
+        <Property id="NUM_CENTROIDS" value="1"/>
+    </GeneralProperties>
+    <CsdProperties>
+        <Property id="CSD_AUTOTUNE" value="HWTH"/>
+        <Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
+        <Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
+        <Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
+        <Property id="CSD_IDAC_MIN" value="20"/>
+        <Property id="CSD_IDAC_COMP_EN" value="true"/>
+        <Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
+        <Property id="CSD_VREF_CUSTOM" value="false"/>
+        <Property id="CSD_VREF" value="1219"/>
+        <Property id="CSD_SHIELD_EN" value="false"/>
+        <Property id="CSD_SHIELD_TANK_EN" value="false"/>
+        <Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
+        <Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
+        <Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_FINE_INIT_TIME" value="10"/>
+        <Property id="CSD_CALIBRATION_ERROR" value="10"/>
+        <Property id="CSD_R_CONST" value="1000"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsdProperties>
+    <CsxProperties>
+        <Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSX_MAX_FINGERS" value="3"/>
+        <Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
+        <Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
+        <Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_FINE_INIT_TIME" value="10"/>
+        <Property id="CSX_CALIBRATION_ERROR" value="20"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsxProperties>
+    <Widgets>
+        <Widget id="Button0" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="Button1" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="LinearSlider0" type="LINEAR_SLIDER">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Sns0" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns1" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns2" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns3" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns4" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+    </Widgets>
+</Configuration>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
new file mode 100644
index 00000000000..3c5fbe94fb8
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
+<Configuration app="QSPI" major="2" minor="0">
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <PartNumber>S25FL512S-4byteaddr</PartNumber>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x4000000</Size>
+            <EndAddress>0x1BFFFFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</Configuration>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus
similarity index 78%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/design.modus
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus
index d67856d97de..089526cce09 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/design.modus
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus
@@ -2,13 +2,121 @@
 <Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
     <ToolInfo version="1.0.0"/>
     <Devices>
-        <Device mpn="CY8C624ABZI-D44">
+        <Device mpn="CY8C6247BZI-D54">
             <BlockConfig>
                 <Block location="cpuss[0].dap[0]" alias="" template="mxs40dap" version="1.0">
                     <Param id="dbgMode" value="SWD"/>
                     <Param id="traceEnable" value="false"/>
                 </Block>
-                <Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="1.1">
+                <Block location="cpuss[0].dw0[0].chan[0]" alias="" template="mxs40dma" version="1.0">
+                    <Param id="CRC_DATA_REVERSE" value="false"/>
+                    <Param id="CRC_DATA_XOR" value="0"/>
+                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
+                    <Param id="CRC_REMINDER_XOR" value="0"/>
+                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
+                    <Param id="CHANNEL_PRIORITY" value="1"/>
+                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
+                    <Param id="PREEMPTABLE" value="true"/>
+                    <Param id="BUFFERABLE" value="false"/>
+                    <Param id="DESCR_SELECTION" value="0"/>
+                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="ENABLE_CHAINING_0" value="false"/>
+                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
+                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
+                    <Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
+                    <Param id="X_NUM_OF_ELEMENTS_0" value="6"/>
+                    <Param id="X_SRC_INCREMENT_0" value="0"/>
+                    <Param id="X_DST_INCREMENT_0" value="1"/>
+                    <Param id="CRC_0" value="false"/>
+                    <Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
+                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
+                    <Param id="Y_DST_INCREMENT_0" value="0"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="cpuss[0].dw0[0].chan[1]" alias="" template="mxs40dma" version="1.0">
+                    <Param id="CRC_DATA_REVERSE" value="false"/>
+                    <Param id="CRC_DATA_XOR" value="0"/>
+                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
+                    <Param id="CRC_REMINDER_XOR" value="0"/>
+                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
+                    <Param id="CHANNEL_PRIORITY" value="1"/>
+                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
+                    <Param id="PREEMPTABLE" value="true"/>
+                    <Param id="BUFFERABLE" value="false"/>
+                    <Param id="DESCR_SELECTION" value="0"/>
+                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="ENABLE_CHAINING_0" value="false"/>
+                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
+                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_16CYC"/>
+                    <Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
+                    <Param id="X_NUM_OF_ELEMENTS_0" value="5"/>
+                    <Param id="X_SRC_INCREMENT_0" value="1"/>
+                    <Param id="X_DST_INCREMENT_0" value="0"/>
+                    <Param id="CRC_0" value="false"/>
+                    <Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
+                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
+                    <Param id="Y_DST_INCREMENT_0" value="0"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="cpuss[0].dw1[0].chan[1]" alias="" template="mxs40dma" version="1.0">
+                    <Param id="CRC_DATA_REVERSE" value="false"/>
+                    <Param id="CRC_DATA_XOR" value="0"/>
+                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
+                    <Param id="CRC_REMINDER_XOR" value="0"/>
+                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
+                    <Param id="CHANNEL_PRIORITY" value="0"/>
+                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
+                    <Param id="PREEMPTABLE" value="false"/>
+                    <Param id="BUFFERABLE" value="false"/>
+                    <Param id="DESCR_SELECTION" value="0"/>
+                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
+                    <Param id="ENABLE_CHAINING_0" value="false"/>
+                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
+                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
+                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_4CYC"/>
+                    <Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
+                    <Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
+                    <Param id="X_SRC_INCREMENT_0" value="2"/>
+                    <Param id="X_DST_INCREMENT_0" value="0"/>
+                    <Param id="CRC_0" value="false"/>
+                    <Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
+                    <Param id="Y_SRC_INCREMENT_0" value="10"/>
+                    <Param id="Y_DST_INCREMENT_0" value="0"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="cpuss[0].dw1[0].chan[3]" alias="" template="mxs40dma" version="1.0">
+                    <Param id="CRC_DATA_REVERSE" value="false"/>
+                    <Param id="CRC_DATA_XOR" value="0"/>
+                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
+                    <Param id="CRC_REMINDER_XOR" value="0"/>
+                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
+                    <Param id="CHANNEL_PRIORITY" value="0"/>
+                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
+                    <Param id="PREEMPTABLE" value="false"/>
+                    <Param id="BUFFERABLE" value="false"/>
+                    <Param id="DESCR_SELECTION" value="0"/>
+                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
+                    <Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
+                    <Param id="ENABLE_CHAINING_0" value="false"/>
+                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
+                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
+                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
+                    <Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
+                    <Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
+                    <Param id="X_SRC_INCREMENT_0" value="0"/>
+                    <Param id="X_DST_INCREMENT_0" value="2"/>
+                    <Param id="CRC_0" value="false"/>
+                    <Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
+                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
+                    <Param id="Y_DST_INCREMENT_0" value="10"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
+                <Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
                     <Param id="CapSenseEnable" value="true"/>
                     <Param id="CapSenseCore" value="4"/>
                     <Param id="SensorCount" value="12"/>
@@ -39,10 +147,8 @@
                     <Param id="csdInitTime" value="25"/>
                     <Param id="inFlash" value="true"/>
                     <Param id="CsdIdacEnable" value="false"/>
-                    <Param id="CsdIdacAEnable" value="false"/>
-                    <Param id="IdacAbusOnly" value="false"/>
-                    <Param id="CsdIdacBEnable" value="false"/>
-                    <Param id="IdacBbusOnly" value="false"/>
+                    <Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
+                    <Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
                     <Param id="csdIdacInitTime" value="25"/>
                     <Param id="idacInFlash" value="true"/>
                 </Block>
@@ -66,16 +172,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[0].pin[4]" alias="CYBSP_BTN2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
                     <Param id="initialState" value="1"/>
@@ -86,7 +182,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[3]" alias="CYBSP_QSPI_DATA3" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[11].pin[3]" alias="CYBSP_QSPI_D3" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -96,7 +192,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[4]" alias="CYBSP_QSPI_DATA2" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[11].pin[4]" alias="CYBSP_QSPI_D2" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -106,7 +202,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[5]" alias="CYBSP_QSPI_DATA1" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[11].pin[5]" alias="CYBSP_QSPI_D1" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -116,7 +212,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[6]" alias="CYBSP_QSPI_DATA0" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[11].pin[6]" alias="CYBSP_QSPI_D0" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -136,17 +232,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[13].pin[7]" alias="CYBSP_LED_RED" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[14].pin[0]" alias="" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -156,38 +242,8 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[2].pin[0]" alias="CYBSP_WIFI_SDIO_DAT0" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[1]" alias="CYBSP_WIFI_SDIO_DAT1" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[2]" alias="CYBSP_WIFI_SDIO_DAT2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[3]" alias="CYBSP_WIFI_SDIO_DAT3" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
+                <Block location="ioss[0].port[14].pin[1]" alias="" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
@@ -196,8 +252,8 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[2].pin[4]" alias="CYBSP_WIFI_SDIO_CMD" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
+                <Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
@@ -206,9 +262,9 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[2].pin[5]" alias="CYBSP_WIFI_SDIO_CLK" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
+                <Block location="ioss[0].port[2].pin[7]" alias="CYBSP_WIFI_HOST_WAKE" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="0"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
                     <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
@@ -286,26 +342,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[5].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
                     <Param id="initialState" value="1"/>
@@ -456,18 +492,28 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="peri[0].div_8[0]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="256"/>
+                <Block location="peri[0].div_16[0]" alias="CYBSP_USB_CLK_DIV" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="1000"/>
+                    <Param id="fracDivider" value="0"/>
+                    <Param id="startOnReset" value="true"/>
+                </Block>
+                <Block location="peri[0].div_8[0]" alias="CYBSP_SDIO_DIV" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="1"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
                 <Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="4"/>
+                    <Param id="intDivider" value="8"/>
+                    <Param id="fracDivider" value="0"/>
+                    <Param id="startOnReset" value="true"/>
+                </Block>
+                <Block location="peri[0].div_8[3]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="256"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
-                <Block location="peri[0].div_8[2]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="36"/>
+                <Block location="peri[0].div_8[4]" alias="" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="109"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
@@ -475,7 +521,7 @@
                     <Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
                     <Param id="IrdaLowPower" value="false"/>
                     <Param id="BaudRate" value="115200"/>
-                    <Param id="Oversample" value="12"/>
+                    <Param id="Oversample" value="8"/>
                     <Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
                     <Param id="DataWidth" value="8"/>
                     <Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
@@ -525,61 +571,8 @@
                     <Param id="EnableWakeup" value="false"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
-                    <Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
-                    <Param id="IrdaLowPower" value="false"/>
-                    <Param id="BaudRate" value="115200"/>
-                    <Param id="Oversample" value="12"/>
-                    <Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
-                    <Param id="DataWidth" value="9"/>
-                    <Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
-                    <Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
-                    <Param id="EnableInputFilter" value="false"/>
-                    <Param id="EnableTxEn" value="false"/>
-                    <Param id="FlowControl" value="false"/>
-                    <Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_HIGH"/>
-                    <Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
-                    <Param id="RtsTriggerLevel" value="63"/>
-                    <Param id="RxTriggerLevel" value="63"/>
-                    <Param id="TxTriggerLevel" value="63"/>
-                    <Param id="MultiProc" value="false"/>
-                    <Param id="MpRxAddress" value="0"/>
-                    <Param id="MpRxAddressMask" value="255"/>
-                    <Param id="MpRxAcceptAddress" value="false"/>
-                    <Param id="DropOnFrameErr" value="false"/>
-                    <Param id="DropOnParityErr" value="false"/>
-                    <Param id="BreakSignalBits" value="11"/>
-                    <Param id="SmCardRetryOnNack" value="false"/>
-                    <Param id="IrdaPolarity" value="NON_INVERTING"/>
-                    <Param id="inFlash" value="true"/>
-                    <Param id="ApiMode" value="HIGH_LEVEL"/>
-                    <Param id="IntrRxNotEmpty" value="false"/>
-                    <Param id="IntrRxFull" value="false"/>
-                    <Param id="IntrRxOverflow" value="false"/>
-                    <Param id="IntrRxUnderflow" value="false"/>
-                    <Param id="IntrRxFrameErr" value="false"/>
-                    <Param id="IntrRxParityErr" value="false"/>
-                    <Param id="IntrRxBreakDetected" value="false"/>
-                    <Param id="IntrRxTrigger" value="false"/>
-                    <Param id="IntrTxUartDone" value="false"/>
-                    <Param id="IntrTxUartLostArb" value="false"/>
-                    <Param id="IntrTxUartNack" value="false"/>
-                    <Param id="IntrTxEmpty" value="false"/>
-                    <Param id="IntrTxNotFull" value="false"/>
-                    <Param id="IntrTxOverflow" value="false"/>
-                    <Param id="IntrTxUnderflow" value="false"/>
-                    <Param id="IntrTxTrigger" value="false"/>
-                </Block>
-                <Block location="sdhc[0]" alias="CYBSP_RADIO" template="mxs40sdhost" version="1.0">
-                    <Param id="cardType" value="nonEmmc"/>
-                    <Param id="dmaType" value="CY_SD_HOST_DMA_SDMA"/>
-                    <Param id="enableLedControl" value="false"/>
-                    <Param id="busWidth" value="CY_SD_HOST_BUS_WIDTH_4_BIT"/>
-                    <Param id="lowVoltageSignaling" value="false"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
-                    <Param id="configurator" value=""/>
+                    <Param id="configurator" value="0"/>
                     <Param id="isrAlignment" value="false"/>
                     <Param id="isrUnderflow" value="false"/>
                     <Param id="isrCmdOverflow" value="false"/>
@@ -589,6 +582,9 @@
                     <Param id="inFlash" value="true"/>
                 </Block>
                 <Block location="srss[0].clock[0]" alias="" template="mxs40sysclocks" version="1.2"/>
+                <Block location="srss[0].clock[0].altsystickclk[0]" alias="" template="mxs40altsystick" version="1.0">
+                    <Param id="sourceClock" value="lfclk"/>
+                </Block>
                 <Block location="srss[0].clock[0].bakclk[0]" alias="" template="mxs40bakclk" version="1.0">
                     <Param id="sourceClock" value="wco"/>
                 </Block>
@@ -603,19 +599,23 @@
                     <Param id="sourceClockNumber" value="0"/>
                     <Param id="divider" value="1"/>
                 </Block>
+                <Block location="srss[0].clock[0].hfclk[1]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="1"/>
+                    <Param id="divider" value="1"/>
+                </Block>
                 <Block location="srss[0].clock[0].hfclk[2]" alias="" template="mxs40hfclk" version="1.1">
                     <Param id="sourceClockNumber" value="0"/>
                     <Param id="divider" value="2"/>
                 </Block>
-                <Block location="srss[0].clock[0].hfclk[4]" alias="" template="mxs40hfclk" version="1.1">
-                    <Param id="sourceClockNumber" value="0"/>
+                <Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="1"/>
                     <Param id="divider" value="1"/>
                 </Block>
                 <Block location="srss[0].clock[0].ilo[0]" alias="" template="mxs40ilo" version="1.0">
                     <Param id="hibernate" value="true"/>
                 </Block>
                 <Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
-                    <Param id="trim" value="1"/>
+                    <Param id="trim" value="0.25"/>
                 </Block>
                 <Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
                     <Param id="sourceClock" value="wco"/>
@@ -635,15 +635,22 @@
                 <Block location="srss[0].clock[0].pathmux[4]" alias="" template="mxs40pathmux" version="1.0">
                     <Param id="sourceClock" value="imo"/>
                 </Block>
-                <Block location="srss[0].clock[0].pathmux[5]" alias="" template="mxs40pathmux" version="1.0">
-                    <Param id="sourceClock" value="imo"/>
-                </Block>
                 <Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
-                    <Param id="divider" value="2"/>
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].pll[0]" alias="" template="mxs40pll" version="1.0">
+                    <Param id="lowFrequencyMode" value="false"/>
+                    <Param id="configuration" value="auto"/>
+                    <Param id="desiredFrequency" value="48.000"/>
+                    <Param id="optimization" value="MinPower"/>
                 </Block>
                 <Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
                     <Param id="divider" value="1"/>
                 </Block>
+                <Block location="srss[0].clock[0].timerclk[0]" alias="" template="mxs40timerclk" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                    <Param id="timerDivider" value="1"/>
+                </Block>
                 <Block location="srss[0].clock[0].wco[0]" alias="" template="mxs40wco" version="1.0">
                     <Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
                     <Param id="clockLostDetection" value="false"/>
@@ -706,6 +713,29 @@
                     <Param id="dstStopHour" value="0"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
+                <Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.0">
+                    <Param id="configurator" value="0"/>
+                    <Param id="UsbCore" value="4"/>
+                    <Param id="epMask" value="0"/>
+                    <Param id="bufSize" value="512"/>
+                    <Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
+                    <Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
+                    <Param id="enableLpm" value="false"/>
+                    <Param id="lpmIntr" value="0x0U"/>
+                    <Param id="ArbIntr" value="0x0U"/>
+                    <Param id="ep0CntrIntr" value="0x2U"/>
+                    <Param id="busResetIntr" value="0x2U"/>
+                    <Param id="sofIntr" value="0x1U"/>
+                    <Param id="ep0Intr" value="0x1U"/>
+                    <Param id="ep1Intr" value="0x1U"/>
+                    <Param id="ep2Intr" value="0x1U"/>
+                    <Param id="ep3Intr" value="0x1U"/>
+                    <Param id="ep4Intr" value="0x1U"/>
+                    <Param id="ep5Intr" value="0x1U"/>
+                    <Param id="ep6Intr" value="0x1U"/>
+                    <Param id="ep7Intr" value="0x1U"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
             </BlockConfig>
             <Netlist>
                 <Net>
@@ -722,7 +752,7 @@
                 </Net>
                 <Net>
                     <Port name="csd[0].csd[0].clock[0]"/>
-                    <Port name="peri[0].div_8[0].clk[0]"/>
+                    <Port name="peri[0].div_8[3].clk[0]"/>
                 </Net>
                 <Net>
                     <Port name="ioss[0].port[0].pin[0].analog[0]"/>
@@ -732,30 +762,6 @@
                     <Port name="ioss[0].port[0].pin[1].analog[0]"/>
                     <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
                 </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[0].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[1].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[1]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[2].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[2]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[3].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_dat_3to0[3]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[4].digital_inout[0]"/>
-                    <Port name="sdhc[0].card_cmd[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[5].digital_out[0]"/>
-                    <Port name="sdhc[0].clk_card[0]"/>
-                </Net>
                 <Net>
                     <Port name="ioss[0].port[3].pin[0].digital_inout[0]"/>
                     <Port name="scb[2].uart_rx[0]"/>
@@ -772,14 +778,6 @@
                     <Port name="ioss[0].port[3].pin[3].digital_in[0]"/>
                     <Port name="scb[2].uart_cts[0]"/>
                 </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
-                    <Port name="scb[5].uart_rx[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
-                    <Port name="scb[5].uart_tx[0]"/>
-                </Net>
                 <Net>
                     <Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
                     <Port name="scb[3].i2c_scl[0]"/>
@@ -812,18 +810,25 @@
                     <Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
                     <Port name="smif[0].spi_clk[0]"/>
                 </Net>
+                <Net>
+                    <Port name="ioss[0].port[14].pin[0].aux[0]"/>
+                    <Port name="usb[0].usb_dp_pad[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[14].pin[1].aux[0]"/>
+                    <Port name="usb[0].usb_dm_pad[0]"/>
+                </Net>
+                <Net>
+                    <Port name="peri[0].div_16[0].clk[0]"/>
+                    <Port name="usb[0].clock_dev_brs[0]"/>
+                </Net>
                 <Net>
                     <Port name="peri[0].div_8[1].clk[0]"/>
                     <Port name="scb[3].clock[0]"/>
                 </Net>
                 <Net>
-                    <Port name="peri[0].div_8[2].clk[0]"/>
+                    <Port name="peri[0].div_8[4].clk[0]"/>
                     <Port name="scb[2].clock[0]"/>
-                    <Port name="scb[5].clock[0]"/>
-                </Net>
-                <Net>
-                    <Port name="sdhc[0].clk_hf[0]"/>
-                    <Port name="srss[0].clock[0].hfclk[4].root_clk[0]"/>
                 </Net>
                 <Net>
                     <Port name="smif[0].clk_hf[0]"/>
@@ -833,6 +838,10 @@
                     <Port name="smif[0].clk_if[0]"/>
                     <Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
                 </Net>
+                <Net>
+                    <Port name="srss[0].clock[0].hfclk[3].root_clk[0]"/>
+                    <Port name="usb[0].clk_usb_dev[0]"/>
+                </Net>
                 <Mux name="sense" location="csd[0].csd[0]">
                     <Arm>
                         <Port name="ioss[0].port[7].pin[7].analog[0]"/>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h
deleted file mode 100644
index a2b112783e4..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h
+++ /dev/null
@@ -1,631 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.h
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PINS_H)
-#define CYCFG_PINS_H
-
-#include "cycfg_notices.h"
-#include "cy_gpio.h"
-#include "cycfg_routing.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_WCO_IN_ENABLED 1U
-#define CYBSP_WCO_IN_PORT GPIO_PRT0
-#define CYBSP_WCO_IN_PIN 0U
-#define CYBSP_WCO_IN_NUM 0U
-#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_0_HSIOM
-	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_WCO_OUT_ENABLED 1U
-#define CYBSP_WCO_OUT_PORT GPIO_PRT0
-#define CYBSP_WCO_OUT_PIN 1U
-#define CYBSP_WCO_OUT_NUM 1U
-#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_1_HSIOM
-	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_LED_RED_ENABLED 1U
-#define CYBSP_LED_RED_PORT GPIO_PRT0
-#define CYBSP_LED_RED_PIN 3U
-#define CYBSP_LED_RED_NUM 3U
-#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_RED_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_3_HSIOM
-	#define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
-#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_BTN2_ENABLED 1U
-#define CYBSP_BTN2_PORT GPIO_PRT0
-#define CYBSP_BTN2_PIN 4U
-#define CYBSP_BTN2_NUM 4U
-#define CYBSP_BTN2_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_BTN2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_4_HSIOM
-	#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BTN2_HSIOM ioss_0_port_0_pin_4_HSIOM
-#define CYBSP_BTN2_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_LED_BLUE_ENABLED 1U
-#define CYBSP_LED_BLUE_PORT GPIO_PRT11
-#define CYBSP_LED_BLUE_PIN 1U
-#define CYBSP_LED_BLUE_NUM 1U
-#define CYBSP_LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_BLUE_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_1_HSIOM
-	#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
-#define CYBSP_LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SS_ENABLED 1U
-#define CYBSP_QSPI_SS_PORT GPIO_PRT11
-#define CYBSP_QSPI_SS_PIN 2U
-#define CYBSP_QSPI_SS_NUM 2U
-#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_2_HSIOM
-	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
-#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D3_ENABLED 1U
-#define CYBSP_QSPI_D3_PORT GPIO_PRT11
-#define CYBSP_QSPI_D3_PIN 3U
-#define CYBSP_QSPI_D3_NUM 3U
-#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_3_HSIOM
-	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
-#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D2_ENABLED 1U
-#define CYBSP_QSPI_D2_PORT GPIO_PRT11
-#define CYBSP_QSPI_D2_PIN 4U
-#define CYBSP_QSPI_D2_NUM 4U
-#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_4_HSIOM
-	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
-#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D1_ENABLED 1U
-#define CYBSP_QSPI_D1_PORT GPIO_PRT11
-#define CYBSP_QSPI_D1_PIN 5U
-#define CYBSP_QSPI_D1_NUM 5U
-#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_5_HSIOM
-	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
-#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D0_ENABLED 1U
-#define CYBSP_QSPI_D0_PORT GPIO_PRT11
-#define CYBSP_QSPI_D0_PIN 6U
-#define CYBSP_QSPI_D0_NUM 6U
-#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_6_HSIOM
-	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
-#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SCK_ENABLED 1U
-#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
-#define CYBSP_QSPI_SCK_PIN 7U
-#define CYBSP_QSPI_SCK_NUM 7U
-#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_7_HSIOM
-	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
-#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_LED9_ENABLED 1U
-#define CYBSP_LED9_PORT GPIO_PRT13
-#define CYBSP_LED9_PIN 7U
-#define CYBSP_LED9_NUM 7U
-#define CYBSP_LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED9_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_13_pin_7_HSIOM
-	#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
-#define CYBSP_LED9_IRQ ioss_interrupts_gpio_13_IRQn
-#define ioss_0_port_14_pin_0_ENABLED 1U
-#define ioss_0_port_14_pin_0_PORT GPIO_PRT14
-#define ioss_0_port_14_pin_0_PIN 0U
-#define ioss_0_port_14_pin_0_NUM 0U
-#define ioss_0_port_14_pin_0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define ioss_0_port_14_pin_0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_14_pin_0_HSIOM
-	#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn
-#define ioss_0_port_14_pin_1_ENABLED 1U
-#define ioss_0_port_14_pin_1_PORT GPIO_PRT14
-#define ioss_0_port_14_pin_1_PIN 1U
-#define ioss_0_port_14_pin_1_NUM 1U
-#define ioss_0_port_14_pin_1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define ioss_0_port_14_pin_1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_14_pin_1_HSIOM
-	#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn
-#define CYBSP_CSD_TX_ENABLED 1U
-#define CYBSP_CSD_TX_PORT GPIO_PRT1
-#define CYBSP_CSD_TX_PIN 0U
-#define CYBSP_CSD_TX_NUM 0U
-#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_0_HSIOM
-	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_LED_GREEN_ENABLED 1U
-#define CYBSP_LED_GREEN_PORT GPIO_PRT1
-#define CYBSP_LED_GREEN_PIN 1U
-#define CYBSP_LED_GREEN_NUM 1U
-#define CYBSP_LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_GREEN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_1_HSIOM
-	#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
-#define CYBSP_LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_LED8_ENABLED 1U
-#define CYBSP_LED8_PORT GPIO_PRT1
-#define CYBSP_LED8_PIN 5U
-#define CYBSP_LED8_NUM 5U
-#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED8_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_5_HSIOM
-	#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
-#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_WIFI_SDIO_D0_ENABLED 1U
-#define CYBSP_WIFI_SDIO_D0_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_D0_PIN 0U
-#define CYBSP_WIFI_SDIO_D0_NUM 0U
-#define CYBSP_WIFI_SDIO_D0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_D0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_0_HSIOM
-	#define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_D0_HSIOM ioss_0_port_2_pin_0_HSIOM
-#define CYBSP_WIFI_SDIO_D0_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_D1_ENABLED 1U
-#define CYBSP_WIFI_SDIO_D1_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_D1_PIN 1U
-#define CYBSP_WIFI_SDIO_D1_NUM 1U
-#define CYBSP_WIFI_SDIO_D1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_D1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_1_HSIOM
-	#define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_D1_HSIOM ioss_0_port_2_pin_1_HSIOM
-#define CYBSP_WIFI_SDIO_D1_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_D2_ENABLED 1U
-#define CYBSP_WIFI_SDIO_D2_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_D2_PIN 2U
-#define CYBSP_WIFI_SDIO_D2_NUM 2U
-#define CYBSP_WIFI_SDIO_D2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_D2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_2_HSIOM
-	#define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_D2_HSIOM ioss_0_port_2_pin_2_HSIOM
-#define CYBSP_WIFI_SDIO_D2_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_D3_ENABLED 1U
-#define CYBSP_WIFI_SDIO_D3_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_D3_PIN 3U
-#define CYBSP_WIFI_SDIO_D3_NUM 3U
-#define CYBSP_WIFI_SDIO_D3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_D3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_3_HSIOM
-	#define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_D3_HSIOM ioss_0_port_2_pin_3_HSIOM
-#define CYBSP_WIFI_SDIO_D3_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_CMD_ENABLED 1U
-#define CYBSP_WIFI_SDIO_CMD_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_CMD_PIN 4U
-#define CYBSP_WIFI_SDIO_CMD_NUM 4U
-#define CYBSP_WIFI_SDIO_CMD_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_CMD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_4_HSIOM
-	#define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
-#define CYBSP_WIFI_SDIO_CMD_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_CLK_ENABLED 1U
-#define CYBSP_WIFI_SDIO_CLK_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_CLK_PIN 5U
-#define CYBSP_WIFI_SDIO_CLK_NUM 5U
-#define CYBSP_WIFI_SDIO_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_WIFI_SDIO_CLK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_5_HSIOM
-	#define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
-#define CYBSP_WIFI_SDIO_CLK_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_WL_REG_ON_ENABLED 1U
-#define CYBSP_WIFI_WL_REG_ON_PORT GPIO_PRT2
-#define CYBSP_WIFI_WL_REG_ON_PIN 6U
-#define CYBSP_WIFI_WL_REG_ON_NUM 6U
-#define CYBSP_WIFI_WL_REG_ON_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_WIFI_WL_REG_ON_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_2_pin_6_HSIOM
-	#define ioss_0_port_2_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_WL_REG_ON_HSIOM ioss_0_port_2_pin_6_HSIOM
-#define CYBSP_WIFI_WL_REG_ON_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
-#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2
-#define CYBSP_WIFI_HOST_WAKE_PIN 7U
-#define CYBSP_WIFI_HOST_WAKE_NUM 7U
-#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_2_pin_7_HSIOM
-	#define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM
-#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_BT_UART_RX_ENABLED 1U
-#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
-#define CYBSP_BT_UART_RX_PIN 0U
-#define CYBSP_BT_UART_RX_NUM 0U
-#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_0_HSIOM
-	#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
-#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_TX_ENABLED 1U
-#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
-#define CYBSP_BT_UART_TX_PIN 1U
-#define CYBSP_BT_UART_TX_NUM 1U
-#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_1_HSIOM
-	#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
-#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_RTS_ENABLED 1U
-#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
-#define CYBSP_BT_UART_RTS_PIN 2U
-#define CYBSP_BT_UART_RTS_NUM 2U
-#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_2_HSIOM
-	#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
-#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_CTS_ENABLED 1U
-#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
-#define CYBSP_BT_UART_CTS_PIN 3U
-#define CYBSP_BT_UART_CTS_NUM 3U
-#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_3_HSIOM
-	#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
-#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_POWER_ENABLED 1U
-#define CYBSP_BT_POWER_PORT GPIO_PRT3
-#define CYBSP_BT_POWER_PIN 4U
-#define CYBSP_BT_POWER_NUM 4U
-#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
-#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_4_HSIOM
-	#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
-#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_HOST_WAKE_ENABLED 1U
-#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
-#define CYBSP_BT_HOST_WAKE_PIN 5U
-#define CYBSP_BT_HOST_WAKE_NUM 5U
-#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_3_pin_5_HSIOM
-	#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
-#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
-#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
-#define CYBSP_BT_DEVICE_WAKE_PIN 0U
-#define CYBSP_BT_DEVICE_WAKE_NUM 0U
-#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_4_pin_0_HSIOM
-	#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
-#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
-#define CYBSP_DEBUG_UART_RX_ENABLED 1U
-#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_RX_PIN 0U
-#define CYBSP_DEBUG_UART_RX_NUM 0U
-#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_0_HSIOM
-	#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
-#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_DEBUG_UART_TX_ENABLED 1U
-#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_TX_PIN 1U
-#define CYBSP_DEBUG_UART_TX_NUM 1U
-#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_1_HSIOM
-	#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
-#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_EZI2C_SCL_ENABLED 1U
-#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SCL_PIN 0U
-#define CYBSP_EZI2C_SCL_NUM 0U
-#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_0_HSIOM
-	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
-#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_EZI2C_SDA_ENABLED 1U
-#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SDA_PIN 1U
-#define CYBSP_EZI2C_SDA_NUM 1U
-#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_1_HSIOM
-	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
-#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWO_ENABLED 1U
-#define CYBSP_SWO_PORT GPIO_PRT6
-#define CYBSP_SWO_PIN 4U
-#define CYBSP_SWO_NUM 4U
-#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_SWO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_4_HSIOM
-	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDIO_ENABLED 1U
-#define CYBSP_SWDIO_PORT GPIO_PRT6
-#define CYBSP_SWDIO_PIN 6U
-#define CYBSP_SWDIO_NUM 6U
-#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SWDIO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_6_HSIOM
-	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDCK_ENABLED 1U
-#define CYBSP_SWDCK_PORT GPIO_PRT6
-#define CYBSP_SWDCK_PIN 7U
-#define CYBSP_SWDCK_NUM 7U
-#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define CYBSP_SWDCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_7_HSIOM
-	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_CINA_ENABLED 1U
-#define CYBSP_CINA_PORT GPIO_PRT7
-#define CYBSP_CINA_PIN 1U
-#define CYBSP_CINA_NUM 1U
-#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_1_HSIOM
-	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
-#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CINB_ENABLED 1U
-#define CYBSP_CINB_PORT GPIO_PRT7
-#define CYBSP_CINB_PIN 2U
-#define CYBSP_CINB_NUM 2U
-#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINB_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_2_HSIOM
-	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
-#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CMOD_ENABLED 1U
-#define CYBSP_CMOD_PORT GPIO_PRT7
-#define CYBSP_CMOD_PIN 7U
-#define CYBSP_CMOD_NUM 7U
-#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CMOD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_7_HSIOM
-	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
-#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CSD_BTN0_ENABLED 1U
-#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN0_PIN 1U
-#define CYBSP_CSD_BTN0_NUM 1U
-#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_1_HSIOM
-	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_BTN1_ENABLED 1U
-#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN1_PIN 2U
-#define CYBSP_CSD_BTN1_NUM 2U
-#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_2_HSIOM
-	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
-#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD0_ENABLED 1U
-#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD0_PIN 3U
-#define CYBSP_CSD_SLD0_NUM 3U
-#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_3_HSIOM
-	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD1_ENABLED 1U
-#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD1_PIN 4U
-#define CYBSP_CSD_SLD1_NUM 4U
-#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_4_HSIOM
-	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
-#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD2_ENABLED 1U
-#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD2_PIN 5U
-#define CYBSP_CSD_SLD2_NUM 5U
-#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_5_HSIOM
-	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
-#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD3_ENABLED 1U
-#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD3_PIN 6U
-#define CYBSP_CSD_SLD3_NUM 6U
-#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_6_HSIOM
-	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
-#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD4_ENABLED 1U
-#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD4_PIN 7U
-#define CYBSP_CSD_SLD4_NUM 7U
-#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_7_HSIOM
-	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
-#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
-
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BTN2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED9_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
-
-void init_cycfg_pins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PINS_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/qspi_config.cfg
deleted file mode 100644
index a561643dcf1..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/qspi_config.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-set SMIF_BANKS {
-}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/PeripheralPins.c
index 8ff59be3cb9..433e728ea3c 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/PeripheralPins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/PeripheralPins.c
@@ -104,7 +104,9 @@ const PinMap PinMap_I2C_SCL[] = {
     {P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_0_SCB7_I2C_SCL)},
     {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
     {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
+    {P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
     {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
+    {P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
     {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
     {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
     {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
@@ -122,7 +124,9 @@ const PinMap PinMap_I2C_SDA[] = {
     {P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_1_SCB7_I2C_SDA)},
     {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
     {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
+    {P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
     {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
+    {P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
     {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
     {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
     {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
@@ -144,7 +148,9 @@ const PinMap PinMap_SPI_MOSI[] = {
     {P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)},
     {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
     {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
+    {P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
     {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
+    {P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
     {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
     {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
     {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
@@ -162,7 +168,9 @@ const PinMap PinMap_SPI_MISO[] = {
     {P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)},
     {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
     {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
+    {P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
     {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
+    {P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
     {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
     {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
     {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
@@ -179,7 +187,9 @@ const PinMap PinMap_SPI_SCLK[] = {
     {P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)},
     {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
     {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
+    {P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
     {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
+    {P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
     {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
     {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
     {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
@@ -195,7 +205,9 @@ const PinMap PinMap_SPI_SSEL[] = {
     {P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)},
     {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
     {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
+    {P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
     {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
+    {P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
     {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
     {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
     {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
@@ -430,7 +442,6 @@ const PinMap PinMap_ADC[] = {
 #if DEVICE_ANALOGOUT
 const PinMap PinMap_DAC[] = {
     {P9_6,  DAC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
-    {P10_5, DAC_0, CY_GPIO_CFG_CREATE(HSIOM_SEL_AMUXA, CY_GPIO_DM_ANALOG)},  // CTDAC connects to the P10_5 pin through the AMUXA bus
     {NC,    NC,     0}
 };
 #endif // DEVICE_ANALOGIN
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/PinNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/PinNames.h
index b5104545ee9..88b383965c7 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/PinNames.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/PinNames.h
@@ -20,38 +20,8 @@
 #ifndef MBED_PINNAMES_H
 #define MBED_PINNAMES_H
 
-#include "cmsis.h"
 #include "PinNamesTypes.h"
-#include "PortNames.h"
 #include "cyhal_pin_package.h"
-#include "cyhal_utils.h"
-
-typedef cyhal_gpio_t PinName;
-
-// Arduino connector namings
-#define A0 P10_0
-#define A1 P10_1
-#define A2 P10_2
-#define A3 P10_3
-#define A4 P10_4
-#define A5 P10_5
-
-#define D0 P5_0
-#define D1 P5_1
-#define D2 P5_2
-#define D3 P5_3
-#define D4 P5_4
-#define D5 P5_5
-#define D6 P5_6
-#define D7 P0_2
-#define D8 P13_0
-#define D9 P13_1
-#define D10 P12_3
-#define D11 P12_0
-#define D12 P12_1
-#define D13 P12_2
-#define D14 P6_1
-#define D15 P6_0
 
 // Generic signal names
 
@@ -68,28 +38,17 @@ typedef cyhal_gpio_t PinName;
 #define UART_RTS P5_2
 #define UART_CTS P5_3
 
-#define BT_UART_RX P3_0
-#define BT_UART_TX P3_1
-#define BT_UART_CTS P3_3
-#define BT_UART_RTS P3_2
-
-#define BT_PIN_POWER P3_4
-#define BT_PIN_HOST_WAKE P3_5
-#define BT_PIN_DEVICE_WAKE P4_0
-// Reset pin unavailable
-
-
-#define SWITCH2 P0_4
 #define LED1 P0_3
-#define LED2 P1_1
-#define LED3 P11_1
+#define LED2 P11_1
+#define LED3 P1_1
 #define LED4 P1_5
 #define LED5 P13_7
-
 #define LED_RED LED1
-#define LED_BLUE LED3
-#define LED_GREEN LED2
+#define LED_BLUE LED2
+#define LED_GREEN LED3
 
+// Reset pin unavailable
+#define SWITCH2 P0_4
 #define USER_BUTTON SWITCH2
 #define BUTTON1 USER_BUTTON
 
@@ -113,26 +72,9 @@ typedef cyhal_gpio_t PinName;
 #define STDIO_UART_CTS UART_CTS
 #define STDIO_UART_RTS UART_RTS
 
-#define CY_STDIO_UART_RX STDIO_UART_RX
-#define CY_STDIO_UART_TX STDIO_UART_TX
-#define CY_STDIO_UART_CTS STDIO_UART_CTS
-#define CY_STDIO_UART_RTS STDIO_UART_RTS
-
-#define CY_BT_UART_RX BT_UART_RX
-#define CY_BT_UART_TX BT_UART_TX
-#define CY_BT_UART_CTS BT_UART_CTS
-#define CY_BT_UART_RTS BT_UART_RTS
-
-#define CY_BT_PIN_POWER BT_PIN_POWER
-#define CY_BT_PIN_HOST_WAKE BT_PIN_HOST_WAKE
-#define CY_BT_PIN_DEVICE_WAKE BT_PIN_DEVICE_WAKE
-
-
 #define USBTX UART_TX
 #define USBRX UART_RX
 
-#define CY_WIFI_HOST_WAKE P2_7
-
 #define AOUT P9_6
 
 #endif
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c
index 9cab459a4dd..dac8480d91f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c
@@ -28,13 +28,23 @@
 extern "C" {
 #endif
 
-#ifdef SEMAPHORE
-#include "cyabs_rtos.h"
+#ifdef CY_RTOS_AWARE
 
-#define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL )
-static cy_semaphore_t sdio_transfer_finished_semaphore;
+    #include "cyabs_rtos.h"
+
+    #define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL )
+    static cy_semaphore_t sdio_transfer_finished_semaphore;
+    static bool sema_initialized = false;
 #endif
 
+/* Backup struct used to store and restore non retention UDB registers */
+typedef struct
+{
+    uint32_t CY_SDIO_UDB_WRKMULT_CTL_0;
+    uint32_t CY_SDIO_UDB_WRKMULT_CTL_1;
+    uint32_t CY_SDIO_UDB_WRKMULT_CTL_2;
+    uint32_t CY_SDIO_UDB_WRKMULT_CTL_3;
+} stc_sdio_backup_regs_t;
 
 /*Globals Needed for DMA */
 /*DMA channel structures*/
@@ -61,14 +71,63 @@ static uint8_t crcTable[256];
 static uint32_t yCountRemainder;
 static uint32_t yCounts;
 
+/* Global value for card interrupt */
+static uint8_t pfnCardInt_count = 0;
+
+/*Global structure to store UDB registers */
+static stc_sdio_backup_regs_t regs;
+
 static uint32_t udb_initialized = 0;
 
+cy_stc_syspm_callback_params_t      sdio_pm_callback_params;
+cy_stc_syspm_callback_t             sdio_pm_callback_handler;
+
+/* Deep Sleep Mode API Support */
+static void SDIO_SaveConfig(void);
+static void SDIO_RestoreConfig(void);
+
+/*******************************************************************************
+* Function Name: SDIO_DeepSleepCallback
+****************************************************************************//**
+*
+* Callback executed during Deep Sleep entry/exit
+*
+* \note
+* Saves/Restores SDIO UDB registers
+*******************************************************************************/
+cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode)
+{
+    cy_en_syspm_status_t status = CY_SYSPM_FAIL;
+
+    switch (mode) 
+    {
+        case CY_SYSPM_CHECK_READY:
+        case CY_SYSPM_CHECK_FAIL:
+            status = CY_SYSPM_SUCCESS;
+            break;
+
+        case CY_SYSPM_BEFORE_TRANSITION:
+            SDIO_SaveConfig();
+            status = CY_SYSPM_SUCCESS;
+            break;
+
+        case CY_SYSPM_AFTER_TRANSITION:
+            SDIO_RestoreConfig();
+            status = CY_SYSPM_SUCCESS;
+            break;
+
+        default:
+            break;
+    }
+
+    return status;
+}
 
 /*******************************************************************************
 * Function Name: SDIO_Init
 ****************************************************************************//**
 *
-* Initializes the SDIO hardware, and register the callback
+* Initializes the SDIO hardware
 *
 * \param pfuCb
 * Pointer to structure that holds pointers to callback function
@@ -132,11 +191,6 @@ void SDIO_Init(stc_sdio_irq_cb_t* pfuCb)
     SDIO_SetSdClkFrequency(400000);
     SDIO_EnableIntClock();
     SDIO_EnableSdClk();
-
-     /*Initalize the semaphore*/
-#ifdef SEMAPHORE
-    cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 1 );
-#endif
 }
 
 
@@ -560,41 +614,49 @@ void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig)
 *******************************************************************************/
 en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
 {
-    /*Store the command and data configurations*/
+    /* Store the command and data configurations*/
     stc_sdio_cmd_config_t   stcCmdConfig;
     stc_sdio_data_config_t  stcDataConfig;
 
-#ifdef SEMAPHORE
-    en_sdio_result_t result;
-#endif
-
-    /*variable used for holding timeout value*/
-#ifndef SEMAPHORE
-    uint32_t    u32Timeout = 0;
-#endif
-
-#ifndef SEMAPHORE_CMD
     uint32_t u32CmdTimeout = 0;
-#endif
 
     /*Returns from various function calls*/
     en_sdio_result_t enRet = Error;
     en_sdio_result_t enRetTmp = Ok;
 
-    /*Hold value of if these checks are needed*/
+    /* Hold value of if these checks are needed */
     uint8_t             bCmdIndexCheck;
     uint8_t             bCmdCrcCheck;
     static uint8_t      u8responseBuf[6];
 
-    /*Clear statuses*/
+    /* Clear statuses */
     gstcInternalData.stcEvents.u8CmdComplete = 0;
     gstcInternalData.stcEvents.u8TransComplete = 0;
     gstcInternalData.stcEvents.u8CRCError = 0;
 
-    /*Setup the command configuration*/
+    /* Setup the command configuration */
     stcCmdConfig.u8CmdIndex = (uint8_t)pstcCmd->u32CmdIdx;
     stcCmdConfig.u32Argument =  pstcCmd->u32Arg;
 
+#ifdef CY_RTOS_AWARE
+
+    cy_rslt_t result;
+
+    /* Initialize the semaphore. This is not done in init because init is called
+    * in interrupt thread. cy_rtos_init_semaphore call is prohibited in 
+    * interrupt thread.
+    */
+    if(!sema_initialized)
+    {
+        cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 0 );
+        sema_initialized = true;
+    }
+#else
+
+    /* Variable used for holding timeout value */
+    uint32_t    u32Timeout = 0;
+#endif
+
     /*Determine the type of response and if we need to do any checks*/
     /*Command 0 and 8 have no response, so don't wait for one*/
     if (pstcCmd->u32CmdIdx == 0 || pstcCmd->u32CmdIdx == 8)
@@ -694,30 +756,41 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
                             SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_WRITE;
                         }
 
-#ifndef SEMAPHORE
-                        /*Wait for the transfer to finish*/
+                    #ifdef CY_RTOS_AWARE
+                        /* Wait for the transfer to finish.
+                        *  Acquire semaphore and wait until it will be released 
+                        *  in SDIO_IRQ:
+                        *  1. sdio_transfer_finished_semaphore count is equal to 
+                        *     zero. cy_rtos_get_semaphore waits until semaphore 
+                        *     count is increased by cy_rtos_set_semaphore() in 
+                        *     SDIO_IRQ.
+                        *  2. The cy_rtos_set_semaphore() increases 
+                        *     sdio_transfer_finished_semaphore count.
+                        *  3. The cy_rtos_get_semaphore() function decreases 
+                        *     sdio_transfer_finished_semaphore back to zero 
+                        *     and exit. Or timeout occurs
+                        */
+                        result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false );
+
+                        enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone);
+
+                        if (result != CY_RSLT_SUCCESS)
+                    #else
+                         /* Wait for the transfer to finish */
                         do
                         {
-
                             u32Timeout++;
                             enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone);
 
                         } while (!((enRetTmp == Ok) || (enRetTmp == DataCrcError) || (u32Timeout >= SDIO_DAT_TIMEOUT)));
 
-                        /*if it was a read it is possible there is still extra data hanging out, trigger the
-                          DMA again. This can result in extra data being transfered so the read buffer should be
-                          3 bytes bigger than needed*/
-                        if (pstcCmd->bRead == true)
+                        if (u32Timeout == SDIO_DAT_TIMEOUT)
+                    #endif
                         {
-                            Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2);
+                            enRet |= DataTimeout;
                         }
 
-                        if (u32Timeout == SDIO_DAT_TIMEOUT)
-#else
-                         result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false );
-                         enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone);
-
-                         /* if it was a read it is possible there is still extra data hanging out, trigger the
+                        /* if it was a read it is possible there is still extra data hanging out, trigger the
                            DMA again. This can result in extra data being transfered so the read buffer should be
                            3 bytes bigger than needed*/
                         if (pstcCmd->bRead == true)
@@ -725,12 +798,6 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
                             Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2);
                         }
 
-                        if (result != Ok)
-#endif
-                        {
-                            enRet |= DataTimeout;
-                        }
-
                         if (enRetTmp == DataCrcError)
                         {
                             enRet |= DataCrcError;
@@ -741,9 +808,8 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
         } /*No Response Required, thus no CMD53*/
     } /*CMD Passed*/
 
-
-#ifndef SEMAPHORE
-     u32Timeout = 0;
+#ifndef CY_RTOS_AWARE
+    u32Timeout = 0;
 #endif
 
     /*If there were no errors then indicate transfer was okay*/
@@ -1161,63 +1227,72 @@ void SDIO_IRQ(void)
 {
     uint8_t u8Status;
 
-    /*first read the status register*/
+    /* First read the status register */
     u8Status = SDIO_STATUS_REG;
 
-    /*Check card interrupt*/
+    /* Check card interrupt */
     if (u8Status & SDIO_STS_CARD_INT )
     {
+        pfnCardInt_count++;
+    }
+    
+    /* Execute card interrupt callback if neccesary */
+    if (0 != pfnCardInt_count)
+    {        
         if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb)
         {
-              gstcInternalData.pstcCallBacks.pfnCardIntCb();
+            gstcInternalData.pstcCallBacks.pfnCardIntCb();
         }
+        pfnCardInt_count--;
     }
 
-    /*If the command is complete set the flag*/
+    /* If the command is complete set the flag */
     if (u8Status & SDIO_STS_CMD_DONE)
     {
         gstcInternalData.stcEvents.u8CmdComplete++;
     }
 
-    /*Check if a write is complete*/
+    /* Check if a write is complete */
     if (u8Status & SDIO_STS_WRITE_DONE )
     {
 
-        /*Clear the Write flag and CMD53 flag*/
+        /* Clear the Write flag and CMD53 flag */
         SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_INT);
 
-        /*Check if the CRC status return was bad*/
-        if (u8Status & SDIO_STS_CRC_ERR )
+        /* Check if the CRC status return was bad */
+        if (u8Status & SDIO_STS_CRC_ERR)
         {
-            /*CRC was bad, set the flag*/
+            /* CRC was bad, set the flag */
             gstcInternalData.stcEvents.u8CRCError++;
         }
-        /*set the done flag*/
-#ifdef SEMAPHORE
+        
+        /* Set the done flag */
+
+    #ifdef CY_RTOS_AWARE
         cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true );
-#else
+    #else
         gstcInternalData.stcEvents.u8TransComplete++;
-#endif
+    #endif
     }
 
-    /*Check if a read is complete*/
+    /* Check if a read is complete */
     if (u8Status & SDIO_STS_READ_DONE)
     {
-        /*Clear the read flag*/
+        /* Clear the read flag */
         SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_READ| SDIO_CTRL_ENABLE_INT);
 
-        /*check the CRC*/
+        /* Check the CRC */
         if (u8Status & SDIO_STS_CRC_ERR)
         {
-            /*CRC was bad, set the flag*/
+            /* CRC was bad, set the flag */
             gstcInternalData.stcEvents.u8CRCError++;
         }
-        /*Okay we're done so set the done flag*/
-#ifdef SEMAPHORE
+        /* Okay we're done so set the done flag */
+    #ifdef CY_RTOS_AWARE
         cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true );
-#else
+    #else
         gstcInternalData.stcEvents.u8TransComplete++;
-#endif
+    #endif
     }
 
     NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER);
@@ -1286,7 +1361,6 @@ void SDIO_READ_DMA_IRQ(void)
     yCounts--;
 }
 
-
 void SDIO_WRITE_DMA_IRQ(void)
 {
     /*We shouldn't have to change anything unless it is the last descriptor*/
@@ -1348,6 +1422,46 @@ void SDIO_WRITE_DMA_IRQ(void)
     yCounts--;
 }
 
+void SDIO_Free(void)
+{
+#ifdef CY_RTOS_AWARE
+    cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore);
+#endif
+}
+
+/*******************************************************************************
+* Function Name: SDIO_SaveConfig
+********************************************************************************
+*
+* Saves the user configuration of the SDIO UDB non-retention registers. Call the
+* SDIO_SaveConfig() function before the Cy_SysPm_CpuEnterDeepSleep() function.
+*
+*******************************************************************************/
+static void SDIO_SaveConfig(void)
+{
+    regs.CY_SDIO_UDB_WRKMULT_CTL_0 = UDB->WRKMULT.CTL[0];
+    regs.CY_SDIO_UDB_WRKMULT_CTL_1 = UDB->WRKMULT.CTL[1];
+    regs.CY_SDIO_UDB_WRKMULT_CTL_2 = UDB->WRKMULT.CTL[2];
+    regs.CY_SDIO_UDB_WRKMULT_CTL_3 = UDB->WRKMULT.CTL[3];
+}
+
+
+/*******************************************************************************
+* Function Name: SDIO_RestoreConfig
+********************************************************************************
+*
+* Restores the user configuration of the SDIO UDB non-retention registers. Call
+* the SDIO_Wakeup() function after the Cy_SysPm_CpuEnterDeepSleep() function.
+*
+*******************************************************************************/
+static void SDIO_RestoreConfig(void)
+{
+    UDB->WRKMULT.CTL[0] = regs.CY_SDIO_UDB_WRKMULT_CTL_0;
+    UDB->WRKMULT.CTL[1] = regs.CY_SDIO_UDB_WRKMULT_CTL_1;
+    UDB->WRKMULT.CTL[2] = regs.CY_SDIO_UDB_WRKMULT_CTL_2;
+    UDB->WRKMULT.CTL[3] = regs.CY_SDIO_UDB_WRKMULT_CTL_3;
+}
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h
index ceeb41995c4..05fff02eda6 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h
@@ -35,7 +35,6 @@
 
 /**
 * \defgroup group_udb_sdio UDB_SDIO
-* \ingroup group_bsp
 * \{
 *  SDIO - Secure Digital Input Output Is a standard for communicating with various
     external devices such as Wifi and bluetooth devices. 
@@ -272,6 +271,7 @@ void                SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz);
 void                SDIO_Reset(void);
 void                SDIO_EnableChipInt(void);
 void                SDIO_DisableChipInt(void);
+void                SDIO_Free(void);
 
 /*Low Level Functions*/
 void                SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig);
@@ -293,6 +293,8 @@ void                SDIO_WRITE_DMA_IRQ(void);
 
 void                SDIO_Crc7Init(void);
 
+cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode);
+
 /** \endcond */
 
 /** \} group_udb_sdio_functions */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h
index fb8caec7ce1..38114272872 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h
@@ -23,14 +23,6 @@
 * limitations under the License.
 *******************************************************************************/
 
-/**
-* \addtogroup group_bsp_cy8ckit_062_wifi_bt CY8CKIT-062-WIFI-BT
-* \ingroup group_bsp
-* \{
-* \defgroup group_bsp_cy8ckit_062_wifi_bt_macros Macros
-* \defgroup group_bsp_cy8ckit_062_wifi_bt_enums Enumerated Types
-*/
-
 #pragma once
 
 #include "cyhal.h"
@@ -40,10 +32,56 @@ extern "C" {
 #endif
 
 /**
-* \addtogroup group_bsp_cy8ckit_062_wifi_bt_macros
+* \addtogroup group_bsp_pins Pin Mappings
 * \{
 */
 
+// Arduino connector namings
+/** Arduino A0 */
+#define CYBSP_A0 P10_0
+/** Arduino A1 */
+#define CYBSP_A1 P10_1
+/** Arduino A2 */
+#define CYBSP_A2 P10_2
+/** Arduino A3 */
+#define CYBSP_A3 P10_3
+/** Arduino A4 */
+#define CYBSP_A4 P10_4
+/** Arduino A5 */
+#define CYBSP_A5 P10_5
+/** Arduino D0 */
+#define CYBSP_D0 P5_0
+/** Arduino D1 */
+#define CYBSP_D1 P5_1
+/** Arduino D2 */
+#define CYBSP_D2 P5_2
+/** Arduino D3 */
+#define CYBSP_D3 P5_3
+/** Arduino D4 */
+#define CYBSP_D4 P5_4
+/** Arduino D5 */
+#define CYBSP_D5 P5_5
+/** Arduino D6 */
+#define CYBSP_D6 P5_6
+/** Arduino D7 */
+#define CYBSP_D7 P0_2
+/** Arduino D8 */
+#define CYBSP_D8 P13_0
+/** Arduino D9 */
+#define CYBSP_D9 P13_1
+/** Arduino D10 */
+#define CYBSP_D10 P12_3
+/** Arduino D11 */
+#define CYBSP_D11 P12_0
+/** Arduino D12 */
+#define CYBSP_D12 P12_1
+/** Arduino D13 */
+#define CYBSP_D13 P12_2
+/** Arduino D14 */
+#define CYBSP_D14 P6_1
+/** Arduino D15 */
+#define CYBSP_D15 P6_0
+
 // Generic signal names
 /** Pin: WCO input */
 #define CYBSP_WCO_IN           P0_0
@@ -51,18 +89,25 @@ extern "C" {
 #define CYBSP_WCO_OUT          P0_1
 
 /** Pin: WIFI SDIO D0 */
+/* Corresponds to: ioss[0].port[2].pin[0], udb[0] */
 #define CYBSP_WIFI_SDIO_D0     P2_0
 /** Pin: WIFI SDIO D1 */
+/* Corresponds to: ioss[0].port[2].pin[1], udb[0] */
 #define CYBSP_WIFI_SDIO_D1     P2_1
 /** Pin: WIFI SDIO D2 */
+/* Corresponds to: ioss[0].port[2].pin[2], udb[0] */
 #define CYBSP_WIFI_SDIO_D2     P2_2
 /** Pin: WIFI SDIO D3 */
+/* Corresponds to: ioss[0].port[2].pin[3], udb[0] */
 #define CYBSP_WIFI_SDIO_D3     P2_3
 /** Pin: WIFI SDIO CMD */
+/* Corresponds to: ioss[0].port[2].pin[4], udb[0] */
 #define CYBSP_WIFI_SDIO_CMD    P2_4
 /** Pin: WIFI SDIO CLK */
+/* Corresponds to: ioss[0].port[2].pin[5], udb[0] */
 #define CYBSP_WIFI_SDIO_CLK    P2_5
 /** Pin: WIFI ON */
+/* Corresponds to: ioss[0].port[2].pin[6], udb[0] */
 #define CYBSP_WIFI_WL_REG_ON   P2_6
 /** Pin: WIFI Host Wakeup */
 #define CYBSP_WIFI_HOST_WAKE   P2_7
@@ -84,8 +129,10 @@ extern "C" {
 #define CYBSP_BT_DEVICE_WAKE   P4_0
 
 /** Pin: UART RX */
+/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
 #define CYBSP_DEBUG_UART_RX    P5_0
 /** Pin: UART TX */
+/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
 #define CYBSP_DEBUG_UART_TX    P5_1
 
 /** Pin: I2C SCL */
@@ -141,10 +188,10 @@ extern "C" {
 /** Host-wake IRQ event */
 #define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE
 
-/** \} group_bsp_cy8ckit_062_wifi_bt_macros */
+/** \} group_bsp_pins */
 
 /**
-* \addtogroup group_bsp_cy8ckit_062_wifi_bt_enums
+* \addtogroup group_bsp_enums Enumerated Types
 * \{
 */
 
@@ -171,10 +218,15 @@ typedef enum
     CYBSP_LED_RGB_GREEN = P1_1,
     CYBSP_LED_RGB_BLUE = P11_1,
 
+    /* Corresponds to: ioss[0].port[1].pin[5] */
     CYBSP_USER_LED1 = CYBSP_LED8,
+    /* Corresponds to: ioss[0].port[13].pin[7] */
     CYBSP_USER_LED2 = CYBSP_LED9,
+    /* Corresponds to: ioss[0].port[0].pin[3] */
     CYBSP_USER_LED3 = CYBSP_LED_RGB_RED,
+    /* Corresponds to: ioss[0].port[1].pin[1] */
     CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN,
+    /* Corresponds to: ioss[0].port[11].pin[1] */
     CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE,
     CYBSP_USER_LED = CYBSP_USER_LED1,
 } cybsp_led_t;
@@ -184,14 +236,13 @@ typedef enum
 {
     CYBSP_SW2 = P0_4,
 
+    /* Corresponds to: ioss[0].port[0].pin[4] */
     CYBSP_USER_BTN1 = CYBSP_SW2,
     CYBSP_USER_BTN = CYBSP_USER_BTN1,
 } cybsp_btn_t;
 
-/** \} group_bsp_cy8ckit_062_wifi_bt_enums */
+/** \} group_bsp_enums */
 
 #if defined(__cplusplus)
 }
 #endif
-
-/** \} group_bsp_cy8ckit_062_wifi_bt */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/design.modus
deleted file mode 100644
index bf3e7a0e770..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/design.modus
+++ /dev/null
@@ -1,1183 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
-    <ToolInfo version="1.0.0"/>
-    <Devices>
-        <Device mpn="CY8C6247BZI-D54">
-            <BlockConfig>
-                <Block location="cpuss[0].dap[0]" alias="" template="mxs40dap" version="1.0">
-                    <Param id="dbgMode" value="SWD"/>
-                    <Param id="traceEnable" value="false"/>
-                </Block>
-                <Block location="cpuss[0].dw0[0].chan[0]" alias="" template="mxs40dma" version="1.0">
-                    <Param id="CRC_DATA_REVERSE" value="false"/>
-                    <Param id="CRC_DATA_XOR" value="0"/>
-                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
-                    <Param id="CRC_REMINDER_XOR" value="0"/>
-                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
-                    <Param id="CHANNEL_PRIORITY" value="1"/>
-                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
-                    <Param id="PREEMPTABLE" value="true"/>
-                    <Param id="BUFFERABLE" value="false"/>
-                    <Param id="DESCR_SELECTION" value="0"/>
-                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="ENABLE_CHAINING_0" value="false"/>
-                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
-                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
-                    <Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
-                    <Param id="X_NUM_OF_ELEMENTS_0" value="6"/>
-                    <Param id="X_SRC_INCREMENT_0" value="0"/>
-                    <Param id="X_DST_INCREMENT_0" value="1"/>
-                    <Param id="CRC_0" value="false"/>
-                    <Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
-                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
-                    <Param id="Y_DST_INCREMENT_0" value="0"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="cpuss[0].dw0[0].chan[1]" alias="" template="mxs40dma" version="1.0">
-                    <Param id="CRC_DATA_REVERSE" value="false"/>
-                    <Param id="CRC_DATA_XOR" value="0"/>
-                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
-                    <Param id="CRC_REMINDER_XOR" value="0"/>
-                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
-                    <Param id="CHANNEL_PRIORITY" value="1"/>
-                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
-                    <Param id="PREEMPTABLE" value="true"/>
-                    <Param id="BUFFERABLE" value="false"/>
-                    <Param id="DESCR_SELECTION" value="0"/>
-                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="ENABLE_CHAINING_0" value="false"/>
-                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
-                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_16CYC"/>
-                    <Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
-                    <Param id="X_NUM_OF_ELEMENTS_0" value="5"/>
-                    <Param id="X_SRC_INCREMENT_0" value="1"/>
-                    <Param id="X_DST_INCREMENT_0" value="0"/>
-                    <Param id="CRC_0" value="false"/>
-                    <Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
-                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
-                    <Param id="Y_DST_INCREMENT_0" value="0"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="cpuss[0].dw1[0].chan[1]" alias="" template="mxs40dma" version="1.0">
-                    <Param id="CRC_DATA_REVERSE" value="false"/>
-                    <Param id="CRC_DATA_XOR" value="0"/>
-                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
-                    <Param id="CRC_REMINDER_XOR" value="0"/>
-                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
-                    <Param id="CHANNEL_PRIORITY" value="0"/>
-                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
-                    <Param id="PREEMPTABLE" value="false"/>
-                    <Param id="BUFFERABLE" value="false"/>
-                    <Param id="DESCR_SELECTION" value="0"/>
-                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
-                    <Param id="ENABLE_CHAINING_0" value="false"/>
-                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
-                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
-                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_4CYC"/>
-                    <Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
-                    <Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
-                    <Param id="X_SRC_INCREMENT_0" value="2"/>
-                    <Param id="X_DST_INCREMENT_0" value="0"/>
-                    <Param id="CRC_0" value="false"/>
-                    <Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
-                    <Param id="Y_SRC_INCREMENT_0" value="10"/>
-                    <Param id="Y_DST_INCREMENT_0" value="0"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="cpuss[0].dw1[0].chan[3]" alias="" template="mxs40dma" version="1.0">
-                    <Param id="CRC_DATA_REVERSE" value="false"/>
-                    <Param id="CRC_DATA_XOR" value="0"/>
-                    <Param id="CRC_REMINDER_REVERSE" value="false"/>
-                    <Param id="CRC_REMINDER_XOR" value="0"/>
-                    <Param id="CRC_POLYNOMIAL" value="79764919"/>
-                    <Param id="CHANNEL_PRIORITY" value="0"/>
-                    <Param id="NUM_OF_DESCRIPTORS" value="1"/>
-                    <Param id="PREEMPTABLE" value="false"/>
-                    <Param id="BUFFERABLE" value="false"/>
-                    <Param id="DESCR_SELECTION" value="0"/>
-                    <Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
-                    <Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
-                    <Param id="ENABLE_CHAINING_0" value="false"/>
-                    <Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
-                    <Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
-                    <Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
-                    <Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
-                    <Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
-                    <Param id="X_SRC_INCREMENT_0" value="0"/>
-                    <Param id="X_DST_INCREMENT_0" value="2"/>
-                    <Param id="CRC_0" value="false"/>
-                    <Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
-                    <Param id="Y_SRC_INCREMENT_0" value="0"/>
-                    <Param id="Y_DST_INCREMENT_0" value="10"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
-                    <Param id="CapSenseEnable" value="true"/>
-                    <Param id="CapSenseCore" value="4"/>
-                    <Param id="SensorCount" value="12"/>
-                    <Param id="CapacitorCount" value="3"/>
-                    <Param id="SensorName0" value="Cmod"/>
-                    <Param id="SensorName1" value="CintA"/>
-                    <Param id="SensorName2" value="CintB"/>
-                    <Param id="SensorName3" value="Button0_Rx0"/>
-                    <Param id="SensorName4" value="Button0_Tx"/>
-                    <Param id="SensorName5" value="Button1_Rx0"/>
-                    <Param id="SensorName6" value="Button1_Tx"/>
-                    <Param id="SensorName7" value="LinearSlider0_Sns0"/>
-                    <Param id="SensorName8" value="LinearSlider0_Sns1"/>
-                    <Param id="SensorName9" value="LinearSlider0_Sns2"/>
-                    <Param id="SensorName10" value="LinearSlider0_Sns3"/>
-                    <Param id="SensorName11" value="LinearSlider0_Sns4"/>
-                    <Param id="CapSenseConfigurator" value="0"/>
-                    <Param id="CapSenseTuner" value="0"/>
-                    <Param id="CsdAdcEnable" value="false"/>
-                    <Param id="numChannels" value="1"/>
-                    <Param id="resolution" value="CY_CSDADC_RESOLUTION_10BIT"/>
-                    <Param id="range" value="CY_CSDADC_RANGE_VDDA"/>
-                    <Param id="acqTime" value="10"/>
-                    <Param id="autoCalibrInterval" value="30"/>
-                    <Param id="vref" value="-1"/>
-                    <Param id="operClkDivider" value="1"/>
-                    <Param id="azTime" value="5"/>
-                    <Param id="csdInitTime" value="25"/>
-                    <Param id="inFlash" value="true"/>
-                    <Param id="CsdIdacEnable" value="false"/>
-                    <Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
-                    <Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
-                    <Param id="csdIdacInitTime" value="25"/>
-                    <Param id="idacInFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[0].pin[0]" alias="CYBSP_WCO_IN" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[0].pin[1]" alias="CYBSP_WCO_OUT" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[0].pin[3]" alias="CYBSP_LED_RED" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[0].pin[4]" alias="CYBSP_BTN2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[11].pin[1]" alias="CYBSP_LED_BLUE" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[11].pin[3]" alias="CYBSP_QSPI_D3" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[11].pin[4]" alias="CYBSP_QSPI_D2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[11].pin[5]" alias="CYBSP_QSPI_D1" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[11].pin[6]" alias="CYBSP_QSPI_D0" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[11].pin[7]" alias="CYBSP_QSPI_SCK" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[13].pin[7]" alias="CYBSP_LED9" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[14].pin[0]" alias="" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[14].pin[1]" alias="" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[1].pin[1]" alias="CYBSP_LED_GREEN" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[1].pin[5]" alias="CYBSP_LED8" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[0]" alias="CYBSP_WIFI_SDIO_D0" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[1]" alias="CYBSP_WIFI_SDIO_D1" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[2]" alias="CYBSP_WIFI_SDIO_D2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[3]" alias="CYBSP_WIFI_SDIO_D3" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[4]" alias="CYBSP_WIFI_SDIO_CMD" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[5]" alias="CYBSP_WIFI_SDIO_CLK" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[6]" alias="CYBSP_WIFI_WL_REG_ON" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="0"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[7]" alias="CYBSP_WIFI_HOST_WAKE" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="0"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[3].pin[0]" alias="CYBSP_BT_UART_RX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[3].pin[1]" alias="CYBSP_BT_UART_TX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[3].pin[2]" alias="CYBSP_BT_UART_RTS" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[3].pin[3]" alias="CYBSP_BT_UART_CTS" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[3].pin[4]" alias="CYBSP_BT_POWER" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[3].pin[5]" alias="CYBSP_BT_HOST_WAKE" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="0"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[4].pin[0]" alias="CYBSP_BT_DEVICE_WAKE" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="0"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[5].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[6].pin[1]" alias="CYBSP_EZI2C_SDA" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[6].pin[4]" alias="CYBSP_SWO" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[6].pin[6]" alias="CYBSP_SWDIO" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[6].pin[7]" alias="CYBSP_SWDCK" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[7].pin[1]" alias="CYBSP_CINA" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[7].pin[2]" alias="CYBSP_CINB" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[7].pin[7]" alias="CYBSP_CMOD" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[8].pin[1]" alias="CYBSP_CSD_BTN0" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[8].pin[2]" alias="CYBSP_CSD_BTN1" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[8].pin[3]" alias="CYBSP_CSD_SLD0" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[8].pin[4]" alias="CYBSP_CSD_SLD1" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[8].pin[5]" alias="CYBSP_CSD_SLD2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[8].pin[6]" alias="CYBSP_CSD_SLD3" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[8].pin[7]" alias="CYBSP_CSD_SLD4" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="peri[0].div_16[0]" alias="CYBSP_USB_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="1000"/>
-                    <Param id="fracDivider" value="0"/>
-                    <Param id="startOnReset" value="true"/>
-                </Block>
-                <Block location="peri[0].div_8[0]" alias="CYBSP_SDIO_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="1"/>
-                    <Param id="fracDivider" value="0"/>
-                    <Param id="startOnReset" value="true"/>
-                </Block>
-                <Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="8"/>
-                    <Param id="fracDivider" value="0"/>
-                    <Param id="startOnReset" value="true"/>
-                </Block>
-                <Block location="peri[0].div_8[2]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="109"/>
-                    <Param id="fracDivider" value="0"/>
-                    <Param id="startOnReset" value="true"/>
-                </Block>
-                <Block location="peri[0].div_8[3]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="256"/>
-                    <Param id="fracDivider" value="0"/>
-                    <Param id="startOnReset" value="true"/>
-                </Block>
-                <Block location="scb[2]" alias="CYBSP_BT_UART" template="mxs40uart" version="1.0">
-                    <Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
-                    <Param id="IrdaLowPower" value="false"/>
-                    <Param id="BaudRate" value="115200"/>
-                    <Param id="Oversample" value="8"/>
-                    <Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
-                    <Param id="DataWidth" value="8"/>
-                    <Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
-                    <Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
-                    <Param id="EnableInputFilter" value="false"/>
-                    <Param id="EnableTxEn" value="false"/>
-                    <Param id="FlowControl" value="true"/>
-                    <Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
-                    <Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
-                    <Param id="RtsTriggerLevel" value="63"/>
-                    <Param id="RxTriggerLevel" value="1"/>
-                    <Param id="TxTriggerLevel" value="63"/>
-                    <Param id="MultiProc" value="false"/>
-                    <Param id="MpRxAddress" value="0"/>
-                    <Param id="MpRxAddressMask" value="255"/>
-                    <Param id="MpRxAcceptAddress" value="false"/>
-                    <Param id="DropOnFrameErr" value="false"/>
-                    <Param id="DropOnParityErr" value="false"/>
-                    <Param id="BreakSignalBits" value="11"/>
-                    <Param id="SmCardRetryOnNack" value="false"/>
-                    <Param id="IrdaPolarity" value="NON_INVERTING"/>
-                    <Param id="inFlash" value="true"/>
-                    <Param id="ApiMode" value="HIGH_LEVEL"/>
-                    <Param id="IntrRxNotEmpty" value="false"/>
-                    <Param id="IntrRxFull" value="false"/>
-                    <Param id="IntrRxOverflow" value="false"/>
-                    <Param id="IntrRxUnderflow" value="false"/>
-                    <Param id="IntrRxFrameErr" value="false"/>
-                    <Param id="IntrRxParityErr" value="false"/>
-                    <Param id="IntrRxBreakDetected" value="false"/>
-                    <Param id="IntrRxTrigger" value="false"/>
-                    <Param id="IntrTxUartDone" value="false"/>
-                    <Param id="IntrTxUartLostArb" value="false"/>
-                    <Param id="IntrTxUartNack" value="false"/>
-                    <Param id="IntrTxEmpty" value="false"/>
-                    <Param id="IntrTxNotFull" value="false"/>
-                    <Param id="IntrTxOverflow" value="false"/>
-                    <Param id="IntrTxUnderflow" value="false"/>
-                    <Param id="IntrTxTrigger" value="false"/>
-                </Block>
-                <Block location="scb[3]" alias="CYBSP_CSD_COMM" template="mxs40ezi2c" version="1.0">
-                    <Param id="DataRate" value="100"/>
-                    <Param id="NumOfAddr" value="CY_SCB_EZI2C_ONE_ADDRESS"/>
-                    <Param id="SlaveAddress1" value="8"/>
-                    <Param id="SlaveAddress2" value="9"/>
-                    <Param id="SubAddrSize" value="CY_SCB_EZI2C_SUB_ADDR16_BITS"/>
-                    <Param id="EnableWakeup" value="false"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
-                    <Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
-                    <Param id="IrdaLowPower" value="false"/>
-                    <Param id="BaudRate" value="115200"/>
-                    <Param id="Oversample" value="8"/>
-                    <Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
-                    <Param id="DataWidth" value="8"/>
-                    <Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
-                    <Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
-                    <Param id="EnableInputFilter" value="false"/>
-                    <Param id="EnableTxEn" value="false"/>
-                    <Param id="FlowControl" value="false"/>
-                    <Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
-                    <Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
-                    <Param id="RtsTriggerLevel" value="63"/>
-                    <Param id="RxTriggerLevel" value="63"/>
-                    <Param id="TxTriggerLevel" value="63"/>
-                    <Param id="MultiProc" value="false"/>
-                    <Param id="MpRxAddress" value="0"/>
-                    <Param id="MpRxAddressMask" value="255"/>
-                    <Param id="MpRxAcceptAddress" value="false"/>
-                    <Param id="DropOnFrameErr" value="false"/>
-                    <Param id="DropOnParityErr" value="false"/>
-                    <Param id="BreakSignalBits" value="11"/>
-                    <Param id="SmCardRetryOnNack" value="false"/>
-                    <Param id="IrdaPolarity" value="NON_INVERTING"/>
-                    <Param id="inFlash" value="true"/>
-                    <Param id="ApiMode" value="HIGH_LEVEL"/>
-                    <Param id="IntrRxNotEmpty" value="false"/>
-                    <Param id="IntrRxFull" value="false"/>
-                    <Param id="IntrRxOverflow" value="false"/>
-                    <Param id="IntrRxUnderflow" value="false"/>
-                    <Param id="IntrRxFrameErr" value="false"/>
-                    <Param id="IntrRxParityErr" value="false"/>
-                    <Param id="IntrRxBreakDetected" value="false"/>
-                    <Param id="IntrRxTrigger" value="false"/>
-                    <Param id="IntrTxUartDone" value="false"/>
-                    <Param id="IntrTxUartLostArb" value="false"/>
-                    <Param id="IntrTxUartNack" value="false"/>
-                    <Param id="IntrTxEmpty" value="false"/>
-                    <Param id="IntrTxNotFull" value="false"/>
-                    <Param id="IntrTxOverflow" value="false"/>
-                    <Param id="IntrTxUnderflow" value="false"/>
-                    <Param id="IntrTxTrigger" value="false"/>
-                </Block>
-                <Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
-                    <Param id="configurator" value="0"/>
-                    <Param id="isrAlignment" value="false"/>
-                    <Param id="isrUnderflow" value="false"/>
-                    <Param id="isrCmdOverflow" value="false"/>
-                    <Param id="isrDataOverflow" value="false"/>
-                    <Param id="rxTriggerLevel" value="0"/>
-                    <Param id="txTriggerLevel" value="0"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="srss[0].clock[0]" alias="" template="mxs40sysclocks" version="1.2"/>
-                <Block location="srss[0].clock[0].altsystickclk[0]" alias="" template="mxs40altsystick" version="1.0">
-                    <Param id="sourceClock" value="lfclk"/>
-                </Block>
-                <Block location="srss[0].clock[0].bakclk[0]" alias="" template="mxs40bakclk" version="1.0">
-                    <Param id="sourceClock" value="wco"/>
-                </Block>
-                <Block location="srss[0].clock[0].fastclk[0]" alias="" template="mxs40fastclk" version="1.0">
-                    <Param id="divider" value="1"/>
-                </Block>
-                <Block location="srss[0].clock[0].fll[0]" alias="" template="mxs40fll" version="1.0">
-                    <Param id="configuration" value="auto"/>
-                    <Param id="desiredFrequency" value="100.000"/>
-                </Block>
-                <Block location="srss[0].clock[0].hfclk[0]" alias="" template="mxs40hfclk" version="1.1">
-                    <Param id="sourceClockNumber" value="0"/>
-                    <Param id="divider" value="1"/>
-                </Block>
-                <Block location="srss[0].clock[0].hfclk[1]" alias="" template="mxs40hfclk" version="1.1">
-                    <Param id="sourceClockNumber" value="1"/>
-                    <Param id="divider" value="1"/>
-                </Block>
-                <Block location="srss[0].clock[0].hfclk[2]" alias="" template="mxs40hfclk" version="1.1">
-                    <Param id="sourceClockNumber" value="0"/>
-                    <Param id="divider" value="2"/>
-                </Block>
-                <Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
-                    <Param id="sourceClockNumber" value="1"/>
-                    <Param id="divider" value="1"/>
-                </Block>
-                <Block location="srss[0].clock[0].ilo[0]" alias="" template="mxs40ilo" version="1.0">
-                    <Param id="hibernate" value="true"/>
-                </Block>
-                <Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
-                    <Param id="trim" value="0.25"/>
-                </Block>
-                <Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
-                    <Param id="sourceClock" value="wco"/>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[0]" alias="" template="mxs40pathmux" version="1.0">
-                    <Param id="sourceClock" value="imo"/>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[1]" alias="" template="mxs40pathmux" version="1.0">
-                    <Param id="sourceClock" value="imo"/>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[2]" alias="" template="mxs40pathmux" version="1.0">
-                    <Param id="sourceClock" value="imo"/>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[3]" alias="" template="mxs40pathmux" version="1.0">
-                    <Param id="sourceClock" value="imo"/>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[4]" alias="" template="mxs40pathmux" version="1.0">
-                    <Param id="sourceClock" value="imo"/>
-                </Block>
-                <Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
-                    <Param id="divider" value="1"/>
-                </Block>
-                <Block location="srss[0].clock[0].pll[0]" alias="" template="mxs40pll" version="1.0">
-                    <Param id="lowFrequencyMode" value="false"/>
-                    <Param id="configuration" value="auto"/>
-                    <Param id="desiredFrequency" value="48.000"/>
-                    <Param id="optimization" value="MinPower"/>
-                </Block>
-                <Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
-                    <Param id="divider" value="1"/>
-                </Block>
-                <Block location="srss[0].clock[0].timerclk[0]" alias="" template="mxs40timerclk" version="1.0">
-                    <Param id="sourceClock" value="imo"/>
-                    <Param id="timerDivider" value="1"/>
-                </Block>
-                <Block location="srss[0].clock[0].wco[0]" alias="" template="mxs40wco" version="1.0">
-                    <Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
-                    <Param id="clockLostDetection" value="false"/>
-                    <Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
-                    <Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
-                    <Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
-                    <Param id="accuracyPpm" value="150"/>
-                </Block>
-                <Block location="srss[0].mcwdt[0]" alias="CYBSP_MCWDT0" template="mxs40mcwdt" version="1.0">
-                    <Param id="C0ClearOnMatch" value="FREE_RUNNING"/>
-                    <Param id="C0Match" value="32768"/>
-                    <Param id="C0Mode" value="CY_MCWDT_MODE_NONE"/>
-                    <Param id="C1ClearOnMatch" value="FREE_RUNNING"/>
-                    <Param id="C1Match" value="32768"/>
-                    <Param id="C1Mode" value="CY_MCWDT_MODE_NONE"/>
-                    <Param id="C2Mode" value="CY_MCWDT_MODE_NONE"/>
-                    <Param id="C2Period" value="16"/>
-                    <Param id="CascadeC0C1" value="true"/>
-                    <Param id="CascadeC1C2" value="false"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
-                    <Param id="pwrEstimator" value="0"/>
-                    <Param id="pwrMode" value="LDO_1_1"/>
-                    <Param id="actPwrMode" value="LP"/>
-                    <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
-                    <Param id="pmicEnable" value="false"/>
-                    <Param id="backupSrc" value="VDDD"/>
-                    <Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
-                    <Param id="deepsleepLatency" value="0"/>
-                    <Param id="vddaMv" value="3300"/>
-                    <Param id="vdddMv" value="3300"/>
-                    <Param id="vBackupMv" value="3300"/>
-                    <Param id="vddNsMv" value="3300"/>
-                    <Param id="vddio0Mv" value="3300"/>
-                    <Param id="vddio1Mv" value="3300"/>
-                </Block>
-                <Block location="srss[0].rtc[0]" alias="CYBSP_RTC" template="mxs40rtc" version="1.1">
-                    <Param id="format" value="0"/>
-                    <Param id="dst" value="false"/>
-                    <Param id="dstFormat" value="CY_RTC_DST_RELATIVE"/>
-                    <Param id="sec" value="0"/>
-                    <Param id="min" value="0"/>
-                    <Param id="hrFormat" value="CY_RTC_24_HOURS"/>
-                    <Param id="hr" value="12"/>
-                    <Param id="amPmPeriodOfDay" value="CY_RTC_AM"/>
-                    <Param id="dayOfTheWeek" value="CY_RTC_SUNDAY"/>
-                    <Param id="dayOfTheMonth" value="1"/>
-                    <Param id="month" value="CY_RTC_JANUARY"/>
-                    <Param id="year" value="0"/>
-                    <Param id="dstStartMonth" value="CY_RTC_MARCH"/>
-                    <Param id="dstStartDay" value="22"/>
-                    <Param id="dstStartWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
-                    <Param id="dstStartDayOfWeek" value="CY_RTC_SUNDAY"/>
-                    <Param id="dstStartHour" value="0"/>
-                    <Param id="dstStopMonth" value="CY_RTC_OCTOBER"/>
-                    <Param id="dstStopDay" value="22"/>
-                    <Param id="dstStopWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
-                    <Param id="dstStopDayOfWeek" value="CY_RTC_SUNDAY"/>
-                    <Param id="dstStopHour" value="0"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="udb[0]" alias="CYBSP_SDIO" template="mxs40udbsdio" version="1.0"/>
-                <Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.0">
-                    <Param id="configurator" value="0"/>
-                    <Param id="UsbCore" value="4"/>
-                    <Param id="epMask" value="0"/>
-                    <Param id="bufSize" value="512"/>
-                    <Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
-                    <Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
-                    <Param id="enableLpm" value="false"/>
-                    <Param id="lpmIntr" value="0x0U"/>
-                    <Param id="ArbIntr" value="0x0U"/>
-                    <Param id="ep0CntrIntr" value="0x2U"/>
-                    <Param id="busResetIntr" value="0x2U"/>
-                    <Param id="sofIntr" value="0x1U"/>
-                    <Param id="ep0Intr" value="0x1U"/>
-                    <Param id="ep1Intr" value="0x1U"/>
-                    <Param id="ep2Intr" value="0x1U"/>
-                    <Param id="ep3Intr" value="0x1U"/>
-                    <Param id="ep4Intr" value="0x1U"/>
-                    <Param id="ep5Intr" value="0x1U"/>
-                    <Param id="ep6Intr" value="0x1U"/>
-                    <Param id="ep7Intr" value="0x1U"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-            </BlockConfig>
-            <Netlist>
-                <Net>
-                    <Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
-                    <Port name="ioss[0].port[6].pin[7].digital_in[0]"/>
-                </Net>
-                <Net>
-                    <Port name="cpuss[0].dap[0].swj_swdio_tms[0]"/>
-                    <Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
-                </Net>
-                <Net>
-                    <Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
-                    <Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
-                </Net>
-                <Net>
-                    <Port name="cpuss[0].dw0[0].chan[0].tr_in[0]"/>
-                    <Port name="udb[0].out_p[119]"/>
-                </Net>
-                <Net>
-                    <Port name="cpuss[0].dw0[0].chan[1].tr_in[0]"/>
-                    <Port name="udb[0].out_p[117]"/>
-                </Net>
-                <Net>
-                    <Port name="cpuss[0].dw1[0].chan[1].tr_in[0]"/>
-                    <Port name="udb[0].out_p[116]"/>
-                </Net>
-                <Net>
-                    <Port name="cpuss[0].dw1[0].chan[3].tr_in[0]"/>
-                    <Port name="udb[0].out_p[123]"/>
-                </Net>
-                <Net>
-                    <Port name="csd[0].csd[0].clock[0]"/>
-                    <Port name="peri[0].div_8[3].clk[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[0].pin[0].analog[0]"/>
-                    <Port name="srss[0].clock[0].wco[0].wco_in[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[0].pin[1].analog[0]"/>
-                    <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[0].digital_in[0]"/>
-                    <Port name="udb[0].in_p[48]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[0].digital_out[0]"/>
-                    <Port name="udb[0].port_if[16]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[0].oe[0]"/>
-                    <Port name="udb[0].port_oe[16]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[1].digital_in[0]"/>
-                    <Port name="udb[0].in_p[49]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[1].digital_out[0]"/>
-                    <Port name="udb[0].port_if[17]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[1].oe[0]"/>
-                    <Port name="udb[0].port_oe[17]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[2].digital_in[0]"/>
-                    <Port name="udb[0].in_p[50]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[2].digital_out[0]"/>
-                    <Port name="udb[0].port_if[18]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[2].oe[0]"/>
-                    <Port name="udb[0].port_oe[18]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[3].digital_in[0]"/>
-                    <Port name="udb[0].in_p[51]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[3].digital_out[0]"/>
-                    <Port name="udb[0].port_if[19]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[3].oe[0]"/>
-                    <Port name="udb[0].port_oe[19]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[4].digital_in[0]"/>
-                    <Port name="udb[0].in_p[52]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[4].digital_out[0]"/>
-                    <Port name="udb[0].port_if[20]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[4].oe[0]"/>
-                    <Port name="udb[0].port_oe[20]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[5].digital_out[0]"/>
-                    <Port name="udb[0].port_if[21]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[3].pin[0].digital_inout[0]"/>
-                    <Port name="scb[2].uart_rx[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[3].pin[1].digital_inout[0]"/>
-                    <Port name="scb[2].uart_tx[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[3].pin[2].digital_out[0]"/>
-                    <Port name="scb[2].uart_rts[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[3].pin[3].digital_in[0]"/>
-                    <Port name="scb[2].uart_cts[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
-                    <Port name="scb[5].uart_rx[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
-                    <Port name="scb[5].uart_tx[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
-                    <Port name="scb[3].i2c_scl[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[6].pin[1].digital_inout[0]"/>
-                    <Port name="scb[3].i2c_sda[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[11].pin[2].digital_out[0]"/>
-                    <Port name="smif[0].spi_select0[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[11].pin[3].digital_out[0]"/>
-                    <Port name="smif[0].spi_data3[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[11].pin[4].digital_out[0]"/>
-                    <Port name="smif[0].spi_data2[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[11].pin[5].digital_out[0]"/>
-                    <Port name="smif[0].spi_data1[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[11].pin[6].digital_out[0]"/>
-                    <Port name="smif[0].spi_data0[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
-                    <Port name="smif[0].spi_clk[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[14].pin[0].aux[0]"/>
-                    <Port name="usb[0].usb_dp_pad[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[14].pin[1].aux[0]"/>
-                    <Port name="usb[0].usb_dm_pad[0]"/>
-                </Net>
-                <Net>
-                    <Port name="peri[0].div_16[0].clk[0]"/>
-                    <Port name="usb[0].clock_dev_brs[0]"/>
-                </Net>
-                <Net>
-                    <Port name="peri[0].div_8[0].clk[0]"/>
-                    <Port name="udb[0].clocks[0]"/>
-                </Net>
-                <Net>
-                    <Port name="peri[0].div_8[1].clk[0]"/>
-                    <Port name="scb[3].clock[0]"/>
-                </Net>
-                <Net>
-                    <Port name="peri[0].div_8[2].clk[0]"/>
-                    <Port name="scb[2].clock[0]"/>
-                    <Port name="scb[5].clock[0]"/>
-                </Net>
-                <Net>
-                    <Port name="smif[0].clk_hf[0]"/>
-                    <Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
-                </Net>
-                <Net>
-                    <Port name="smif[0].clk_if[0]"/>
-                    <Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
-                </Net>
-                <Net>
-                    <Port name="srss[0].clock[0].hfclk[3].root_clk[0]"/>
-                    <Port name="usb[0].clk_usb_dev[0]"/>
-                </Net>
-                <Mux name="sense" location="csd[0].csd[0]">
-                    <Arm>
-                        <Port name="ioss[0].port[7].pin[7].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[7].pin[1].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[7].pin[2].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[1].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[2].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[3].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[4].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[5].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[6].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[7].analog[0]"/>
-                    </Arm>
-                </Mux>
-            </Netlist>
-        </Device>
-        <Device mpn="CYW4343WKUBG">
-            <BlockConfig/>
-            <Netlist/>
-        </Device>
-    </Devices>
-    <Libraries>
-        <Library name="psoc6sw" version="1.2"/>
-    </Libraries>
-    <ConfiguratorData/>
-</Design>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
deleted file mode 100644
index 0152835028f..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
+++ /dev/null
@@ -1,310 +0,0 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm0plus.scat
-;* \version 2.50
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2019 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    0x08047600
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation. 
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        .ANY (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0
-    { 
-        * (HEAP) 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
-    {
-        * (STACK)
-    }
-}
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    .cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S
deleted file mode 100644
index 536d029f52a..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S
+++ /dev/null
@@ -1,307 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_psoc6_01_cm0plus.S
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0plus Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-                IF :DEF:__STACK_SIZE
-Stack_Size      EQU     __STACK_SIZE
-                ELSE
-Stack_Size      EQU     0x00000400
-                ENDIF
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-                IF :DEF:__HEAP_SIZE
-Heap_Size       EQU     __HEAP_SIZE
-                ELSE
-Heap_Size       EQU     0x00000400
-                ENDIF
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-
-                DCD     0x0000000D                ; NMI Handler located at ROM code
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External interrupts                           Description
-                DCD     NvicMux0_IRQHandler                   ; CM0+ NVIC Mux input 0 
-                DCD     NvicMux1_IRQHandler                   ; CM0+ NVIC Mux input 1 
-                DCD     NvicMux2_IRQHandler                   ; CM0+ NVIC Mux input 2 
-                DCD     NvicMux3_IRQHandler                   ; CM0+ NVIC Mux input 3 
-                DCD     NvicMux4_IRQHandler                   ; CM0+ NVIC Mux input 4 
-                DCD     NvicMux5_IRQHandler                   ; CM0+ NVIC Mux input 5 
-                DCD     NvicMux6_IRQHandler                   ; CM0+ NVIC Mux input 6 
-                DCD     NvicMux7_IRQHandler                   ; CM0+ NVIC Mux input 7 
-                DCD     NvicMux8_IRQHandler                   ; CM0+ NVIC Mux input 8 
-                DCD     NvicMux9_IRQHandler                   ; CM0+ NVIC Mux input 9 
-                DCD     NvicMux10_IRQHandler                  ; CM0+ NVIC Mux input 10 
-                DCD     NvicMux11_IRQHandler                  ; CM0+ NVIC Mux input 11 
-                DCD     NvicMux12_IRQHandler                  ; CM0+ NVIC Mux input 12 
-                DCD     NvicMux13_IRQHandler                  ; CM0+ NVIC Mux input 13 
-                DCD     NvicMux14_IRQHandler                  ; CM0+ NVIC Mux input 14 
-                DCD     NvicMux15_IRQHandler                  ; CM0+ NVIC Mux input 15 
-                DCD     NvicMux16_IRQHandler                  ; CM0+ NVIC Mux input 16 
-                DCD     NvicMux17_IRQHandler                  ; CM0+ NVIC Mux input 17 
-                DCD     NvicMux18_IRQHandler                  ; CM0+ NVIC Mux input 18 
-                DCD     NvicMux19_IRQHandler                  ; CM0+ NVIC Mux input 19 
-                DCD     NvicMux20_IRQHandler                  ; CM0+ NVIC Mux input 20 
-                DCD     NvicMux21_IRQHandler                  ; CM0+ NVIC Mux input 21 
-                DCD     NvicMux22_IRQHandler                  ; CM0+ NVIC Mux input 22 
-                DCD     NvicMux23_IRQHandler                  ; CM0+ NVIC Mux input 23 
-                DCD     NvicMux24_IRQHandler                  ; CM0+ NVIC Mux input 24 
-                DCD     NvicMux25_IRQHandler                  ; CM0+ NVIC Mux input 25 
-                DCD     NvicMux26_IRQHandler                  ; CM0+ NVIC Mux input 26 
-                DCD     NvicMux27_IRQHandler                  ; CM0+ NVIC Mux input 27 
-                DCD     NvicMux28_IRQHandler                  ; CM0+ NVIC Mux input 28 
-                DCD     NvicMux29_IRQHandler                  ; CM0+ NVIC Mux input 29 
-                DCD     NvicMux30_IRQHandler                  ; CM0+ NVIC Mux input 30 
-                DCD     NvicMux31_IRQHandler                  ; CM0+ NVIC Mux input 31 
-
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-                EXPORT __ramVectors
-                AREA    RESET_RAM, READWRITE, NOINIT
-__ramVectors    SPACE   __Vectors_Size
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Weak function for startup customization
-;
-; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
-; because this function is executed as the first instruction in the ResetHandler.
-; The PDL is also not initialized to use the proper register offsets.
-; The user of this function is responsible for initializing the PDL and resources before using them.
-;
-Cy_OnResetUser  PROC
-                EXPORT  Cy_OnResetUser            [WEAK]
-                BX      LR
-                ENDP
-
-; Reset Handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-
-                ; Define strong function for startup customization
-                BL      Cy_OnResetUser
-
-                ; Copy vectors from ROM to RAM
-                LDR r1, =__Vectors
-                LDR r0, =__ramVectors
-                LDR r2, =__Vectors_Size
-Vectors_Copy
-                LDR r3, [r1]
-                STR r3, [r0]
-                ADDS r0, r0, #4
-                ADDS r1, r1, #4
-                SUBS r2, r2, #1
-                CMP r2, #0
-                BNE Vectors_Copy
-
-                ; Update Vector Table Offset Register. */
-                LDR r0, =__ramVectors
-                LDR r1, =0xE000ED08
-                STR r0, [r1]
-                dsb 0xF
-
-                LDR     R0, =__main
-                BLX     R0
-
-                ; Should never get here
-                B       .
-
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-NMI_Handler         PROC
-                    EXPORT  NMI_Handler               [WEAK]
-                    B       .
-                    ENDP
-
-Cy_SysLib_FaultHandler PROC
-                    EXPORT  Cy_SysLib_FaultHandler    [WEAK]
-                    B       .
-                    ENDP
-
-HardFault_Handler   PROC
-                    EXPORT HardFault_Handler          [WEAK]
-                    movs r0, #4
-                    mov r1, LR
-                    tst r0, r1
-                    beq L_MSP
-                    mrs r0, PSP
-                    bl L_API_call
-L_MSP
-                    mrs r0, MSP
-L_API_call
-                    bl Cy_SysLib_FaultHandler
-                    ENDP
-
-SVC_Handler         PROC
-                    EXPORT  SVC_Handler               [WEAK]
-                    B       .
-                    ENDP
-PendSV_Handler      PROC
-                    EXPORT  PendSV_Handler            [WEAK]
-                    B       .
-                    ENDP
-SysTick_Handler     PROC
-                    EXPORT  SysTick_Handler           [WEAK]
-                    B       .
-                    ENDP
-
-Default_Handler     PROC
-                    EXPORT  Default_Handler                       [WEAK]
-                    EXPORT  NvicMux0_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux1_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux2_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux3_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux4_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux5_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux6_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux7_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux8_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux9_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux10_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux11_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux12_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux13_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux14_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux15_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux16_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux17_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux18_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux19_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux20_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux21_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux22_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux23_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux24_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux25_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux26_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux27_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux28_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux29_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux30_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux31_IRQHandler                  [WEAK]
-
-NvicMux0_IRQHandler
-NvicMux1_IRQHandler
-NvicMux2_IRQHandler
-NvicMux3_IRQHandler
-NvicMux4_IRQHandler
-NvicMux5_IRQHandler
-NvicMux6_IRQHandler
-NvicMux7_IRQHandler
-NvicMux8_IRQHandler
-NvicMux9_IRQHandler
-NvicMux10_IRQHandler
-NvicMux11_IRQHandler
-NvicMux12_IRQHandler
-NvicMux13_IRQHandler
-NvicMux14_IRQHandler
-NvicMux15_IRQHandler
-NvicMux16_IRQHandler
-NvicMux17_IRQHandler
-NvicMux18_IRQHandler
-NvicMux19_IRQHandler
-NvicMux20_IRQHandler
-NvicMux21_IRQHandler
-NvicMux22_IRQHandler
-NvicMux23_IRQHandler
-NvicMux24_IRQHandler
-NvicMux25_IRQHandler
-NvicMux26_IRQHandler
-NvicMux27_IRQHandler
-NvicMux28_IRQHandler
-NvicMux29_IRQHandler
-NvicMux30_IRQHandler
-NvicMux31_IRQHandler
-
-                B       .
-                ENDP
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT __use_two_region_memory
-
-                ALIGN
-
-                ENDIF
-
-                END
-
-
-; [] END OF FILE
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
deleted file mode 100644
index 45285e64c3a..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
+++ /dev/null
@@ -1,468 +0,0 @@
-/***************************************************************************//**
-* \file cy8c6xx7_cm0plus.ld
-* \version 2.50
-*
-* Linker file for the GNU C compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point location is fixed and starts at 0x10000000. The valid
-* application image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-ENTRY(Reset_Handler)
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-/* MBED_APP_START is being  used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_START
-* is equal to MBED_ROM_START
-*/
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-/* MBED_APP_SIZE is being  used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-* is equal to MBED_ROM_SIZE
-*/
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    0x08047600
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-    #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-STACK_SIZE = MBED_BOOT_STACK_SIZE;
-
-/* Force symbol to be entered in the output file as an undefined symbol. Doing
-* this may, for example, trigger linking of additional modules from standard
-* libraries. You may list several symbols for each EXTERN, and you may use
-* EXTERN multiple times. This command has the same effect as the -u command-line
-* option.
-*/
-EXTERN(Reset_Handler)
-
-/* The MEMORY section below describes the location and size of blocks of memory in the target.
-* Use this section to specify the memory regions available for allocation.
-*/
-MEMORY
-{
-    /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
-     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
-     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-     * Using this memory region for other purposes will lead to unexpected behavior.
-     * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
-     * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
-     */
-    ram               (rwx)   : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
-    public_ram        (rw)    : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE
-    flash             (rx)    : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000)
-
-    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
-     * You can assign sections to this memory region for only one of the cores.
-     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-     * Therefore, repurposing this memory region will prevent such middleware from operation.
-     */
-    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
-
-    /* The following regions define device specific memory regions and must not be changed. */
-    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
-    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
-    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
-    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
-    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
-    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
-    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-
-
-SECTIONS
-{
-    .cy_app_header :
-    {
-        KEEP(*(.cy_app_header))
-    } > flash
-
-    .text :
-    {
-        . = ALIGN(4);
-        __Vectors = . ;
-        KEEP(*(.vectors))
-        . = ALIGN(4);
-        __Vectors_End = .;
-        __Vectors_Size = __Vectors_End - __Vectors;
-        __end__ = .;
-
-        . = ALIGN(4);
-        *(.text*)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        /* Read-only code (constants). */
-        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
-
-        KEEP(*(.eh_frame*))
-    } > flash
-
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    __exidx_start = .;
-
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > flash
-    __exidx_end = .;
-
-
-    /* To copy multiple ROM to RAM sections,
-     * uncomment .copy.table section and,
-     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */
-    .copy.table :
-    {
-        . = ALIGN(4);
-        __copy_table_start__ = .;
-
-        /* Copy interrupt vectors from flash to RAM */
-        LONG (__Vectors)                                    /* From */
-        LONG (__ram_vectors_start__)                        /* To   */
-        LONG (__Vectors_End - __Vectors)                    /* Size */
-
-        /* Copy data section to RAM */
-        LONG (__etext)                                      /* From */
-        LONG (__data_start__)                               /* To   */
-        LONG (__data_end__ - __data_start__)                /* Size */
-
-        __copy_table_end__ = .;
-    } > flash
-
-
-    /* To clear multiple BSS sections,
-     * uncomment .zero.table section and,
-     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */
-    .zero.table :
-    {
-        . = ALIGN(4);
-        __zero_table_start__ = .;
-        LONG (__bss_start__)
-        LONG (__bss_end__ - __bss_start__)
-        __zero_table_end__ = .;
-    } > flash
-
-    __etext =  . ;
-
-
-    .ramVectors (NOLOAD) : ALIGN(8)
-    {
-        __ram_vectors_start__ = .;
-        KEEP(*(.ram_vectors))
-        __ram_vectors_end__   = .;
-    } > ram
-
-
-    .data __ram_vectors_end__ : AT (__etext)
-    {
-        __data_start__ = .;
-
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-
-        KEEP(*(.cy_ramfunc*))
-        . = ALIGN(4);
-
-        __data_end__ = .;
-
-    } > ram
-
-
-    /* Place variables in the section that should not be initialized during the
-    *  device startup.
-    */
-    .noinit (NOLOAD) : ALIGN(8)
-    {
-      KEEP(*(.noinit))
-    } > ram
-
-
-    /* The uninitialized global or static variables are placed in this section.
-    *
-    * The NOLOAD attribute tells linker that .bss section does not consume
-    * any space in the image. The NOLOAD attribute changes the .bss type to
-    * NOBITS, and that  makes linker to A) not allocate section in memory, and
-    * A) put information to clear the section with all zeros during application
-    * loading.
-    *
-    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
-    * This  makes linker to A) allocate zeroed section in memory, and B) copy
-    * this section to RAM during application loading.
-    */
-    .bss (NOLOAD):
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram
-
-
-    .heap (NOLOAD):
-    {
-        __HeapBase = .;
-        __end__ = .;
-        end = __end__;
-        KEEP(*(.heap*))
-        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
-        __HeapLimit = .;
-    } > ram
-
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (NOLOAD):
-    {
-        KEEP(*(.stack*))
-    } > ram
-
-
-    /* Public RAM */
-    .cy_sharedmem (NOLOAD):
-    {
-        . = ALIGN(4);
-        KEEP(*(.cy_sharedmem))
-    } > public_ram
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(ram) + LENGTH(ram);
-        __StackLimit = __StackTop - STACK_SIZE;
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-
-
-    /* Emulated EEPROM Flash area */
-    .cy_em_eeprom :
-    {
-        KEEP(*(.cy_em_eeprom))
-    } > em_eeprom
-
-
-    /* Supervisory Flash: User data */
-    .cy_sflash_user_data :
-    {
-        KEEP(*(.cy_sflash_user_data))
-    } > sflash_user_data
-
-
-    /* Supervisory Flash: Normal Access Restrictions (NAR) */
-    .cy_sflash_nar :
-    {
-        KEEP(*(.cy_sflash_nar))
-    } > sflash_nar
-
-
-    /* Supervisory Flash: Public Key */
-    .cy_sflash_public_key :
-    {
-        KEEP(*(.cy_sflash_public_key))
-    } > sflash_public_key
-
-
-    /* Supervisory Flash: Table of Content # 2 */
-    .cy_toc_part2 :
-    {
-        KEEP(*(.cy_toc_part2))
-    } > sflash_toc_2
-
-    
-    /* Supervisory Flash: Table of Content # 2 Copy */
-    .cy_rtoc_part2 :
-    {
-        KEEP(*(.cy_rtoc_part2))
-    } > sflash_rtoc_2
-
-
-    /* Places the code in the Execute in Place (XIP) section. See the smif driver
-    *  documentation for details.
-    */
-    .cy_xip :
-    {
-        KEEP(*(.cy_xip))
-    } > xip
-
-
-    /* eFuse */
-    .cy_efuse :
-    {
-        KEEP(*(.cy_efuse))
-    } > efuse
-
-
-    /* These sections are used for additional metadata (silicon revision,
-    *  Silicon/JTAG ID, etc.) storage.
-    */
-    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
-}
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-__cy_memory_0_start    = 0x10000000;
-__cy_memory_0_length   = 0x00100000;
-__cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-__cy_memory_1_start    = 0x14000000;
-__cy_memory_1_length   = 0x8000;
-__cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-__cy_memory_2_start    = 0x16000000;
-__cy_memory_2_length   = 0x8000;
-__cy_memory_2_row_size = 0x200;
-
-/* XIP */
-__cy_memory_3_start    = 0x18000000;
-__cy_memory_3_length   = 0x08000000;
-__cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-__cy_memory_4_start    = 0x90700000;
-__cy_memory_4_length   = 0x100000;
-__cy_memory_4_row_size = 1;
-
-/* EOF */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S
deleted file mode 100644
index b46556a8a7a..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S
+++ /dev/null
@@ -1,399 +0,0 @@
-/**************************************************************************//**
- * @file     startup_psoc6_01_cm0plus.S
- * @brief    CMSIS Core Device Startup File for
- *           ARMCM0plus Device Series
- * @version  V5.00
- * @date     02. March 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-    /* Address of the NMI handler */
-    #define CY_NMI_HANLDER_ADDR         0x0000000D
-
-    /* The CPU VTOR register */
-    #define CY_CPU_VTOR_ADDR            0xE000ED08
-
-    /* Copy flash vectors and data section to RAM */
-    #define __STARTUP_COPY_MULTIPLE
-
-    /* Clear single BSS section */
-    #define __STARTUP_CLEAR_BSS
-
-    .syntax    unified
-    .arch    armv6-m
-
-    .section .stack
-    .align    3
-#ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
-#else
-    .equ    Stack_Size, 0x00001000
-#endif
-    .globl    __StackTop
-    .globl    __StackLimit
-__StackLimit:
-    .space    Stack_Size
-    .size    __StackLimit, . - __StackLimit
-__StackTop:
-    .size    __StackTop, . - __StackTop
-
-    .section .heap
-    .align    3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0x00000400
-#endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
-__HeapBase:
-    .if    Heap_Size
-    .space    Heap_Size
-    .endif
-    .size    __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size    __HeapLimit, . - __HeapLimit
-
-    .section .vectors
-    .align 2
-    .globl    __Vectors
-__Vectors:
-    .long    __StackTop            /* Top of Stack */
-    .long    Reset_Handler         /* Reset Handler */
-    .long    CY_NMI_HANLDER_ADDR   /* NMI Handler */
-    .long    HardFault_Handler     /* Hard Fault Handler */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    SVC_Handler           /* SVCall Handler */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    PendSV_Handler        /* PendSV Handler */
-    .long    SysTick_Handler       /* SysTick Handler */
-
-     /* External interrupts                             Description */
-    .long    NvicMux0_IRQHandler                     /* CM0+ NVIC Mux input 0 */
-    .long    NvicMux1_IRQHandler                     /* CM0+ NVIC Mux input 1 */
-    .long    NvicMux2_IRQHandler                     /* CM0+ NVIC Mux input 2 */
-    .long    NvicMux3_IRQHandler                     /* CM0+ NVIC Mux input 3 */
-    .long    NvicMux4_IRQHandler                     /* CM0+ NVIC Mux input 4 */
-    .long    NvicMux5_IRQHandler                     /* CM0+ NVIC Mux input 5 */
-    .long    NvicMux6_IRQHandler                     /* CM0+ NVIC Mux input 6 */
-    .long    NvicMux7_IRQHandler                     /* CM0+ NVIC Mux input 7 */
-    .long    NvicMux8_IRQHandler                     /* CM0+ NVIC Mux input 8 */
-    .long    NvicMux9_IRQHandler                     /* CM0+ NVIC Mux input 9 */
-    .long    NvicMux10_IRQHandler                    /* CM0+ NVIC Mux input 10 */
-    .long    NvicMux11_IRQHandler                    /* CM0+ NVIC Mux input 11 */
-    .long    NvicMux12_IRQHandler                    /* CM0+ NVIC Mux input 12 */
-    .long    NvicMux13_IRQHandler                    /* CM0+ NVIC Mux input 13 */
-    .long    NvicMux14_IRQHandler                    /* CM0+ NVIC Mux input 14 */
-    .long    NvicMux15_IRQHandler                    /* CM0+ NVIC Mux input 15 */
-    .long    NvicMux16_IRQHandler                    /* CM0+ NVIC Mux input 16 */
-    .long    NvicMux17_IRQHandler                    /* CM0+ NVIC Mux input 17 */
-    .long    NvicMux18_IRQHandler                    /* CM0+ NVIC Mux input 18 */
-    .long    NvicMux19_IRQHandler                    /* CM0+ NVIC Mux input 19 */
-    .long    NvicMux20_IRQHandler                    /* CM0+ NVIC Mux input 20 */
-    .long    NvicMux21_IRQHandler                    /* CM0+ NVIC Mux input 21 */
-    .long    NvicMux22_IRQHandler                    /* CM0+ NVIC Mux input 22 */
-    .long    NvicMux23_IRQHandler                    /* CM0+ NVIC Mux input 23 */
-    .long    NvicMux24_IRQHandler                    /* CM0+ NVIC Mux input 24 */
-    .long    NvicMux25_IRQHandler                    /* CM0+ NVIC Mux input 25 */
-    .long    NvicMux26_IRQHandler                    /* CM0+ NVIC Mux input 26 */
-    .long    NvicMux27_IRQHandler                    /* CM0+ NVIC Mux input 27 */
-    .long    NvicMux28_IRQHandler                    /* CM0+ NVIC Mux input 28 */
-    .long    NvicMux29_IRQHandler                    /* CM0+ NVIC Mux input 29 */
-    .long    NvicMux30_IRQHandler                    /* CM0+ NVIC Mux input 30 */
-    .long    NvicMux31_IRQHandler                    /* CM0+ NVIC Mux input 31 */
-
-    .size    __Vectors, . - __Vectors
-    .equ    __VectorsSize, . - __Vectors
-
-    .section .ram_vectors
-    .align 2
-    .globl __ramVectors
-__ramVectors:
-    .space  __VectorsSize
-    .size   __ramVectors, . - __ramVectors
-
-
-    .text
-    .thumb
-    .thumb_func
-    .align  2
-
-    /* 
-     * Device startup customization 
-     *
-     * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
-     * because this function is executed as the first instruction in the ResetHandler.
-     * The PDL is also not initialized to use the proper register offsets.
-     * The user of this function is responsible for initializing the PDL and resources before using them.
-     */
-    .weak   Cy_OnResetUser
-    .func   Cy_OnResetUser, Cy_OnResetUser
-    .type   Cy_OnResetUser, %function
-
-Cy_OnResetUser:
-    bx lr
-    .size   Cy_OnResetUser, . - Cy_OnResetUser
-    .endfunc
-
-    /* Reset handler */
-    .weak    Reset_Handler
-    .type    Reset_Handler, %function
-
-Reset_Handler:
-    bl Cy_OnResetUser
-
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r4, =__copy_table_start__
-    ldr    r5, =__copy_table_end__
-
-.L_loop0:
-    cmp    r4, r5
-    bge    .L_loop0_done
-    ldr    r1, [r4]
-    ldr    r2, [r4, #4]
-    ldr    r3, [r4, #8]
-
-.L_loop0_0:
-    subs    r3, #4
-    blt    .L_loop0_0_done
-    ldr    r0, [r1, r3]
-    str    r0, [r2, r3]
-    b    .L_loop0_0
-
-.L_loop0_0_done:
-    adds    r4, #12
-    b    .L_loop0
-
-.L_loop0_done:
-#else
-/*  Single section scheme.
- *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r1, =__etext
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
-
-    subs    r3, r2
-    ble    .L_loop1_done
-
-.L_loop1:
-    subs    r3, #4
-    ldr    r0, [r1,r3]
-    str    r0, [r2,r3]
-    bgt    .L_loop1
-
-.L_loop1_done:
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
- *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
- *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
- */
-    ldr    r3, =__zero_table_start__
-    ldr    r4, =__zero_table_end__
-
-.L_loop2:
-    cmp    r3, r4
-    bge    .L_loop2_done
-    ldr    r1, [r3]
-    ldr    r2, [r3, #4]
-    movs    r0, 0
-
-.L_loop2_0:
-    subs    r2, #4
-    blt    .L_loop2_0_done
-    str    r0, [r1, r2]
-    b    .L_loop2_0
-.L_loop2_0_done:
-
-    adds    r3, #8
-    b    .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
- *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
- *
- *  Both addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r1, =__bss_start__
-    ldr    r2, =__bss_end__
-
-    movs    r0, 0
-
-    subs    r2, r1
-    ble    .L_loop3_done
-
-.L_loop3:
-    subs    r2, #4
-    str    r0, [r1, r2]
-    bgt    .L_loop3
-.L_loop3_done:
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
-    /* Update Vector Table Offset Register. */
-    ldr r0, =__ramVectors
-    ldr r1, =CY_CPU_VTOR_ADDR
-    str r0, [r1]
-    dsb 0xF
-
-    bl  _start
-
-    /* Should never get here */
-    b   .
-
-    .pool
-    .size    Reset_Handler, . - Reset_Handler
-
-    .align    1
-    .thumb_func
-    .weak    Default_Handler
-    .type    Default_Handler, %function
-Default_Handler:
-    b    .
-    .size    Default_Handler, . - Default_Handler
-    .weak    Cy_SysLib_FaultHandler
-    .type    Cy_SysLib_FaultHandler, %function
-
-Cy_SysLib_FaultHandler:
-    b    .
-    .size    Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
-    .type Fault_Handler, %function
-
-Fault_Handler:
-    /* Storing LR content for Creator call stack trace */
-    push {LR}
-    movs r0, #4
-    mov r1, LR
-    tst r0, r1
-    beq .L_MSP
-    mrs r0, PSP
-    b .L_API_call
-.L_MSP:
-    mrs r0, MSP
-.L_API_call:
-    /* Compensation of stack pointer address due to pushing 4 bytes of LR */
-    adds r0, r0, #4
-    bl Cy_SysLib_FaultHandler
-    b   .
-    .size    Fault_Handler, . - Fault_Handler
-
-.macro    def_fault_Handler    fault_handler_name
-    .weak    \fault_handler_name
-    .set    \fault_handler_name, Fault_Handler
-    .endm
-
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-    .macro    def_irq_handler    handler_name
-    .weak    \handler_name
-    .set    \handler_name, Default_Handler
-    .endm
-
-    def_irq_handler    NMI_Handler
-
-    def_fault_Handler  HardFault_Handler
-
-    def_irq_handler    SVC_Handler
-    def_irq_handler    PendSV_Handler
-    def_irq_handler    SysTick_Handler
-
-    def_irq_handler  NvicMux0_IRQHandler                     /* CM0+ NVIC Mux input 0 */
-    def_irq_handler  NvicMux1_IRQHandler                     /* CM0+ NVIC Mux input 1 */
-    def_irq_handler  NvicMux2_IRQHandler                     /* CM0+ NVIC Mux input 2 */
-    def_irq_handler  NvicMux3_IRQHandler                     /* CM0+ NVIC Mux input 3 */
-    def_irq_handler  NvicMux4_IRQHandler                     /* CM0+ NVIC Mux input 4 */
-    def_irq_handler  NvicMux5_IRQHandler                     /* CM0+ NVIC Mux input 5 */
-    def_irq_handler  NvicMux6_IRQHandler                     /* CM0+ NVIC Mux input 6 */
-    def_irq_handler  NvicMux7_IRQHandler                     /* CM0+ NVIC Mux input 7 */
-    def_irq_handler  NvicMux8_IRQHandler                     /* CM0+ NVIC Mux input 8 */
-    def_irq_handler  NvicMux9_IRQHandler                     /* CM0+ NVIC Mux input 9 */
-    def_irq_handler  NvicMux10_IRQHandler                    /* CM0+ NVIC Mux input 10 */
-    def_irq_handler  NvicMux11_IRQHandler                    /* CM0+ NVIC Mux input 11 */
-    def_irq_handler  NvicMux12_IRQHandler                    /* CM0+ NVIC Mux input 12 */
-    def_irq_handler  NvicMux13_IRQHandler                    /* CM0+ NVIC Mux input 13 */
-    def_irq_handler  NvicMux14_IRQHandler                    /* CM0+ NVIC Mux input 14 */
-    def_irq_handler  NvicMux15_IRQHandler                    /* CM0+ NVIC Mux input 15 */
-    def_irq_handler  NvicMux16_IRQHandler                    /* CM0+ NVIC Mux input 16 */
-    def_irq_handler  NvicMux17_IRQHandler                    /* CM0+ NVIC Mux input 17 */
-    def_irq_handler  NvicMux18_IRQHandler                    /* CM0+ NVIC Mux input 18 */
-    def_irq_handler  NvicMux19_IRQHandler                    /* CM0+ NVIC Mux input 19 */
-    def_irq_handler  NvicMux20_IRQHandler                    /* CM0+ NVIC Mux input 20 */
-    def_irq_handler  NvicMux21_IRQHandler                    /* CM0+ NVIC Mux input 21 */
-    def_irq_handler  NvicMux22_IRQHandler                    /* CM0+ NVIC Mux input 22 */
-    def_irq_handler  NvicMux23_IRQHandler                    /* CM0+ NVIC Mux input 23 */
-    def_irq_handler  NvicMux24_IRQHandler                    /* CM0+ NVIC Mux input 24 */
-    def_irq_handler  NvicMux25_IRQHandler                    /* CM0+ NVIC Mux input 25 */
-    def_irq_handler  NvicMux26_IRQHandler                    /* CM0+ NVIC Mux input 26 */
-    def_irq_handler  NvicMux27_IRQHandler                    /* CM0+ NVIC Mux input 27 */
-    def_irq_handler  NvicMux28_IRQHandler                    /* CM0+ NVIC Mux input 28 */
-    def_irq_handler  NvicMux29_IRQHandler                    /* CM0+ NVIC Mux input 29 */
-    def_irq_handler  NvicMux30_IRQHandler                    /* CM0+ NVIC Mux input 30 */
-    def_irq_handler  NvicMux31_IRQHandler                    /* CM0+ NVIC Mux input 31 */
-
-    .end
-
-
-/* [] END OF FILE */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
deleted file mode 100644
index dc77b4ce238..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
+++ /dev/null
@@ -1,287 +0,0 @@
-/***************************************************************************//**
-* \file cy8c6xx7_cm0plus.icf
-* \version 2.50
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-if (!isdefinedsymbol(MBED_ROM_START)) {
-  define symbol MBED_ROM_START = 0x10000000;
-}
-
-/* MBED_APP_START is being  used by the bootloader build script and
- * will be calculate by the system. Without bootloader the MBED_APP_START
- * is equal to MBED_ROM_START
- */
-if (!isdefinedsymbol(MBED_APP_START)) {
-  define symbol MBED_APP_START = MBED_ROM_START;
-}
-
-if (!isdefinedsymbol(MBED_ROM_SIZE)) {
-  define symbol MBED_ROM_SIZE = 0x80000;
-}
-
-/* MBED_APP_SIZE is being  used by the bootloader build script and
- * will be calculate by the system. Without bootloader the MBED_APP_SIZE
- * is equal to MBED_ROM_SIZE
- */
-if (!isdefinedsymbol(MBED_APP_SIZE)) {
-  define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
-}
-
-if (!isdefinedsymbol(MBED_RAM_START)) {
-  define symbol MBED_RAM_START = 0x08000000;
-}
-
-if (!isdefinedsymbol(MBED_RAM_SIZE)) {
-  define symbol MBED_RAM_SIZE = 0x00010000;
-}
-
-if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) {
-  define symbol MBED_PUBLIC_RAM_START = 0x08047600;
-}
-
-if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) {
-  define symbol MBED_PUBLIC_RAM_SIZE = 0x200;
-}
-
-if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
-    define symbol MBED_BOOT_STACK_SIZE = 0x400;
-}
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM0+ core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
-define symbol __ICFEDIT_region_IRAM1_end__   = (MBED_RAM_START + MBED_RAM_SIZE);
-/* Public RAM */
-define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START;
-define symbol __ICFEDIT_region_IRAM2_end__   = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE);
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
-define symbol __ICFEDIT_region_IROM1_end__   = (MBED_APP_START + MBED_APP_SIZE - 0x8000);
-
-/* The following symbols define a 32K flash region used for EEPROM emulation. 
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__   = 0x160007FF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-
-
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
-  define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
-} else {
-  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x400;
-} else {
-  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
-
-define block RAM_DATA {readwrite section .data};
-define block RAM_OTHER {readwrite section * };
-define block RAM_NOINIT {readwrite section .noinit};
-define block RAM_BSS {readwrite section .bss};
-define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};
-define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block RO     {first section .intvec, readonly};
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize  { section .noinit, section .intvec_ram };
-
-
-/*-Placement-*/
-
-/* Flash */
-".cy_app_header" : place at start of IROM1_region  { section .cy_app_header };
-place in          IROM1_region  { block RO };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-".cy_xip" : place at start of EROM1_region  { section .cy_xip };
-
-/* RAM */
-place at start of IRAM1_region  { readwrite section .intvec_ram};
-place in IRAM1_region  { block RAM};
-place in IRAM1_region  { readwrite section .cy_ramfunc };
-place at end   of IRAM1_region  { block HSTACK };
-
-/* Public RAM */
-place at start of IRAM2_region  { section .cy_sharedmem };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep {  section .cy_app_header,
-        section .cy_em_eeprom,
-        section .cy_sflash_user_data,
-        section .cy_sflash_nar,
-        section .cy_sflash_public_key,
-        section .cy_toc_part2,
-        section .cy_rtoc_part2,
-        section .cy_efuse,
-        section .cy_xip,
-        section .cymeta,
-         };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start    = 0x10000000;
-define exported symbol __cy_memory_0_length   = 0x00100000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start    = 0x14000000;
-define exported symbol __cy_memory_1_length   = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start    = 0x16000000;
-define exported symbol __cy_memory_2_length   = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start    = 0x18000000;
-define exported symbol __cy_memory_3_length   = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start    = 0x90700000;
-define exported symbol __cy_memory_4_length   = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S
deleted file mode 100644
index e926966cf7e..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S
+++ /dev/null
@@ -1,413 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_psoc6_01_cm0plus.S
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0plus Device Series
-; * @version  V5.00
-; * @date     08. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-        SECTION .intvec_ram:DATA:NOROOT(2)
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        EXTERN __iar_data_init3
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
-        PUBLIC  __ramVectors
-
-        DATA
-
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     0x0000000D      ; NMI_Handler is defined in ROM code
-        DCD     HardFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
-__vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     0
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External interrupts                           Description
-        DCD     NvicMux0_IRQHandler                   ; CM0+ NVIC Mux input 0
-        DCD     NvicMux1_IRQHandler                   ; CM0+ NVIC Mux input 1
-        DCD     NvicMux2_IRQHandler                   ; CM0+ NVIC Mux input 2
-        DCD     NvicMux3_IRQHandler                   ; CM0+ NVIC Mux input 3
-        DCD     NvicMux4_IRQHandler                   ; CM0+ NVIC Mux input 4
-        DCD     NvicMux5_IRQHandler                   ; CM0+ NVIC Mux input 5
-        DCD     NvicMux6_IRQHandler                   ; CM0+ NVIC Mux input 6
-        DCD     NvicMux7_IRQHandler                   ; CM0+ NVIC Mux input 7
-        DCD     NvicMux8_IRQHandler                   ; CM0+ NVIC Mux input 8
-        DCD     NvicMux9_IRQHandler                   ; CM0+ NVIC Mux input 9
-        DCD     NvicMux10_IRQHandler                  ; CM0+ NVIC Mux input 10
-        DCD     NvicMux11_IRQHandler                  ; CM0+ NVIC Mux input 11
-        DCD     NvicMux12_IRQHandler                  ; CM0+ NVIC Mux input 12
-        DCD     NvicMux13_IRQHandler                  ; CM0+ NVIC Mux input 13
-        DCD     NvicMux14_IRQHandler                  ; CM0+ NVIC Mux input 14
-        DCD     NvicMux15_IRQHandler                  ; CM0+ NVIC Mux input 15
-        DCD     NvicMux16_IRQHandler                  ; CM0+ NVIC Mux input 16
-        DCD     NvicMux17_IRQHandler                  ; CM0+ NVIC Mux input 17
-        DCD     NvicMux18_IRQHandler                  ; CM0+ NVIC Mux input 18
-        DCD     NvicMux19_IRQHandler                  ; CM0+ NVIC Mux input 19
-        DCD     NvicMux20_IRQHandler                  ; CM0+ NVIC Mux input 20
-        DCD     NvicMux21_IRQHandler                  ; CM0+ NVIC Mux input 21
-        DCD     NvicMux22_IRQHandler                  ; CM0+ NVIC Mux input 22
-        DCD     NvicMux23_IRQHandler                  ; CM0+ NVIC Mux input 23
-        DCD     NvicMux24_IRQHandler                  ; CM0+ NVIC Mux input 24
-        DCD     NvicMux25_IRQHandler                  ; CM0+ NVIC Mux input 25
-        DCD     NvicMux26_IRQHandler                  ; CM0+ NVIC Mux input 26
-        DCD     NvicMux27_IRQHandler                  ; CM0+ NVIC Mux input 27
-        DCD     NvicMux28_IRQHandler                  ; CM0+ NVIC Mux input 28
-        DCD     NvicMux29_IRQHandler                  ; CM0+ NVIC Mux input 29
-        DCD     NvicMux30_IRQHandler                  ; CM0+ NVIC Mux input 30
-        DCD     NvicMux31_IRQHandler                  ; CM0+ NVIC Mux input 31
-
-__Vectors_End
-
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
-
-        SECTION .intvec_ram:DATA:REORDER:NOROOT(2)
-__ramVectors
-        DS32     __Vectors_Size
-
-
-        THUMB
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default handlers
-;;
-        PUBWEAK Default_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Default_Handler
-        B Default_Handler
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Weak function for startup customization
-;;
-;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
-;; because this function is executed as the first instruction in the ResetHandler.
-;; The PDL is also not initialized to use the proper register offsets.
-;; The user of this function is responsible for initializing the PDL and resources before using them.
-;;
-        PUBWEAK Cy_OnResetUser
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Cy_OnResetUser
-        BX LR
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Define strong version to return zero for
-;; __iar_program_start to skip data sections
-;; initialization.
-;;
-        PUBLIC __low_level_init
-        SECTION .text:CODE:REORDER:NOROOT(2)
-__low_level_init
-        MOVS R0, #0
-        BX LR
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        ; Define strong function for startup customization
-        LDR     R0, =Cy_OnResetUser
-        BLX     R0
-
-        ; Copy vectors from ROM to RAM
-        LDR r1, =__vector_table
-        LDR r0, =__ramVectors
-        LDR r2, =__Vectors_Size
-intvec_copy
-        LDR r3, [r1]
-        STR r3, [r0]
-        ADDS r0, r0, #4
-        ADDS r1, r1, #4
-        SUBS r2, r2, #1
-        CMP r2, #0
-        BNE intvec_copy
-
-        ; Update Vector Table Offset Register
-        LDR r0, =__ramVectors
-        LDR r1, =0xE000ED08
-        STR r0, [r1]
-        dsb
-
-        LDR     R0, =__iar_program_start
-        BLX     R0
-
-; Should never get here
-Cy_Main_Exited
-        B Cy_Main_Exited
-
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-
-        PUBWEAK Cy_SysLib_FaultHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Cy_SysLib_FaultHandler
-        B Cy_SysLib_FaultHandler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        IMPORT Cy_SysLib_FaultHandler
-        movs r0, #4
-        mov r1, LR
-        tst r0, r1
-        beq L_MSP
-        mrs r0, PSP
-        b L_API_call
-L_MSP
-        mrs r0, MSP
-L_API_call
-        ; Storing LR content for Creator call stack trace
-        push {LR}
-        bl Cy_SysLib_FaultHandler
-
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-
-        ; External interrupts
-        PUBWEAK NvicMux0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux0_IRQHandler
-        B       NvicMux0_IRQHandler
-
-        PUBWEAK NvicMux1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux1_IRQHandler
-        B       NvicMux1_IRQHandler
-
-        PUBWEAK NvicMux2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux2_IRQHandler
-        B       NvicMux2_IRQHandler
-
-        PUBWEAK NvicMux3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux3_IRQHandler
-        B       NvicMux3_IRQHandler
-
-        PUBWEAK NvicMux4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux4_IRQHandler
-        B       NvicMux4_IRQHandler
-
-        PUBWEAK NvicMux5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux5_IRQHandler
-        B       NvicMux5_IRQHandler
-
-        PUBWEAK NvicMux6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux6_IRQHandler
-        B       NvicMux6_IRQHandler
-
-        PUBWEAK NvicMux7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux7_IRQHandler
-        B       NvicMux7_IRQHandler
-
-        PUBWEAK NvicMux8_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux8_IRQHandler
-        B       NvicMux8_IRQHandler
-
-        PUBWEAK NvicMux9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux9_IRQHandler
-        B       NvicMux9_IRQHandler
-
-        PUBWEAK NvicMux10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux10_IRQHandler
-        B       NvicMux10_IRQHandler
-
-        PUBWEAK NvicMux11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux11_IRQHandler
-        B       NvicMux11_IRQHandler
-
-        PUBWEAK NvicMux12_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux12_IRQHandler
-        B       NvicMux12_IRQHandler
-
-        PUBWEAK NvicMux13_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux13_IRQHandler
-        B       NvicMux13_IRQHandler
-
-        PUBWEAK NvicMux14_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux14_IRQHandler
-        B       NvicMux14_IRQHandler
-
-        PUBWEAK NvicMux15_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux15_IRQHandler
-        B       NvicMux15_IRQHandler
-
-        PUBWEAK NvicMux16_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux16_IRQHandler
-        B       NvicMux16_IRQHandler
-
-        PUBWEAK NvicMux17_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux17_IRQHandler
-        B       NvicMux17_IRQHandler
-
-        PUBWEAK NvicMux18_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux18_IRQHandler
-        B       NvicMux18_IRQHandler
-
-        PUBWEAK NvicMux19_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux19_IRQHandler
-        B       NvicMux19_IRQHandler
-
-        PUBWEAK NvicMux20_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux20_IRQHandler
-        B       NvicMux20_IRQHandler
-
-        PUBWEAK NvicMux21_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux21_IRQHandler
-        B       NvicMux21_IRQHandler
-
-        PUBWEAK NvicMux22_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux22_IRQHandler
-        B       NvicMux22_IRQHandler
-
-        PUBWEAK NvicMux23_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux23_IRQHandler
-        B       NvicMux23_IRQHandler
-
-        PUBWEAK NvicMux24_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux24_IRQHandler
-        B       NvicMux24_IRQHandler
-
-        PUBWEAK NvicMux25_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux25_IRQHandler
-        B       NvicMux25_IRQHandler
-
-        PUBWEAK NvicMux26_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux26_IRQHandler
-        B       NvicMux26_IRQHandler
-
-        PUBWEAK NvicMux27_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux27_IRQHandler
-        B       NvicMux27_IRQHandler
-
-        PUBWEAK NvicMux28_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux28_IRQHandler
-        B       NvicMux28_IRQHandler
-
-        PUBWEAK NvicMux29_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux29_IRQHandler
-        B       NvicMux29_IRQHandler
-
-        PUBWEAK NvicMux30_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux30_IRQHandler
-        B       NvicMux30_IRQHandler
-
-        PUBWEAK NvicMux31_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux31_IRQHandler
-        B       NvicMux31_IRQHandler
-
-
-        END
-
-
-; [] END OF FILE
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c
deleted file mode 100644
index 010eac6188e..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c
+++ /dev/null
@@ -1,710 +0,0 @@
-/***************************************************************************//**
-* \file system_psoc6_cm0plus.c
-* \version 2.50
-*
-* The device system-source file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#include <stdbool.h>
-#include "system_psoc6.h"
-#include "cy_device.h"
-#include "cy_device_headers.h"
-#include "cy_syslib.h"
-#include "cy_wdt.h"
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-    #include "cy_ipc_sema.h"
-    #include "cy_ipc_pipe.h"
-    #include "cy_ipc_drv.h"
-
-    #if defined(CY_DEVICE_PSOC6ABLE2)
-        #include "cy_flash.h"
-    #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
-
-#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
-
-
-/*******************************************************************************
-* SystemCoreClockUpdate()
-*******************************************************************************/
-
-/** Default HFClk frequency in Hz */
-#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT       (8000000UL)
-
-/** Default PeriClk frequency in Hz */
-#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT      (4000000UL)
-
-/** Default SlowClk system core frequency in Hz */
-#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT       (4000000UL)
-
-/** IMO frequency in Hz */
-#define CY_CLK_IMO_FREQ_HZ                  (8000000UL)
-
-/** HVILO frequency in Hz */
-#define CY_CLK_HVILO_FREQ_HZ                (32000UL)
-
-/** PILO frequency in Hz */
-#define CY_CLK_PILO_FREQ_HZ                 (32768UL)
-
-/** WCO frequency in Hz */
-#define CY_CLK_WCO_FREQ_HZ                  (32768UL)
-
-/** ALTLF frequency in Hz */
-#define CY_CLK_ALTLF_FREQ_HZ                (32768UL)
-
-
-/**
-* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
-* which is the system clock frequency supplied to the SysTick timer and the
-* processor core clock.
-* This variable implements CMSIS Core global variable.
-* Refer to the [CMSIS documentation]
-* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
-* for more details.
-* This variable can be used by debuggers to query the frequency
-* of the debug timer or to configure the trace clock speed.
-*
-* \attention Compilers must be configured to avoid removing this variable in case
-* the application program is not using it. Debugging systems require the variable
-* to be physically present in memory so that it can be examined to configure the debugger. */
-uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
-
-/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
-uint32_t cy_Hfclk0FreqHz  = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
-
-/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
-uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
-
-/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
-#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
-    uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
-#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
-
-
-/*******************************************************************************
-* SystemInit()
-*******************************************************************************/
-
-/* CLK_FLL_CONFIG default values */
-#define CY_FB_CLK_FLL_CONFIG_VALUE      (0x01000000u)
-#define CY_FB_CLK_FLL_CONFIG2_VALUE     (0x00020001u)
-#define CY_FB_CLK_FLL_CONFIG3_VALUE     (0x00002800u)
-#define CY_FB_CLK_FLL_CONFIG4_VALUE     (0x000000FFu)
-
-
-/*******************************************************************************
-* SystemCoreClockUpdate (void)
-*******************************************************************************/
-
-/* Do not use these definitions directly in your application */
-#define CY_DELAY_MS_OVERFLOW_THRESHOLD  (0x8000u)
-#define CY_DELAY_1K_THRESHOLD           (1000u)
-#define CY_DELAY_1K_MINUS_1_THRESHOLD   (CY_DELAY_1K_THRESHOLD - 1u)
-#define CY_DELAY_1M_THRESHOLD           (1000000u)
-#define CY_DELAY_1M_MINUS_1_THRESHOLD   (CY_DELAY_1M_THRESHOLD - 1u)
-uint32_t cy_delayFreqHz   = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
-
-uint32_t cy_delayFreqKhz  = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
-                            CY_DELAY_1K_THRESHOLD;
-
-uint8_t cy_delayFreqMhz  = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
-                            CY_DELAY_1M_THRESHOLD);
-
-uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
-                            ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
-
-#define CY_ROOT_PATH_SRC_IMO                (0UL)
-#define CY_ROOT_PATH_SRC_EXT                (1UL)
-#if (SRSS_ECO_PRESENT == 1U)
-    #define CY_ROOT_PATH_SRC_ECO            (2UL)
-#endif /* (SRSS_ECO_PRESENT == 1U) */
-#if (SRSS_ALTHF_PRESENT == 1U)
-    #define CY_ROOT_PATH_SRC_ALTHF          (3UL)
-#endif /* (SRSS_ALTHF_PRESENT == 1U) */
-#define CY_ROOT_PATH_SRC_DSI_MUX            (4UL)
-#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO      (16UL)
-#define CY_ROOT_PATH_SRC_DSI_MUX_WCO        (17UL)
-#if (SRSS_ALTLF_PRESENT == 1U)
-    #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF  (18UL)
-#endif /* (SRSS_ALTLF_PRESENT == 1U) */
-#if (SRSS_PILO_PRESENT == 1U)
-    #define CY_ROOT_PATH_SRC_DSI_MUX_PILO   (19UL)
-#endif /* (SRSS_PILO_PRESENT == 1U) */
-
-
-/*******************************************************************************
-* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
-*******************************************************************************/
-#define CY_SYS_CM4_PWR_CTL_KEY_OPEN  (0x05FAUL)
-#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
-#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR  (0x000003FFUL)
-
-
-/*******************************************************************************
-* Function Name: SystemInit
-****************************************************************************//**
-*
-* Initializes the system:
-* - Restores FLL registers to the default state.
-* - Unlocks and disables WDT.
-* - Calls Cy_PDL_Init() function to define the driver library.
-* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
-* - Calls \ref SystemCoreClockUpdate().
-*
-*******************************************************************************/
-void SystemInit(void)
-{
-    Cy_PDL_Init(CY_DEVICE_CFG);
-
-    /* Restore FLL registers to the default state as they are not restored by the ROM code */
-    uint32_t copy = SRSS->CLK_FLL_CONFIG;
-    copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
-    SRSS->CLK_FLL_CONFIG = copy;
-
-    copy = SRSS->CLK_ROOT_SELECT[0u];
-    copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
-    SRSS->CLK_ROOT_SELECT[0u] = copy;
-
-    SRSS->CLK_FLL_CONFIG  = CY_FB_CLK_FLL_CONFIG_VALUE;
-    SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
-    SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
-    SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
-
-    /* Unlock and disable WDT */
-    Cy_WDT_Unlock();
-    Cy_WDT_Disable();
-
-    Cy_SystemInit();
-    SystemCoreClockUpdate();
-
-#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
-    if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
-    {
-        /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
-        IPC_STRUCT7->DATA = 0UL;
-        /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
-        IPC_STRUCT7->RELEASE = 0UL;
-    }
-#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-    /* Allocate and initialize semaphores for the system operations. */
-    CY_SECTION(".cy_sharedmem")
-    static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
-
-    (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
-
-
-    /********************************************************************************
-    *
-    * Initializes the system pipes. The system pipes are used by BLE and Flash.
-    *
-    * If the default startup file is not used, or SystemInit() is not called in your
-    * project, call the following three functions prior to executing any flash or
-    * EmEEPROM write or erase operation:
-    *  -# Cy_IPC_Sema_Init()
-    *  -# Cy_IPC_Pipe_Config()
-    *  -# Cy_IPC_Pipe_Init()
-    *  -# Cy_Flash_Init()
-    *
-    *******************************************************************************/
-
-    /* Create an array of endpoint structures */
-    static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
-
-    Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
-
-    static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
-
-    static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
-    {
-    /* .ep0ConfigData */
-        {
-            /* .ipcNotifierNumber    */  CY_IPC_INTR_CYPIPE_EP0,
-            /* .ipcNotifierPriority  */  CY_SYS_INTR_CYPIPE_PRIOR_EP0,
-            /* .ipcNotifierMuxNumber */  CY_SYS_INTR_CYPIPE_MUX_EP0,
-            /* .epAddress            */  CY_IPC_EP_CYPIPE_CM0_ADDR,
-            /* .epConfig             */  CY_SYS_CYPIPE_CONFIG_EP0
-        },
-    /* .ep1ConfigData */
-        {
-            /* .ipcNotifierNumber    */  CY_IPC_INTR_CYPIPE_EP1,
-            /* .ipcNotifierPriority  */  CY_SYS_INTR_CYPIPE_PRIOR_EP1,
-            /* .ipcNotifierMuxNumber */  0u,
-            /* .epAddress            */  CY_IPC_EP_CYPIPE_CM4_ADDR,
-            /* .epConfig             */  CY_SYS_CYPIPE_CONFIG_EP1
-        },
-    /* .endpointClientsCount     */  CY_SYS_CYPIPE_CLIENT_CNT,
-    /* .endpointsCallbacksArray  */  systemIpcPipeSysCbArray,
-    /* .userPipeIsrHandler       */  &Cy_SysIpcPipeIsrCm0
-    };
-
-    if (cy_device->flashPipeRequired != 0u)
-    {
-        Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
-    }
-
-#if defined(CY_DEVICE_PSOC6ABLE2)
-    Cy_Flash_Init();
-#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
-
-#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SystemInit
-****************************************************************************//**
-*
-* The function is called during device startup. Once project compiled as part of
-* the PSoC Creator project, the Cy_SystemInit() function is generated by the
-* PSoC Creator.
-*
-* The function generated by PSoC Creator performs all of the necessary device
-* configuration based on the design settings.  This includes settings from the
-* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
-* configuration that is necessary.
-*
-*******************************************************************************/
-__WEAK void Cy_SystemInit(void)
-{
-     /* Empty weak function. The actual implementation to be in the PSoC Creator
-      * generated strong function.
-     */
-}
-
-
-/*******************************************************************************
-* Function Name: SystemCoreClockUpdate
-****************************************************************************//**
-*
-* Gets core clock frequency and updates \ref SystemCoreClock, \ref
-* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
-*
-* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
-* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
-*
-*******************************************************************************/
-void SystemCoreClockUpdate (void)
-{
-    uint32_t srcFreqHz;
-    uint32_t pathFreqHz;
-    uint32_t slowClkDiv;
-    uint32_t periClkDiv;
-    uint32_t rootPath;
-    uint32_t srcClk;
-
-    /* Get root path clock for the high-frequency clock # 0 */
-    rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
-
-    /* Get source of the root path clock */
-    srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
-
-    /* Get frequency of the source */
-    switch (srcClk)
-    {
-    case CY_ROOT_PATH_SRC_IMO:
-        srcFreqHz = CY_CLK_IMO_FREQ_HZ;
-    break;
-
-    case CY_ROOT_PATH_SRC_EXT:
-        srcFreqHz = CY_CLK_EXT_FREQ_HZ;
-    break;
-
-    #if (SRSS_ECO_PRESENT == 1U)
-        case CY_ROOT_PATH_SRC_ECO:
-            srcFreqHz = CY_CLK_ECO_FREQ_HZ;
-        break;
-    #endif /* (SRSS_ECO_PRESENT == 1U) */
-
-#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
-    case CY_ROOT_PATH_SRC_ALTHF:
-        srcFreqHz = cy_BleEcoClockFreqHz;
-    break;
-#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
-
-    case CY_ROOT_PATH_SRC_DSI_MUX:
-    {
-        uint32_t dsi_src;
-        dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX,  SRSS->CLK_DSI_SELECT[rootPath]);
-        switch (dsi_src)
-        {
-        case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
-            srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
-        break;
-
-        case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
-            srcFreqHz = CY_CLK_WCO_FREQ_HZ;
-        break;
-
-        #if (SRSS_ALTLF_PRESENT == 1U)
-            case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
-                srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
-            break;
-        #endif /* (SRSS_ALTLF_PRESENT == 1U) */
-
-        #if (SRSS_PILO_PRESENT == 1U)
-            case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
-                srcFreqHz = CY_CLK_PILO_FREQ_HZ;
-            break;
-        #endif /* (SRSS_PILO_PRESENT == 1U) */
-
-        default:
-            srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
-        break;
-        }
-    }
-    break;
-
-    default:
-        srcFreqHz = CY_CLK_EXT_FREQ_HZ;
-    break;
-    }
-
-    if (rootPath == 0UL)
-    {
-        /* FLL */
-        bool fllLocked       = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
-        bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
-        bool fllOutputAuto   = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
-                                (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
-        if ((fllOutputAuto && fllLocked) || fllOutputOutput)
-        {
-            uint32_t fllMult;
-            uint32_t refDiv;
-            uint32_t outputDiv;
-
-            fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
-            refDiv  = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
-            outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
-
-            pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
-        }
-        else
-        {
-            pathFreqHz = srcFreqHz;
-        }
-    }
-    else if ((rootPath == 1UL) || (rootPath == 2UL))
-    {
-        /* PLL */
-        bool pllLocked       = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED,     SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
-        bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
-        bool pllOutputAuto   = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
-                                (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
-        if ((pllOutputAuto && pllLocked) || pllOutputOutput)
-        {
-            uint32_t feedbackDiv;
-            uint32_t referenceDiv;
-            uint32_t outputDiv;
-
-            feedbackDiv  = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV,  SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
-            referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
-            outputDiv    = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV,    SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
-
-            pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
-
-        }
-        else
-        {
-            pathFreqHz = srcFreqHz;
-        }
-    }
-    else
-    {
-        /* Direct */
-        pathFreqHz = srcFreqHz;
-    }
-
-    /* Get frequency after hf_clk pre-divider */
-    pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
-    cy_Hfclk0FreqHz = pathFreqHz;
-
-    /* Slow Clock Divider */
-    slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL);
-
-    /* Peripheral Clock Divider */
-    periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
-
-    pathFreqHz = pathFreqHz / periClkDiv;
-    cy_PeriClkFreqHz = pathFreqHz;
-    pathFreqHz = pathFreqHz / slowClkDiv;
-    SystemCoreClock = pathFreqHz;
-
-    /* Sets clock frequency for Delay API */
-    cy_delayFreqHz = SystemCoreClock;
-    cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
-    cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
-    cy_delay32kMs   = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
-}
-
-
-#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
-/*******************************************************************************
-* Function Name: Cy_SysGetCM4Status
-****************************************************************************//**
-*
-* Returns the Cortex-M4 core power mode.
-*
-* \return \ref group_system_config_cm4_status_macro
-*
-*******************************************************************************/
-uint32_t Cy_SysGetCM4Status(void)
-{
-    uint32_t regValue;
-
-    /* Get current power mode */
-    regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
-
-    return (regValue);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysEnableCM4
-****************************************************************************//**
-*
-* Sets vector table base address and enables the Cortex-M4 core.
-*
-* \note If the CPU is already enabled, it is reset and then enabled.
-*
-* \param vectorTableOffset The offset of the vector table base address from
-* memory address 0x00000000. The offset should be multiple to 1024 bytes.
-*
-*******************************************************************************/
-void Cy_SysEnableCM4(uint32_t vectorTableOffset)
-{
-    uint32_t regValue;
-    uint32_t interruptState;
-    uint32_t cpuState;
-
-    CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    cpuState = Cy_SysGetCM4Status();
-    if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
-    {
-        Cy_SysResetCM4();
-    }
-
-    CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_ENABLED;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
-    {
-        /* Wait for the power mode to take effect */
-    }
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysDisableCM4
-****************************************************************************//**
-*
-* Disables the Cortex-M4 core and waits for the mode to take the effect.
-*
-* \warning Do not call the function while the Cortex-M4 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
-* CPU.
-*
-*******************************************************************************/
-void Cy_SysDisableCM4(void)
-{
-    uint32_t interruptState;
-    uint32_t regValue;
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_DISABLED;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
-    {
-        /* Wait for the power mode to take effect */
-    }
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysRetainCM4
-****************************************************************************//**
-*
-* Retains the Cortex-M4 core and exists without waiting for the mode to take
-* effect.
-*
-* \note The retained mode can be entered only from the enabled mode.
-*
-* \warning Do not call the function while the Cortex-M4 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
-*
-*******************************************************************************/
-void Cy_SysRetainCM4(void)
-{
-    uint32_t interruptState;
-    uint32_t regValue;
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_RETAINED;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysResetCM4
-****************************************************************************//**
-*
-* Resets the Cortex-M4 core and waits for the mode to take the effect.
-*
-* \note The reset mode can not be entered from the retained mode.
-*
-* \warning Do not call the function while the Cortex-M4 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
-*
-*******************************************************************************/
-void Cy_SysResetCM4(void)
-{
-    uint32_t interruptState;
-    uint32_t regValue;
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_RESET;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
-    {
-        /* Wait for the power mode to take effect */
-    }
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-/*******************************************************************************
-* Function Name: Cy_SysIpcPipeIsrCm0
-****************************************************************************//**
-*
-* This is the interrupt service routine for the system pipe.
-*
-*******************************************************************************/
-void Cy_SysIpcPipeIsrCm0(void)
-{
-    Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR);
-}
-#endif
-
-
-/*******************************************************************************
-* Function Name: Cy_MemorySymbols
-****************************************************************************//**
-*
-* The intention of the function is to declare boundaries of the memories for the
-* MDK compilers. For the rest of the supported compilers, this is done using
-* linker configuration files. The following symbols used by the cymcuelftool.
-*
-*******************************************************************************/
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
-__asm void Cy_MemorySymbols(void)
-{
-    /* Flash */
-    EXPORT __cy_memory_0_start
-    EXPORT __cy_memory_0_length
-    EXPORT __cy_memory_0_row_size
-
-    /* Working Flash */
-    EXPORT __cy_memory_1_start
-    EXPORT __cy_memory_1_length
-    EXPORT __cy_memory_1_row_size
-
-    /* Supervisory Flash */
-    EXPORT __cy_memory_2_start
-    EXPORT __cy_memory_2_length
-    EXPORT __cy_memory_2_row_size
-
-    /* XIP */
-    EXPORT __cy_memory_3_start
-    EXPORT __cy_memory_3_length
-    EXPORT __cy_memory_3_row_size
-
-    /* eFuse */
-    EXPORT __cy_memory_4_start
-    EXPORT __cy_memory_4_length
-    EXPORT __cy_memory_4_row_size
-
-    /* Flash */
-__cy_memory_0_start     EQU __cpp(CY_FLASH_BASE)
-__cy_memory_0_length    EQU __cpp(CY_FLASH_SIZE)
-__cy_memory_0_row_size  EQU 0x200
-
-    /* Flash region for EEPROM emulation */
-__cy_memory_1_start     EQU __cpp(CY_EM_EEPROM_BASE)
-__cy_memory_1_length    EQU __cpp(CY_EM_EEPROM_SIZE)
-__cy_memory_1_row_size  EQU 0x200
-
-    /* Supervisory Flash */
-__cy_memory_2_start     EQU __cpp(CY_SFLASH_BASE)
-__cy_memory_2_length    EQU __cpp(CY_SFLASH_SIZE)
-__cy_memory_2_row_size  EQU 0x200
-
-    /* XIP */
-__cy_memory_3_start     EQU __cpp(CY_XIP_BASE)
-__cy_memory_3_length    EQU __cpp(CY_XIP_SIZE)
-__cy_memory_3_row_size  EQU 0x200
-
-    /* eFuse */
-__cy_memory_4_start     EQU __cpp(0x90700000)
-__cy_memory_4_length    EQU __cpp(0x100000)
-__cy_memory_4_row_size  EQU __cpp(1)
-}
-#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
-
-
-/* [] END OF FILE */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
similarity index 94%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
index a23e6e13f61..32e78ff05af 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
@@ -3,7 +3,7 @@
 ; to pass a scatter file through a C preprocessor.
 
 ;*******************************************************************************
-;* \file cy8c6xx7_cm4_dual.scat
+;* \file cy8c6xx7_cm4_dual.sct
 ;* \version 2.50
 ;*
 ;* Linker file for the ARMCC.
@@ -78,6 +78,7 @@
   #define MBED_BOOT_STACK_SIZE 0x400
 #endif
 
+; Size of the stack section at the end of CM4 SRAM
 #define STACK_SIZE MBED_BOOT_STACK_SIZE
 
 ; The defines below describe the location and size of blocks of memory in the target.
@@ -96,6 +97,9 @@
 #define FLASH_START             MBED_APP_START
 #define FLASH_SIZE              MBED_APP_SIZE
 
+; Size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
 ; The following defines describe a 32K flash region used for EEPROM emulation.
 ; This region can also be used as the general purpose flash.
 ; You can assign sections to this memory region for only one of the cores.
@@ -133,17 +137,9 @@
 #define EFUSE_START             0x90700000
 #define EFUSE_SIZE              0x100000
 
-; Size and start address of the Cortex-M0+ application image
-#define FLASH_CM0P_SIZE         0x2000
-#define FLASH_CM0P_START        FLASH_START
-
-; Size and start address of the Cortex-M4 application image
-#define FLASH_CM4_SIZE          (FLASH_SIZE - FLASH_CM0P_SIZE)
-#define FLASH_CM4_START         (FLASH_CM0P_START + FLASH_CM0P_SIZE)
-
 
-; Cortex-M0+ application image
-LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
 {
     .cy_m0p_image +0 FLASH_CM0P_SIZE
     {
@@ -151,8 +147,8 @@ LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
     }
 }
 
-; Cortex-M4 application image
-LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
 {
     ER_FLASH_VECTORS +0
     {
@@ -173,7 +169,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
     RW_RAM_DATA +0
     {
         * (.cy_ramfunc)
-        .ANY (+RW, +ZI)
+        * (+RW, +ZI)
     }
 
     ; Place variables in the section that should not be initialized during the
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
similarity index 96%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
index 0cfd336d6ec..a2e3f35a65e 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
@@ -76,8 +76,12 @@ ENTRY(Reset_Handler)
     #define MBED_BOOT_STACK_SIZE 0x400
 #endif
 
+/* Size of the stack section at the end of CM4 SRAM */
 STACK_SIZE = MBED_BOOT_STACK_SIZE;
 
+/* Size of the Cortex-M0+ application image at the start of FLASH */
+FLASH_CM0P_SIZE  = 0x2000;
+
 /* Force symbol to be entered in the output file as an undefined symbol. Doing
 * this may, for example, trigger linking of additional modules from standard
 * libraries. You may list several symbols for each EXTERN, and you may use
@@ -118,13 +122,6 @@ MEMORY
     efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
 }
 
-/* Size and start address of the Cortex-M0+ application image */
-FLASH_CM0P_SIZE  = 0x2000;
-FLASH_CM0P_START = ORIGIN(flash);
-/* Size and start address of the Cortex-M4 application image */
-FLASH_CM4_SIZE   = LENGTH(flash) - FLASH_CM0P_SIZE;
-FLASH_CM4_START  = FLASH_CM0P_START + FLASH_CM0P_SIZE;
-
 /* Library configurations */
 GROUP(libgcc.a libc.a libm.a libnosys.a)
 
@@ -164,8 +161,8 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
 
 SECTIONS
 {
-     /* Cortex-M0+ application image */
-    .cy_m0p_image FLASH_CM0P_START :
+     /* Cortex-M0+ application flash image area */
+    .cy_m0p_image ORIGIN(flash) :
     {
         . = ALIGN(4);
         __cy_m0p_code_start = . ;
@@ -173,8 +170,11 @@ SECTIONS
         __cy_m0p_code_end = . ;
     } > flash
 
-    /* Cortex-M4 application image */
-    .text FLASH_CM4_START :
+    /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
+    ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
+
+    /* Cortex-M4 application flash area */
+    .text ORIGIN(flash) + FLASH_CM0P_SIZE :
     {
         . = ALIGN(4);
         __Vectors = . ;
@@ -290,7 +290,6 @@ SECTIONS
         KEEP(*(.init_array))
         PROVIDE_HIDDEN (__init_array_end = .);
 
-
         . = ALIGN(4);
         /* finit data */
         PROVIDE_HIDDEN (__fini_array_start = .);
@@ -351,7 +350,7 @@ SECTIONS
         __HeapLimit = .;
     } > ram
 
-    
+
     /* Set stack top to end of RAM, and stack limit move down by
      * size of stack_dummy section */
     __StackTop = ORIGIN(ram) + LENGTH(ram);
@@ -404,7 +403,7 @@ SECTIONS
         KEEP(*(.cy_toc_part2))
     } > sflash_toc_2
 
-    
+
     /* Supervisory Flash: Table of Content # 2 Copy */
     .cy_rtoc_part2 :
     {
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
similarity index 98%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
index 1fd2e3e5783..1f3e2aa9ef5 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
@@ -156,7 +156,7 @@ if (!isdefinedsymbol(__STACK_SIZE)) {
 
 /* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
 if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x400;
+    define symbol __ICFEDIT_size_heap__ = 0x0400;
 } else {
   define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
 }
@@ -198,8 +198,10 @@ do not initialize  { section .noinit, section .intvec_ram };
 /* Flash - Cortex-M0+ application image */
 place at start of IROM1_region  { block CM0P_RO };
 
-/* Flash - Cortex-M4 application image */
+/* Flash - Cortex-M4 application */
 place in          IROM1_region  { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
 ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
 
 /* Emulated EEPROM Flash area */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
similarity index 99%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
index 75747c4face..f4ca47b4579 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
@@ -310,10 +310,6 @@ intvec_copy
         STR r0, [r1]
         dsb
 
-        ; Enable the FPU if used
-        LDR     R0, =Cy_SystemInitFpuEnable
-        BLX     R0
-
         ; Initialize data sections
         LDR     R0, =__iar_data_init3
         BLX     R0
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6_cm4.c
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6_cm4.c
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralPins.c
index b6c226f5327..e42fe6998bc 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralPins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralPins.c
@@ -124,7 +124,9 @@ const PinMap PinMap_I2C_SCL[] = {
     {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
     {P5_4, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_4_SCB10_I2C_SCL)},
     {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
+    {P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
     {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
+    {P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
     {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
     {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
     {P8_4, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_4_SCB11_I2C_SCL)},
@@ -146,7 +148,9 @@ const PinMap PinMap_I2C_SDA[] = {
     {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
     {P5_5, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_5_SCB10_I2C_SDA)},
     {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
+    {P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
     {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
+    {P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
     {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
     {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
     {P8_5, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_5_SCB11_I2C_SDA)},
@@ -170,7 +174,9 @@ const PinMap PinMap_SPI_MOSI[] = {
     {P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)},
     {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
     {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
+    {P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
     {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
+    {P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
     {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
     {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
     {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
@@ -188,7 +194,9 @@ const PinMap PinMap_SPI_MISO[] = {
     {P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)},
     {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
     {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
+    {P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
     {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
+    {P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
     {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
     {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
     {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
@@ -205,7 +213,9 @@ const PinMap PinMap_SPI_SCLK[] = {
     {P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)},
     {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
     {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
+    {P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
     {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
+    {P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
     {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
     {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
     {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
@@ -222,7 +232,9 @@ const PinMap PinMap_SPI_SSEL[] = {
     {P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)},
     {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
     {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
+    {P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
     {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
+    {P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
     {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
     {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
     {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
@@ -445,30 +457,23 @@ const PinMap PinMap_PWM_OUT[] = {
 
 #if DEVICE_ANALOGIN
 const PinMap PinMap_ADC[] = {
-    {P9_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},  // The SAR ADC Vplus input connects to the P9_0 pin through the AMUXA bus
-    {P9_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},  // The SAR ADC Vplus input connects to the P9_1 pin through the AMUXA bus
-    {P9_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},  // The SAR ADC Vplus input connects to the P9_2 pin through the AMUXA bus
-    {P9_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},  // The SAR ADC Vplus input connects to the P9_4 pin through the AMUXA bus
-    {P9_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},  // The SAR ADC Vplus input connects to the P9_5 pin through the AMUXA bus
-    {P9_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},  // The SAR ADC Vplus input connects to the P9_6 pin through the AMUXA bus
-    {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_0 pin
-    {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_1 pin
-    {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_2 pin
-    {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_3 pin
-    {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_4 pin
-    {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_5 pin
-    {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_6 pin
-    {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_7 pin
+    {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
     {NC,    NC,     0}
 };
 #endif // DEVICE_ANALOGIN
 
 #if DEVICE_QSPI
-const PinMap PinMap_QSPI_SCLK[] = {          // does not use PERI clock, uses HFCLK2
+const PinMap PinMap_QSPI_SCLK[] = {
     {P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
-    {NC,    NC,    0}
+    {NC, NC, 0},
 };
-
 const PinMap PinMap_QSPI_SSEL[] = {
     {P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
     {NC, NC, 0},
@@ -488,6 +493,5 @@ const PinMap PinMap_QSPI_DATA2[] = {
 const PinMap PinMap_QSPI_DATA3[] = {
     {P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
     {NC, NC, 0},
- };
+};
 #endif // DEVICE_QSPI
-
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
deleted file mode 100644
index e39ef20f7cd..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
+++ /dev/null
@@ -1,308 +0,0 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm0plus.sct
-;* \version 2.50
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2019 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    0x08047600
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation. 
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        .ANY (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-}
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    .cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S
deleted file mode 100644
index c1a7ad8ed4f..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S
+++ /dev/null
@@ -1,218 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_psoc6_02_cm0plus.S
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0plus Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-                IMPORT |Image$$ARM_LIB_STACK$$Base|
-__Vectors       DCD    |Image$$ARM_LIB_STACK$$Base| ; Top of Stack
-
-                DCD     Reset_Handler             ; Reset Handler
-
-                DCD     0x0000000D                ; NMI Handler located at ROM code
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External interrupts                           Description
-                DCD     NvicMux0_IRQHandler                   ; CPU User Interrupt #0 
-                DCD     NvicMux1_IRQHandler                   ; CPU User Interrupt #1 
-                DCD     NvicMux2_IRQHandler                   ; CPU User Interrupt #2 
-                DCD     NvicMux3_IRQHandler                   ; CPU User Interrupt #3 
-                DCD     NvicMux4_IRQHandler                   ; CPU User Interrupt #4 
-                DCD     NvicMux5_IRQHandler                   ; CPU User Interrupt #5 
-                DCD     NvicMux6_IRQHandler                   ; CPU User Interrupt #6 
-                DCD     NvicMux7_IRQHandler                   ; CPU User Interrupt #7 
-                DCD     Internal0_IRQHandler                  ; Internal SW Interrupt #0 
-                DCD     Internal1_IRQHandler                  ; Internal SW Interrupt #1 
-                DCD     Internal2_IRQHandler                  ; Internal SW Interrupt #2 
-                DCD     Internal3_IRQHandler                  ; Internal SW Interrupt #3 
-                DCD     Internal4_IRQHandler                  ; Internal SW Interrupt #4 
-                DCD     Internal5_IRQHandler                  ; Internal SW Interrupt #5 
-                DCD     Internal6_IRQHandler                  ; Internal SW Interrupt #6 
-                DCD     Internal7_IRQHandler                  ; Internal SW Interrupt #7 
-
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-                EXPORT __ramVectors
-                AREA    RESET_RAM, READWRITE, NOINIT
-__ramVectors    SPACE   __Vectors_Size
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Weak function for startup customization
-;
-; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
-; because this function is executed as the first instruction in the ResetHandler.
-; The PDL is also not initialized to use the proper register offsets.
-; The user of this function is responsible for initializing the PDL and resources before using them.
-;
-Cy_OnResetUser  PROC
-                EXPORT  Cy_OnResetUser            [WEAK]
-                BX      LR
-                ENDP
-
-; Reset Handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-
-                ; Define strong function for startup customization
-                BL      Cy_OnResetUser
-
-                ; Copy vectors from ROM to RAM
-                LDR r1, =__Vectors
-                LDR r0, =__ramVectors
-                LDR r2, =__Vectors_Size
-Vectors_Copy
-                LDR r3, [r1]
-                STR r3, [r0]
-                ADDS r0, r0, #4
-                ADDS r1, r1, #4
-                SUBS r2, r2, #1
-                CMP r2, #0
-                BNE Vectors_Copy
-
-                ; Update Vector Table Offset Register. */
-                LDR r0, =__ramVectors
-                LDR r1, =0xE000ED08
-                STR r0, [r1]
-                dsb 0xF
-
-                LDR     R0, =__main
-                BLX     R0
-
-                ; Should never get here
-                B       .
-
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-NMI_Handler         PROC
-                    EXPORT  NMI_Handler               [WEAK]
-                    B       .
-                    ENDP
-
-Cy_SysLib_FaultHandler PROC
-                    EXPORT  Cy_SysLib_FaultHandler    [WEAK]
-                    B       .
-                    ENDP
-
-HardFault_Handler   PROC
-                    EXPORT HardFault_Handler          [WEAK]
-                    movs r0, #4
-                    mov r1, LR
-                    tst r0, r1
-                    beq L_MSP
-                    mrs r0, PSP
-                    bl L_API_call
-L_MSP
-                    mrs r0, MSP
-L_API_call
-                    bl Cy_SysLib_FaultHandler
-                    ENDP
-
-SVC_Handler         PROC
-                    EXPORT  SVC_Handler               [WEAK]
-                    B       .
-                    ENDP
-PendSV_Handler      PROC
-                    EXPORT  PendSV_Handler            [WEAK]
-                    B       .
-                    ENDP
-SysTick_Handler     PROC
-                    EXPORT  SysTick_Handler           [WEAK]
-                    B       .
-                    ENDP
-
-Default_Handler     PROC
-                    EXPORT  Default_Handler                       [WEAK]
-                    EXPORT  NvicMux0_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux1_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux2_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux3_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux4_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux5_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux6_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux7_IRQHandler                   [WEAK]
-                    EXPORT  Internal0_IRQHandler                  [WEAK]
-                    EXPORT  Internal1_IRQHandler                  [WEAK]
-                    EXPORT  Internal2_IRQHandler                  [WEAK]
-                    EXPORT  Internal3_IRQHandler                  [WEAK]
-                    EXPORT  Internal4_IRQHandler                  [WEAK]
-                    EXPORT  Internal5_IRQHandler                  [WEAK]
-                    EXPORT  Internal6_IRQHandler                  [WEAK]
-                    EXPORT  Internal7_IRQHandler                  [WEAK]
-
-NvicMux0_IRQHandler
-NvicMux1_IRQHandler
-NvicMux2_IRQHandler
-NvicMux3_IRQHandler
-NvicMux4_IRQHandler
-NvicMux5_IRQHandler
-NvicMux6_IRQHandler
-NvicMux7_IRQHandler
-Internal0_IRQHandler
-Internal1_IRQHandler
-Internal2_IRQHandler
-Internal3_IRQHandler
-Internal4_IRQHandler
-Internal5_IRQHandler
-Internal6_IRQHandler
-Internal7_IRQHandler
-
-                B       .
-                ENDP
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-                IMPORT   __use_two_region_memory
-
-                END
-
-
-; [] END OF FILE
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld
deleted file mode 100644
index ca0a58be38f..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld
+++ /dev/null
@@ -1,468 +0,0 @@
-/***************************************************************************//**
-* \file cy8c6xxa_cm0plus.ld
-* \version 2.50
-*
-* Linker file for the GNU C compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point location is fixed and starts at 0x10000000. The valid
-* application image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-ENTRY(Reset_Handler)
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-/* MBED_APP_START is being  used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_START
-* is equal to MBED_ROM_START
-*/
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-/* MBED_APP_SIZE is being  used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-* is equal to MBED_ROM_SIZE
-*/
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    0x08047600
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-    #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-STACK_SIZE = MBED_BOOT_STACK_SIZE;
-
-/* Force symbol to be entered in the output file as an undefined symbol. Doing
-* this may, for example, trigger linking of additional modules from standard
-* libraries. You may list several symbols for each EXTERN, and you may use
-* EXTERN multiple times. This command has the same effect as the -u command-line
-* option.
-*/
-EXTERN(Reset_Handler)
-
-/* The MEMORY section below describes the location and size of blocks of memory in the target.
-* Use this section to specify the memory regions available for allocation.
-*/
-MEMORY
-{
-    /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
-     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
-     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-     * Using this memory region for other purposes will lead to unexpected behavior.
-     * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
-     * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
-     */
-    ram               (rwx)   : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
-    public_ram        (rw)    : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE
-    flash             (rx)    : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000)
-
-    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
-     * You can assign sections to this memory region for only one of the cores.
-     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-     * Therefore, repurposing this memory region will prevent such middleware from operation.
-     */
-    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
-
-    /* The following regions define device specific memory regions and must not be changed. */
-    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
-    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
-    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
-    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
-    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
-    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
-    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-
-
-SECTIONS
-{
-    .cy_app_header :
-    {
-        KEEP(*(.cy_app_header))
-    } > flash
-
-    .text :
-    {
-        . = ALIGN(4);
-        __Vectors = . ;
-        KEEP(*(.vectors))
-        . = ALIGN(4);
-        __Vectors_End = .;
-        __Vectors_Size = __Vectors_End - __Vectors;
-        __end__ = .;
-
-        . = ALIGN(4);
-        *(.text*)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        /* Read-only code (constants). */
-        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
-
-        KEEP(*(.eh_frame*))
-    } > flash
-
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    __exidx_start = .;
-
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > flash
-    __exidx_end = .;
-
-
-    /* To copy multiple ROM to RAM sections,
-     * uncomment .copy.table section and,
-     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */
-    .copy.table :
-    {
-        . = ALIGN(4);
-        __copy_table_start__ = .;
-
-        /* Copy interrupt vectors from flash to RAM */
-        LONG (__Vectors)                                    /* From */
-        LONG (__ram_vectors_start__)                        /* To   */
-        LONG (__Vectors_End - __Vectors)                    /* Size */
-
-        /* Copy data section to RAM */
-        LONG (__etext)                                      /* From */
-        LONG (__data_start__)                               /* To   */
-        LONG (__data_end__ - __data_start__)                /* Size */
-
-        __copy_table_end__ = .;
-    } > flash
-
-
-    /* To clear multiple BSS sections,
-     * uncomment .zero.table section and,
-     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */
-    .zero.table :
-    {
-        . = ALIGN(4);
-        __zero_table_start__ = .;
-        LONG (__bss_start__)
-        LONG (__bss_end__ - __bss_start__)
-        __zero_table_end__ = .;
-    } > flash
-
-    __etext =  . ;
-
-
-    .ramVectors (NOLOAD) : ALIGN(8)
-    {
-        __ram_vectors_start__ = .;
-        KEEP(*(.ram_vectors))
-        __ram_vectors_end__   = .;
-    } > ram
-
-
-    .data __ram_vectors_end__ : AT (__etext)
-    {
-        __data_start__ = .;
-
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-
-        KEEP(*(.cy_ramfunc*))
-        . = ALIGN(4);
-
-        __data_end__ = .;
-
-    } > ram
-
-
-    /* Place variables in the section that should not be initialized during the
-    *  device startup.
-    */
-    .noinit (NOLOAD) : ALIGN(8)
-    {
-      KEEP(*(.noinit))
-    } > ram
-
-
-    /* The uninitialized global or static variables are placed in this section.
-    *
-    * The NOLOAD attribute tells linker that .bss section does not consume
-    * any space in the image. The NOLOAD attribute changes the .bss type to
-    * NOBITS, and that  makes linker to A) not allocate section in memory, and
-    * A) put information to clear the section with all zeros during application
-    * loading.
-    *
-    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
-    * This  makes linker to A) allocate zeroed section in memory, and B) copy
-    * this section to RAM during application loading.
-    */
-    .bss (NOLOAD):
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram
-
-
-    .heap (NOLOAD):
-    {
-        __HeapBase = .;
-        __end__ = .;
-        end = __end__;
-        KEEP(*(.heap*))
-        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
-        __HeapLimit = .;
-    } > ram
-
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (NOLOAD):
-    {
-        KEEP(*(.stack*))
-    } > ram
-
-
-    /* Public RAM */
-    .cy_sharedmem (NOLOAD):
-    {
-        . = ALIGN(4);
-        KEEP(*(.cy_sharedmem))
-    } > public_ram
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(ram) + LENGTH(ram);
-        __StackLimit = __StackTop - STACK_SIZE;
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-
-
-    /* Emulated EEPROM Flash area */
-    .cy_em_eeprom :
-    {
-        KEEP(*(.cy_em_eeprom))
-    } > em_eeprom
-
-
-    /* Supervisory Flash: User data */
-    .cy_sflash_user_data :
-    {
-        KEEP(*(.cy_sflash_user_data))
-    } > sflash_user_data
-
-
-    /* Supervisory Flash: Normal Access Restrictions (NAR) */
-    .cy_sflash_nar :
-    {
-        KEEP(*(.cy_sflash_nar))
-    } > sflash_nar
-
-
-    /* Supervisory Flash: Public Key */
-    .cy_sflash_public_key :
-    {
-        KEEP(*(.cy_sflash_public_key))
-    } > sflash_public_key
-
-
-    /* Supervisory Flash: Table of Content # 2 */
-    .cy_toc_part2 :
-    {
-        KEEP(*(.cy_toc_part2))
-    } > sflash_toc_2
-
-    
-    /* Supervisory Flash: Table of Content # 2 Copy */
-    .cy_rtoc_part2 :
-    {
-        KEEP(*(.cy_rtoc_part2))
-    } > sflash_rtoc_2
-
-
-    /* Places the code in the Execute in Place (XIP) section. See the smif driver
-    *  documentation for details.
-    */
-    .cy_xip :
-    {
-        KEEP(*(.cy_xip))
-    } > xip
-
-
-    /* eFuse */
-    .cy_efuse :
-    {
-        KEEP(*(.cy_efuse))
-    } > efuse
-
-
-    /* These sections are used for additional metadata (silicon revision,
-    *  Silicon/JTAG ID, etc.) storage.
-    */
-    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
-}
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-__cy_memory_0_start    = 0x10000000;
-__cy_memory_0_length   = 0x00200000;
-__cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-__cy_memory_1_start    = 0x14000000;
-__cy_memory_1_length   = 0x8000;
-__cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-__cy_memory_2_start    = 0x16000000;
-__cy_memory_2_length   = 0x8000;
-__cy_memory_2_row_size = 0x200;
-
-/* XIP */
-__cy_memory_3_start    = 0x18000000;
-__cy_memory_3_length   = 0x08000000;
-__cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-__cy_memory_4_start    = 0x90700000;
-__cy_memory_4_length   = 0x100000;
-__cy_memory_4_row_size = 1;
-
-/* EOF */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S
deleted file mode 100644
index 3fed47b01f1..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S
+++ /dev/null
@@ -1,367 +0,0 @@
-/**************************************************************************//**
- * @file     startup_psoc6_02_cm0plus.S
- * @brief    CMSIS Core Device Startup File for
- *           ARMCM0plus Device Series
- * @version  V5.00
- * @date     02. March 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-    /* Address of the NMI handler */
-    #define CY_NMI_HANLDER_ADDR         0x0000000D
-
-    /* The CPU VTOR register */
-    #define CY_CPU_VTOR_ADDR            0xE000ED08
-
-    /* Copy flash vectors and data section to RAM */
-    #define __STARTUP_COPY_MULTIPLE
-
-    /* Clear single BSS section */
-    #define __STARTUP_CLEAR_BSS
-
-    .syntax    unified
-    .arch    armv6-m
-
-    .section .stack
-    .align    3
-#ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
-#else
-    .equ    Stack_Size, 0x00001000
-#endif
-    .globl    __StackTop
-    .globl    __StackLimit
-__StackLimit:
-    .space    Stack_Size
-    .size    __StackLimit, . - __StackLimit
-__StackTop:
-    .size    __StackTop, . - __StackTop
-
-    .section .heap
-    .align    3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0x00000400
-#endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
-__HeapBase:
-    .if    Heap_Size
-    .space    Heap_Size
-    .endif
-    .size    __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size    __HeapLimit, . - __HeapLimit
-
-    .section .vectors
-    .align 2
-    .globl    __Vectors
-__Vectors:
-    .long    __StackTop            /* Top of Stack */
-    .long    Reset_Handler         /* Reset Handler */
-    .long    CY_NMI_HANLDER_ADDR   /* NMI Handler */
-    .long    HardFault_Handler     /* Hard Fault Handler */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    SVC_Handler           /* SVCall Handler */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    PendSV_Handler        /* PendSV Handler */
-    .long    SysTick_Handler       /* SysTick Handler */
-
-     /* External interrupts                             Description */
-    .long    NvicMux0_IRQHandler                     /* CPU User Interrupt #0 */
-    .long    NvicMux1_IRQHandler                     /* CPU User Interrupt #1 */
-    .long    NvicMux2_IRQHandler                     /* CPU User Interrupt #2 */
-    .long    NvicMux3_IRQHandler                     /* CPU User Interrupt #3 */
-    .long    NvicMux4_IRQHandler                     /* CPU User Interrupt #4 */
-    .long    NvicMux5_IRQHandler                     /* CPU User Interrupt #5 */
-    .long    NvicMux6_IRQHandler                     /* CPU User Interrupt #6 */
-    .long    NvicMux7_IRQHandler                     /* CPU User Interrupt #7 */
-    .long    Internal0_IRQHandler                    /* Internal SW Interrupt #0 */
-    .long    Internal1_IRQHandler                    /* Internal SW Interrupt #1 */
-    .long    Internal2_IRQHandler                    /* Internal SW Interrupt #2 */
-    .long    Internal3_IRQHandler                    /* Internal SW Interrupt #3 */
-    .long    Internal4_IRQHandler                    /* Internal SW Interrupt #4 */
-    .long    Internal5_IRQHandler                    /* Internal SW Interrupt #5 */
-    .long    Internal6_IRQHandler                    /* Internal SW Interrupt #6 */
-    .long    Internal7_IRQHandler                    /* Internal SW Interrupt #7 */
-
-    .size    __Vectors, . - __Vectors
-    .equ    __VectorsSize, . - __Vectors
-
-    .section .ram_vectors
-    .align 2
-    .globl __ramVectors
-__ramVectors:
-    .space  __VectorsSize
-    .size   __ramVectors, . - __ramVectors
-
-
-    .text
-    .thumb
-    .thumb_func
-    .align  2
-
-    /* 
-     * Device startup customization 
-     *
-     * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
-     * because this function is executed as the first instruction in the ResetHandler.
-     * The PDL is also not initialized to use the proper register offsets.
-     * The user of this function is responsible for initializing the PDL and resources before using them.
-     */
-    .weak   Cy_OnResetUser
-    .func   Cy_OnResetUser, Cy_OnResetUser
-    .type   Cy_OnResetUser, %function
-
-Cy_OnResetUser:
-    bx lr
-    .size   Cy_OnResetUser, . - Cy_OnResetUser
-    .endfunc
-
-    /* Reset handler */
-    .weak    Reset_Handler
-    .type    Reset_Handler, %function
-
-Reset_Handler:
-    bl Cy_OnResetUser
-
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r4, =__copy_table_start__
-    ldr    r5, =__copy_table_end__
-
-.L_loop0:
-    cmp    r4, r5
-    bge    .L_loop0_done
-    ldr    r1, [r4]
-    ldr    r2, [r4, #4]
-    ldr    r3, [r4, #8]
-
-.L_loop0_0:
-    subs    r3, #4
-    blt    .L_loop0_0_done
-    ldr    r0, [r1, r3]
-    str    r0, [r2, r3]
-    b    .L_loop0_0
-
-.L_loop0_0_done:
-    adds    r4, #12
-    b    .L_loop0
-
-.L_loop0_done:
-#else
-/*  Single section scheme.
- *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r1, =__etext
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
-
-    subs    r3, r2
-    ble    .L_loop1_done
-
-.L_loop1:
-    subs    r3, #4
-    ldr    r0, [r1,r3]
-    str    r0, [r2,r3]
-    bgt    .L_loop1
-
-.L_loop1_done:
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
- *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
- *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
- */
-    ldr    r3, =__zero_table_start__
-    ldr    r4, =__zero_table_end__
-
-.L_loop2:
-    cmp    r3, r4
-    bge    .L_loop2_done
-    ldr    r1, [r3]
-    ldr    r2, [r3, #4]
-    movs    r0, 0
-
-.L_loop2_0:
-    subs    r2, #4
-    blt    .L_loop2_0_done
-    str    r0, [r1, r2]
-    b    .L_loop2_0
-.L_loop2_0_done:
-
-    adds    r3, #8
-    b    .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
- *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
- *
- *  Both addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r1, =__bss_start__
-    ldr    r2, =__bss_end__
-
-    movs    r0, 0
-
-    subs    r2, r1
-    ble    .L_loop3_done
-
-.L_loop3:
-    subs    r2, #4
-    str    r0, [r1, r2]
-    bgt    .L_loop3
-.L_loop3_done:
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
-    /* Update Vector Table Offset Register. */
-    ldr r0, =__ramVectors
-    ldr r1, =CY_CPU_VTOR_ADDR
-    str r0, [r1]
-    dsb 0xF
-
-    bl  _start
-
-    /* Should never get here */
-    b   .
-
-    .pool
-    .size    Reset_Handler, . - Reset_Handler
-
-    .align    1
-    .thumb_func
-    .weak    Default_Handler
-    .type    Default_Handler, %function
-Default_Handler:
-    b    .
-    .size    Default_Handler, . - Default_Handler
-    .weak    Cy_SysLib_FaultHandler
-    .type    Cy_SysLib_FaultHandler, %function
-
-Cy_SysLib_FaultHandler:
-    b    .
-    .size    Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
-    .type Fault_Handler, %function
-
-Fault_Handler:
-    /* Storing LR content for Creator call stack trace */
-    push {LR}
-    movs r0, #4
-    mov r1, LR
-    tst r0, r1
-    beq .L_MSP
-    mrs r0, PSP
-    b .L_API_call
-.L_MSP:
-    mrs r0, MSP
-.L_API_call:
-    /* Compensation of stack pointer address due to pushing 4 bytes of LR */
-    adds r0, r0, #4
-    bl Cy_SysLib_FaultHandler
-    b   .
-    .size    Fault_Handler, . - Fault_Handler
-
-.macro    def_fault_Handler    fault_handler_name
-    .weak    \fault_handler_name
-    .set    \fault_handler_name, Fault_Handler
-    .endm
-
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-    .macro    def_irq_handler    handler_name
-    .weak    \handler_name
-    .set    \handler_name, Default_Handler
-    .endm
-
-    def_irq_handler    NMI_Handler
-
-    def_fault_Handler  HardFault_Handler
-
-    def_irq_handler    SVC_Handler
-    def_irq_handler    PendSV_Handler
-    def_irq_handler    SysTick_Handler
-
-    def_irq_handler  NvicMux0_IRQHandler                     /* CPU User Interrupt #0 */
-    def_irq_handler  NvicMux1_IRQHandler                     /* CPU User Interrupt #1 */
-    def_irq_handler  NvicMux2_IRQHandler                     /* CPU User Interrupt #2 */
-    def_irq_handler  NvicMux3_IRQHandler                     /* CPU User Interrupt #3 */
-    def_irq_handler  NvicMux4_IRQHandler                     /* CPU User Interrupt #4 */
-    def_irq_handler  NvicMux5_IRQHandler                     /* CPU User Interrupt #5 */
-    def_irq_handler  NvicMux6_IRQHandler                     /* CPU User Interrupt #6 */
-    def_irq_handler  NvicMux7_IRQHandler                     /* CPU User Interrupt #7 */
-    def_irq_handler  Internal0_IRQHandler                    /* Internal SW Interrupt #0 */
-    def_irq_handler  Internal1_IRQHandler                    /* Internal SW Interrupt #1 */
-    def_irq_handler  Internal2_IRQHandler                    /* Internal SW Interrupt #2 */
-    def_irq_handler  Internal3_IRQHandler                    /* Internal SW Interrupt #3 */
-    def_irq_handler  Internal4_IRQHandler                    /* Internal SW Interrupt #4 */
-    def_irq_handler  Internal5_IRQHandler                    /* Internal SW Interrupt #5 */
-    def_irq_handler  Internal6_IRQHandler                    /* Internal SW Interrupt #6 */
-    def_irq_handler  Internal7_IRQHandler                    /* Internal SW Interrupt #7 */
-
-    .end
-
-
-/* [] END OF FILE */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
deleted file mode 100644
index bd95799b077..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
+++ /dev/null
@@ -1,287 +0,0 @@
-/***************************************************************************//**
-* \file cy8c6xxa_cm0plus.icf
-* \version 2.50
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-if (!isdefinedsymbol(MBED_ROM_START)) {
-  define symbol MBED_ROM_START = 0x10000000;
-}
-
-/* MBED_APP_START is being  used by the bootloader build script and
- * will be calculate by the system. Without bootloader the MBED_APP_START
- * is equal to MBED_ROM_START
- */
-if (!isdefinedsymbol(MBED_APP_START)) {
-  define symbol MBED_APP_START = MBED_ROM_START;
-}
-
-if (!isdefinedsymbol(MBED_ROM_SIZE)) {
-  define symbol MBED_ROM_SIZE = 0x80000;
-}
-
-/* MBED_APP_SIZE is being  used by the bootloader build script and
- * will be calculate by the system. Without bootloader the MBED_APP_SIZE
- * is equal to MBED_ROM_SIZE
- */
-if (!isdefinedsymbol(MBED_APP_SIZE)) {
-  define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
-}
-
-if (!isdefinedsymbol(MBED_RAM_START)) {
-  define symbol MBED_RAM_START = 0x08000000;
-}
-
-if (!isdefinedsymbol(MBED_RAM_SIZE)) {
-  define symbol MBED_RAM_SIZE = 0x00010000;
-}
-
-if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) {
-  define symbol MBED_PUBLIC_RAM_START = 0x08047600;
-}
-
-if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) {
-  define symbol MBED_PUBLIC_RAM_SIZE = 0x200;
-}
-
-if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
-    define symbol MBED_BOOT_STACK_SIZE = 0x400;
-}
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM0+ core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
-define symbol __ICFEDIT_region_IRAM1_end__   = (MBED_RAM_START + MBED_RAM_SIZE);
-/* Public RAM */
-define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START;
-define symbol __ICFEDIT_region_IRAM2_end__   = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE);
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
-define symbol __ICFEDIT_region_IROM1_end__   = (MBED_APP_START + MBED_APP_SIZE - 0x8000);
-
-/* The following symbols define a 32K flash region used for EEPROM emulation. 
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__   = 0x160007FF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-
-
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
-  define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
-} else {
-  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x400;
-} else {
-  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
-
-define block RAM_DATA {readwrite section .data};
-define block RAM_OTHER {readwrite section * };
-define block RAM_NOINIT {readwrite section .noinit};
-define block RAM_BSS {readwrite section .bss};
-define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};
-define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block RO     {first section .intvec, readonly};
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize  { section .noinit, section .intvec_ram };
-
-
-/*-Placement-*/
-
-/* Flash */
-".cy_app_header" : place at start of IROM1_region  { section .cy_app_header };
-place in          IROM1_region  { block RO };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-".cy_xip" : place at start of EROM1_region  { section .cy_xip };
-
-/* RAM */
-place at start of IRAM1_region  { readwrite section .intvec_ram};
-place in IRAM1_region  { block RAM};
-place in IRAM1_region  { readwrite section .cy_ramfunc };
-place at end   of IRAM1_region  { block HSTACK };
-
-/* Public RAM */
-place at start of IRAM2_region  { section .cy_sharedmem };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep {  section .cy_app_header,
-        section .cy_em_eeprom,
-        section .cy_sflash_user_data,
-        section .cy_sflash_nar,
-        section .cy_sflash_public_key,
-        section .cy_toc_part2,
-        section .cy_rtoc_part2,
-        section .cy_efuse,
-        section .cy_xip,
-        section .cymeta,
-         };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start    = 0x10000000;
-define exported symbol __cy_memory_0_length   = 0x00200000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start    = 0x14000000;
-define exported symbol __cy_memory_1_length   = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start    = 0x16000000;
-define exported symbol __cy_memory_2_length   = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start    = 0x18000000;
-define exported symbol __cy_memory_3_length   = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start    = 0x90700000;
-define exported symbol __cy_memory_4_length   = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S
deleted file mode 100644
index 3b77acffe37..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S
+++ /dev/null
@@ -1,317 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_psoc6_02_cm0plus.S
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0plus Device Series
-; * @version  V5.00
-; * @date     08. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-        SECTION .intvec_ram:DATA:NOROOT(2)
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        EXTERN __iar_data_init3
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
-        PUBLIC  __ramVectors
-
-        DATA
-
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     0x0000000D      ; NMI_Handler is defined in ROM code
-        DCD     HardFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
-__vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     0
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External interrupts                           Description
-        DCD     NvicMux0_IRQHandler                   ; CPU User Interrupt #0
-        DCD     NvicMux1_IRQHandler                   ; CPU User Interrupt #1
-        DCD     NvicMux2_IRQHandler                   ; CPU User Interrupt #2
-        DCD     NvicMux3_IRQHandler                   ; CPU User Interrupt #3
-        DCD     NvicMux4_IRQHandler                   ; CPU User Interrupt #4
-        DCD     NvicMux5_IRQHandler                   ; CPU User Interrupt #5
-        DCD     NvicMux6_IRQHandler                   ; CPU User Interrupt #6
-        DCD     NvicMux7_IRQHandler                   ; CPU User Interrupt #7
-        DCD     Internal0_IRQHandler                  ; Internal SW Interrupt #0
-        DCD     Internal1_IRQHandler                  ; Internal SW Interrupt #1
-        DCD     Internal2_IRQHandler                  ; Internal SW Interrupt #2
-        DCD     Internal3_IRQHandler                  ; Internal SW Interrupt #3
-        DCD     Internal4_IRQHandler                  ; Internal SW Interrupt #4
-        DCD     Internal5_IRQHandler                  ; Internal SW Interrupt #5
-        DCD     Internal6_IRQHandler                  ; Internal SW Interrupt #6
-        DCD     Internal7_IRQHandler                  ; Internal SW Interrupt #7
-
-__Vectors_End
-
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
-
-        SECTION .intvec_ram:DATA:REORDER:NOROOT(2)
-__ramVectors
-        DS32     __Vectors_Size
-
-
-        THUMB
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default handlers
-;;
-        PUBWEAK Default_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Default_Handler
-        B Default_Handler
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Weak function for startup customization
-;;
-;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
-;; because this function is executed as the first instruction in the ResetHandler.
-;; The PDL is also not initialized to use the proper register offsets.
-;; The user of this function is responsible for initializing the PDL and resources before using them.
-;;
-        PUBWEAK Cy_OnResetUser
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Cy_OnResetUser
-        BX LR
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Define strong version to return zero for
-;; __iar_program_start to skip data sections
-;; initialization.
-;;
-        PUBLIC __low_level_init
-        SECTION .text:CODE:REORDER:NOROOT(2)
-__low_level_init
-        MOVS R0, #0
-        BX LR
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        ; Define strong function for startup customization
-        LDR     R0, =Cy_OnResetUser
-        BLX     R0
-
-        ; Copy vectors from ROM to RAM
-        LDR r1, =__vector_table
-        LDR r0, =__ramVectors
-        LDR r2, =__Vectors_Size
-intvec_copy
-        LDR r3, [r1]
-        STR r3, [r0]
-        ADDS r0, r0, #4
-        ADDS r1, r1, #4
-        SUBS r2, r2, #1
-        CMP r2, #0
-        BNE intvec_copy
-
-        ; Update Vector Table Offset Register
-        LDR r0, =__ramVectors
-        LDR r1, =0xE000ED08
-        STR r0, [r1]
-        dsb
-
-        LDR     R0, =__iar_program_start
-        BLX     R0
-
-; Should never get here
-Cy_Main_Exited
-        B Cy_Main_Exited
-
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-
-        PUBWEAK Cy_SysLib_FaultHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Cy_SysLib_FaultHandler
-        B Cy_SysLib_FaultHandler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        IMPORT Cy_SysLib_FaultHandler
-        movs r0, #4
-        mov r1, LR
-        tst r0, r1
-        beq L_MSP
-        mrs r0, PSP
-        b L_API_call
-L_MSP
-        mrs r0, MSP
-L_API_call
-        ; Storing LR content for Creator call stack trace
-        push {LR}
-        bl Cy_SysLib_FaultHandler
-
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-
-        ; External interrupts
-        PUBWEAK NvicMux0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux0_IRQHandler
-        B       NvicMux0_IRQHandler
-
-        PUBWEAK NvicMux1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux1_IRQHandler
-        B       NvicMux1_IRQHandler
-
-        PUBWEAK NvicMux2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux2_IRQHandler
-        B       NvicMux2_IRQHandler
-
-        PUBWEAK NvicMux3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux3_IRQHandler
-        B       NvicMux3_IRQHandler
-
-        PUBWEAK NvicMux4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux4_IRQHandler
-        B       NvicMux4_IRQHandler
-
-        PUBWEAK NvicMux5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux5_IRQHandler
-        B       NvicMux5_IRQHandler
-
-        PUBWEAK NvicMux6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux6_IRQHandler
-        B       NvicMux6_IRQHandler
-
-        PUBWEAK NvicMux7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux7_IRQHandler
-        B       NvicMux7_IRQHandler
-
-        PUBWEAK Internal0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal0_IRQHandler
-        B       Internal0_IRQHandler
-
-        PUBWEAK Internal1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal1_IRQHandler
-        B       Internal1_IRQHandler
-
-        PUBWEAK Internal2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal2_IRQHandler
-        B       Internal2_IRQHandler
-
-        PUBWEAK Internal3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal3_IRQHandler
-        B       Internal3_IRQHandler
-
-        PUBWEAK Internal4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal4_IRQHandler
-        B       Internal4_IRQHandler
-
-        PUBWEAK Internal5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal5_IRQHandler
-        B       Internal5_IRQHandler
-
-        PUBWEAK Internal6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal6_IRQHandler
-        B       Internal6_IRQHandler
-
-        PUBWEAK Internal7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal7_IRQHandler
-        B       Internal7_IRQHandler
-
-
-        END
-
-
-; [] END OF FILE
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c
deleted file mode 100644
index 010eac6188e..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c
+++ /dev/null
@@ -1,710 +0,0 @@
-/***************************************************************************//**
-* \file system_psoc6_cm0plus.c
-* \version 2.50
-*
-* The device system-source file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#include <stdbool.h>
-#include "system_psoc6.h"
-#include "cy_device.h"
-#include "cy_device_headers.h"
-#include "cy_syslib.h"
-#include "cy_wdt.h"
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-    #include "cy_ipc_sema.h"
-    #include "cy_ipc_pipe.h"
-    #include "cy_ipc_drv.h"
-
-    #if defined(CY_DEVICE_PSOC6ABLE2)
-        #include "cy_flash.h"
-    #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
-
-#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
-
-
-/*******************************************************************************
-* SystemCoreClockUpdate()
-*******************************************************************************/
-
-/** Default HFClk frequency in Hz */
-#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT       (8000000UL)
-
-/** Default PeriClk frequency in Hz */
-#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT      (4000000UL)
-
-/** Default SlowClk system core frequency in Hz */
-#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT       (4000000UL)
-
-/** IMO frequency in Hz */
-#define CY_CLK_IMO_FREQ_HZ                  (8000000UL)
-
-/** HVILO frequency in Hz */
-#define CY_CLK_HVILO_FREQ_HZ                (32000UL)
-
-/** PILO frequency in Hz */
-#define CY_CLK_PILO_FREQ_HZ                 (32768UL)
-
-/** WCO frequency in Hz */
-#define CY_CLK_WCO_FREQ_HZ                  (32768UL)
-
-/** ALTLF frequency in Hz */
-#define CY_CLK_ALTLF_FREQ_HZ                (32768UL)
-
-
-/**
-* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
-* which is the system clock frequency supplied to the SysTick timer and the
-* processor core clock.
-* This variable implements CMSIS Core global variable.
-* Refer to the [CMSIS documentation]
-* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
-* for more details.
-* This variable can be used by debuggers to query the frequency
-* of the debug timer or to configure the trace clock speed.
-*
-* \attention Compilers must be configured to avoid removing this variable in case
-* the application program is not using it. Debugging systems require the variable
-* to be physically present in memory so that it can be examined to configure the debugger. */
-uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
-
-/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
-uint32_t cy_Hfclk0FreqHz  = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
-
-/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
-uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
-
-/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
-#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
-    uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
-#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
-
-
-/*******************************************************************************
-* SystemInit()
-*******************************************************************************/
-
-/* CLK_FLL_CONFIG default values */
-#define CY_FB_CLK_FLL_CONFIG_VALUE      (0x01000000u)
-#define CY_FB_CLK_FLL_CONFIG2_VALUE     (0x00020001u)
-#define CY_FB_CLK_FLL_CONFIG3_VALUE     (0x00002800u)
-#define CY_FB_CLK_FLL_CONFIG4_VALUE     (0x000000FFu)
-
-
-/*******************************************************************************
-* SystemCoreClockUpdate (void)
-*******************************************************************************/
-
-/* Do not use these definitions directly in your application */
-#define CY_DELAY_MS_OVERFLOW_THRESHOLD  (0x8000u)
-#define CY_DELAY_1K_THRESHOLD           (1000u)
-#define CY_DELAY_1K_MINUS_1_THRESHOLD   (CY_DELAY_1K_THRESHOLD - 1u)
-#define CY_DELAY_1M_THRESHOLD           (1000000u)
-#define CY_DELAY_1M_MINUS_1_THRESHOLD   (CY_DELAY_1M_THRESHOLD - 1u)
-uint32_t cy_delayFreqHz   = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
-
-uint32_t cy_delayFreqKhz  = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
-                            CY_DELAY_1K_THRESHOLD;
-
-uint8_t cy_delayFreqMhz  = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
-                            CY_DELAY_1M_THRESHOLD);
-
-uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
-                            ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
-
-#define CY_ROOT_PATH_SRC_IMO                (0UL)
-#define CY_ROOT_PATH_SRC_EXT                (1UL)
-#if (SRSS_ECO_PRESENT == 1U)
-    #define CY_ROOT_PATH_SRC_ECO            (2UL)
-#endif /* (SRSS_ECO_PRESENT == 1U) */
-#if (SRSS_ALTHF_PRESENT == 1U)
-    #define CY_ROOT_PATH_SRC_ALTHF          (3UL)
-#endif /* (SRSS_ALTHF_PRESENT == 1U) */
-#define CY_ROOT_PATH_SRC_DSI_MUX            (4UL)
-#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO      (16UL)
-#define CY_ROOT_PATH_SRC_DSI_MUX_WCO        (17UL)
-#if (SRSS_ALTLF_PRESENT == 1U)
-    #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF  (18UL)
-#endif /* (SRSS_ALTLF_PRESENT == 1U) */
-#if (SRSS_PILO_PRESENT == 1U)
-    #define CY_ROOT_PATH_SRC_DSI_MUX_PILO   (19UL)
-#endif /* (SRSS_PILO_PRESENT == 1U) */
-
-
-/*******************************************************************************
-* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
-*******************************************************************************/
-#define CY_SYS_CM4_PWR_CTL_KEY_OPEN  (0x05FAUL)
-#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
-#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR  (0x000003FFUL)
-
-
-/*******************************************************************************
-* Function Name: SystemInit
-****************************************************************************//**
-*
-* Initializes the system:
-* - Restores FLL registers to the default state.
-* - Unlocks and disables WDT.
-* - Calls Cy_PDL_Init() function to define the driver library.
-* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
-* - Calls \ref SystemCoreClockUpdate().
-*
-*******************************************************************************/
-void SystemInit(void)
-{
-    Cy_PDL_Init(CY_DEVICE_CFG);
-
-    /* Restore FLL registers to the default state as they are not restored by the ROM code */
-    uint32_t copy = SRSS->CLK_FLL_CONFIG;
-    copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
-    SRSS->CLK_FLL_CONFIG = copy;
-
-    copy = SRSS->CLK_ROOT_SELECT[0u];
-    copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
-    SRSS->CLK_ROOT_SELECT[0u] = copy;
-
-    SRSS->CLK_FLL_CONFIG  = CY_FB_CLK_FLL_CONFIG_VALUE;
-    SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
-    SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
-    SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
-
-    /* Unlock and disable WDT */
-    Cy_WDT_Unlock();
-    Cy_WDT_Disable();
-
-    Cy_SystemInit();
-    SystemCoreClockUpdate();
-
-#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
-    if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
-    {
-        /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
-        IPC_STRUCT7->DATA = 0UL;
-        /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
-        IPC_STRUCT7->RELEASE = 0UL;
-    }
-#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-    /* Allocate and initialize semaphores for the system operations. */
-    CY_SECTION(".cy_sharedmem")
-    static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
-
-    (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
-
-
-    /********************************************************************************
-    *
-    * Initializes the system pipes. The system pipes are used by BLE and Flash.
-    *
-    * If the default startup file is not used, or SystemInit() is not called in your
-    * project, call the following three functions prior to executing any flash or
-    * EmEEPROM write or erase operation:
-    *  -# Cy_IPC_Sema_Init()
-    *  -# Cy_IPC_Pipe_Config()
-    *  -# Cy_IPC_Pipe_Init()
-    *  -# Cy_Flash_Init()
-    *
-    *******************************************************************************/
-
-    /* Create an array of endpoint structures */
-    static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
-
-    Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
-
-    static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
-
-    static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
-    {
-    /* .ep0ConfigData */
-        {
-            /* .ipcNotifierNumber    */  CY_IPC_INTR_CYPIPE_EP0,
-            /* .ipcNotifierPriority  */  CY_SYS_INTR_CYPIPE_PRIOR_EP0,
-            /* .ipcNotifierMuxNumber */  CY_SYS_INTR_CYPIPE_MUX_EP0,
-            /* .epAddress            */  CY_IPC_EP_CYPIPE_CM0_ADDR,
-            /* .epConfig             */  CY_SYS_CYPIPE_CONFIG_EP0
-        },
-    /* .ep1ConfigData */
-        {
-            /* .ipcNotifierNumber    */  CY_IPC_INTR_CYPIPE_EP1,
-            /* .ipcNotifierPriority  */  CY_SYS_INTR_CYPIPE_PRIOR_EP1,
-            /* .ipcNotifierMuxNumber */  0u,
-            /* .epAddress            */  CY_IPC_EP_CYPIPE_CM4_ADDR,
-            /* .epConfig             */  CY_SYS_CYPIPE_CONFIG_EP1
-        },
-    /* .endpointClientsCount     */  CY_SYS_CYPIPE_CLIENT_CNT,
-    /* .endpointsCallbacksArray  */  systemIpcPipeSysCbArray,
-    /* .userPipeIsrHandler       */  &Cy_SysIpcPipeIsrCm0
-    };
-
-    if (cy_device->flashPipeRequired != 0u)
-    {
-        Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
-    }
-
-#if defined(CY_DEVICE_PSOC6ABLE2)
-    Cy_Flash_Init();
-#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
-
-#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SystemInit
-****************************************************************************//**
-*
-* The function is called during device startup. Once project compiled as part of
-* the PSoC Creator project, the Cy_SystemInit() function is generated by the
-* PSoC Creator.
-*
-* The function generated by PSoC Creator performs all of the necessary device
-* configuration based on the design settings.  This includes settings from the
-* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
-* configuration that is necessary.
-*
-*******************************************************************************/
-__WEAK void Cy_SystemInit(void)
-{
-     /* Empty weak function. The actual implementation to be in the PSoC Creator
-      * generated strong function.
-     */
-}
-
-
-/*******************************************************************************
-* Function Name: SystemCoreClockUpdate
-****************************************************************************//**
-*
-* Gets core clock frequency and updates \ref SystemCoreClock, \ref
-* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
-*
-* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
-* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
-*
-*******************************************************************************/
-void SystemCoreClockUpdate (void)
-{
-    uint32_t srcFreqHz;
-    uint32_t pathFreqHz;
-    uint32_t slowClkDiv;
-    uint32_t periClkDiv;
-    uint32_t rootPath;
-    uint32_t srcClk;
-
-    /* Get root path clock for the high-frequency clock # 0 */
-    rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
-
-    /* Get source of the root path clock */
-    srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
-
-    /* Get frequency of the source */
-    switch (srcClk)
-    {
-    case CY_ROOT_PATH_SRC_IMO:
-        srcFreqHz = CY_CLK_IMO_FREQ_HZ;
-    break;
-
-    case CY_ROOT_PATH_SRC_EXT:
-        srcFreqHz = CY_CLK_EXT_FREQ_HZ;
-    break;
-
-    #if (SRSS_ECO_PRESENT == 1U)
-        case CY_ROOT_PATH_SRC_ECO:
-            srcFreqHz = CY_CLK_ECO_FREQ_HZ;
-        break;
-    #endif /* (SRSS_ECO_PRESENT == 1U) */
-
-#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
-    case CY_ROOT_PATH_SRC_ALTHF:
-        srcFreqHz = cy_BleEcoClockFreqHz;
-    break;
-#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
-
-    case CY_ROOT_PATH_SRC_DSI_MUX:
-    {
-        uint32_t dsi_src;
-        dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX,  SRSS->CLK_DSI_SELECT[rootPath]);
-        switch (dsi_src)
-        {
-        case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
-            srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
-        break;
-
-        case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
-            srcFreqHz = CY_CLK_WCO_FREQ_HZ;
-        break;
-
-        #if (SRSS_ALTLF_PRESENT == 1U)
-            case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
-                srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
-            break;
-        #endif /* (SRSS_ALTLF_PRESENT == 1U) */
-
-        #if (SRSS_PILO_PRESENT == 1U)
-            case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
-                srcFreqHz = CY_CLK_PILO_FREQ_HZ;
-            break;
-        #endif /* (SRSS_PILO_PRESENT == 1U) */
-
-        default:
-            srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
-        break;
-        }
-    }
-    break;
-
-    default:
-        srcFreqHz = CY_CLK_EXT_FREQ_HZ;
-    break;
-    }
-
-    if (rootPath == 0UL)
-    {
-        /* FLL */
-        bool fllLocked       = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
-        bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
-        bool fllOutputAuto   = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
-                                (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
-        if ((fllOutputAuto && fllLocked) || fllOutputOutput)
-        {
-            uint32_t fllMult;
-            uint32_t refDiv;
-            uint32_t outputDiv;
-
-            fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
-            refDiv  = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
-            outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
-
-            pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
-        }
-        else
-        {
-            pathFreqHz = srcFreqHz;
-        }
-    }
-    else if ((rootPath == 1UL) || (rootPath == 2UL))
-    {
-        /* PLL */
-        bool pllLocked       = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED,     SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
-        bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
-        bool pllOutputAuto   = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
-                                (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
-        if ((pllOutputAuto && pllLocked) || pllOutputOutput)
-        {
-            uint32_t feedbackDiv;
-            uint32_t referenceDiv;
-            uint32_t outputDiv;
-
-            feedbackDiv  = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV,  SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
-            referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
-            outputDiv    = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV,    SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
-
-            pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
-
-        }
-        else
-        {
-            pathFreqHz = srcFreqHz;
-        }
-    }
-    else
-    {
-        /* Direct */
-        pathFreqHz = srcFreqHz;
-    }
-
-    /* Get frequency after hf_clk pre-divider */
-    pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
-    cy_Hfclk0FreqHz = pathFreqHz;
-
-    /* Slow Clock Divider */
-    slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL);
-
-    /* Peripheral Clock Divider */
-    periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
-
-    pathFreqHz = pathFreqHz / periClkDiv;
-    cy_PeriClkFreqHz = pathFreqHz;
-    pathFreqHz = pathFreqHz / slowClkDiv;
-    SystemCoreClock = pathFreqHz;
-
-    /* Sets clock frequency for Delay API */
-    cy_delayFreqHz = SystemCoreClock;
-    cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
-    cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
-    cy_delay32kMs   = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
-}
-
-
-#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
-/*******************************************************************************
-* Function Name: Cy_SysGetCM4Status
-****************************************************************************//**
-*
-* Returns the Cortex-M4 core power mode.
-*
-* \return \ref group_system_config_cm4_status_macro
-*
-*******************************************************************************/
-uint32_t Cy_SysGetCM4Status(void)
-{
-    uint32_t regValue;
-
-    /* Get current power mode */
-    regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
-
-    return (regValue);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysEnableCM4
-****************************************************************************//**
-*
-* Sets vector table base address and enables the Cortex-M4 core.
-*
-* \note If the CPU is already enabled, it is reset and then enabled.
-*
-* \param vectorTableOffset The offset of the vector table base address from
-* memory address 0x00000000. The offset should be multiple to 1024 bytes.
-*
-*******************************************************************************/
-void Cy_SysEnableCM4(uint32_t vectorTableOffset)
-{
-    uint32_t regValue;
-    uint32_t interruptState;
-    uint32_t cpuState;
-
-    CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    cpuState = Cy_SysGetCM4Status();
-    if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
-    {
-        Cy_SysResetCM4();
-    }
-
-    CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_ENABLED;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
-    {
-        /* Wait for the power mode to take effect */
-    }
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysDisableCM4
-****************************************************************************//**
-*
-* Disables the Cortex-M4 core and waits for the mode to take the effect.
-*
-* \warning Do not call the function while the Cortex-M4 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
-* CPU.
-*
-*******************************************************************************/
-void Cy_SysDisableCM4(void)
-{
-    uint32_t interruptState;
-    uint32_t regValue;
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_DISABLED;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
-    {
-        /* Wait for the power mode to take effect */
-    }
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysRetainCM4
-****************************************************************************//**
-*
-* Retains the Cortex-M4 core and exists without waiting for the mode to take
-* effect.
-*
-* \note The retained mode can be entered only from the enabled mode.
-*
-* \warning Do not call the function while the Cortex-M4 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
-*
-*******************************************************************************/
-void Cy_SysRetainCM4(void)
-{
-    uint32_t interruptState;
-    uint32_t regValue;
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_RETAINED;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysResetCM4
-****************************************************************************//**
-*
-* Resets the Cortex-M4 core and waits for the mode to take the effect.
-*
-* \note The reset mode can not be entered from the retained mode.
-*
-* \warning Do not call the function while the Cortex-M4 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
-*
-*******************************************************************************/
-void Cy_SysResetCM4(void)
-{
-    uint32_t interruptState;
-    uint32_t regValue;
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_RESET;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
-    {
-        /* Wait for the power mode to take effect */
-    }
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-/*******************************************************************************
-* Function Name: Cy_SysIpcPipeIsrCm0
-****************************************************************************//**
-*
-* This is the interrupt service routine for the system pipe.
-*
-*******************************************************************************/
-void Cy_SysIpcPipeIsrCm0(void)
-{
-    Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR);
-}
-#endif
-
-
-/*******************************************************************************
-* Function Name: Cy_MemorySymbols
-****************************************************************************//**
-*
-* The intention of the function is to declare boundaries of the memories for the
-* MDK compilers. For the rest of the supported compilers, this is done using
-* linker configuration files. The following symbols used by the cymcuelftool.
-*
-*******************************************************************************/
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
-__asm void Cy_MemorySymbols(void)
-{
-    /* Flash */
-    EXPORT __cy_memory_0_start
-    EXPORT __cy_memory_0_length
-    EXPORT __cy_memory_0_row_size
-
-    /* Working Flash */
-    EXPORT __cy_memory_1_start
-    EXPORT __cy_memory_1_length
-    EXPORT __cy_memory_1_row_size
-
-    /* Supervisory Flash */
-    EXPORT __cy_memory_2_start
-    EXPORT __cy_memory_2_length
-    EXPORT __cy_memory_2_row_size
-
-    /* XIP */
-    EXPORT __cy_memory_3_start
-    EXPORT __cy_memory_3_length
-    EXPORT __cy_memory_3_row_size
-
-    /* eFuse */
-    EXPORT __cy_memory_4_start
-    EXPORT __cy_memory_4_length
-    EXPORT __cy_memory_4_row_size
-
-    /* Flash */
-__cy_memory_0_start     EQU __cpp(CY_FLASH_BASE)
-__cy_memory_0_length    EQU __cpp(CY_FLASH_SIZE)
-__cy_memory_0_row_size  EQU 0x200
-
-    /* Flash region for EEPROM emulation */
-__cy_memory_1_start     EQU __cpp(CY_EM_EEPROM_BASE)
-__cy_memory_1_length    EQU __cpp(CY_EM_EEPROM_SIZE)
-__cy_memory_1_row_size  EQU 0x200
-
-    /* Supervisory Flash */
-__cy_memory_2_start     EQU __cpp(CY_SFLASH_BASE)
-__cy_memory_2_length    EQU __cpp(CY_SFLASH_SIZE)
-__cy_memory_2_row_size  EQU 0x200
-
-    /* XIP */
-__cy_memory_3_start     EQU __cpp(CY_XIP_BASE)
-__cy_memory_3_length    EQU __cpp(CY_XIP_SIZE)
-__cy_memory_3_row_size  EQU 0x200
-
-    /* eFuse */
-__cy_memory_4_start     EQU __cpp(0x90700000)
-__cy_memory_4_length    EQU __cpp(0x100000)
-__cy_memory_4_row_size  EQU __cpp(1)
-}
-#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
-
-
-/* [] END OF FILE */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
similarity index 93%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
index f684a0cb0e6..c5ff156fe10 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
@@ -78,6 +78,7 @@
   #define MBED_BOOT_STACK_SIZE 0x400
 #endif
 
+; Size of the stack section at the end of CM4 SRAM
 #define STACK_SIZE MBED_BOOT_STACK_SIZE
 
 ; The defines below describe the location and size of blocks of memory in the target.
@@ -96,6 +97,9 @@
 #define FLASH_START             MBED_APP_START
 #define FLASH_SIZE              MBED_APP_SIZE
 
+; Size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
 ; The following defines describe a 32K flash region used for EEPROM emulation.
 ; This region can also be used as the general purpose flash.
 ; You can assign sections to this memory region for only one of the cores.
@@ -133,17 +137,9 @@
 #define EFUSE_START             0x90700000
 #define EFUSE_SIZE              0x100000
 
-; Size and start address of the Cortex-M0+ application image
-#define FLASH_CM0P_SIZE         0x2000
-#define FLASH_CM0P_START        FLASH_START
-
-; Size and start address of the Cortex-M4 application image
-#define FLASH_CM4_SIZE          (FLASH_SIZE - FLASH_CM0P_SIZE)
-#define FLASH_CM4_START         (FLASH_CM0P_START + FLASH_CM0P_SIZE)
-
 
-; Cortex-M0+ application image
-LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
 {
     .cy_m0p_image +0 FLASH_CM0P_SIZE
     {
@@ -151,8 +147,8 @@ LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
     }
 }
 
-; Cortex-M4 application image
-LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
 {
     ER_FLASH_VECTORS +0
     {
@@ -173,7 +169,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
     RW_RAM_DATA +0
     {
         * (.cy_ramfunc)
-        .ANY (+RW, +ZI)
+        * (+RW, +ZI)
     }
 
     ; Place variables in the section that should not be initialized during the
@@ -184,13 +180,15 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
     }
 
     ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    ARM_LIB_HEAP  +0
     { 
+        * (HEAP) 
     }
     
     ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE 
     {
+        * (STACK)
     }
 
     ; Used for the digital signature of the secure application and the
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
similarity index 97%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
index ed6da9fd49c..dddf31e622e 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
@@ -23,6 +23,36 @@
 ; * limitations under the License.
 ; */
 
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+                IF :DEF:__STACK_SIZE
+Stack_Size      EQU     __STACK_SIZE
+                ELSE
+Stack_Size      EQU     0x00000400
+                ENDIF
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+                IF :DEF:__HEAP_SIZE
+Heap_Size       EQU     __HEAP_SIZE
+                ELSE
+Heap_Size       EQU     0x00000400
+                ENDIF
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
                 PRESERVE8
                 THUMB
 
@@ -33,9 +63,7 @@
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
 
-                IMPORT |Image$$ARM_LIB_STACK$$Base|
-__Vectors       DCD    |Image$$ARM_LIB_STACK$$Base| ; Top of Stack
-
+__Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     Reset_Handler             ; Reset Handler
 
                 DCD     0x0000000D                            ; NMI Handler located at ROM code
@@ -698,7 +726,20 @@ sdhc_1_interrupt_general_IRQHandler
 
 
 ; User Initial Stack & Heap
-                IMPORT   __use_two_region_memory
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT __use_two_region_memory
+
+                ALIGN
+
+                ENDIF
 
                 END
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
similarity index 96%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
index d1e01ff2bfa..1c6cf348fab 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
@@ -76,8 +76,12 @@ ENTRY(Reset_Handler)
     #define MBED_BOOT_STACK_SIZE 0x400
 #endif
 
+/* Size of the stack section at the end of CM4 SRAM */
 STACK_SIZE = MBED_BOOT_STACK_SIZE;
 
+/* Size of the Cortex-M0+ application image at the start of FLASH */
+FLASH_CM0P_SIZE  = 0x2000;
+
 /* Force symbol to be entered in the output file as an undefined symbol. Doing
 * this may, for example, trigger linking of additional modules from standard
 * libraries. You may list several symbols for each EXTERN, and you may use
@@ -118,13 +122,6 @@ MEMORY
     efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
 }
 
-/* Size and start address of the Cortex-M0+ application image */
-FLASH_CM0P_SIZE  = 0x2000;
-FLASH_CM0P_START = ORIGIN(flash);
-/* Size and start address of the Cortex-M4 application image */
-FLASH_CM4_SIZE   = LENGTH(flash) - FLASH_CM0P_SIZE;
-FLASH_CM4_START  = FLASH_CM0P_START + FLASH_CM0P_SIZE;
-
 /* Library configurations */
 GROUP(libgcc.a libc.a libm.a libnosys.a)
 
@@ -164,8 +161,8 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
 
 SECTIONS
 {
-     /* Cortex-M0+ application image */
-    .cy_m0p_image FLASH_CM0P_START :
+     /* Cortex-M0+ application flash image area */
+    .cy_m0p_image ORIGIN(flash) :
     {
         . = ALIGN(4);
         __cy_m0p_code_start = . ;
@@ -173,8 +170,11 @@ SECTIONS
         __cy_m0p_code_end = . ;
     } > flash
 
-    /* Cortex-M4 application image */
-    .text FLASH_CM4_START :
+    /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
+    ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
+
+    /* Cortex-M4 application flash area */
+    .text ORIGIN(flash) + FLASH_CM0P_SIZE :
     {
         . = ALIGN(4);
         __Vectors = . ;
@@ -290,7 +290,6 @@ SECTIONS
         KEEP(*(.init_array))
         PROVIDE_HIDDEN (__init_array_end = .);
 
-
         . = ALIGN(4);
         /* finit data */
         PROVIDE_HIDDEN (__fini_array_start = .);
@@ -351,7 +350,7 @@ SECTIONS
         __HeapLimit = .;
     } > ram
 
-    
+
     /* Set stack top to end of RAM, and stack limit move down by
      * size of stack_dummy section */
     __StackTop = ORIGIN(ram) + LENGTH(ram);
@@ -404,7 +403,7 @@ SECTIONS
         KEEP(*(.cy_toc_part2))
     } > sflash_toc_2
 
-    
+
     /* Supervisory Flash: Table of Content # 2 Copy */
     .cy_rtoc_part2 :
     {
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
similarity index 98%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
index 2ee6f7c67d1..cc133130138 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
@@ -156,7 +156,7 @@ if (!isdefinedsymbol(__STACK_SIZE)) {
 
 /* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
 if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x400;
+    define symbol __ICFEDIT_size_heap__ = 0x0400;
 } else {
   define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
 }
@@ -198,8 +198,10 @@ do not initialize  { section .noinit, section .intvec_ram };
 /* Flash - Cortex-M0+ application image */
 place at start of IROM1_region  { block CM0P_RO };
 
-/* Flash - Cortex-M4 application image */
+/* Flash - Cortex-M4 application */
 place in          IROM1_region  { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
 ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
 
 /* Emulated EEPROM Flash area */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S
similarity index 99%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S
index ade874af4d4..3257b6f20c9 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S
@@ -331,10 +331,6 @@ intvec_copy
         STR r0, [r1]
         dsb
 
-        ; Enable the FPU if used
-        LDR     R0, =Cy_SystemInitFpuEnable
-        BLX     R0
-
         ; Initialize data sections
         LDR     R0, =__iar_data_init3
         BLX     R0
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6_cm4.c
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6_cm4.c
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/PeripheralPins.c
index 6f8b53be7db..e42fe6998bc 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/PeripheralPins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/PeripheralPins.c
@@ -124,7 +124,9 @@ const PinMap PinMap_I2C_SCL[] = {
     {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
     {P5_4, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_4_SCB10_I2C_SCL)},
     {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
+    {P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
     {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
+    {P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
     {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
     {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
     {P8_4, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_4_SCB11_I2C_SCL)},
@@ -146,7 +148,9 @@ const PinMap PinMap_I2C_SDA[] = {
     {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
     {P5_5, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_5_SCB10_I2C_SDA)},
     {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
+    {P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
     {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
+    {P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
     {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
     {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
     {P8_5, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_5_SCB11_I2C_SDA)},
@@ -170,7 +174,9 @@ const PinMap PinMap_SPI_MOSI[] = {
     {P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)},
     {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
     {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
+    {P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
     {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
+    {P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
     {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
     {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
     {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
@@ -188,7 +194,9 @@ const PinMap PinMap_SPI_MISO[] = {
     {P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)},
     {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
     {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
+    {P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
     {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
+    {P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
     {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
     {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
     {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
@@ -205,7 +213,9 @@ const PinMap PinMap_SPI_SCLK[] = {
     {P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)},
     {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
     {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
+    {P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
     {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
+    {P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
     {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
     {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
     {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
@@ -222,7 +232,9 @@ const PinMap PinMap_SPI_SSEL[] = {
     {P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)},
     {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
     {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
+    {P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
     {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
+    {P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
     {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
     {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
     {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
@@ -445,20 +457,14 @@ const PinMap PinMap_PWM_OUT[] = {
 
 #if DEVICE_ANALOGIN
 const PinMap PinMap_ADC[] = {
-    {P9_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},  // The SAR ADC Vplus input connects to the P9_0 pin through the AMUXA bus
-    {P9_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},  // The SAR ADC Vplus input connects to the P9_1 pin through the AMUXA bus
-    {P9_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},  // The SAR ADC Vplus input connects to the P9_2 pin through the AMUXA bus
-    {P9_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},  // The SAR ADC Vplus input connects to the P9_4 pin through the AMUXA bus
-    {P9_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},  // The SAR ADC Vplus input connects to the P9_5 pin through the AMUXA bus
-    {P9_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},  // The SAR ADC Vplus input connects to the P9_6 pin through the AMUXA bus
-    {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_0 pin
-    {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_1 pin
-    {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_2 pin
-    {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_3 pin
-    {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_4 pin
-    {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_5 pin
-    {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_6 pin
-    {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_7 pin
+    {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
+    {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
     {NC,    NC,     0}
 };
 #endif // DEVICE_ANALOGIN
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h
deleted file mode 100644
index c6a2238ed63..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h
+++ /dev/null
@@ -1,537 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.h
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PINS_H)
-#define CYCFG_PINS_H
-
-#include "cycfg_notices.h"
-#include "cy_gpio.h"
-#include "cycfg_routing.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_WCO_IN_ENABLED 1U
-#define CYBSP_WCO_IN_PORT GPIO_PRT0
-#define CYBSP_WCO_IN_PIN 0U
-#define CYBSP_WCO_IN_NUM 0U
-#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_0_HSIOM
-	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_WCO_OUT_ENABLED 1U
-#define CYBSP_WCO_OUT_PORT GPIO_PRT0
-#define CYBSP_WCO_OUT_PIN 1U
-#define CYBSP_WCO_OUT_NUM 1U
-#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_1_HSIOM
-	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_BTN2_ENABLED 1U
-#define CYBSP_BTN2_PORT GPIO_PRT0
-#define CYBSP_BTN2_PIN 4U
-#define CYBSP_BTN2_NUM 4U
-#define CYBSP_BTN2_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_BTN2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_4_HSIOM
-	#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BTN2_HSIOM ioss_0_port_0_pin_4_HSIOM
-#define CYBSP_BTN2_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_QSPI_SS_ENABLED 1U
-#define CYBSP_QSPI_SS_PORT GPIO_PRT11
-#define CYBSP_QSPI_SS_PIN 2U
-#define CYBSP_QSPI_SS_NUM 2U
-#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_2_HSIOM
-	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
-#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_DATA3_ENABLED 1U
-#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11
-#define CYBSP_QSPI_DATA3_PIN 3U
-#define CYBSP_QSPI_DATA3_NUM 3U
-#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_3_HSIOM
-	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
-#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_DATA2_ENABLED 1U
-#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11
-#define CYBSP_QSPI_DATA2_PIN 4U
-#define CYBSP_QSPI_DATA2_NUM 4U
-#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_4_HSIOM
-	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
-#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_DATA1_ENABLED 1U
-#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11
-#define CYBSP_QSPI_DATA1_PIN 5U
-#define CYBSP_QSPI_DATA1_NUM 5U
-#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_5_HSIOM
-	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
-#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_DATA0_ENABLED 1U
-#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11
-#define CYBSP_QSPI_DATA0_PIN 6U
-#define CYBSP_QSPI_DATA0_NUM 6U
-#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_6_HSIOM
-	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
-#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SCK_ENABLED 1U
-#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
-#define CYBSP_QSPI_SCK_PIN 7U
-#define CYBSP_QSPI_SCK_NUM 7U
-#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_7_HSIOM
-	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
-#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_LED_RED_ENABLED 1U
-#define CYBSP_LED_RED_PORT GPIO_PRT13
-#define CYBSP_LED_RED_PIN 7U
-#define CYBSP_LED_RED_NUM 7U
-#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_RED_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_13_pin_7_HSIOM
-	#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_RED_HSIOM ioss_0_port_13_pin_7_HSIOM
-#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_13_IRQn
-#define CYBSP_CSD_TX_ENABLED 1U
-#define CYBSP_CSD_TX_PORT GPIO_PRT1
-#define CYBSP_CSD_TX_PIN 0U
-#define CYBSP_CSD_TX_NUM 0U
-#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_0_HSIOM
-	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_WIFI_SDIO_DAT0_ENABLED 1U
-#define CYBSP_WIFI_SDIO_DAT0_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_DAT0_PIN 0U
-#define CYBSP_WIFI_SDIO_DAT0_NUM 0U
-#define CYBSP_WIFI_SDIO_DAT0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_DAT0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_0_HSIOM
-	#define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM
-#define CYBSP_WIFI_SDIO_DAT0_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_DAT1_ENABLED 1U
-#define CYBSP_WIFI_SDIO_DAT1_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_DAT1_PIN 1U
-#define CYBSP_WIFI_SDIO_DAT1_NUM 1U
-#define CYBSP_WIFI_SDIO_DAT1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_DAT1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_1_HSIOM
-	#define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM
-#define CYBSP_WIFI_SDIO_DAT1_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_DAT2_ENABLED 1U
-#define CYBSP_WIFI_SDIO_DAT2_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_DAT2_PIN 2U
-#define CYBSP_WIFI_SDIO_DAT2_NUM 2U
-#define CYBSP_WIFI_SDIO_DAT2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_DAT2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_2_HSIOM
-	#define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM
-#define CYBSP_WIFI_SDIO_DAT2_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_DAT3_ENABLED 1U
-#define CYBSP_WIFI_SDIO_DAT3_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_DAT3_PIN 3U
-#define CYBSP_WIFI_SDIO_DAT3_NUM 3U
-#define CYBSP_WIFI_SDIO_DAT3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_DAT3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_3_HSIOM
-	#define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM
-#define CYBSP_WIFI_SDIO_DAT3_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_CMD_ENABLED 1U
-#define CYBSP_WIFI_SDIO_CMD_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_CMD_PIN 4U
-#define CYBSP_WIFI_SDIO_CMD_NUM 4U
-#define CYBSP_WIFI_SDIO_CMD_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_CMD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_4_HSIOM
-	#define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
-#define CYBSP_WIFI_SDIO_CMD_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_CLK_ENABLED 1U
-#define CYBSP_WIFI_SDIO_CLK_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_CLK_PIN 5U
-#define CYBSP_WIFI_SDIO_CLK_NUM 5U
-#define CYBSP_WIFI_SDIO_CLK_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_CLK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_5_HSIOM
-	#define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
-#define CYBSP_WIFI_SDIO_CLK_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_BT_UART_RX_ENABLED 1U
-#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
-#define CYBSP_BT_UART_RX_PIN 0U
-#define CYBSP_BT_UART_RX_NUM 0U
-#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_0_HSIOM
-	#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
-#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_TX_ENABLED 1U
-#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
-#define CYBSP_BT_UART_TX_PIN 1U
-#define CYBSP_BT_UART_TX_NUM 1U
-#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_1_HSIOM
-	#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
-#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_RTS_ENABLED 1U
-#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
-#define CYBSP_BT_UART_RTS_PIN 2U
-#define CYBSP_BT_UART_RTS_NUM 2U
-#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_2_HSIOM
-	#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
-#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_CTS_ENABLED 1U
-#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
-#define CYBSP_BT_UART_CTS_PIN 3U
-#define CYBSP_BT_UART_CTS_NUM 3U
-#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_3_HSIOM
-	#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
-#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_POWER_ENABLED 1U
-#define CYBSP_BT_POWER_PORT GPIO_PRT3
-#define CYBSP_BT_POWER_PIN 4U
-#define CYBSP_BT_POWER_NUM 4U
-#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
-#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_4_HSIOM
-	#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
-#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_HOST_WAKE_ENABLED 1U
-#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
-#define CYBSP_BT_HOST_WAKE_PIN 5U
-#define CYBSP_BT_HOST_WAKE_NUM 5U
-#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_3_pin_5_HSIOM
-	#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
-#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
-#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
-#define CYBSP_BT_DEVICE_WAKE_PIN 0U
-#define CYBSP_BT_DEVICE_WAKE_NUM 0U
-#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_4_pin_0_HSIOM
-	#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
-#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
-#define CYBSP_DEBUG_UART_RX_ENABLED 1U
-#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_RX_PIN 0U
-#define CYBSP_DEBUG_UART_RX_NUM 0U
-#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_0_HSIOM
-	#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
-#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_DEBUG_UART_TX_ENABLED 1U
-#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
-#define CYBSP_DEBUG_UART_TX_PIN 1U
-#define CYBSP_DEBUG_UART_TX_NUM 1U
-#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_1_HSIOM
-	#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
-#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
-#define CYBSP_EZI2C_SCL_ENABLED 1U
-#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SCL_PIN 0U
-#define CYBSP_EZI2C_SCL_NUM 0U
-#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_0_HSIOM
-	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
-#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_EZI2C_SDA_ENABLED 1U
-#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SDA_PIN 1U
-#define CYBSP_EZI2C_SDA_NUM 1U
-#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_1_HSIOM
-	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
-#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWO_ENABLED 1U
-#define CYBSP_SWO_PORT GPIO_PRT6
-#define CYBSP_SWO_PIN 4U
-#define CYBSP_SWO_NUM 4U
-#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_SWO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_4_HSIOM
-	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDIO_ENABLED 1U
-#define CYBSP_SWDIO_PORT GPIO_PRT6
-#define CYBSP_SWDIO_PIN 6U
-#define CYBSP_SWDIO_NUM 6U
-#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SWDIO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_6_HSIOM
-	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDCK_ENABLED 1U
-#define CYBSP_SWDCK_PORT GPIO_PRT6
-#define CYBSP_SWDCK_PIN 7U
-#define CYBSP_SWDCK_NUM 7U
-#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define CYBSP_SWDCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_7_HSIOM
-	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_CINA_ENABLED 1U
-#define CYBSP_CINA_PORT GPIO_PRT7
-#define CYBSP_CINA_PIN 1U
-#define CYBSP_CINA_NUM 1U
-#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_1_HSIOM
-	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
-#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CINB_ENABLED 1U
-#define CYBSP_CINB_PORT GPIO_PRT7
-#define CYBSP_CINB_PIN 2U
-#define CYBSP_CINB_NUM 2U
-#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINB_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_2_HSIOM
-	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
-#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CMOD_ENABLED 1U
-#define CYBSP_CMOD_PORT GPIO_PRT7
-#define CYBSP_CMOD_PIN 7U
-#define CYBSP_CMOD_NUM 7U
-#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CMOD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_7_HSIOM
-	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
-#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CSD_BTN0_ENABLED 1U
-#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN0_PIN 1U
-#define CYBSP_CSD_BTN0_NUM 1U
-#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_1_HSIOM
-	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_BTN1_ENABLED 1U
-#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN1_PIN 2U
-#define CYBSP_CSD_BTN1_NUM 2U
-#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_2_HSIOM
-	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
-#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD0_ENABLED 1U
-#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD0_PIN 3U
-#define CYBSP_CSD_SLD0_NUM 3U
-#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_3_HSIOM
-	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD1_ENABLED 1U
-#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD1_PIN 4U
-#define CYBSP_CSD_SLD1_NUM 4U
-#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_4_HSIOM
-	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
-#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD2_ENABLED 1U
-#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD2_PIN 5U
-#define CYBSP_CSD_SLD2_NUM 5U
-#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_5_HSIOM
-	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
-#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD3_ENABLED 1U
-#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD3_PIN 6U
-#define CYBSP_CSD_SLD3_NUM 6U
-#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_6_HSIOM
-	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
-#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD4_ENABLED 1U
-#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD4_PIN 7U
-#define CYBSP_CSD_SLD4_NUM 7U
-#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_7_HSIOM
-	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
-#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
-
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BTN2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
-
-void init_cycfg_pins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PINS_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.c
deleted file mode 100644
index 25d22aef505..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_qspi_memslot.c
-*
-* Description:
-* Provides definitions of the SMIF-driver memory configuration.
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_qspi_memslot.h"
-
-cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xECU,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_QUAD,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0x01U,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_QUAD,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 8U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_QUAD
-};
-
-cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeEnCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x06U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeDisCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x04U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_eraseCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x21U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_chipEraseCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x60U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_programCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x12U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegQeCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x35U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegWipCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x05U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeStsRegQeCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x01U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-cy_stc_smif_mem_device_cfg_t deviceCfg_S25HL512T_SlaveSlot_0 =
-{
-    /* Specifies the number of address bytes used by the memory slave device. */
-    .numOfAddrBytes = 0x04U,
-    /* The size of the memory. */
-    .memSize = 0x04000000U,
-    /* Specifies the Read command. */
-    .readCmd = &S25HL512T_SlaveSlot_0_readCmd,
-    /* Specifies the Write Enable command. */
-    .writeEnCmd = &S25HL512T_SlaveSlot_0_writeEnCmd,
-    /* Specifies the Write Disable command. */
-    .writeDisCmd = &S25HL512T_SlaveSlot_0_writeDisCmd,
-    /* Specifies the Erase command. */
-    .eraseCmd = &S25HL512T_SlaveSlot_0_eraseCmd,
-    /* Specifies the sector size of each erase. */
-    .eraseSize = 0x0001000U,
-    /* Specifies the Chip Erase command. */
-    .chipEraseCmd = &S25HL512T_SlaveSlot_0_chipEraseCmd,
-    /* Specifies the Program command. */
-    .programCmd = &S25HL512T_SlaveSlot_0_programCmd,
-    /* Specifies the page size for programming. */
-    .programSize = 0x0000100U,
-    /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = &S25HL512T_SlaveSlot_0_readStsRegQeCmd,
-    /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = &S25HL512T_SlaveSlot_0_readStsRegWipCmd,
-    /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = &S25HL512T_SlaveSlot_0_writeStsRegQeCmd,
-    /* The mask for the status register. */
-    .stsRegBusyMask = 0x01U,
-    /* The mask for the status register. */
-    .stsRegQuadEnableMask = 0x02U,
-    /* The max time for the erase type-1 cycle-time in ms. */
-    .eraseTime = 42U,
-    /* The max time for the chip-erase cycle-time in ms. */
-    .chipEraseTime = 201000U,
-    /* The max time for the page-program cycle-time in us. */
-    .programTime = 418U
-};
-
-const cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_0 =
-{
-    /* Determines the slot number where the memory device is placed. */
-    .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
-    /* Flags. */
-    .flags = CY_SMIF_FLAG_WR_EN,
-    /* The data-line selection options for a slave device. */
-    .dataSelect = CY_SMIF_DATA_SEL0,
-    /* The base address the memory slave is mapped to in the PSoC memory map.
-    Valid when the memory-mapped mode is enabled. */
-    .baseAddress = 0x18000000U,
-    /* The size allocated in the PSoC memory map, for the memory slave device.
-    The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
-    .memMappedSize = 0x10000U,
-    /* If this memory device is one of the devices in the dual quad SPI configuration.
-    Valid when the memory mapped mode is enabled. */
-    .dualQuadSlots = 0,
-    /* The configuration of the device. */
-    .deviceCfg = &deviceCfg_S25HL512T_SlaveSlot_0
-};
-
-const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
-   &S25HL512T_SlaveSlot_0
-};
-
-const cy_stc_smif_block_config_t smifBlockConfig =
-{
-    /* The number of SMIF memories defined. */
-    .memCount = CY_SMIF_DEVICE_NUM,
-    /* The pointer to the array of memory config structures of size memCount. */
-    .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
-    /* The version of the SMIF driver. */
-    .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
-    /* The version of the SMIF driver. */
-    .minorVersion = CY_SMIF_DRV_VERSION_MINOR
-};
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/qspi_config.cfg
deleted file mode 100644
index a561643dcf1..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/qspi_config.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-set SMIF_BANKS {
-}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
index 4cac0dd77d0..edd03e2bf1c 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
@@ -3,7 +3,7 @@
 ; to pass a scatter file through a C preprocessor.
 
 ;*******************************************************************************
-;* \file cy8c6xxa_cm4_dual.scat
+;* \file cy8c6xxa_cm4_dual.sct
 ;* \version 2.50
 ;*
 ;* Linker file for the ARMCC.
@@ -173,7 +173,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
     RW_RAM_DATA +0
     {
         * (.cy_ramfunc)
-        .ANY (+RW, +ZI)
+        * (+RW, +ZI)
     }
 
     ; Place variables in the section that should not be initialized during the
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
new file mode 100644
index 00000000000..6911b5befd4
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
@@ -0,0 +1,24 @@
+/*******************************************************************************
+* File Name: cycfg.timestamp
+*
+* Description:
+* Sentinel file for determining if generated source is up to date.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
similarity index 54%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
index b9306818f3a..3639c4da05d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
@@ -24,26 +24,52 @@
 
 #include "cycfg_clocks.h"
 
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_BT_UART_CLK_DIV_HW,
+		.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+
 
 void init_cycfg_clocks(void)
 {
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
-
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 35U);
 	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
similarity index 72%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
index 34da2e34d96..30aec8b8b40 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
@@ -27,6 +27,9 @@
 
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 
 #if defined(__cplusplus)
 extern "C" {
@@ -38,9 +41,19 @@ extern "C" {
 #define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
-#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
+#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_BT_UART_CLK_DIV_NUM 3U
+
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_clocks(void);
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_notices.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
similarity index 68%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
index 2c05696e1cb..022f8d72083 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
@@ -56,6 +56,14 @@ const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
 	.txFifoTriggerLevel = 63UL,
 	.txFifoIntEnableMask = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = 
 {
 	.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
@@ -64,51 +72,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
 	.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
 	.enableWakeFromSleep = false,
 };
-const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = 
-{
-	.uartMode = CY_SCB_UART_STANDARD,
-	.enableMutliProcessorMode = false,
-	.smartCardRetryOnNack = false,
-	.irdaInvertRx = false,
-	.irdaEnableLowPowerReceiver = false,
-	.oversample = 12,
-	.enableMsbFirst = false,
-	.dataWidth = 9UL,
-	.parity = CY_SCB_UART_PARITY_NONE,
-	.stopBits = CY_SCB_UART_STOP_BITS_1,
-	.enableInputFilter = false,
-	.breakWidth = 11UL,
-	.dropOnFrameError = false,
-	.dropOnParityError = false,
-	.receiverAddress = 0x0UL,
-	.receiverAddressMask = 0x0UL,
-	.acceptAddrInFifo = false,
-	.enableCts = false,
-	.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rtsRxFifoLevel = 0UL,
-	.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rxFifoTriggerLevel = 63UL,
-	.rxFifoIntEnableMask = 0UL,
-	.txFifoTriggerLevel = 63UL,
-	.txFifoIntEnableMask = 0UL,
-};
-cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity = CY_SD_HOST_SDSC;
-cy_en_sd_host_card_type_t CYBSP_RADIO_cardType = CY_SD_HOST_NOT_EMMC;
-uint32_t CYBSP_RADIO_rca = 0u;
-const cy_stc_sd_host_init_config_t CYBSP_RADIO_config = 
-{
-	.emmc = false,
-	.dmaType = CY_SD_HOST_DMA_SDMA,
-	.enableLedControl = false,
-};
-cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg = 
-{
-	.lowVoltageSignaling = false,
-	.busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT,
-	.cardType = &CYBSP_RADIO_cardType,
-	.rca = &CYBSP_RADIO_rca,
-	.cardCapacity = &CYBSP_RADIO_cardCapacity,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_smif_config_t CYBSP_QSPI_config = 
 {
 	.mode = (uint32_t)CY_SMIF_NORMAL,
@@ -116,6 +87,14 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
 	.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
 	.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_obj = 
+	{
+		.type = CYHAL_RSC_SMIF,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config = 
 {
 	.c0Match = 32768U,
@@ -129,6 +108,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
 	.c0c1Cascade = true,
 	.c1c2Cascade = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_MCWDT0_obj = 
+	{
+		.type = CYHAL_RSC_LPTIMER,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_rtc_config_t CYBSP_RTC_config = 
 {
 	.sec = 0U,
@@ -141,15 +128,39 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
 	.month = CY_RTC_JANUARY,
 	.year = 0U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_RTC_obj = 
+	{
+		.type = CYHAL_RSC_RTC,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_peripherals(void)
 {
 	Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
+	Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
similarity index 86%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
index 24a66b86c5f..2749cb0f4b6 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
@@ -29,9 +29,12 @@
 #include "cy_sysclk.h"
 #include "cy_csd.h"
 #include "cy_scb_uart.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_scb_ezi2c.h"
-#include "cy_sd_host.h"
 #include "cy_smif.h"
+#include "cycfg_qspi_memslot.h"
 #include "cy_mcwdt.h"
 #include "cy_rtc.h"
 
@@ -81,12 +84,6 @@ extern "C" {
 #define CYBSP_CSD_COMM_ENABLED 1U
 #define CYBSP_CSD_COMM_HW SCB3
 #define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
-#define CYBSP_DEBUG_UART_ENABLED 1U
-#define CYBSP_DEBUG_UART_HW SCB5
-#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
-#define CYBSP_RADIO_ENABLED 1U
-#define CYBSP_RADIO_HW SDHC0
-#define CYBSP_RADIO_IRQ sdhc_0_interrupt_general_IRQn
 #define CYBSP_QSPI_ENABLED 1U
 #define CYBSP_QSPI_HW SMIF0
 #define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@@ -119,16 +116,25 @@ extern "C" {
 
 extern cy_stc_csd_context_t cy_csd_0_context;
 extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
-extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
-extern cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity;
-extern cy_en_sd_host_card_type_t CYBSP_RADIO_cardType;
-extern uint32_t CYBSP_RADIO_rca;
-extern const cy_stc_sd_host_init_config_t CYBSP_RADIO_config;
-extern cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_rtc_config_t CYBSP_RTC_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_RTC_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_peripherals(void);
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
similarity index 58%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
index 43b7426f580..998cc3792f8 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
@@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_IN_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_IN_PORT_NUM,
+		.channel_num = CYBSP_WCO_IN_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = 
 {
 	.outVal = 1,
@@ -56,22 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_BTN2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_PULLUP,
-	.hsiom = CYBSP_BTN2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_OUT_PORT_NUM,
+		.channel_num = CYBSP_WCO_OUT_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = 
 {
 	.outVal = 1,
@@ -88,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SS_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config = 
 {
 	.outVal = 1,
@@ -104,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_DATA3_PORT_NUM,
+		.channel_num = CYBSP_QSPI_DATA3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config = 
 {
 	.outVal = 1,
@@ -120,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_DATA2_PORT_NUM,
+		.channel_num = CYBSP_QSPI_DATA2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config = 
 {
 	.outVal = 1,
@@ -136,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_DATA1_PORT_NUM,
+		.channel_num = CYBSP_QSPI_DATA1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config = 
 {
 	.outVal = 1,
@@ -152,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_DATA0_PORT_NUM,
+		.channel_num = CYBSP_QSPI_DATA0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = 
 {
 	.outVal = 1,
@@ -168,22 +208,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_RED_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SCK_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = 
 {
 	.outVal = 1,
@@ -200,102 +232,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT0_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_DAT0_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT1_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_DAT1_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_DAT2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT3_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_DAT3_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_CMD_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_CLK_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_TX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_TX_PORT_NUM,
+		.channel_num = CYBSP_CSD_TX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = 
 {
 	.outVal = 1,
@@ -312,6 +256,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_RX_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_RX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = 
 {
 	.outVal = 1,
@@ -328,6 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_TX_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_TX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = 
 {
 	.outVal = 1,
@@ -344,6 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_RTS_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_RTS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = 
 {
 	.outVal = 1,
@@ -360,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_CTS_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_CTS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config = 
 {
 	.outVal = 1,
@@ -376,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_POWER_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_POWER_PORT_NUM,
+		.channel_num = CYBSP_BT_POWER_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = 
 {
 	.outVal = 0,
@@ -392,6 +376,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
+		.channel_num = CYBSP_BT_HOST_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config = 
 {
 	.outVal = 0,
@@ -408,38 +400,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_HIGHZ,
-	.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM,
+		.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = 
 {
 	.outVal = 1,
@@ -456,6 +424,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SCL_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = 
 {
 	.outVal = 1,
@@ -472,6 +448,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SDA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWO_config = 
 {
 	.outVal = 1,
@@ -488,6 +472,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWO_PORT_NUM,
+		.channel_num = CYBSP_SWO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = 
 {
 	.outVal = 1,
@@ -504,6 +496,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDIO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDIO_PORT_NUM,
+		.channel_num = CYBSP_SWDIO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = 
 {
 	.outVal = 1,
@@ -520,6 +520,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDCK_PORT_NUM,
+		.channel_num = CYBSP_SWDCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINA_config = 
 {
 	.outVal = 1,
@@ -536,6 +544,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINA_PORT_NUM,
+		.channel_num = CYBSP_CINA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINB_config = 
 {
 	.outVal = 1,
@@ -552,6 +568,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINB_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINB_PORT_NUM,
+		.channel_num = CYBSP_CINB_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = 
 {
 	.outVal = 1,
@@ -568,6 +592,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CMOD_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CMOD_PORT_NUM,
+		.channel_num = CYBSP_CMOD_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = 
 {
 	.outVal = 1,
@@ -584,6 +616,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN0_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = 
 {
 	.outVal = 1,
@@ -600,6 +640,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN1_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = 
 {
 	.outVal = 1,
@@ -616,6 +664,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD0_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = 
 {
 	.outVal = 1,
@@ -632,6 +688,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD1_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = 
 {
 	.outVal = 1,
@@ -648,6 +712,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD2_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = 
 {
 	.outVal = 1,
@@ -664,6 +736,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD3_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = 
 {
 	.outVal = 1,
@@ -680,78 +760,159 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD4_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD4_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_pins(void)
 {
 	Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_BTN2_PORT, CYBSP_BTN2_PIN, &CYBSP_BTN2_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA3_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA2_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA1_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA0_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
-
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT0_PORT, CYBSP_WIFI_SDIO_DAT0_PIN, &CYBSP_WIFI_SDIO_DAT0_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT1_PORT, CYBSP_WIFI_SDIO_DAT1_PIN, &CYBSP_WIFI_SDIO_DAT1_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT2_PORT, CYBSP_WIFI_SDIO_DAT2_PIN, &CYBSP_WIFI_SDIO_DAT2_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT3_PORT, CYBSP_WIFI_SDIO_DAT3_PIN, &CYBSP_WIFI_SDIO_DAT3_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CMD_PORT, CYBSP_WIFI_SDIO_CMD_PIN, &CYBSP_WIFI_SDIO_CMD_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CLK_PORT, CYBSP_WIFI_SDIO_CLK_PIN, &CYBSP_WIFI_SDIO_CLK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
new file mode 100644
index 00000000000..685d0687bd3
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
@@ -0,0 +1,916 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cycfg_notices.h"
+#include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cycfg_routing.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PORT_NUM 0U
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_0_HSIOM
+	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PORT_NUM 0U
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_1_HSIOM
+	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SS_ENABLED 1U
+#define CYBSP_QSPI_SS_PORT GPIO_PRT11
+#define CYBSP_QSPI_SS_PORT_NUM 11U
+#define CYBSP_QSPI_SS_PIN 2U
+#define CYBSP_QSPI_SS_NUM 2U
+#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_2_HSIOM
+	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
+#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_DATA3_ENABLED 1U
+#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA3_PORT_NUM 11U
+#define CYBSP_QSPI_DATA3_PIN 3U
+#define CYBSP_QSPI_DATA3_NUM 3U
+#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_3_HSIOM
+	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
+#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA3_HAL_PORT_PIN P11_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_DATA2_ENABLED 1U
+#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA2_PORT_NUM 11U
+#define CYBSP_QSPI_DATA2_PIN 4U
+#define CYBSP_QSPI_DATA2_NUM 4U
+#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_4_HSIOM
+	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
+#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA2_HAL_PORT_PIN P11_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_DATA1_ENABLED 1U
+#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA1_PORT_NUM 11U
+#define CYBSP_QSPI_DATA1_PIN 5U
+#define CYBSP_QSPI_DATA1_NUM 5U
+#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_5_HSIOM
+	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
+#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA1_HAL_PORT_PIN P11_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_DATA0_ENABLED 1U
+#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA0_PORT_NUM 11U
+#define CYBSP_QSPI_DATA0_PIN 6U
+#define CYBSP_QSPI_DATA0_NUM 6U
+#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_6_HSIOM
+	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
+#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA0_HAL_PORT_PIN P11_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_DATA0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SCK_ENABLED 1U
+#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
+#define CYBSP_QSPI_SCK_PORT_NUM 11U
+#define CYBSP_QSPI_SCK_PIN 7U
+#define CYBSP_QSPI_SCK_NUM 7U
+#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_7_HSIOM
+	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_TX_ENABLED 1U
+#define CYBSP_CSD_TX_PORT GPIO_PRT1
+#define CYBSP_CSD_TX_PORT_NUM 1U
+#define CYBSP_CSD_TX_PIN 0U
+#define CYBSP_CSD_TX_NUM 0U
+#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_0_HSIOM
+	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_PORT_PIN P1_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_RX_ENABLED 1U
+#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RX_PORT_NUM 3U
+#define CYBSP_BT_UART_RX_PIN 0U
+#define CYBSP_BT_UART_RX_NUM 0U
+#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_0_HSIOM
+	#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
+#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_TX_ENABLED 1U
+#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_TX_PORT_NUM 3U
+#define CYBSP_BT_UART_TX_PIN 1U
+#define CYBSP_BT_UART_TX_NUM 1U
+#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_1_HSIOM
+	#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
+#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_RTS_ENABLED 1U
+#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RTS_PORT_NUM 3U
+#define CYBSP_BT_UART_RTS_PIN 2U
+#define CYBSP_BT_UART_RTS_NUM 2U
+#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_2_HSIOM
+	#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
+#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_CTS_ENABLED 1U
+#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_CTS_PORT_NUM 3U
+#define CYBSP_BT_UART_CTS_PIN 3U
+#define CYBSP_BT_UART_CTS_NUM 3U
+#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_3_HSIOM
+	#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
+#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_POWER_ENABLED 1U
+#define CYBSP_BT_POWER_PORT GPIO_PRT3
+#define CYBSP_BT_POWER_PORT_NUM 3U
+#define CYBSP_BT_POWER_PIN 4U
+#define CYBSP_BT_POWER_NUM 4U
+#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
+#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_4_HSIOM
+	#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
+#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_PORT_PIN P3_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_HOST_WAKE_ENABLED 1U
+#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
+#define CYBSP_BT_HOST_WAKE_PORT_NUM 3U
+#define CYBSP_BT_HOST_WAKE_PIN 5U
+#define CYBSP_BT_HOST_WAKE_NUM 5U
+#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_3_pin_5_HSIOM
+	#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
+#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P3_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
+#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
+#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 4U
+#define CYBSP_BT_DEVICE_WAKE_PIN 0U
+#define CYBSP_BT_DEVICE_WAKE_NUM 0U
+#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_4_pin_0_HSIOM
+	#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
+#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P4_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SCL_ENABLED 1U
+#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SCL_PORT_NUM 6U
+#define CYBSP_EZI2C_SCL_PIN 0U
+#define CYBSP_EZI2C_SCL_NUM 0U
+#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_0_HSIOM
+	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
+#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SDA_ENABLED 1U
+#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SDA_PORT_NUM 6U
+#define CYBSP_EZI2C_SDA_PIN 1U
+#define CYBSP_EZI2C_SDA_NUM 1U
+#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_1_HSIOM
+	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
+#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PORT_NUM 6U
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_4_HSIOM
+	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_PORT_PIN P6_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PORT_NUM 6U
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_6_HSIOM
+	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDCK_ENABLED 1U
+#define CYBSP_SWDCK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PORT_NUM 6U
+#define CYBSP_SWDCK_PIN 7U
+#define CYBSP_SWDCK_NUM 7U
+#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_7_HSIOM
+	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINA_ENABLED 1U
+#define CYBSP_CINA_PORT GPIO_PRT7
+#define CYBSP_CINA_PORT_NUM 7U
+#define CYBSP_CINA_PIN 1U
+#define CYBSP_CINA_NUM 1U
+#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_1_HSIOM
+	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_PORT_PIN P7_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINB_ENABLED 1U
+#define CYBSP_CINB_PORT GPIO_PRT7
+#define CYBSP_CINB_PORT_NUM 7U
+#define CYBSP_CINB_PIN 2U
+#define CYBSP_CINB_NUM 2U
+#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINB_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_2_HSIOM
+	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_PORT_PIN P7_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PORT_NUM 7U
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_7_HSIOM
+	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_PORT_PIN P7_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN0_PORT_NUM 8U
+#define CYBSP_CSD_BTN0_PIN 1U
+#define CYBSP_CSD_BTN0_NUM 1U
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_1_HSIOM
+	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN1_PORT_NUM 8U
+#define CYBSP_CSD_BTN1_PIN 2U
+#define CYBSP_CSD_BTN1_NUM 2U
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_2_HSIOM
+	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD0_PORT_NUM 8U
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_3_HSIOM
+	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD1_PORT_NUM 8U
+#define CYBSP_CSD_SLD1_PIN 4U
+#define CYBSP_CSD_SLD1_NUM 4U
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_4_HSIOM
+	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD2_PORT_NUM 8U
+#define CYBSP_CSD_SLD2_PIN 5U
+#define CYBSP_CSD_SLD2_NUM 5U
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_5_HSIOM
+	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD3_PORT_NUM 8U
+#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_6_HSIOM
+	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD4_PORT_NUM 8U
+#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_7_HSIOM
+	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINB_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
similarity index 81%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
index 12487034d72..c4e5bcf916f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
@@ -24,10 +24,10 @@
 
 #include "cycfg_qspi_memslot.h"
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xEBU,
+    .command = 0xECU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -42,7 +42,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x06U,
@@ -60,7 +60,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x04U,
@@ -78,10 +78,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xD8U,
+    .command = 0xDCU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -96,7 +96,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x60U,
@@ -114,10 +114,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x38U,
+    .command = 0x34U,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -132,7 +132,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
     .dataWidth = CY_SMIF_WIDTH_QUAD
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x35U,
@@ -150,7 +150,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x05U,
@@ -168,7 +168,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
     .command = 0x01U,
@@ -186,52 +186,52 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
     .dataWidth = CY_SMIF_WIDTH_SINGLE
 };
 
-cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Specifies the number of address bytes used by the memory slave device. */
-    .numOfAddrBytes = 0x03U,
+    .numOfAddrBytes = 0x04U,
     /* The size of the memory. */
     .memSize = 0x04000000U,
     /* Specifies the Read command. */
-    .readCmd = &S25FL512S_SlaveSlot_0_readCmd,
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
     /* Specifies the Write Enable command. */
-    .writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
     /* Specifies the Write Disable command. */
-    .writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
     /* Specifies the Erase command. */
-    .eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
     /* Specifies the sector size of each erase. */
     .eraseSize = 0x00040000U,
     /* Specifies the Chip Erase command. */
-    .chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
     /* Specifies the Program command. */
-    .programCmd = &S25FL512S_SlaveSlot_0_programCmd,
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
     /* Specifies the page size for programming. */
     .programSize = 0x00000200U,
     /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
     /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
     /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
     /* The mask for the status register. */
     .stsRegBusyMask = 0x01U,
     /* The mask for the status register. */
     .stsRegQuadEnableMask = 0x02U,
     /* The max time for the erase type-1 cycle-time in ms. */
-    .eraseTime = 520U,
+    .eraseTime = 2600U,
     /* The max time for the chip-erase cycle-time in ms. */
-    .chipEraseTime = 134000U,
+    .chipEraseTime = 460000U,
     /* The max time for the page-program cycle-time in us. */
-    .programTime = 340U
+    .programTime = 1300U
 };
 
-const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
+const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
 {
     /* Determines the slot number where the memory device is placed. */
     .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
     /* Flags. */
-    .flags = CY_SMIF_FLAG_WR_EN,
+    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
     /* The data-line selection options for a slave device. */
     .dataSelect = CY_SMIF_DATA_SEL0,
     /* The base address the memory slave is mapped to in the PSoC memory map.
@@ -239,16 +239,16 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
     .baseAddress = 0x18000000U,
     /* The size allocated in the PSoC memory map, for the memory slave device.
     The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
-    .memMappedSize = 0x10000U,
+    .memMappedSize = 0x4000000U,
     /* If this memory device is one of the devices in the dual quad SPI configuration.
     Valid when the memory mapped mode is enabled. */
     .dualQuadSlots = 0,
     /* The configuration of the device. */
-    .deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
 };
 
-const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
-   &S25FL512S_SlaveSlot_0
+const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
+   &S25FL512SX4byteaddr_SlaveSlot_0
 };
 
 const cy_stc_smif_block_config_t smifBlockConfig =
@@ -262,3 +262,4 @@ const cy_stc_smif_block_config_t smifBlockConfig =
     /* The version of the SMIF driver. */
     .minorVersion = CY_SMIF_DRV_VERSION_MINOR
 };
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
similarity index 57%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
index 1f4fb5dfcae..32f9b49b2e6 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
@@ -28,22 +28,23 @@
 
 #define CY_SMIF_DEVICE_NUM 1
 
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
 
-extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
 
-extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
-extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
+extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
 
 extern const cy_stc_smif_block_config_t smifBlockConfig;
 
 
 #endif /*CY_SMIF_MEMCONFIG_H*/
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
similarity index 65%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
index 16be9931a13..a72bfb0020b 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
@@ -40,50 +40,27 @@ void init_cycfg_routing(void);
 #define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
 #define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
 #define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
-#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD
-#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD
 #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_2_pin_0_HSIOM P2_0_DSI_DSI
-#define ioss_0_port_2_pin_1_HSIOM P2_1_DSI_DSI
-#define ioss_0_port_2_pin_2_HSIOM P2_2_DSI_DSI
-#define ioss_0_port_2_pin_3_HSIOM P2_3_DSI_DSI
-#define ioss_0_port_2_pin_4_HSIOM P2_4_DSI_DSI
-#define ioss_0_port_2_pin_5_HSIOM P2_5_DSI_GPIO
 #define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
 #define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
 #define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
 #define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
-#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
-#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
 #define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
 #define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
 #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
 #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
 #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
-#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
 
-#define CYBSP_SDIO_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
-#define CYBSP_SDIO_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0
-#define CYBSP_SDIO_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT4
-#define CYBSP_SDIO_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
-#define CYBSP_SDIO_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3
-#define CYBSP_SDIO_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
-#define CYBSP_SDIO_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
-#define CYBSP_SDIO_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT1
-#define cpuss_0_dw0_0_chan_0_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN0
-#define cpuss_0_dw0_0_chan_1_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN1
-#define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1
-#define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3
-
 #if defined(__cplusplus)
 }
 #endif
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
similarity index 83%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
index b17c36bbc32..89e36dce129 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
@@ -38,6 +38,9 @@
 #define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
 #define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
 #define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH2
 #define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
 #define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
 #define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
@@ -57,6 +60,7 @@
 #define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1
 #define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
 #define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
+#define CY_CFG_SYSCLK_PLL1_ENABLED 1
 #define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
 #define CY_CFG_SYSCLK_WCO_ENABLED 1
 #define CY_CFG_PWR_ENABLED 1
@@ -79,6 +83,62 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
 	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
 	.cco_Freq = 355U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 1U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 4U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 5U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = 
+{
+	.feedbackDiv = 30,
+	.referenceDiv = 1,
+	.outputDiv = 5,
+	.lfMode = false,
+	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
 
 __WEAK void cycfg_ClockStartupError(uint32_t error)
 {
@@ -115,6 +175,12 @@ __STATIC_INLINE void Cy_SysClk_ClkHf2Init()
     Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
     Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
 }
+__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
+}
 __STATIC_INLINE void Cy_SysClk_ClkHf4Init()
 {
     Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
@@ -160,6 +226,17 @@ __STATIC_INLINE void Cy_SysClk_ClkPeriInit()
 {
     Cy_SysClk_ClkPeriSetDivider(1U);
 }
+__STATIC_INLINE void Cy_SysClk_Pll1Init()
+{
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+}
 __STATIC_INLINE void Cy_SysClk_ClkSlowInit()
 {
     Cy_SysClk_ClkSlowSetDivider(0U);
@@ -487,4 +564,28 @@ void init_cycfg_system(void)
 	
 	/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
 	SystemCoreClockUpdate();
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
similarity index 75%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
index 75f065e2262..c3f4bf6b4a9 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
@@ -27,6 +27,9 @@
 
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_gpio.h"
 #include "cy_syspm.h"
 
@@ -43,6 +46,8 @@ extern "C" {
 #define CY_CFG_SYSCLK_CLKHF0 0UL
 #define srss_0_clock_0_hfclk_2_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF2 2UL
+#define srss_0_clock_0_hfclk_3_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF3 3UL
 #define srss_0_clock_0_hfclk_4_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF4 4UL
 #define srss_0_clock_0_ilo_0_ENABLED 1U
@@ -56,6 +61,7 @@ extern "C" {
 #define srss_0_clock_0_pathmux_4_ENABLED 1U
 #define srss_0_clock_0_pathmux_5_ENABLED 1U
 #define srss_0_clock_0_periclk_0_ENABLED 1U
+#define srss_0_clock_0_pll_1_ENABLED 1U
 #define srss_0_clock_0_slowclk_0_ENABLED 1U
 #define srss_0_clock_0_wco_0_ENABLED 1U
 #define srss_0_power_0_ENABLED 1U
@@ -75,6 +81,25 @@ extern "C" {
 #define CY_CFG_PWR_VDDIO0_MV 3300
 #define CY_CFG_PWR_VDDIO1_MV 3300
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj;
+#endif //defined (CY_USING_HAL)
+
 void init_cycfg_system(void);
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
new file mode 100644
index 00000000000..5557ddecddf
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
@@ -0,0 +1,4 @@
+set SMIF_BANKS {
+  0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+}
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
new file mode 100644
index 00000000000..239c647ba50
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
@@ -0,0 +1,78 @@
+<?xml version="1.0"?>
+<Configuration major="2" minor="0">
+    <!--
+       File Name: cycfg_capsense.cycapsense 
+
+       Description: 
+       CapSense middleware configuration 
+       This file should not be modified. It was automatically generated by 
+       CapSense Configurator 2.0.0 build 351 
+-->
+    <GeneralProperties>
+        <Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="REGULAR_IIR_RC_N" value="128"/>
+        <Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="PROX_IIR_RC_N" value="128"/>
+        <Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="REGULAR_IIR_BL_N" value="1"/>
+        <Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="PROX_IIR_BL_N" value="1"/>
+        <Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="MULTI_FREQ_SCAN_EN" value="false"/>
+        <Property id="SENSOR_AUTO_RESET_EN" value="false"/>
+        <Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
+        <Property id="VREF_SOURCE" value="SRSS"/>
+        <Property id="IREF_SOURCE" value="SRSS"/>
+        <Property id="PROX_TOUCH_COEFF" value="300"/>
+        <Property id="NUM_CENTROIDS" value="1"/>
+    </GeneralProperties>
+    <CsdProperties>
+        <Property id="CSD_AUTOTUNE" value="HWTH"/>
+        <Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
+        <Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
+        <Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
+        <Property id="CSD_IDAC_MIN" value="20"/>
+        <Property id="CSD_IDAC_COMP_EN" value="true"/>
+        <Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
+        <Property id="CSD_VREF_CUSTOM" value="false"/>
+        <Property id="CSD_VREF" value="1219"/>
+        <Property id="CSD_SHIELD_EN" value="false"/>
+        <Property id="CSD_SHIELD_TANK_EN" value="false"/>
+        <Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
+        <Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
+        <Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_FINE_INIT_TIME" value="10"/>
+        <Property id="CSD_CALIBRATION_ERROR" value="10"/>
+        <Property id="CSD_R_CONST" value="1000"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsdProperties>
+    <CsxProperties>
+        <Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSX_MAX_FINGERS" value="3"/>
+        <Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
+        <Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
+        <Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_FINE_INIT_TIME" value="10"/>
+        <Property id="CSX_CALIBRATION_ERROR" value="20"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsxProperties>
+    <Widgets/>
+</Configuration>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
new file mode 100644
index 00000000000..6df618b3a8d
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
+<Configuration app="QSPI" major="2" minor="0">
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <PartNumber>S25FL512S-4byteaddr</PartNumber>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x4000000</Size>
+            <EndAddress>0x1BFFFFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</Configuration>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus
similarity index 90%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/design.modus
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus
index 0e5a069a960..2f65153f2fe 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/design.modus
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus
@@ -2,13 +2,8 @@
 <Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
     <ToolInfo version="1.0.0"/>
     <Devices>
-        <Device mpn="CY8C6347BZI-BLD53">
+        <Device mpn="CY8C624ABZI-D44">
             <BlockConfig>
-                <Block location="bless[0]" alias="CYBSP_BLE" template="mxs40ble" version="1.1">
-                    <Param id="BleConfigurator" value="0"/>
-                    <Param id="BleSharing" value="0"/>
-                    <Param id="ExtPaLnaEnable" value="false"/>
-                </Block>
                 <Block location="cpuss[0].dap[0]" alias="" template="mxs40dap" version="1.0">
                     <Param id="dbgMode" value="SWD"/>
                     <Param id="traceEnable" value="false"/>
@@ -69,7 +64,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[0].pin[3]" alias="CYBSP_LED_RED" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -79,18 +74,8 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[0].pin[4]" alias="CYBSP_BTN2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[11].pin[1]" alias="CYBSP_LED_BLUE" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                <Block location="ioss[0].port[11].pin[3]" alias="CYBSP_QSPI_DATA3" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
@@ -99,8 +84,8 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                <Block location="ioss[0].port[11].pin[4]" alias="CYBSP_QSPI_DATA2" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
@@ -109,7 +94,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[3]" alias="CYBSP_QSPI_D3" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[11].pin[5]" alias="CYBSP_QSPI_DATA1" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -119,7 +104,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[4]" alias="CYBSP_QSPI_D2" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[11].pin[6]" alias="CYBSP_QSPI_DATA0" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -129,8 +114,8 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[5]" alias="CYBSP_QSPI_D1" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
+                <Block location="ioss[0].port[11].pin[7]" alias="CYBSP_QSPI_SCK" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
@@ -139,8 +124,8 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[6]" alias="CYBSP_QSPI_D0" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
+                <Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
@@ -149,8 +134,8 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[11].pin[7]" alias="CYBSP_QSPI_SCK" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                <Block location="ioss[0].port[3].pin[0]" alias="CYBSP_BT_UART_RX" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
@@ -159,7 +144,7 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[13].pin[7]" alias="CYBSP_LED9" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[3].pin[1]" alias="CYBSP_BT_UART_TX" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@@ -169,8 +154,8 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                <Block location="ioss[0].port[3].pin[2]" alias="CYBSP_BT_UART_RTS" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
@@ -179,8 +164,8 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[1].pin[1]" alias="CYBSP_LED_GREEN" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                <Block location="ioss[0].port[3].pin[3]" alias="CYBSP_BT_UART_CTS" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
@@ -189,8 +174,8 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[1].pin[5]" alias="CYBSP_LED8" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                <Block location="ioss[0].port[3].pin[4]" alias="CYBSP_BT_POWER" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF"/>
                     <Param id="initialState" value="1"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
@@ -199,9 +184,9 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[5].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
-                    <Param id="initialState" value="1"/>
+                <Block location="ioss[0].port[3].pin[5]" alias="CYBSP_BT_HOST_WAKE" template="mxs40pin" version="1.1">
+                    <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                    <Param id="initialState" value="0"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
                     <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
@@ -209,9 +194,9 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[5].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
+                <Block location="ioss[0].port[4].pin[0]" alias="CYBSP_BT_DEVICE_WAKE" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
+                    <Param id="initialState" value="0"/>
                     <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
                     <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
@@ -375,40 +360,31 @@
                     <Param id="startOnReset" value="true"/>
                 </Block>
                 <Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="8"/>
+                    <Param id="intDivider" value="4"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
-                <Block location="peri[0].div_8[2]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
-                    <Param id="intDivider" value="109"/>
+                <Block location="peri[0].div_8[3]" alias="CYBSP_BT_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
+                    <Param id="intDivider" value="36"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
-                <Block location="scb[3]" alias="CYBSP_CSD_COMM" template="mxs40ezi2c" version="1.0">
-                    <Param id="DataRate" value="100"/>
-                    <Param id="NumOfAddr" value="CY_SCB_EZI2C_ONE_ADDRESS"/>
-                    <Param id="SlaveAddress1" value="8"/>
-                    <Param id="SlaveAddress2" value="9"/>
-                    <Param id="SubAddrSize" value="CY_SCB_EZI2C_SUB_ADDR16_BITS"/>
-                    <Param id="EnableWakeup" value="false"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
+                <Block location="scb[2]" alias="CYBSP_BT_UART" template="mxs40uart" version="1.0">
                     <Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
                     <Param id="IrdaLowPower" value="false"/>
                     <Param id="BaudRate" value="115200"/>
-                    <Param id="Oversample" value="8"/>
+                    <Param id="Oversample" value="12"/>
                     <Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
                     <Param id="DataWidth" value="8"/>
                     <Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
                     <Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
                     <Param id="EnableInputFilter" value="false"/>
                     <Param id="EnableTxEn" value="false"/>
-                    <Param id="FlowControl" value="false"/>
+                    <Param id="FlowControl" value="true"/>
                     <Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
                     <Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
                     <Param id="RtsTriggerLevel" value="63"/>
-                    <Param id="RxTriggerLevel" value="63"/>
+                    <Param id="RxTriggerLevel" value="1"/>
                     <Param id="TxTriggerLevel" value="63"/>
                     <Param id="MultiProc" value="false"/>
                     <Param id="MpRxAddress" value="0"/>
@@ -438,8 +414,17 @@
                     <Param id="IntrTxUnderflow" value="false"/>
                     <Param id="IntrTxTrigger" value="false"/>
                 </Block>
+                <Block location="scb[3]" alias="CYBSP_CSD_COMM" template="mxs40ezi2c" version="1.0">
+                    <Param id="DataRate" value="100"/>
+                    <Param id="NumOfAddr" value="CY_SCB_EZI2C_ONE_ADDRESS"/>
+                    <Param id="SlaveAddress1" value="8"/>
+                    <Param id="SlaveAddress2" value="9"/>
+                    <Param id="SubAddrSize" value="CY_SCB_EZI2C_SUB_ADDR16_BITS"/>
+                    <Param id="EnableWakeup" value="false"/>
+                    <Param id="inFlash" value="true"/>
+                </Block>
                 <Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
-                    <Param id="configurator" value="0"/>
+                    <Param id="configurator" value=""/>
                     <Param id="isrAlignment" value="false"/>
                     <Param id="isrUnderflow" value="false"/>
                     <Param id="isrCmdOverflow" value="false"/>
@@ -449,9 +434,6 @@
                     <Param id="inFlash" value="true"/>
                 </Block>
                 <Block location="srss[0].clock[0]" alias="" template="mxs40sysclocks" version="1.2"/>
-                <Block location="srss[0].clock[0].altsystickclk[0]" alias="" template="mxs40altsystick" version="1.0">
-                    <Param id="sourceClock" value="lfclk"/>
-                </Block>
                 <Block location="srss[0].clock[0].bakclk[0]" alias="" template="mxs40bakclk" version="1.0">
                     <Param id="sourceClock" value="wco"/>
                 </Block>
@@ -466,16 +448,16 @@
                     <Param id="sourceClockNumber" value="0"/>
                     <Param id="divider" value="1"/>
                 </Block>
-                <Block location="srss[0].clock[0].hfclk[1]" alias="" template="mxs40hfclk" version="1.1">
-                    <Param id="sourceClockNumber" value="1"/>
-                    <Param id="divider" value="1"/>
-                </Block>
                 <Block location="srss[0].clock[0].hfclk[2]" alias="" template="mxs40hfclk" version="1.1">
                     <Param id="sourceClockNumber" value="0"/>
                     <Param id="divider" value="2"/>
                 </Block>
                 <Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
-                    <Param id="sourceClockNumber" value="1"/>
+                    <Param id="sourceClockNumber" value="2"/>
+                    <Param id="divider" value="1"/>
+                </Block>
+                <Block location="srss[0].clock[0].hfclk[4]" alias="" template="mxs40hfclk" version="1.1">
+                    <Param id="sourceClockNumber" value="0"/>
                     <Param id="divider" value="1"/>
                 </Block>
                 <Block location="srss[0].clock[0].ilo[0]" alias="" template="mxs40ilo" version="1.0">
@@ -502,10 +484,13 @@
                 <Block location="srss[0].clock[0].pathmux[4]" alias="" template="mxs40pathmux" version="1.0">
                     <Param id="sourceClock" value="imo"/>
                 </Block>
+                <Block location="srss[0].clock[0].pathmux[5]" alias="" template="mxs40pathmux" version="1.0">
+                    <Param id="sourceClock" value="imo"/>
+                </Block>
                 <Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
-                    <Param id="divider" value="1"/>
+                    <Param id="divider" value="2"/>
                 </Block>
-                <Block location="srss[0].clock[0].pll[0]" alias="" template="mxs40pll" version="1.0">
+                <Block location="srss[0].clock[0].pll[1]" alias="" template="mxs40pll" version="1.0">
                     <Param id="lowFrequencyMode" value="false"/>
                     <Param id="configuration" value="auto"/>
                     <Param id="desiredFrequency" value="48.000"/>
@@ -514,10 +499,6 @@
                 <Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
                     <Param id="divider" value="1"/>
                 </Block>
-                <Block location="srss[0].clock[0].timerclk[0]" alias="" template="mxs40timerclk" version="1.0">
-                    <Param id="sourceClock" value="imo"/>
-                    <Param id="timerDivider" value="1"/>
-                </Block>
                 <Block location="srss[0].clock[0].wco[0]" alias="" template="mxs40wco" version="1.0">
                     <Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
                     <Param id="clockLostDetection" value="false"/>
@@ -607,12 +588,20 @@
                     <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
                 </Net>
                 <Net>
-                    <Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
-                    <Port name="scb[5].uart_rx[0]"/>
+                    <Port name="ioss[0].port[3].pin[0].digital_inout[0]"/>
+                    <Port name="scb[2].uart_rx[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[3].pin[1].digital_inout[0]"/>
+                    <Port name="scb[2].uart_tx[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[3].pin[2].digital_out[0]"/>
+                    <Port name="scb[2].uart_rts[0]"/>
                 </Net>
                 <Net>
-                    <Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
-                    <Port name="scb[5].uart_tx[0]"/>
+                    <Port name="ioss[0].port[3].pin[3].digital_in[0]"/>
+                    <Port name="scb[2].uart_cts[0]"/>
                 </Net>
                 <Net>
                     <Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
@@ -651,8 +640,8 @@
                     <Port name="scb[3].clock[0]"/>
                 </Net>
                 <Net>
-                    <Port name="peri[0].div_8[2].clk[0]"/>
-                    <Port name="scb[5].clock[0]"/>
+                    <Port name="peri[0].div_8[3].clk[0]"/>
+                    <Port name="scb[2].clock[0]"/>
                 </Net>
                 <Net>
                     <Port name="smif[0].clk_hf[0]"/>
@@ -702,6 +691,10 @@
                 </Mux>
             </Netlist>
         </Device>
+        <Device mpn="CYW4343WKUBG">
+            <BlockConfig/>
+            <Netlist/>
+        </Device>
     </Devices>
     <Libraries>
         <Library name="psoc6sw" version="1.2"/>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/PinNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/PinNames.h
similarity index 74%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/PinNames.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/PinNames.h
index 4b3a79b30de..b0624156a25 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/PinNames.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/PinNames.h
@@ -20,13 +20,8 @@
 #ifndef MBED_PINNAMES_H
 #define MBED_PINNAMES_H
 
-#include "cmsis.h"
 #include "PinNamesTypes.h"
-#include "PortNames.h"
 #include "cyhal_pin_package.h"
-#include "cyhal_utils.h"
-
-typedef cyhal_gpio_t PinName;
 
 // Generic signal names
 
@@ -38,23 +33,15 @@ typedef cyhal_gpio_t PinName;
 #define UART_RTS P5_2
 #define UART_CTS P5_3
 
-#define BT_UART_RX P3_0
-#define BT_UART_TX P3_1
-#define BT_UART_CTS P3_3
-#define BT_UART_RTS P3_2
-
-#define BT_PIN_POWER P3_4
-#define BT_PIN_HOST_WAKE P3_5
-#define BT_PIN_DEVICE_WAKE P4_0
 // Reset pin unavailable
 
-#define SWITCH2 P0_4
 #define LED1 P13_7
 #define LED2 NC
 #define LED3 NC
 #define LED4 NC
 #define LED_RED LED1
 
+#define SWITCH2 P0_4
 #define USER_BUTTON SWITCH2
 #define BUTTON1 USER_BUTTON
 
@@ -96,23 +83,7 @@ typedef cyhal_gpio_t PinName;
 #define STDIO_UART_CTS UART_CTS
 #define STDIO_UART_RTS UART_RTS
 
-#define CY_STDIO_UART_RX STDIO_UART_RX
-#define CY_STDIO_UART_TX STDIO_UART_TX
-#define CY_STDIO_UART_CTS STDIO_UART_CTS
-#define CY_STDIO_UART_RTS STDIO_UART_RTS
-
-#define CY_BT_UART_RX BT_UART_RX
-#define CY_BT_UART_TX BT_UART_TX
-#define CY_BT_UART_CTS BT_UART_CTS
-#define CY_BT_UART_RTS BT_UART_RTS
-
-#define CY_BT_PIN_POWER BT_PIN_POWER
-#define CY_BT_PIN_HOST_WAKE BT_PIN_HOST_WAKE
-#define CY_BT_PIN_DEVICE_WAKE BT_PIN_DEVICE_WAKE
-
 #define USBTX UART_TX
 #define USBRX UART_RX
 
-#define CY_WIFI_HOST_WAKE P2_7
-
 #endif
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.c
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.c
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.h
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_cy8cproto_062_4343w.h
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h
similarity index 59%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_types.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h
index 1c0ba6c8e69..dbe43d4c36e 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/cybsp_types.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h
@@ -23,14 +23,6 @@
 * limitations under the License.
 *******************************************************************************/
 
-/**
-* \addtogroup group_bsp_cy8cproto_062_4343w CY8CPROTO-062-4343W
-* \ingroup group_bsp
-* \{
-* \defgroup group_bsp_cy8cproto_062_4343w_macros Macros
-* \defgroup group_bsp_cy8cproto_062_4343w_enums Enumerated Types
-*/
-
 #pragma once
 
 #include "cyhal.h"
@@ -40,56 +32,94 @@ extern "C" {
 #endif
 
 /**
-* \addtogroup group_bsp_cy8cproto_062_4343w_macros
+* \addtogroup group_bsp_pins Pin Mappings
 * \{
 */
 
 /** Pin: WIFI SDIO D0 */
+/* Corresponds to: ioss[0].port[2].pin[0], sdhc[0] */
 #define CYBSP_WIFI_SDIO_D0     P2_0
 /** Pin: WIFI SDIO D1 */
+/* Corresponds to: ioss[0].port[2].pin[1], sdhc[0] */
 #define CYBSP_WIFI_SDIO_D1     P2_1
 /** Pin: WIFI SDIO D2 */
+/* Corresponds to: ioss[0].port[2].pin[2], sdhc[0] */
 #define CYBSP_WIFI_SDIO_D2     P2_2
 /** Pin: WIFI SDIO D3 */
+/* Corresponds to: ioss[0].port[2].pin[3], sdhc[0] */
 #define CYBSP_WIFI_SDIO_D3     P2_3
 /** Pin: WIFI SDIO CMD */
+/* Corresponds to: ioss[0].port[2].pin[4], sdhc[0] */
 #define CYBSP_WIFI_SDIO_CMD    P2_4
 /** Pin: WIFI SDIO CLK */
+/* Corresponds to: ioss[0].port[2].pin[5], sdhc[0] */
 #define CYBSP_WIFI_SDIO_CLK    P2_5
 /** Pin: WIFI ON */
+/* Corresponds to: ioss[0].port[2].pin[6], sdhc[0] */
 #define CYBSP_WIFI_WL_REG_ON   P2_6
 /** Pin: WIFI Host Wakeup */
-#define CYBSP_WIFI_HOST_WAKE   P1_4
+#define CYBSP_WIFI_HOST_WAKE   P0_4
+
+/** Pin: BT UART RX */
+#define CYBSP_BT_UART_RX       P3_0
+/** Pin: BT UART TX */
+#define CYBSP_BT_UART_TX       P3_1
+/** Pin: BT UART RTS */
+#define CYBSP_BT_UART_RTS      P3_2
+/** Pin: BT UART CTS */
+#define CYBSP_BT_UART_CTS      P3_3
+
+/** Pin: BT Power */
+#define CYBSP_BT_POWER         P3_4
+/** Pin: BT Host Wakeup */
+#define CYBSP_BT_HOST_WAKE     P4_0
+/** Pin: BT Device Wakeup */
+#define CYBSP_BT_DEVICE_WAKE   P3_5
 
 /** Pin: UART RX */
+/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
 #define CYBSP_DEBUG_UART_RX    P5_0
 /** Pin: UART TX */
+/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
 #define CYBSP_DEBUG_UART_TX    P5_1
 
+/** Pin: QUAD SPI SS */
+#define CYBSP_QSPI_SS          P11_2
+/** Pin: QUAD SPI D3 */
+#define CYBSP_QSPI_D3          P11_3
+/** Pin: QUAD SPI D2 */
+#define CYBSP_QSPI_D2          P11_4
+/** Pin: QUAD SPI D1 */
+#define CYBSP_QSPI_D1          P11_5
+/** Pin: QUAD SPI D0 */
+#define CYBSP_QSPI_D0          P11_6
+/** Pin: QUAD SPI SCK */
+#define CYBSP_QSPI_SCK         P11_7
+
 /** Host-wake GPIO drive mode */
 #define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG
 /** Host-wake IRQ event */
 #define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE
 
-/** \} group_bsp_cy8cproto_062_4343w_macros */
+/** \} group_bsp_pins */
 
 /**
-* \addtogroup group_bsp_cy8cproto_062_4343w_enums
+* \addtogroup group_bsp_enums Enumerated Types
 * \{
 */
 
 /** Enum defining the different states for the LED. */
 typedef enum
 {
-	CYBSP_LED_STATE_ON        	= 0,
-	CYBSP_LED_STATE_OFF        	= 1,
+    CYBSP_LED_STATE_ON          = 0,
+    CYBSP_LED_STATE_OFF         = 1,
 } cybsp_led_state_t;
 
 /** Enum defining the different states for a button. */
 typedef enum
 {
-	CYBSP_BTN_PRESSED  	      	= 0,
-	CYBSP_BTN_OFF	          	= 1,
+    CYBSP_BTN_PRESSED           = 0,
+    CYBSP_BTN_OFF               = 1,
 } cybsp_btn_state_t;
 
 /** Enum defining the different LED pins on the board. */
@@ -97,6 +127,7 @@ typedef enum
 {
     CYBSP_LED_RED = P13_7,
 
+    /* Corresponds to: ioss[0].port[13].pin[7] */
     CYBSP_USER_LED1 = CYBSP_LED_RED,
     CYBSP_USER_LED = CYBSP_USER_LED1,
 } cybsp_led_t;
@@ -106,14 +137,13 @@ typedef enum
 {
     CYBSP_SW2 = P0_4,
     
+    /* Corresponds to: ioss[0].port[0].pin[4] */
     CYBSP_USER_BTN1 = CYBSP_SW2,
     CYBSP_USER_BTN = CYBSP_USER_BTN1,
 } cybsp_btn_t;
 
-/** \} group_bsp_cy8cproto_062_4343w_enums */
+/** \} group_bsp_enums */
 
 #if defined(__cplusplus)
 }
 #endif
-
-/** \} group_bsp_cy8cproto_062_4343w */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
similarity index 98%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
index cb430a41643..cda6d4025b1 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
@@ -28,6 +28,7 @@ void init_cycfg_all(void)
 {
 	init_cycfg_system();
 	init_cycfg_clocks();
+	init_cycfg_dmas();
 	init_cycfg_routing();
 	init_cycfg_peripherals();
 	init_cycfg_pins();
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
new file mode 100644
index 00000000000..6911b5befd4
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
@@ -0,0 +1,24 @@
+/*******************************************************************************
+* File Name: cycfg.timestamp
+*
+* Description:
+* Sentinel file for determining if generated source is up to date.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
new file mode 100644
index 00000000000..54d1df91cbd
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
@@ -0,0 +1,135 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.c
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_clocks.h"
+
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_UART_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_USB_UART_CLK_DIV_HW,
+		.channel_num = CYBSP_USB_UART_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SDIO_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_SDIO_CLK_DIV_HW,
+		.channel_num = CYBSP_SDIO_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t peri_0_div_8_3_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = peri_0_div_8_3_HW,
+		.channel_num = peri_0_div_8_3_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_CSD_CLK_DIV_HW,
+		.channel_num = CYBSP_CSD_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SPI_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_SPI_CLK_DIV_HW,
+		.channel_num = CYBSP_SPI_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WL_UART_CLK_DIV_obj = 
+	{
+		.type = CYHAL_RSC_CLOCK,
+		.block_num = CYBSP_WL_UART_CLK_DIV_HW,
+		.channel_num = CYBSP_WL_UART_CLK_DIV_NUM,
+	};
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_clocks(void)
+{
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_UART_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SDIO_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 108U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&peri_0_div_8_3_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 255U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 5U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 5U, 6U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 5U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SPI_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+
+	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 6U);
+	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 6U, 108U);
+	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 6U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WL_UART_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
similarity index 66%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
index 96a4bf51aa7..c1e5915eb07 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
@@ -27,6 +27,9 @@
 
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 
 #if defined(__cplusplus)
 extern "C" {
@@ -41,9 +44,9 @@ extern "C" {
 #define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
-#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
-#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
+#define peri_0_div_8_3_ENABLED 1U
+#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
+#define peri_0_div_8_3_NUM 3U
 #define CYBSP_CSD_CLK_DIV_ENABLED 1U
 #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_CSD_CLK_DIV_NUM 4U
@@ -54,6 +57,28 @@ extern "C" {
 #define CYBSP_WL_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #define CYBSP_WL_UART_CLK_DIV_NUM 6U
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_UART_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SDIO_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t peri_0_div_8_3_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SPI_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WL_UART_CLK_DIV_obj;
+#endif //defined (CY_USING_HAL)
+
 void init_cycfg_clocks(void);
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
similarity index 78%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
index a8e9de3e069..8d869195513 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
@@ -62,6 +62,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig =
 	.enable = false,
 	.bufferable = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj = 
+	{
+		.type = CYHAL_RSC_DMA,
+		.block_num = 0U,
+		.channel_num = cpuss_0_dw0_0_chan_0_CHANNEL,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config = 
 {
 	.retrigger = CY_DMA_RETRIG_16CYC,
@@ -100,6 +108,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig =
 	.enable = false,
 	.bufferable = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj = 
+	{
+		.type = CYHAL_RSC_DMA,
+		.block_num = 0U,
+		.channel_num = cpuss_0_dw0_0_chan_1_CHANNEL,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config = 
 {
 	.retrigger = CY_DMA_RETRIG_4CYC,
@@ -138,6 +154,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig =
 	.enable = false,
 	.bufferable = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj = 
+	{
+		.type = CYHAL_RSC_DMA,
+		.block_num = 1U,
+		.channel_num = cpuss_0_dw1_0_chan_1_CHANNEL,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config = 
 {
 	.retrigger = CY_DMA_RETRIG_IM,
@@ -176,4 +200,31 @@ const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig =
 	.enable = false,
 	.bufferable = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj = 
+	{
+		.type = CYHAL_RSC_DMA,
+		.block_num = 1U,
+		.channel_num = cpuss_0_dw1_0_chan_3_CHANNEL,
+	};
+#endif //defined (CY_USING_HAL)
 
+
+void init_cycfg_dmas(void)
+{
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
similarity index 78%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
index 69a805e9598..d6c0d6587db 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
@@ -27,6 +27,9 @@
 
 #include "cycfg_notices.h"
 #include "cy_dma.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 
 #if defined(__cplusplus)
 extern "C" {
@@ -34,34 +37,47 @@ extern "C" {
 
 #define cpuss_0_dw0_0_chan_0_ENABLED 1U
 #define cpuss_0_dw0_0_chan_0_HW DW0
-#define cpuss_0_dw0_0_chan_0_CHANNEL 0
+#define cpuss_0_dw0_0_chan_0_CHANNEL 0U
 #define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
 #define cpuss_0_dw0_0_chan_1_ENABLED 1U
 #define cpuss_0_dw0_0_chan_1_HW DW0
-#define cpuss_0_dw0_0_chan_1_CHANNEL 1
+#define cpuss_0_dw0_0_chan_1_CHANNEL 1U
 #define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
 #define cpuss_0_dw1_0_chan_1_ENABLED 1U
 #define cpuss_0_dw1_0_chan_1_HW DW1
-#define cpuss_0_dw1_0_chan_1_CHANNEL 1
+#define cpuss_0_dw1_0_chan_1_CHANNEL 1U
 #define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
 #define cpuss_0_dw1_0_chan_3_ENABLED 1U
 #define cpuss_0_dw1_0_chan_3_HW DW1
-#define cpuss_0_dw1_0_chan_3_CHANNEL 3
+#define cpuss_0_dw1_0_chan_3_CHANNEL 3U
 #define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
 
 extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config;
 extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0;
 extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config;
 extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0;
 extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config;
 extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0;
 extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config;
 extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0;
 extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj;
+#endif //defined (CY_USING_HAL)
 
+void init_cycfg_dmas(void);
 
 #if defined(__cplusplus)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_notices.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
similarity index 73%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
index 3d665baafd1..6103597ac7d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
@@ -66,6 +66,14 @@ const cy_stc_scb_spi_config_t CYBSP_SPI_config =
 	.txFifoIntEnableMask = 0UL,
 	.masterSlaveIntEnableMask = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SPI_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 1U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = 
 {
 	.uartMode = CY_SCB_UART_STANDARD,
@@ -94,6 +102,14 @@ const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
 	.txFifoTriggerLevel = 63UL,
 	.txFifoIntEnableMask = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = 
 {
 	.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
@@ -102,6 +118,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
 	.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
 	.enableWakeFromSleep = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_scb_uart_config_t CYBSP_WL_UART_config = 
 {
 	.uartMode = CY_SCB_UART_STANDARD,
@@ -130,34 +154,14 @@ const cy_stc_scb_uart_config_t CYBSP_WL_UART_config =
 	.txFifoTriggerLevel = 63UL,
 	.txFifoIntEnableMask = 0UL,
 };
-const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = 
-{
-	.uartMode = CY_SCB_UART_STANDARD,
-	.enableMutliProcessorMode = false,
-	.smartCardRetryOnNack = false,
-	.irdaInvertRx = false,
-	.irdaEnableLowPowerReceiver = false,
-	.oversample = 8,
-	.enableMsbFirst = false,
-	.dataWidth = 8UL,
-	.parity = CY_SCB_UART_PARITY_NONE,
-	.stopBits = CY_SCB_UART_STOP_BITS_1,
-	.enableInputFilter = false,
-	.breakWidth = 11UL,
-	.dropOnFrameError = false,
-	.dropOnParityError = false,
-	.receiverAddress = 0x0UL,
-	.receiverAddressMask = 0x0UL,
-	.acceptAddrInFifo = false,
-	.enableCts = false,
-	.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rtsRxFifoLevel = 0UL,
-	.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
-	.rxFifoTriggerLevel = 63UL,
-	.rxFifoIntEnableMask = 0UL,
-	.txFifoTriggerLevel = 63UL,
-	.txFifoIntEnableMask = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WL_UART_obj = 
+	{
+		.type = CYHAL_RSC_SCB,
+		.block_num = 5U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_smif_config_t CYBSP_QSPI_config = 
 {
 	.mode = (uint32_t)CY_SMIF_NORMAL,
@@ -165,6 +169,14 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
 	.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
 	.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_obj = 
+	{
+		.type = CYHAL_RSC_SMIF,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config = 
 {
 	.c0Match = 32768U,
@@ -178,6 +190,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
 	.c0c1Cascade = true,
 	.c1c2Cascade = false,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_MCWDT0_obj = 
+	{
+		.type = CYHAL_RSC_LPTIMER,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_rtc_config_t CYBSP_RTC_config = 
 {
 	.sec = 0U,
@@ -190,6 +210,14 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
 	.month = CY_RTC_JANUARY,
 	.year = 0U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_RTC_obj = 
+	{
+		.type = CYHAL_RSC_RTC,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = 
 {
 	.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
@@ -207,6 +235,14 @@ const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
 	.enableLpm = false,
 	.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USBUART_obj = 
+	{
+		.type = CYHAL_RSC_USB,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_peripherals(void)
@@ -214,16 +250,39 @@ void init_cycfg_peripherals(void)
 	Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_SCB1_CLOCK, CY_SYSCLK_DIV_8_BIT, 5U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SPI_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
+	Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 6U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WL_UART_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_SCB6_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
+#endif //defined (CY_USING_HAL)
 
-	Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
similarity index 83%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
index b0503ad9f67..d02d6fc9044 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
@@ -29,9 +29,13 @@
 #include "cy_sysclk.h"
 #include "cy_csd.h"
 #include "cy_scb_spi.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_scb_uart.h"
 #include "cy_scb_ezi2c.h"
 #include "cy_smif.h"
+#include "cycfg_qspi_memslot.h"
 #include "cy_mcwdt.h"
 #include "cy_rtc.h"
 #include "cy_usbfs_dev_drv.h"
@@ -88,9 +92,6 @@ extern "C" {
 #define CYBSP_WL_UART_ENABLED 1U
 #define CYBSP_WL_UART_HW SCB5
 #define CYBSP_WL_UART_IRQ scb_5_interrupt_IRQn
-#define CYBSP_DEBUG_UART_ENABLED 1U
-#define CYBSP_DEBUG_UART_HW SCB6
-#define CYBSP_DEBUG_UART_IRQ scb_6_interrupt_IRQn
 #define CYBSP_QSPI_ENABLED 1U
 #define CYBSP_QSPI_HW SMIF0
 #define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@@ -120,7 +121,6 @@ extern "C" {
 #define CYBSP_RTC_100_YEAR_OFFSET (8U)
 #define CYBSP_RTC_10_YEAR_OFFSET (4U)
 #define CYBSP_RTC_YEAR_OFFSET (0U)
-#define CYBSP_SDIO_ENABLED 1U
 #define CYBSP_USBUART_ENABLED 1U
 #define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 7U
 #define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 140U
@@ -133,14 +133,37 @@ extern "C" {
 
 extern cy_stc_csd_context_t cy_csd_0_context;
 extern const cy_stc_scb_spi_config_t CYBSP_SPI_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SPI_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_scb_uart_config_t CYBSP_WL_UART_config;
-extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WL_UART_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_rtc_config_t CYBSP_RTC_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_RTC_obj;
+#endif //defined (CY_USING_HAL)
 extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
+#endif //defined (CY_USING_HAL)
 
 void init_cycfg_peripherals(void);
 
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
similarity index 58%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
index 3832d774f67..5605f4b0bd9 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
@@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_IN_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_IN_PORT_NUM,
+		.channel_num = CYBSP_WCO_IN_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = 
 {
 	.outVal = 1,
@@ -56,38 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_RED_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_SW6_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_PULLUP,
-	.hsiom = CYBSP_SW6_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WCO_OUT_PORT_NUM,
+		.channel_num = CYBSP_WCO_OUT_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_ROW6_SPI_MOSI_config = 
 {
 	.outVal = 1,
@@ -104,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_ROW6_SPI_MOSI_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_ROW6_SPI_MOSI_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_ROW6_SPI_MOSI_PORT_NUM,
+		.channel_num = CYBSP_ROW6_SPI_MOSI_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_COL8_SPI_MISO_config = 
 {
 	.outVal = 1,
@@ -120,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_COL8_SPI_MISO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_COL8_SPI_MISO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_COL8_SPI_MISO_PORT_NUM,
+		.channel_num = CYBSP_COL8_SPI_MISO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_ROW7_SPI_CLK_config = 
 {
 	.outVal = 1,
@@ -136,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_ROW7_SPI_CLK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_ROW7_SPI_CLK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_ROW7_SPI_CLK_PORT_NUM,
+		.channel_num = CYBSP_ROW7_SPI_CLK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_COL7_SPI_CS_config = 
 {
 	.outVal = 1,
@@ -152,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_COL7_SPI_CS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_COL7_SPI_CS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_COL7_SPI_CS_PORT_NUM,
+		.channel_num = CYBSP_COL7_SPI_CS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BAT_MON_config = 
 {
 	.outVal = 1,
@@ -168,22 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BAT_MON_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_BLUE_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BAT_MON_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BAT_MON_PORT_NUM,
+		.channel_num = CYBSP_BAT_MON_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WL_WAKE_config = 
 {
 	.outVal = 1,
@@ -200,6 +208,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WL_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WL_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WL_WAKE_PORT_NUM,
+		.channel_num = CYBSP_WL_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WL_UART_RX_config = 
 {
 	.outVal = 1,
@@ -216,6 +232,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WL_UART_RX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WL_UART_RX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WL_UART_RX_PORT_NUM,
+		.channel_num = CYBSP_WL_UART_RX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WL_UART_TX_config = 
 {
 	.outVal = 1,
@@ -232,6 +256,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WL_UART_TX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WL_UART_TX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WL_UART_TX_PORT_NUM,
+		.channel_num = CYBSP_WL_UART_TX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = 
 {
 	.outVal = 1,
@@ -248,6 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SS_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = 
 {
 	.outVal = 1,
@@ -264,6 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D3_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = 
 {
 	.outVal = 1,
@@ -280,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D2_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = 
 {
 	.outVal = 1,
@@ -296,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D1_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = 
 {
 	.outVal = 1,
@@ -312,6 +376,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_D0_PORT_NUM,
+		.channel_num = CYBSP_QSPI_D0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = 
 {
 	.outVal = 1,
@@ -328,6 +400,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_QSPI_SCK_PORT_NUM,
+		.channel_num = CYBSP_QSPI_SCK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO4_config = 
 {
 	.outVal = 1,
@@ -344,6 +424,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO4_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_GPIO4_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_GPIO4_PORT_NUM,
+		.channel_num = CYBSP_BT_GPIO4_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO5_config = 
 {
 	.outVal = 1,
@@ -360,6 +448,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO5_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_GPIO5_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_GPIO5_PORT_NUM,
+		.channel_num = CYBSP_BT_GPIO5_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO2_config = 
 {
 	.outVal = 1,
@@ -376,6 +472,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_GPIO2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_GPIO2_PORT_NUM,
+		.channel_num = CYBSP_BT_GPIO2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO3_config = 
 {
 	.outVal = 1,
@@ -392,6 +496,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_GPIO3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_GPIO3_PORT_NUM,
+		.channel_num = CYBSP_BT_GPIO3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = 
 {
 	.outVal = 1,
@@ -408,6 +520,14 @@ const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_ECO_IN_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_ECO_IN_PORT_NUM,
+		.channel_num = CYBSP_ECO_IN_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = 
 {
 	.outVal = 1,
@@ -424,38 +544,14 @@ const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_HIGHZ,
-	.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_ECO_OUT_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_ECO_OUT_PORT_NUM,
+		.channel_num = CYBSP_ECO_OUT_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_USB_DEV_VBUS_DET_config = 
 {
 	.outVal = 1,
@@ -472,6 +568,14 @@ const cy_stc_gpio_pin_config_t CYBSP_USB_DEV_VBUS_DET_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_DEV_VBUS_DET_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_USB_DEV_VBUS_DET_PORT_NUM,
+		.channel_num = CYBSP_USB_DEV_VBUS_DET_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_USB_HOST_EN_config = 
 {
 	.outVal = 1,
@@ -488,6 +592,14 @@ const cy_stc_gpio_pin_config_t CYBSP_USB_HOST_EN_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_HOST_EN_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_USB_HOST_EN_PORT_NUM,
+		.channel_num = CYBSP_USB_HOST_EN_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_USB_INT_L_config = 
 {
 	.outVal = 1,
@@ -504,6 +616,14 @@ const cy_stc_gpio_pin_config_t CYBSP_USB_INT_L_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_INT_L_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_USB_INT_L_PORT_NUM,
+		.channel_num = CYBSP_USB_INT_L_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = 
 {
 	.outVal = 1,
@@ -520,6 +640,14 @@ const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_DP_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_USB_DP_PORT_NUM,
+		.channel_num = CYBSP_USB_DP_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = 
 {
 	.outVal = 1,
@@ -536,6 +664,14 @@ const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_USB_DM_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_USB_DM_PORT_NUM,
+		.channel_num = CYBSP_USB_DM_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = 
 {
 	.outVal = 1,
@@ -552,22 +688,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_LED_GREEN_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_TX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_TX_PORT_NUM,
+		.channel_num = CYBSP_CSD_TX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_IN_config = 
 {
 	.outVal = 1,
@@ -584,6 +712,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_IN_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WL_SECI_IN_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WL_SECI_IN_PORT_NUM,
+		.channel_num = CYBSP_WL_SECI_IN_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WL_FRAM_SYNC_config = 
 {
 	.outVal = 1,
@@ -600,6 +736,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WL_FRAM_SYNC_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WL_FRAM_SYNC_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WL_FRAM_SYNC_PORT_NUM,
+		.channel_num = CYBSP_WL_FRAM_SYNC_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WL_PRIORITY_config = 
 {
 	.outVal = 1,
@@ -616,6 +760,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WL_PRIORITY_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WL_PRIORITY_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WL_PRIORITY_PORT_NUM,
+		.channel_num = CYBSP_WL_PRIORITY_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_OUT_config = 
 {
 	.outVal = 1,
@@ -632,118 +784,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_OUT_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_D0_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_D1_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_D2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_D3_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG,
-	.hsiom = CYBSP_WIFI_SDIO_CMD_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_WIFI_SDIO_CLK_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config = 
-{
-	.outVal = 0,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_WIFI_WL_REG_ON_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WL_SECI_OUT_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WL_SECI_OUT_PORT_NUM,
+		.channel_num = CYBSP_WL_SECI_OUT_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config = 
 {
 	.outVal = 1,
@@ -760,6 +808,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM,
+		.channel_num = CYBSP_WIFI_HOST_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = 
 {
 	.outVal = 1,
@@ -776,6 +832,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_RX_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_RX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = 
 {
 	.outVal = 1,
@@ -792,6 +856,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_TX_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_TX_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = 
 {
 	.outVal = 1,
@@ -808,6 +880,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_RTS_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_RTS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = 
 {
 	.outVal = 1,
@@ -824,6 +904,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_UART_CTS_PORT_NUM,
+		.channel_num = CYBSP_BT_UART_CTS_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_REG_ON_config = 
 {
 	.outVal = 1,
@@ -840,6 +928,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_REG_ON_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_REG_ON_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_REG_ON_PORT_NUM,
+		.channel_num = CYBSP_BT_REG_ON_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = 
 {
 	.outVal = 0,
@@ -856,6 +952,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
+		.channel_num = CYBSP_BT_HOST_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config = 
 {
 	.outVal = 0,
@@ -872,6 +976,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM,
+		.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_BT_RST_config = 
 {
 	.outVal = 1,
@@ -888,6 +1000,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_RST_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_BT_RST_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_BT_RST_PORT_NUM,
+		.channel_num = CYBSP_BT_RST_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = 
 {
 	.outVal = 1,
@@ -904,6 +1024,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SCL_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = 
 {
 	.outVal = 1,
@@ -920,6 +1048,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
+		.channel_num = CYBSP_EZI2C_SDA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWO_config = 
 {
 	.outVal = 1,
@@ -936,6 +1072,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWO_PORT_NUM,
+		.channel_num = CYBSP_SWO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = 
 {
 	.outVal = 1,
@@ -952,6 +1096,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWDIO_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWDIO_PORT_NUM,
+		.channel_num = CYBSP_SWDIO_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config = 
 {
 	.outVal = 1,
@@ -968,6 +1120,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_SWCLK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_SWCLK_PORT_NUM,
+		.channel_num = CYBSP_SWCLK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_TRACECLK_config = 
 {
 	.outVal = 1,
@@ -984,6 +1144,14 @@ const cy_stc_gpio_pin_config_t CYBSP_TRACECLK_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_TRACECLK_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_TRACECLK_PORT_NUM,
+		.channel_num = CYBSP_TRACECLK_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINTA_config = 
 {
 	.outVal = 1,
@@ -1000,6 +1168,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINTA_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINTA_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINTA_PORT_NUM,
+		.channel_num = CYBSP_CINTA_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CINTB_config = 
 {
 	.outVal = 1,
@@ -1016,6 +1192,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINTB_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CINTB_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CINTB_PORT_NUM,
+		.channel_num = CYBSP_CINTB_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = 
 {
 	.outVal = 1,
@@ -1032,6 +1216,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CMOD_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CMOD_PORT_NUM,
+		.channel_num = CYBSP_CMOD_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = 
 {
 	.outVal = 1,
@@ -1048,6 +1240,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN0_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = 
 {
 	.outVal = 1,
@@ -1064,6 +1264,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_BTN1_PORT_NUM,
+		.channel_num = CYBSP_CSD_BTN1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = 
 {
 	.outVal = 1,
@@ -1080,6 +1288,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD0_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = 
 {
 	.outVal = 1,
@@ -1096,6 +1312,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD1_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = 
 {
 	.outVal = 1,
@@ -1112,6 +1336,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD2_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = 
 {
 	.outVal = 1,
@@ -1128,6 +1360,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD3_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = 
 {
 	.outVal = 1,
@@ -1144,6 +1384,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_CSD_SLD4_PORT_NUM,
+		.channel_num = CYBSP_CSD_SLD4_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA3_config = 
 {
 	.outVal = 1,
@@ -1160,6 +1408,14 @@ const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA3_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_TRACEDATA3_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_TRACEDATA3_PORT_NUM,
+		.channel_num = CYBSP_TRACEDATA3_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA2_config = 
 {
 	.outVal = 1,
@@ -1176,6 +1432,14 @@ const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA2_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_TRACEDATA2_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_TRACEDATA2_PORT_NUM,
+		.channel_num = CYBSP_TRACEDATA2_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA1_config = 
 {
 	.outVal = 1,
@@ -1192,6 +1456,14 @@ const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA1_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_TRACEDATA1_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_TRACEDATA1_PORT_NUM,
+		.channel_num = CYBSP_TRACEDATA1_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA0_config = 
 {
 	.outVal = 1,
@@ -1208,144 +1480,309 @@ const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA0_config =
 	.vrefSel = 0UL,
 	.vohSel = 0UL,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t CYBSP_TRACEDATA0_obj = 
+	{
+		.type = CYHAL_RSC_GPIO,
+		.block_num = CYBSP_TRACEDATA0_PORT_NUM,
+		.channel_num = CYBSP_TRACEDATA0_PIN,
+	};
+#endif //defined (CY_USING_HAL)
 
 
 void init_cycfg_pins(void)
 {
 	Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_SW6_PORT, CYBSP_SW6_PIN, &CYBSP_SW6_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_ROW6_SPI_MOSI_PORT, CYBSP_ROW6_SPI_MOSI_PIN, &CYBSP_ROW6_SPI_MOSI_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_ROW6_SPI_MOSI_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_COL8_SPI_MISO_PORT, CYBSP_COL8_SPI_MISO_PIN, &CYBSP_COL8_SPI_MISO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_COL8_SPI_MISO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_ROW7_SPI_CLK_PORT, CYBSP_ROW7_SPI_CLK_PIN, &CYBSP_ROW7_SPI_CLK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_ROW7_SPI_CLK_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_COL7_SPI_CS_PORT, CYBSP_COL7_SPI_CS_PIN, &CYBSP_COL7_SPI_CS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_COL7_SPI_CS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BAT_MON_PORT, CYBSP_BAT_MON_PIN, &CYBSP_BAT_MON_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_BLUE_PORT, CYBSP_LED_BLUE_PIN, &CYBSP_LED_BLUE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BAT_MON_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WL_WAKE_PORT, CYBSP_WL_WAKE_PIN, &CYBSP_WL_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WL_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WL_UART_RX_PORT, CYBSP_WL_UART_RX_PIN, &CYBSP_WL_UART_RX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WL_UART_RX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WL_UART_TX_PORT, CYBSP_WL_UART_TX_PIN, &CYBSP_WL_UART_TX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WL_UART_TX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_GPIO4_PORT, CYBSP_BT_GPIO4_PIN, &CYBSP_BT_GPIO4_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_GPIO4_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_GPIO5_PORT, CYBSP_BT_GPIO5_PIN, &CYBSP_BT_GPIO5_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_GPIO5_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_GPIO2_PORT, CYBSP_BT_GPIO2_PIN, &CYBSP_BT_GPIO2_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_GPIO2_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_GPIO3_PORT, CYBSP_BT_GPIO3_PIN, &CYBSP_BT_GPIO3_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_GPIO3_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_ECO_IN_PORT, CYBSP_ECO_IN_PIN, &CYBSP_ECO_IN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_ECO_IN_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_ECO_OUT_PORT, CYBSP_ECO_OUT_PIN, &CYBSP_ECO_OUT_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_ECO_OUT_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_USB_DEV_VBUS_DET_PORT, CYBSP_USB_DEV_VBUS_DET_PIN, &CYBSP_USB_DEV_VBUS_DET_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_DEV_VBUS_DET_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_USB_HOST_EN_PORT, CYBSP_USB_HOST_EN_PIN, &CYBSP_USB_HOST_EN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_HOST_EN_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_USB_INT_L_PORT, CYBSP_USB_INT_L_PIN, &CYBSP_USB_INT_L_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_INT_L_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
+#endif //defined (CY_USING_HAL)
 
-
-	Cy_GPIO_Pin_Init(CYBSP_LED_GREEN_PORT, CYBSP_LED_GREEN_PIN, &CYBSP_LED_GREEN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WL_SECI_IN_PORT, CYBSP_WL_SECI_IN_PIN, &CYBSP_WL_SECI_IN_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WL_SECI_IN_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WL_FRAM_SYNC_PORT, CYBSP_WL_FRAM_SYNC_PIN, &CYBSP_WL_FRAM_SYNC_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WL_FRAM_SYNC_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WL_PRIORITY_PORT, CYBSP_WL_PRIORITY_PIN, &CYBSP_WL_PRIORITY_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WL_PRIORITY_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WL_SECI_OUT_PORT, CYBSP_WL_SECI_OUT_PIN, &CYBSP_WL_SECI_OUT_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D0_PORT, CYBSP_WIFI_SDIO_D0_PIN, &CYBSP_WIFI_SDIO_D0_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D1_PORT, CYBSP_WIFI_SDIO_D1_PIN, &CYBSP_WIFI_SDIO_D1_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D2_PORT, CYBSP_WIFI_SDIO_D2_PIN, &CYBSP_WIFI_SDIO_D2_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D3_PORT, CYBSP_WIFI_SDIO_D3_PIN, &CYBSP_WIFI_SDIO_D3_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CMD_PORT, CYBSP_WIFI_SDIO_CMD_PIN, &CYBSP_WIFI_SDIO_CMD_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CLK_PORT, CYBSP_WIFI_SDIO_CLK_PIN, &CYBSP_WIFI_SDIO_CLK_config);
-
-	Cy_GPIO_Pin_Init(CYBSP_WIFI_WL_REG_ON_PORT, CYBSP_WIFI_WL_REG_ON_PIN, &CYBSP_WIFI_WL_REG_ON_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WL_SECI_OUT_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_REG_ON_PORT, CYBSP_BT_REG_ON_PIN, &CYBSP_BT_REG_ON_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_REG_ON_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_BT_RST_PORT, CYBSP_BT_RST_PIN, &CYBSP_BT_RST_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_BT_RST_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWCLK_PORT, CYBSP_SWCLK_PIN, &CYBSP_SWCLK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_SWCLK_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_TRACECLK_PORT, CYBSP_TRACECLK_PIN, &CYBSP_TRACECLK_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_TRACECLK_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINTA_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CINTB_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
+#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_TRACEDATA3_PORT, CYBSP_TRACEDATA3_PIN, &CYBSP_TRACEDATA3_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_TRACEDATA3_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_TRACEDATA2_PORT, CYBSP_TRACEDATA2_PIN, &CYBSP_TRACEDATA2_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_TRACEDATA2_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_TRACEDATA1_PORT, CYBSP_TRACEDATA1_PIN, &CYBSP_TRACEDATA1_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_TRACEDATA1_obj);
+#endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_TRACEDATA0_PORT, CYBSP_TRACEDATA0_PIN, &CYBSP_TRACEDATA0_config);
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&CYBSP_TRACEDATA0_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
new file mode 100644
index 00000000000..9062032aae1
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
@@ -0,0 +1,1756 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cycfg_notices.h"
+#include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cycfg_routing.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PORT_NUM 0U
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_0_HSIOM
+	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PORT_NUM 0U
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_1_HSIOM
+	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_ROW6_SPI_MOSI_ENABLED 1U
+#define CYBSP_ROW6_SPI_MOSI_PORT GPIO_PRT10
+#define CYBSP_ROW6_SPI_MOSI_PORT_NUM 10U
+#define CYBSP_ROW6_SPI_MOSI_PIN 0U
+#define CYBSP_ROW6_SPI_MOSI_NUM 0U
+#define CYBSP_ROW6_SPI_MOSI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_ROW6_SPI_MOSI_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_10_pin_0_HSIOM
+	#define ioss_0_port_10_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_ROW6_SPI_MOSI_HSIOM ioss_0_port_10_pin_0_HSIOM
+#define CYBSP_ROW6_SPI_MOSI_IRQ ioss_interrupts_gpio_10_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_ROW6_SPI_MOSI_HAL_PORT_PIN P10_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ROW6_SPI_MOSI_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ROW6_SPI_MOSI_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ROW6_SPI_MOSI_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_COL8_SPI_MISO_ENABLED 1U
+#define CYBSP_COL8_SPI_MISO_PORT GPIO_PRT10
+#define CYBSP_COL8_SPI_MISO_PORT_NUM 10U
+#define CYBSP_COL8_SPI_MISO_PIN 1U
+#define CYBSP_COL8_SPI_MISO_NUM 1U
+#define CYBSP_COL8_SPI_MISO_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_COL8_SPI_MISO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_10_pin_1_HSIOM
+	#define ioss_0_port_10_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_COL8_SPI_MISO_HSIOM ioss_0_port_10_pin_1_HSIOM
+#define CYBSP_COL8_SPI_MISO_IRQ ioss_interrupts_gpio_10_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_COL8_SPI_MISO_HAL_PORT_PIN P10_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_COL8_SPI_MISO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_COL8_SPI_MISO_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_COL8_SPI_MISO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_ROW7_SPI_CLK_ENABLED 1U
+#define CYBSP_ROW7_SPI_CLK_PORT GPIO_PRT10
+#define CYBSP_ROW7_SPI_CLK_PORT_NUM 10U
+#define CYBSP_ROW7_SPI_CLK_PIN 2U
+#define CYBSP_ROW7_SPI_CLK_NUM 2U
+#define CYBSP_ROW7_SPI_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_ROW7_SPI_CLK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_10_pin_2_HSIOM
+	#define ioss_0_port_10_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_ROW7_SPI_CLK_HSIOM ioss_0_port_10_pin_2_HSIOM
+#define CYBSP_ROW7_SPI_CLK_IRQ ioss_interrupts_gpio_10_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_ROW7_SPI_CLK_HAL_PORT_PIN P10_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ROW7_SPI_CLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ROW7_SPI_CLK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ROW7_SPI_CLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_COL7_SPI_CS_ENABLED 1U
+#define CYBSP_COL7_SPI_CS_PORT GPIO_PRT10
+#define CYBSP_COL7_SPI_CS_PORT_NUM 10U
+#define CYBSP_COL7_SPI_CS_PIN 3U
+#define CYBSP_COL7_SPI_CS_NUM 3U
+#define CYBSP_COL7_SPI_CS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_COL7_SPI_CS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_10_pin_3_HSIOM
+	#define ioss_0_port_10_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_COL7_SPI_CS_HSIOM ioss_0_port_10_pin_3_HSIOM
+#define CYBSP_COL7_SPI_CS_IRQ ioss_interrupts_gpio_10_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_COL7_SPI_CS_HAL_PORT_PIN P10_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_COL7_SPI_CS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_COL7_SPI_CS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_COL7_SPI_CS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BAT_MON_ENABLED 1U
+#define CYBSP_BAT_MON_PORT GPIO_PRT10
+#define CYBSP_BAT_MON_PORT_NUM 10U
+#define CYBSP_BAT_MON_PIN 4U
+#define CYBSP_BAT_MON_NUM 4U
+#define CYBSP_BAT_MON_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BAT_MON_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_10_pin_4_HSIOM
+	#define ioss_0_port_10_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BAT_MON_HSIOM ioss_0_port_10_pin_4_HSIOM
+#define CYBSP_BAT_MON_IRQ ioss_interrupts_gpio_10_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BAT_MON_HAL_PORT_PIN P10_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BAT_MON_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BAT_MON_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BAT_MON_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WL_WAKE_ENABLED 1U
+#define CYBSP_WL_WAKE_PORT GPIO_PRT10
+#define CYBSP_WL_WAKE_PORT_NUM 10U
+#define CYBSP_WL_WAKE_PIN 7U
+#define CYBSP_WL_WAKE_NUM 7U
+#define CYBSP_WL_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WL_WAKE_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_10_pin_7_HSIOM
+	#define ioss_0_port_10_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WL_WAKE_HSIOM ioss_0_port_10_pin_7_HSIOM
+#define CYBSP_WL_WAKE_IRQ ioss_interrupts_gpio_10_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_WAKE_HAL_PORT_PIN P10_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WL_UART_RX_ENABLED 1U
+#define CYBSP_WL_UART_RX_PORT GPIO_PRT11
+#define CYBSP_WL_UART_RX_PORT_NUM 11U
+#define CYBSP_WL_UART_RX_PIN 0U
+#define CYBSP_WL_UART_RX_NUM 0U
+#define CYBSP_WL_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_WL_UART_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_0_HSIOM
+	#define ioss_0_port_11_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WL_UART_RX_HSIOM ioss_0_port_11_pin_0_HSIOM
+#define CYBSP_WL_UART_RX_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_UART_RX_HAL_PORT_PIN P11_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WL_UART_TX_ENABLED 1U
+#define CYBSP_WL_UART_TX_PORT GPIO_PRT11
+#define CYBSP_WL_UART_TX_PORT_NUM 11U
+#define CYBSP_WL_UART_TX_PIN 1U
+#define CYBSP_WL_UART_TX_NUM 1U
+#define CYBSP_WL_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WL_UART_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_1_HSIOM
+	#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WL_UART_TX_HSIOM ioss_0_port_11_pin_1_HSIOM
+#define CYBSP_WL_UART_TX_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_UART_TX_HAL_PORT_PIN P11_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SS_ENABLED 1U
+#define CYBSP_QSPI_SS_PORT GPIO_PRT11
+#define CYBSP_QSPI_SS_PORT_NUM 11U
+#define CYBSP_QSPI_SS_PIN 2U
+#define CYBSP_QSPI_SS_NUM 2U
+#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_2_HSIOM
+	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
+#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D3_ENABLED 1U
+#define CYBSP_QSPI_D3_PORT GPIO_PRT11
+#define CYBSP_QSPI_D3_PORT_NUM 11U
+#define CYBSP_QSPI_D3_PIN 3U
+#define CYBSP_QSPI_D3_NUM 3U
+#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_3_HSIOM
+	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
+#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D2_ENABLED 1U
+#define CYBSP_QSPI_D2_PORT GPIO_PRT11
+#define CYBSP_QSPI_D2_PORT_NUM 11U
+#define CYBSP_QSPI_D2_PIN 4U
+#define CYBSP_QSPI_D2_NUM 4U
+#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_4_HSIOM
+	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
+#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D1_ENABLED 1U
+#define CYBSP_QSPI_D1_PORT GPIO_PRT11
+#define CYBSP_QSPI_D1_PORT_NUM 11U
+#define CYBSP_QSPI_D1_PIN 5U
+#define CYBSP_QSPI_D1_NUM 5U
+#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_5_HSIOM
+	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
+#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_D0_ENABLED 1U
+#define CYBSP_QSPI_D0_PORT GPIO_PRT11
+#define CYBSP_QSPI_D0_PORT_NUM 11U
+#define CYBSP_QSPI_D0_PIN 6U
+#define CYBSP_QSPI_D0_NUM 6U
+#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_6_HSIOM
+	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
+#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_QSPI_SCK_ENABLED 1U
+#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
+#define CYBSP_QSPI_SCK_PORT_NUM 11U
+#define CYBSP_QSPI_SCK_PIN 7U
+#define CYBSP_QSPI_SCK_NUM 7U
+#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_11_pin_7_HSIOM
+	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_GPIO4_ENABLED 1U
+#define CYBSP_BT_GPIO4_PORT GPIO_PRT12
+#define CYBSP_BT_GPIO4_PORT_NUM 12U
+#define CYBSP_BT_GPIO4_PIN 0U
+#define CYBSP_BT_GPIO4_NUM 0U
+#define CYBSP_BT_GPIO4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_GPIO4_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_12_pin_0_HSIOM
+	#define ioss_0_port_12_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_GPIO4_HSIOM ioss_0_port_12_pin_0_HSIOM
+#define CYBSP_BT_GPIO4_IRQ ioss_interrupts_gpio_12_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO4_HAL_PORT_PIN P12_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO4_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_GPIO5_ENABLED 1U
+#define CYBSP_BT_GPIO5_PORT GPIO_PRT12
+#define CYBSP_BT_GPIO5_PORT_NUM 12U
+#define CYBSP_BT_GPIO5_PIN 1U
+#define CYBSP_BT_GPIO5_NUM 1U
+#define CYBSP_BT_GPIO5_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_GPIO5_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_12_pin_1_HSIOM
+	#define ioss_0_port_12_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_GPIO5_HSIOM ioss_0_port_12_pin_1_HSIOM
+#define CYBSP_BT_GPIO5_IRQ ioss_interrupts_gpio_12_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO5_HAL_PORT_PIN P12_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO5_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO5_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO5_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_GPIO2_ENABLED 1U
+#define CYBSP_BT_GPIO2_PORT GPIO_PRT12
+#define CYBSP_BT_GPIO2_PORT_NUM 12U
+#define CYBSP_BT_GPIO2_PIN 2U
+#define CYBSP_BT_GPIO2_NUM 2U
+#define CYBSP_BT_GPIO2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_GPIO2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_12_pin_2_HSIOM
+	#define ioss_0_port_12_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_GPIO2_HSIOM ioss_0_port_12_pin_2_HSIOM
+#define CYBSP_BT_GPIO2_IRQ ioss_interrupts_gpio_12_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO2_HAL_PORT_PIN P12_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO2_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_GPIO3_ENABLED 1U
+#define CYBSP_BT_GPIO3_PORT GPIO_PRT12
+#define CYBSP_BT_GPIO3_PORT_NUM 12U
+#define CYBSP_BT_GPIO3_PIN 3U
+#define CYBSP_BT_GPIO3_NUM 3U
+#define CYBSP_BT_GPIO3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_GPIO3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_12_pin_3_HSIOM
+	#define ioss_0_port_12_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_GPIO3_HSIOM ioss_0_port_12_pin_3_HSIOM
+#define CYBSP_BT_GPIO3_IRQ ioss_interrupts_gpio_12_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO3_HAL_PORT_PIN P12_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO3_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_GPIO3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_ECO_IN_ENABLED 1U
+#define CYBSP_ECO_IN_PORT GPIO_PRT12
+#define CYBSP_ECO_IN_PORT_NUM 12U
+#define CYBSP_ECO_IN_PIN 6U
+#define CYBSP_ECO_IN_NUM 6U
+#define CYBSP_ECO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_ECO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_12_pin_6_HSIOM
+	#define ioss_0_port_12_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_ECO_IN_HSIOM ioss_0_port_12_pin_6_HSIOM
+#define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_12_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_IN_HAL_PORT_PIN P12_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_ECO_OUT_ENABLED 1U
+#define CYBSP_ECO_OUT_PORT GPIO_PRT12
+#define CYBSP_ECO_OUT_PORT_NUM 12U
+#define CYBSP_ECO_OUT_PIN 7U
+#define CYBSP_ECO_OUT_NUM 7U
+#define CYBSP_ECO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_ECO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_12_pin_7_HSIOM
+	#define ioss_0_port_12_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_ECO_OUT_HSIOM ioss_0_port_12_pin_7_HSIOM
+#define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_12_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_OUT_HAL_PORT_PIN P12_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_USB_DEV_VBUS_DET_ENABLED 1U
+#define CYBSP_USB_DEV_VBUS_DET_PORT GPIO_PRT13
+#define CYBSP_USB_DEV_VBUS_DET_PORT_NUM 13U
+#define CYBSP_USB_DEV_VBUS_DET_PIN 4U
+#define CYBSP_USB_DEV_VBUS_DET_NUM 4U
+#define CYBSP_USB_DEV_VBUS_DET_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_USB_DEV_VBUS_DET_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_13_pin_4_HSIOM
+	#define ioss_0_port_13_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_USB_DEV_VBUS_DET_HSIOM ioss_0_port_13_pin_4_HSIOM
+#define CYBSP_USB_DEV_VBUS_DET_IRQ ioss_interrupts_gpio_13_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DEV_VBUS_DET_HAL_PORT_PIN P13_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DEV_VBUS_DET_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DEV_VBUS_DET_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DEV_VBUS_DET_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_USB_HOST_EN_ENABLED 1U
+#define CYBSP_USB_HOST_EN_PORT GPIO_PRT13
+#define CYBSP_USB_HOST_EN_PORT_NUM 13U
+#define CYBSP_USB_HOST_EN_PIN 5U
+#define CYBSP_USB_HOST_EN_NUM 5U
+#define CYBSP_USB_HOST_EN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_USB_HOST_EN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_13_pin_5_HSIOM
+	#define ioss_0_port_13_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_USB_HOST_EN_HSIOM ioss_0_port_13_pin_5_HSIOM
+#define CYBSP_USB_HOST_EN_IRQ ioss_interrupts_gpio_13_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_HOST_EN_HAL_PORT_PIN P13_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_HOST_EN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_HOST_EN_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_HOST_EN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_USB_INT_L_ENABLED 1U
+#define CYBSP_USB_INT_L_PORT GPIO_PRT13
+#define CYBSP_USB_INT_L_PORT_NUM 13U
+#define CYBSP_USB_INT_L_PIN 7U
+#define CYBSP_USB_INT_L_NUM 7U
+#define CYBSP_USB_INT_L_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_USB_INT_L_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_13_pin_7_HSIOM
+	#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_USB_INT_L_HSIOM ioss_0_port_13_pin_7_HSIOM
+#define CYBSP_USB_INT_L_IRQ ioss_interrupts_gpio_13_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_INT_L_HAL_PORT_PIN P13_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_INT_L_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_INT_L_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_INT_L_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_USB_DP_ENABLED 1U
+#define CYBSP_USB_DP_PORT GPIO_PRT14
+#define CYBSP_USB_DP_PORT_NUM 14U
+#define CYBSP_USB_DP_PIN 0U
+#define CYBSP_USB_DP_NUM 0U
+#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_USB_DP_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_14_pin_0_HSIOM
+	#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
+#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_USB_DM_ENABLED 1U
+#define CYBSP_USB_DM_PORT GPIO_PRT14
+#define CYBSP_USB_DM_PORT_NUM 14U
+#define CYBSP_USB_DM_PIN 1U
+#define CYBSP_USB_DM_NUM 1U
+#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_USB_DM_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_14_pin_1_HSIOM
+	#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
+#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_TX_ENABLED 1U
+#define CYBSP_CSD_TX_PORT GPIO_PRT1
+#define CYBSP_CSD_TX_PORT_NUM 1U
+#define CYBSP_CSD_TX_PIN 0U
+#define CYBSP_CSD_TX_NUM 0U
+#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_0_HSIOM
+	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_PORT_PIN P1_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WL_SECI_IN_ENABLED 1U
+#define CYBSP_WL_SECI_IN_PORT GPIO_PRT1
+#define CYBSP_WL_SECI_IN_PORT_NUM 1U
+#define CYBSP_WL_SECI_IN_PIN 2U
+#define CYBSP_WL_SECI_IN_NUM 2U
+#define CYBSP_WL_SECI_IN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WL_SECI_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_2_HSIOM
+	#define ioss_0_port_1_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WL_SECI_IN_HSIOM ioss_0_port_1_pin_2_HSIOM
+#define CYBSP_WL_SECI_IN_IRQ ioss_interrupts_gpio_1_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_SECI_IN_HAL_PORT_PIN P1_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_SECI_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_SECI_IN_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_SECI_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WL_FRAM_SYNC_ENABLED 1U
+#define CYBSP_WL_FRAM_SYNC_PORT GPIO_PRT1
+#define CYBSP_WL_FRAM_SYNC_PORT_NUM 1U
+#define CYBSP_WL_FRAM_SYNC_PIN 3U
+#define CYBSP_WL_FRAM_SYNC_NUM 3U
+#define CYBSP_WL_FRAM_SYNC_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WL_FRAM_SYNC_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_3_HSIOM
+	#define ioss_0_port_1_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WL_FRAM_SYNC_HSIOM ioss_0_port_1_pin_3_HSIOM
+#define CYBSP_WL_FRAM_SYNC_IRQ ioss_interrupts_gpio_1_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_FRAM_SYNC_HAL_PORT_PIN P1_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_FRAM_SYNC_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_FRAM_SYNC_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_FRAM_SYNC_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WL_PRIORITY_ENABLED 1U
+#define CYBSP_WL_PRIORITY_PORT GPIO_PRT1
+#define CYBSP_WL_PRIORITY_PORT_NUM 1U
+#define CYBSP_WL_PRIORITY_PIN 4U
+#define CYBSP_WL_PRIORITY_NUM 4U
+#define CYBSP_WL_PRIORITY_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WL_PRIORITY_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_4_HSIOM
+	#define ioss_0_port_1_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WL_PRIORITY_HSIOM ioss_0_port_1_pin_4_HSIOM
+#define CYBSP_WL_PRIORITY_IRQ ioss_interrupts_gpio_1_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_PRIORITY_HAL_PORT_PIN P1_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_PRIORITY_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_PRIORITY_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_PRIORITY_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WL_SECI_OUT_ENABLED 1U
+#define CYBSP_WL_SECI_OUT_PORT GPIO_PRT1
+#define CYBSP_WL_SECI_OUT_PORT_NUM 1U
+#define CYBSP_WL_SECI_OUT_PIN 5U
+#define CYBSP_WL_SECI_OUT_NUM 5U
+#define CYBSP_WL_SECI_OUT_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_WL_SECI_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_5_HSIOM
+	#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WL_SECI_OUT_HSIOM ioss_0_port_1_pin_5_HSIOM
+#define CYBSP_WL_SECI_OUT_IRQ ioss_interrupts_gpio_1_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_SECI_OUT_HAL_PORT_PIN P1_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_SECI_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_SECI_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WL_SECI_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
+#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2
+#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 2U
+#define CYBSP_WIFI_HOST_WAKE_PIN 7U
+#define CYBSP_WIFI_HOST_WAKE_NUM 7U
+#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_2_pin_7_HSIOM
+	#define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM
+#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P2_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_RX_ENABLED 1U
+#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RX_PORT_NUM 3U
+#define CYBSP_BT_UART_RX_PIN 0U
+#define CYBSP_BT_UART_RX_NUM 0U
+#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_0_HSIOM
+	#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
+#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_TX_ENABLED 1U
+#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_TX_PORT_NUM 3U
+#define CYBSP_BT_UART_TX_PIN 1U
+#define CYBSP_BT_UART_TX_NUM 1U
+#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_1_HSIOM
+	#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
+#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_RTS_ENABLED 1U
+#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RTS_PORT_NUM 3U
+#define CYBSP_BT_UART_RTS_PIN 2U
+#define CYBSP_BT_UART_RTS_NUM 2U
+#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_2_HSIOM
+	#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
+#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_CTS_ENABLED 1U
+#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_CTS_PORT_NUM 3U
+#define CYBSP_BT_UART_CTS_PIN 3U
+#define CYBSP_BT_UART_CTS_NUM 3U
+#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_3_HSIOM
+	#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
+#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_REG_ON_ENABLED 1U
+#define CYBSP_BT_REG_ON_PORT GPIO_PRT3
+#define CYBSP_BT_REG_ON_PORT_NUM 3U
+#define CYBSP_BT_REG_ON_PIN 4U
+#define CYBSP_BT_REG_ON_NUM 4U
+#define CYBSP_BT_REG_ON_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
+#define CYBSP_BT_REG_ON_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_4_HSIOM
+	#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_REG_ON_HSIOM ioss_0_port_3_pin_4_HSIOM
+#define CYBSP_BT_REG_ON_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_REG_ON_HAL_PORT_PIN P3_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_REG_ON_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_REG_ON_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_REG_ON_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_HOST_WAKE_ENABLED 1U
+#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
+#define CYBSP_BT_HOST_WAKE_PORT_NUM 3U
+#define CYBSP_BT_HOST_WAKE_PIN 5U
+#define CYBSP_BT_HOST_WAKE_NUM 5U
+#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_3_pin_5_HSIOM
+	#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
+#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P3_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
+#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
+#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 4U
+#define CYBSP_BT_DEVICE_WAKE_PIN 0U
+#define CYBSP_BT_DEVICE_WAKE_NUM 0U
+#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_4_pin_0_HSIOM
+	#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
+#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P4_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_RST_ENABLED 1U
+#define CYBSP_BT_RST_PORT GPIO_PRT4
+#define CYBSP_BT_RST_PORT_NUM 4U
+#define CYBSP_BT_RST_PIN 1U
+#define CYBSP_BT_RST_NUM 1U
+#define CYBSP_BT_RST_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_RST_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_4_pin_1_HSIOM
+	#define ioss_0_port_4_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_RST_HSIOM ioss_0_port_4_pin_1_HSIOM
+#define CYBSP_BT_RST_IRQ ioss_interrupts_gpio_4_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_RST_HAL_PORT_PIN P4_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_RST_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_RST_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_BT_RST_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SCL_ENABLED 1U
+#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SCL_PORT_NUM 6U
+#define CYBSP_EZI2C_SCL_PIN 0U
+#define CYBSP_EZI2C_SCL_NUM 0U
+#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_0_HSIOM
+	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
+#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_EZI2C_SDA_ENABLED 1U
+#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SDA_PORT_NUM 6U
+#define CYBSP_EZI2C_SDA_PIN 1U
+#define CYBSP_EZI2C_SDA_NUM 1U
+#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_1_HSIOM
+	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
+#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PORT_NUM 6U
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_4_HSIOM
+	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_PORT_PIN P6_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PORT_NUM 6U
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_6_HSIOM
+	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWCLK_ENABLED 1U
+#define CYBSP_SWCLK_PORT GPIO_PRT6
+#define CYBSP_SWCLK_PORT_NUM 6U
+#define CYBSP_SWCLK_PIN 7U
+#define CYBSP_SWCLK_NUM 7U
+#define CYBSP_SWCLK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWCLK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_7_HSIOM
+	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWCLK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWCLK_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWCLK_HAL_PORT_PIN P6_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWCLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWCLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#endif //defined (CY_USING_HAL)
+#define CYBSP_TRACECLK_ENABLED 1U
+#define CYBSP_TRACECLK_PORT GPIO_PRT7
+#define CYBSP_TRACECLK_PORT_NUM 7U
+#define CYBSP_TRACECLK_PIN 0U
+#define CYBSP_TRACECLK_NUM 0U
+#define CYBSP_TRACECLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_TRACECLK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_0_HSIOM
+	#define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_TRACECLK_HSIOM ioss_0_port_7_pin_0_HSIOM
+#define CYBSP_TRACECLK_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACECLK_HAL_PORT_PIN P7_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACECLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACECLK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACECLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINTA_ENABLED 1U
+#define CYBSP_CINTA_PORT GPIO_PRT7
+#define CYBSP_CINTA_PORT_NUM 7U
+#define CYBSP_CINTA_PIN 1U
+#define CYBSP_CINTA_NUM 1U
+#define CYBSP_CINTA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINTA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_1_HSIOM
+	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINTA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CINTA_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINTA_HAL_PORT_PIN P7_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINTA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINTA_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINTA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINTB_ENABLED 1U
+#define CYBSP_CINTB_PORT GPIO_PRT7
+#define CYBSP_CINTB_PORT_NUM 7U
+#define CYBSP_CINTB_PIN 2U
+#define CYBSP_CINTB_NUM 2U
+#define CYBSP_CINTB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINTB_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_2_HSIOM
+	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINTB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CINTB_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINTB_HAL_PORT_PIN P7_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINTB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINTB_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINTB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PORT_NUM 7U
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_7_HSIOM
+	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_PORT_PIN P7_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN0_PORT_NUM 8U
+#define CYBSP_CSD_BTN0_PIN 1U
+#define CYBSP_CSD_BTN0_NUM 1U
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_1_HSIOM
+	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN1_PORT_NUM 8U
+#define CYBSP_CSD_BTN1_PIN 2U
+#define CYBSP_CSD_BTN1_NUM 2U
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_2_HSIOM
+	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD0_PORT_NUM 8U
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_3_HSIOM
+	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD1_PORT_NUM 8U
+#define CYBSP_CSD_SLD1_PIN 4U
+#define CYBSP_CSD_SLD1_NUM 4U
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_4_HSIOM
+	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD2_PORT_NUM 8U
+#define CYBSP_CSD_SLD2_PIN 5U
+#define CYBSP_CSD_SLD2_NUM 5U
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_5_HSIOM
+	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD3_PORT_NUM 8U
+#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_6_HSIOM
+	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD4_PORT_NUM 8U
+#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_8_pin_7_HSIOM
+	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_TRACEDATA3_ENABLED 1U
+#define CYBSP_TRACEDATA3_PORT GPIO_PRT9
+#define CYBSP_TRACEDATA3_PORT_NUM 9U
+#define CYBSP_TRACEDATA3_PIN 0U
+#define CYBSP_TRACEDATA3_NUM 0U
+#define CYBSP_TRACEDATA3_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_TRACEDATA3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_9_pin_0_HSIOM
+	#define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_TRACEDATA3_HSIOM ioss_0_port_9_pin_0_HSIOM
+#define CYBSP_TRACEDATA3_IRQ ioss_interrupts_gpio_9_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA3_HAL_PORT_PIN P9_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA3_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_TRACEDATA2_ENABLED 1U
+#define CYBSP_TRACEDATA2_PORT GPIO_PRT9
+#define CYBSP_TRACEDATA2_PORT_NUM 9U
+#define CYBSP_TRACEDATA2_PIN 1U
+#define CYBSP_TRACEDATA2_NUM 1U
+#define CYBSP_TRACEDATA2_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_TRACEDATA2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_9_pin_1_HSIOM
+	#define ioss_0_port_9_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_TRACEDATA2_HSIOM ioss_0_port_9_pin_1_HSIOM
+#define CYBSP_TRACEDATA2_IRQ ioss_interrupts_gpio_9_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA2_HAL_PORT_PIN P9_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA2_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_TRACEDATA1_ENABLED 1U
+#define CYBSP_TRACEDATA1_PORT GPIO_PRT9
+#define CYBSP_TRACEDATA1_PORT_NUM 9U
+#define CYBSP_TRACEDATA1_PIN 2U
+#define CYBSP_TRACEDATA1_NUM 2U
+#define CYBSP_TRACEDATA1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_TRACEDATA1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_9_pin_2_HSIOM
+	#define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_TRACEDATA1_HSIOM ioss_0_port_9_pin_2_HSIOM
+#define CYBSP_TRACEDATA1_IRQ ioss_interrupts_gpio_9_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA1_HAL_PORT_PIN P9_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA1_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_TRACEDATA0_ENABLED 1U
+#define CYBSP_TRACEDATA0_PORT GPIO_PRT9
+#define CYBSP_TRACEDATA0_PORT_NUM 9U
+#define CYBSP_TRACEDATA0_PIN 3U
+#define CYBSP_TRACEDATA0_NUM 3U
+#define CYBSP_TRACEDATA0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_TRACEDATA0_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_9_pin_3_HSIOM
+	#define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_TRACEDATA0_HSIOM ioss_0_port_9_pin_3_HSIOM
+#define CYBSP_TRACEDATA0_IRQ ioss_interrupts_gpio_9_IRQn
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA0_HAL_PORT_PIN P9_3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA0_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_TRACEDATA0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_ROW6_SPI_MOSI_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_ROW6_SPI_MOSI_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_COL8_SPI_MISO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_COL8_SPI_MISO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_ROW7_SPI_CLK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_ROW7_SPI_CLK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_COL7_SPI_CS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_COL7_SPI_CS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BAT_MON_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BAT_MON_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WL_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_UART_RX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WL_UART_RX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_UART_TX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WL_UART_TX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO4_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_GPIO4_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO5_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_GPIO5_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_GPIO2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_GPIO3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_DEV_VBUS_DET_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_DEV_VBUS_DET_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_HOST_EN_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_HOST_EN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_INT_L_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_INT_L_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_IN_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WL_SECI_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_FRAM_SYNC_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WL_FRAM_SYNC_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_PRIORITY_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WL_PRIORITY_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_OUT_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WL_SECI_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_REG_ON_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_REG_ON_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_RST_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_BT_RST_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_SWCLK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_TRACECLK_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_TRACECLK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINTA_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINTA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINTB_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CINTB_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA3_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_TRACEDATA3_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA2_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_TRACEDATA2_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA1_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_TRACEDATA1_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA0_config;
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t CYBSP_TRACEDATA0_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
new file mode 100644
index 00000000000..c4e5bcf916f
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
@@ -0,0 +1,265 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.c
+*
+* Description:
+* Provides definitions of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_qspi_memslot.h"
+
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0xECU,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_QUAD,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0x01U,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_QUAD,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 4U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x06U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x04U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0xDCU,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x60U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x34U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_QUAD,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x35U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x05U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x01U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
+{
+    /* Specifies the number of address bytes used by the memory slave device. */
+    .numOfAddrBytes = 0x04U,
+    /* The size of the memory. */
+    .memSize = 0x04000000U,
+    /* Specifies the Read command. */
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
+    /* Specifies the Write Enable command. */
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
+    /* Specifies the Write Disable command. */
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
+    /* Specifies the Erase command. */
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
+    /* Specifies the sector size of each erase. */
+    .eraseSize = 0x00040000U,
+    /* Specifies the Chip Erase command. */
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
+    /* Specifies the Program command. */
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
+    /* Specifies the page size for programming. */
+    .programSize = 0x00000200U,
+    /* Specifies the command to read the QE-containing status register. */
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
+    /* Specifies the command to read the WIP-containing status register. */
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
+    /* Specifies the command to write into the QE-containing status register. */
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
+    /* The mask for the status register. */
+    .stsRegBusyMask = 0x01U,
+    /* The mask for the status register. */
+    .stsRegQuadEnableMask = 0x02U,
+    /* The max time for the erase type-1 cycle-time in ms. */
+    .eraseTime = 2600U,
+    /* The max time for the chip-erase cycle-time in ms. */
+    .chipEraseTime = 460000U,
+    /* The max time for the page-program cycle-time in us. */
+    .programTime = 1300U
+};
+
+const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
+{
+    /* Determines the slot number where the memory device is placed. */
+    .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
+    /* Flags. */
+    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
+    /* The data-line selection options for a slave device. */
+    .dataSelect = CY_SMIF_DATA_SEL0,
+    /* The base address the memory slave is mapped to in the PSoC memory map.
+    Valid when the memory-mapped mode is enabled. */
+    .baseAddress = 0x18000000U,
+    /* The size allocated in the PSoC memory map, for the memory slave device.
+    The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
+    .memMappedSize = 0x4000000U,
+    /* If this memory device is one of the devices in the dual quad SPI configuration.
+    Valid when the memory mapped mode is enabled. */
+    .dualQuadSlots = 0,
+    /* The configuration of the device. */
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
+};
+
+const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
+   &S25FL512SX4byteaddr_SlaveSlot_0
+};
+
+const cy_stc_smif_block_config_t smifBlockConfig =
+{
+    /* The number of SMIF memories defined. */
+    .memCount = CY_SMIF_DEVICE_NUM,
+    /* The pointer to the array of memory config structures of size memCount. */
+    .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
+    /* The version of the SMIF driver. */
+    .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
+    /* The version of the SMIF driver. */
+    .minorVersion = CY_SMIF_DRV_VERSION_MINOR
+};
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
new file mode 100644
index 00000000000..32f9b49b2e6
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
@@ -0,0 +1,50 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.h
+*
+* Description:
+* Provides declarations of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* 
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#ifndef CYCFG_QSPI_MEMSLOT_H
+#define CYCFG_QSPI_MEMSLOT_H
+#include "cy_smif_memslot.h"
+
+#define CY_SMIF_DEVICE_NUM 1
+
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
+
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
+
+extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
+
+extern const cy_stc_smif_block_config_t smifBlockConfig;
+
+
+#endif /*CY_SMIF_MEMCONFIG_H*/
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
similarity index 64%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
index 5dc2e168698..a1dadb2d0b0 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
@@ -24,22 +24,10 @@
 
 #include "cycfg_routing.h"
 
-#include "cy_trigmux.h"
-
-#include "stdbool.h"
-
 #include "cy_device_headers.h"
 
 void init_cycfg_routing(void)
 {
-	Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT45, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
-	Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT2, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
 	HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
 		HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
 		HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
similarity index 71%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
index 73304eb9401..5c3d565c635 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
@@ -47,17 +47,9 @@ void init_cycfg_routing(void);
 #define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
 #define ioss_0_port_12_pin_6_ANALOG P12_6_SRSS_ECO_IN
 #define ioss_0_port_12_pin_7_ANALOG P12_7_SRSS_ECO_OUT
-#define ioss_0_port_13_pin_0_HSIOM P13_0_SCB6_UART_RX
-#define ioss_0_port_13_pin_1_HSIOM P13_1_SCB6_UART_TX
 #define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD
 #define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD
 #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_2_pin_0_HSIOM P2_0_DSI_DSI
-#define ioss_0_port_2_pin_1_HSIOM P2_1_DSI_DSI
-#define ioss_0_port_2_pin_2_HSIOM P2_2_DSI_DSI
-#define ioss_0_port_2_pin_3_HSIOM P2_3_DSI_DSI
-#define ioss_0_port_2_pin_4_HSIOM P2_4_DSI_DSI
-#define ioss_0_port_2_pin_5_HSIOM P2_5_DSI_GPIO
 #define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
 #define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
 #define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
@@ -74,28 +66,15 @@ void init_cycfg_routing(void);
 #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_9_pin_0_HSIOM P9_0_CPUSS_TRACE_DATA3
 #define ioss_0_port_9_pin_1_HSIOM P9_1_CPUSS_TRACE_DATA2
 #define ioss_0_port_9_pin_2_HSIOM P9_2_CPUSS_TRACE_DATA1
 #define ioss_0_port_9_pin_3_HSIOM P9_3_CPUSS_TRACE_DATA0
 
-#define CYBSP_SDIO_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
-#define CYBSP_SDIO_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0
-#define CYBSP_SDIO_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3
-#define CYBSP_SDIO_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
-#define CYBSP_SDIO_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT1
-#define CYBSP_SDIO_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
-#define CYBSP_SDIO_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
-#define CYBSP_SDIO_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT2
-#define cpuss_0_dw0_0_chan_0_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN0
-#define cpuss_0_dw0_0_chan_1_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN1
-#define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1
-#define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3
-
 #if defined(__cplusplus)
 }
 #endif
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
similarity index 89%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
index ffcf6d1a0ac..1e894506975 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
@@ -32,6 +32,7 @@
 #define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
 #define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
 #define CY_CFG_SYSCLK_ECO_ENABLED 1
+#define CY_CFG_SYSCLK_ECO_FREQ 24000000UL
 #define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
 #define CY_CFG_SYSCLK_FLL_ENABLED 1
 #define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
@@ -84,6 +85,46 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
 	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
 	.cco_Freq = 355U,
 };
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 0U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 1U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 2U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 3U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = 
+	{
+		.type = CYHAL_RSC_CLKPATH,
+		.block_num = 4U,
+		.channel_num = 0U,
+	};
+#endif //defined (CY_USING_HAL)
 static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = 
 {
 	.feedbackDiv = 30,
@@ -108,13 +149,13 @@ __STATIC_INLINE void Cy_SysClk_ClkBakInit()
 }
 __STATIC_INLINE void Cy_SysClk_EcoInit()
 {
-    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT12, 6, 0x00u, 0x00u, HSIOM_SEL_GPIO);
-    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT12, 7, 0x00u, 0x00u, HSIOM_SEL_GPIO);
-    if (CY_SYSCLK_BAD_PARAM == Cy_SysClk_EcoConfigure(24000000U, 18U, 50U, 100U))
+    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT12, 6, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO);
+    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT12, 7, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO);
+    if (CY_SYSCLK_BAD_PARAM == Cy_SysClk_EcoConfigure(CY_CFG_SYSCLK_ECO_FREQ, 18UL, 50UL, 100UL))
     {
         cycfg_ClockStartupError(CY_CFG_SYSCLK_ECO_ERROR);
     }
-    if (CY_SYSCLK_TIMEOUT == Cy_SysClk_EcoEnable(3000u))
+    if (CY_SYSCLK_TIMEOUT == Cy_SysClk_EcoEnable(3000UL))
     {
         cycfg_ClockStartupError(CY_CFG_SYSCLK_ECO_ERROR);
     }
@@ -537,4 +578,24 @@ void init_cycfg_system(void)
 	
 	/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
 	SystemCoreClockUpdate();
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+		cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
+#endif //defined (CY_USING_HAL)
 }
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
similarity index 79%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.h
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
index 9110cd20a62..07fe155d2b6 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
@@ -29,6 +29,9 @@
 #include "cy_sysclk.h"
 #include "cy_systick.h"
 #include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+	#include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
 #include "cy_syspm.h"
 
 #if defined(__cplusplus)
@@ -70,7 +73,7 @@ extern "C" {
 #define CY_CFG_PWR_MODE_ACTIVE 0x04UL
 #define CY_CFG_PWR_MODE_SLEEP 0x08UL
 #define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
-#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_SLEEP
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
 #define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
 #define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
 #define CY_CFG_PWR_USING_LDO 1
@@ -81,6 +84,22 @@ extern "C" {
 #define CY_CFG_PWR_VDDIO0_MV 3300
 #define CY_CFG_PWR_VDDIO1_MV 3300
 
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+#endif //defined (CY_USING_HAL)
+
 void init_cycfg_system(void);
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
new file mode 100644
index 00000000000..5557ddecddf
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
@@ -0,0 +1,4 @@
+set SMIF_BANKS {
+  0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+}
+
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
new file mode 100644
index 00000000000..13cf564a5a6
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
@@ -0,0 +1,409 @@
+<?xml version="1.0"?>
+<Configuration major="2" minor="0">
+    <!--
+       File Name: cycfg_capsense.cycapsense 
+
+       Description: 
+       CapSense middleware configuration 
+       This file should not be modified. It was automatically generated by 
+       CapSense Configurator 2.0.0 build 185 
+-->
+    <GeneralProperties>
+        <Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="REGULAR_IIR_RC_N" value="128"/>
+        <Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="PROX_IIR_RC_N" value="128"/>
+        <Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="REGULAR_IIR_BL_N" value="1"/>
+        <Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="PROX_IIR_BL_N" value="1"/>
+        <Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="MULTI_FREQ_SCAN_EN" value="false"/>
+        <Property id="SENSOR_AUTO_RESET_EN" value="false"/>
+        <Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
+        <Property id="VREF_SOURCE" value="SRSS"/>
+        <Property id="IREF_SOURCE" value="SRSS"/>
+        <Property id="PROX_TOUCH_COEFF" value="300"/>
+        <Property id="NUM_CENTROIDS" value="1"/>
+    </GeneralProperties>
+    <CsdProperties>
+        <Property id="CSD_AUTOTUNE" value="HWTH"/>
+        <Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
+        <Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
+        <Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
+        <Property id="CSD_IDAC_MIN" value="20"/>
+        <Property id="CSD_IDAC_COMP_EN" value="true"/>
+        <Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
+        <Property id="CSD_VREF_CUSTOM" value="false"/>
+        <Property id="CSD_VREF" value="1219"/>
+        <Property id="CSD_SHIELD_EN" value="false"/>
+        <Property id="CSD_SHIELD_TANK_EN" value="false"/>
+        <Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
+        <Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
+        <Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_FINE_INIT_TIME" value="10"/>
+        <Property id="CSD_CALIBRATION_ERROR" value="10"/>
+        <Property id="CSD_R_CONST" value="1000"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsdProperties>
+    <CsxProperties>
+        <Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSX_MAX_FINGERS" value="3"/>
+        <Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
+        <Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
+        <Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_FINE_INIT_TIME" value="10"/>
+        <Property id="CSX_CALIBRATION_ERROR" value="20"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsxProperties>
+    <Widgets>
+        <Widget id="Button0" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="Button1" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="LinearSlider0" type="LINEAR_SLIDER">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Sns0" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns1" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns2" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns3" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns4" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+    </Widgets>
+</Configuration>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
new file mode 100644
index 00000000000..6df618b3a8d
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
+<Configuration app="QSPI" major="2" minor="0">
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <PartNumber>S25FL512S-4byteaddr</PartNumber>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x4000000</Size>
+            <EndAddress>0x1BFFFFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <PartNumber>Not used</PartNumber>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</Configuration>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus
similarity index 83%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/design.modus
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus
index 99308ff45d7..6bc99333172 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/design.modus
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus
@@ -172,26 +172,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[0].pin[3]" alias="CYBSP_LED_RED" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[0].pin[4]" alias="CYBSP_SW6" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[10].pin[0]" alias="CYBSP_ROW6_SPI_MOSI" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
                     <Param id="initialState" value="1"/>
@@ -242,16 +222,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[10].pin[6]" alias="CYBSP_LED_BLUE" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[10].pin[7]" alias="CYBSP_WL_WAKE" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
                     <Param id="initialState" value="1"/>
@@ -402,26 +372,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[13].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[13].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[13].pin[4]" alias="CYBSP_USB_DEV_VBUS_DET" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
                     <Param id="initialState" value="1"/>
@@ -482,16 +432,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[1].pin[1]" alias="CYBSP_LED_GREEN" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[1].pin[2]" alias="CYBSP_WL_SECI_IN" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
                     <Param id="initialState" value="1"/>
@@ -532,76 +472,6 @@
                     <Param id="sioOutputBuffer" value="true"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="ioss[0].port[2].pin[0]" alias="CYBSP_WIFI_SDIO_D0" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[1]" alias="CYBSP_WIFI_SDIO_D1" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[2]" alias="CYBSP_WIFI_SDIO_D2" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[3]" alias="CYBSP_WIFI_SDIO_D3" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[4]" alias="CYBSP_WIFI_SDIO_CMD" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[5]" alias="CYBSP_WIFI_SDIO_CLK" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="1"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
-                <Block location="ioss[0].port[2].pin[6]" alias="CYBSP_WIFI_WL_REG_ON" template="mxs40pin" version="1.1">
-                    <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                    <Param id="initialState" value="0"/>
-                    <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                    <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                    <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                    <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                    <Param id="sioOutputBuffer" value="true"/>
-                    <Param id="inFlash" value="true"/>
-                </Block>
                 <Block location="ioss[0].port[2].pin[7]" alias="CYBSP_WIFI_HOST_WAKE" template="mxs40pin" version="1.1">
                     <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
                     <Param id="initialState" value="1"/>
@@ -907,7 +777,7 @@
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
                 </Block>
-                <Block location="peri[0].div_8[2]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
+                <Block location="peri[0].div_8[3]" alias="" template="mxs40peripheralclock" version="1.0">
                     <Param id="intDivider" value="109"/>
                     <Param id="fracDivider" value="0"/>
                     <Param id="startOnReset" value="true"/>
@@ -1062,51 +932,6 @@
                     <Param id="IntrTxUnderflow" value="false"/>
                     <Param id="IntrTxTrigger" value="false"/>
                 </Block>
-                <Block location="scb[6]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
-                    <Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
-                    <Param id="IrdaLowPower" value="false"/>
-                    <Param id="BaudRate" value="115200"/>
-                    <Param id="Oversample" value="8"/>
-                    <Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
-                    <Param id="DataWidth" value="8"/>
-                    <Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
-                    <Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
-                    <Param id="EnableInputFilter" value="false"/>
-                    <Param id="EnableTxEn" value="false"/>
-                    <Param id="FlowControl" value="false"/>
-                    <Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
-                    <Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
-                    <Param id="RtsTriggerLevel" value="63"/>
-                    <Param id="RxTriggerLevel" value="63"/>
-                    <Param id="TxTriggerLevel" value="63"/>
-                    <Param id="MultiProc" value="false"/>
-                    <Param id="MpRxAddress" value="0"/>
-                    <Param id="MpRxAddressMask" value="255"/>
-                    <Param id="MpRxAcceptAddress" value="false"/>
-                    <Param id="DropOnFrameErr" value="false"/>
-                    <Param id="DropOnParityErr" value="false"/>
-                    <Param id="BreakSignalBits" value="11"/>
-                    <Param id="SmCardRetryOnNack" value="false"/>
-                    <Param id="IrdaPolarity" value="NON_INVERTING"/>
-                    <Param id="inFlash" value="true"/>
-                    <Param id="ApiMode" value="HIGH_LEVEL"/>
-                    <Param id="IntrRxNotEmpty" value="false"/>
-                    <Param id="IntrRxFull" value="false"/>
-                    <Param id="IntrRxOverflow" value="false"/>
-                    <Param id="IntrRxUnderflow" value="false"/>
-                    <Param id="IntrRxFrameErr" value="false"/>
-                    <Param id="IntrRxParityErr" value="false"/>
-                    <Param id="IntrRxBreakDetected" value="false"/>
-                    <Param id="IntrRxTrigger" value="false"/>
-                    <Param id="IntrTxUartDone" value="false"/>
-                    <Param id="IntrTxUartLostArb" value="false"/>
-                    <Param id="IntrTxUartNack" value="false"/>
-                    <Param id="IntrTxEmpty" value="false"/>
-                    <Param id="IntrTxNotFull" value="false"/>
-                    <Param id="IntrTxOverflow" value="false"/>
-                    <Param id="IntrTxUnderflow" value="false"/>
-                    <Param id="IntrTxTrigger" value="false"/>
-                </Block>
                 <Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
                     <Param id="configurator" value=""/>
                     <Param id="isrAlignment" value="false"/>
@@ -1124,8 +949,8 @@
                 <Block location="srss[0].clock[0].bakclk[0]" alias="" template="mxs40bakclk" version="1.0">
                     <Param id="sourceClock" value="wco"/>
                 </Block>
-                <Block location="srss[0].clock[0].eco[0]" alias="" template="mxs40eco" version="1.1">
-                    <Param id="ecoFrequency" value="24.00"/>
+                <Block location="srss[0].clock[0].eco[0]" alias="" template="mxs40eco" version="1.2">
+                    <Param id="ecoFrequency" value="24.0000"/>
                     <Param id="accuracyPpm" value="0"/>
                     <Param id="driveLevel" value="100"/>
                     <Param id="esr" value="50"/>
@@ -1222,7 +1047,7 @@
                     <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
                     <Param id="pmicEnable" value="false"/>
                     <Param id="backupSrc" value="VDDD"/>
-                    <Param id="idlePwrMode" value="CY_CFG_PWR_MODE_SLEEP"/>
+                    <Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
                     <Param id="deepsleepLatency" value="0"/>
                     <Param id="vddaMv" value="3300"/>
                     <Param id="vdddMv" value="3300"/>
@@ -1256,7 +1081,6 @@
                     <Param id="dstStopHour" value="0"/>
                     <Param id="inFlash" value="true"/>
                 </Block>
-                <Block location="udb[0]" alias="CYBSP_SDIO" template="mxs40udbsdio" version="1.0"/>
                 <Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.0">
                     <Param id="configurator" value=""/>
                     <Param id="UsbCore" value="4"/>
@@ -1314,22 +1138,6 @@
                     <Port name="cpuss[0].dap[0].trace_data[3]"/>
                     <Port name="ioss[0].port[9].pin[0].digital_out[0]"/>
                 </Net>
-                <Net>
-                    <Port name="cpuss[0].dw0[0].chan[0].tr_in[0]"/>
-                    <Port name="udb[0].out_p[119]"/>
-                </Net>
-                <Net>
-                    <Port name="cpuss[0].dw0[0].chan[1].tr_in[0]"/>
-                    <Port name="udb[0].out_p[117]"/>
-                </Net>
-                <Net>
-                    <Port name="cpuss[0].dw1[0].chan[1].tr_in[0]"/>
-                    <Port name="udb[0].out_p[116]"/>
-                </Net>
-                <Net>
-                    <Port name="cpuss[0].dw1[0].chan[3].tr_in[0]"/>
-                    <Port name="udb[0].out_p[123]"/>
-                </Net>
                 <Net>
                     <Port name="csd[0].csd[0].clock[0]"/>
                     <Port name="peri[0].div_8[4].clk[0]"/>
@@ -1342,70 +1150,6 @@
                     <Port name="ioss[0].port[0].pin[1].analog[0]"/>
                     <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
                 </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[0].digital_in[0]"/>
-                    <Port name="udb[0].in_p[48]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[0].digital_out[0]"/>
-                    <Port name="udb[0].port_if[16]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[0].oe[0]"/>
-                    <Port name="udb[0].port_oe[16]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[1].digital_in[0]"/>
-                    <Port name="udb[0].in_p[49]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[1].digital_out[0]"/>
-                    <Port name="udb[0].port_if[17]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[1].oe[0]"/>
-                    <Port name="udb[0].port_oe[17]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[2].digital_in[0]"/>
-                    <Port name="udb[0].in_p[50]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[2].digital_out[0]"/>
-                    <Port name="udb[0].port_if[18]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[2].oe[0]"/>
-                    <Port name="udb[0].port_oe[18]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[3].digital_in[0]"/>
-                    <Port name="udb[0].in_p[51]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[3].digital_out[0]"/>
-                    <Port name="udb[0].port_if[19]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[3].oe[0]"/>
-                    <Port name="udb[0].port_oe[19]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[4].digital_in[0]"/>
-                    <Port name="udb[0].in_p[52]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[4].digital_out[0]"/>
-                    <Port name="udb[0].port_if[20]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[4].oe[0]"/>
-                    <Port name="udb[0].port_oe[20]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[2].pin[5].digital_out[0]"/>
-                    <Port name="udb[0].port_if[21]"/>
-                </Net>
                 <Net>
                     <Port name="ioss[0].port[3].pin[0].digital_inout[0]"/>
                     <Port name="scb[2].uart_rx[0]"/>
@@ -1482,14 +1226,6 @@
                     <Port name="ioss[0].port[12].pin[7].analog[0]"/>
                     <Port name="srss[0].clock[0].eco[0].eco_out[0]"/>
                 </Net>
-                <Net>
-                    <Port name="ioss[0].port[13].pin[0].digital_inout[0]"/>
-                    <Port name="scb[6].uart_rx[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[13].pin[1].digital_inout[0]"/>
-                    <Port name="scb[6].uart_tx[0]"/>
-                </Net>
                 <Net>
                     <Port name="ioss[0].port[14].pin[0].aux[0]"/>
                     <Port name="usb[0].usb_dp_pad[0]"/>
@@ -1502,26 +1238,13 @@
                     <Port name="peri[0].div_16[0].clk[0]"/>
                     <Port name="usb[0].clock_dev_brs[0]"/>
                 </Net>
-                <Net>
-                    <Port name="peri[0].div_8[0].clk[0]"/>
-                    <Port name="udb[0].clocks[0]"/>
-                </Net>
                 <Net>
                     <Port name="peri[0].div_8[1].clk[0]"/>
                     <Port name="scb[3].clock[0]"/>
                 </Net>
                 <Net>
-                    <Port name="peri[0].div_8[2].clk[0]"/>
+                    <Port name="peri[0].div_8[3].clk[0]"/>
                     <Port name="scb[2].clock[0]"/>
-                    <Port name="scb[6].clock[0]"/>
-                </Net>
-                <Net>
-                    <Port name="peri[0].div_8[5].clk[0]"/>
-                    <Port name="scb[1].clock[0]"/>
-                </Net>
-                <Net>
-                    <Port name="peri[0].div_8[6].clk[0]"/>
-                    <Port name="scb[5].clock[0]"/>
                 </Net>
                 <Net>
                     <Port name="smif[0].clk_hf[0]"/>
@@ -1575,6 +1298,10 @@
                 </Mux>
             </Netlist>
         </Device>
+        <Device mpn="CYW43012WKWBG">
+            <BlockConfig/>
+            <Netlist/>
+        </Device>
     </Devices>
     <Libraries>
         <Library name="psoc6sw" version="1.2"/>
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.c
deleted file mode 100644
index 025d36c953f..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_clocks.c
-*
-* Description:
-* Clock configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_clocks.h"
-
-
-void init_cycfg_clocks(void)
-{
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 255U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 5U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 5U, 6U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 5U);
-
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 6U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 6U, 108U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 6U);
-}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h
deleted file mode 100644
index a627cb71a59..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h
+++ /dev/null
@@ -1,933 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.h
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PINS_H)
-#define CYCFG_PINS_H
-
-#include "cycfg_notices.h"
-#include "cy_gpio.h"
-#include "cycfg_routing.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_WCO_IN_ENABLED 1U
-#define CYBSP_WCO_IN_PORT GPIO_PRT0
-#define CYBSP_WCO_IN_PIN 0U
-#define CYBSP_WCO_IN_NUM 0U
-#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_0_HSIOM
-	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_WCO_OUT_ENABLED 1U
-#define CYBSP_WCO_OUT_PORT GPIO_PRT0
-#define CYBSP_WCO_OUT_PIN 1U
-#define CYBSP_WCO_OUT_NUM 1U
-#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_1_HSIOM
-	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_LED_RED_ENABLED 1U
-#define CYBSP_LED_RED_PORT GPIO_PRT0
-#define CYBSP_LED_RED_PIN 3U
-#define CYBSP_LED_RED_NUM 3U
-#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_RED_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_3_HSIOM
-	#define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
-#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_SW6_ENABLED 1U
-#define CYBSP_SW6_PORT GPIO_PRT0
-#define CYBSP_SW6_PIN 4U
-#define CYBSP_SW6_NUM 4U
-#define CYBSP_SW6_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SW6_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_4_HSIOM
-	#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SW6_HSIOM ioss_0_port_0_pin_4_HSIOM
-#define CYBSP_SW6_IRQ ioss_interrupts_gpio_0_IRQn
-#define CYBSP_ROW6_SPI_MOSI_ENABLED 1U
-#define CYBSP_ROW6_SPI_MOSI_PORT GPIO_PRT10
-#define CYBSP_ROW6_SPI_MOSI_PIN 0U
-#define CYBSP_ROW6_SPI_MOSI_NUM 0U
-#define CYBSP_ROW6_SPI_MOSI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_ROW6_SPI_MOSI_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_10_pin_0_HSIOM
-	#define ioss_0_port_10_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_ROW6_SPI_MOSI_HSIOM ioss_0_port_10_pin_0_HSIOM
-#define CYBSP_ROW6_SPI_MOSI_IRQ ioss_interrupts_gpio_10_IRQn
-#define CYBSP_COL8_SPI_MISO_ENABLED 1U
-#define CYBSP_COL8_SPI_MISO_PORT GPIO_PRT10
-#define CYBSP_COL8_SPI_MISO_PIN 1U
-#define CYBSP_COL8_SPI_MISO_NUM 1U
-#define CYBSP_COL8_SPI_MISO_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_COL8_SPI_MISO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_10_pin_1_HSIOM
-	#define ioss_0_port_10_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_COL8_SPI_MISO_HSIOM ioss_0_port_10_pin_1_HSIOM
-#define CYBSP_COL8_SPI_MISO_IRQ ioss_interrupts_gpio_10_IRQn
-#define CYBSP_ROW7_SPI_CLK_ENABLED 1U
-#define CYBSP_ROW7_SPI_CLK_PORT GPIO_PRT10
-#define CYBSP_ROW7_SPI_CLK_PIN 2U
-#define CYBSP_ROW7_SPI_CLK_NUM 2U
-#define CYBSP_ROW7_SPI_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_ROW7_SPI_CLK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_10_pin_2_HSIOM
-	#define ioss_0_port_10_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_ROW7_SPI_CLK_HSIOM ioss_0_port_10_pin_2_HSIOM
-#define CYBSP_ROW7_SPI_CLK_IRQ ioss_interrupts_gpio_10_IRQn
-#define CYBSP_COL7_SPI_CS_ENABLED 1U
-#define CYBSP_COL7_SPI_CS_PORT GPIO_PRT10
-#define CYBSP_COL7_SPI_CS_PIN 3U
-#define CYBSP_COL7_SPI_CS_NUM 3U
-#define CYBSP_COL7_SPI_CS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_COL7_SPI_CS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_10_pin_3_HSIOM
-	#define ioss_0_port_10_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_COL7_SPI_CS_HSIOM ioss_0_port_10_pin_3_HSIOM
-#define CYBSP_COL7_SPI_CS_IRQ ioss_interrupts_gpio_10_IRQn
-#define CYBSP_BAT_MON_ENABLED 1U
-#define CYBSP_BAT_MON_PORT GPIO_PRT10
-#define CYBSP_BAT_MON_PIN 4U
-#define CYBSP_BAT_MON_NUM 4U
-#define CYBSP_BAT_MON_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BAT_MON_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_10_pin_4_HSIOM
-	#define ioss_0_port_10_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BAT_MON_HSIOM ioss_0_port_10_pin_4_HSIOM
-#define CYBSP_BAT_MON_IRQ ioss_interrupts_gpio_10_IRQn
-#define CYBSP_LED_BLUE_ENABLED 1U
-#define CYBSP_LED_BLUE_PORT GPIO_PRT10
-#define CYBSP_LED_BLUE_PIN 6U
-#define CYBSP_LED_BLUE_NUM 6U
-#define CYBSP_LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_BLUE_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_10_pin_6_HSIOM
-	#define ioss_0_port_10_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_BLUE_HSIOM ioss_0_port_10_pin_6_HSIOM
-#define CYBSP_LED_BLUE_IRQ ioss_interrupts_gpio_10_IRQn
-#define CYBSP_WL_WAKE_ENABLED 1U
-#define CYBSP_WL_WAKE_PORT GPIO_PRT10
-#define CYBSP_WL_WAKE_PIN 7U
-#define CYBSP_WL_WAKE_NUM 7U
-#define CYBSP_WL_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_WL_WAKE_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_10_pin_7_HSIOM
-	#define ioss_0_port_10_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WL_WAKE_HSIOM ioss_0_port_10_pin_7_HSIOM
-#define CYBSP_WL_WAKE_IRQ ioss_interrupts_gpio_10_IRQn
-#define CYBSP_WL_UART_RX_ENABLED 1U
-#define CYBSP_WL_UART_RX_PORT GPIO_PRT11
-#define CYBSP_WL_UART_RX_PIN 0U
-#define CYBSP_WL_UART_RX_NUM 0U
-#define CYBSP_WL_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_WL_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_0_HSIOM
-	#define ioss_0_port_11_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WL_UART_RX_HSIOM ioss_0_port_11_pin_0_HSIOM
-#define CYBSP_WL_UART_RX_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_WL_UART_TX_ENABLED 1U
-#define CYBSP_WL_UART_TX_PORT GPIO_PRT11
-#define CYBSP_WL_UART_TX_PIN 1U
-#define CYBSP_WL_UART_TX_NUM 1U
-#define CYBSP_WL_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_WL_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_1_HSIOM
-	#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WL_UART_TX_HSIOM ioss_0_port_11_pin_1_HSIOM
-#define CYBSP_WL_UART_TX_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SS_ENABLED 1U
-#define CYBSP_QSPI_SS_PORT GPIO_PRT11
-#define CYBSP_QSPI_SS_PIN 2U
-#define CYBSP_QSPI_SS_NUM 2U
-#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_2_HSIOM
-	#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
-#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D3_ENABLED 1U
-#define CYBSP_QSPI_D3_PORT GPIO_PRT11
-#define CYBSP_QSPI_D3_PIN 3U
-#define CYBSP_QSPI_D3_NUM 3U
-#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_3_HSIOM
-	#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
-#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D2_ENABLED 1U
-#define CYBSP_QSPI_D2_PORT GPIO_PRT11
-#define CYBSP_QSPI_D2_PIN 4U
-#define CYBSP_QSPI_D2_NUM 4U
-#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_4_HSIOM
-	#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
-#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D1_ENABLED 1U
-#define CYBSP_QSPI_D1_PORT GPIO_PRT11
-#define CYBSP_QSPI_D1_PIN 5U
-#define CYBSP_QSPI_D1_NUM 5U
-#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_5_HSIOM
-	#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
-#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_D0_ENABLED 1U
-#define CYBSP_QSPI_D0_PORT GPIO_PRT11
-#define CYBSP_QSPI_D0_PIN 6U
-#define CYBSP_QSPI_D0_NUM 6U
-#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_6_HSIOM
-	#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
-#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_QSPI_SCK_ENABLED 1U
-#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
-#define CYBSP_QSPI_SCK_PIN 7U
-#define CYBSP_QSPI_SCK_NUM 7U
-#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_7_HSIOM
-	#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
-#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
-#define CYBSP_BT_GPIO4_ENABLED 1U
-#define CYBSP_BT_GPIO4_PORT GPIO_PRT12
-#define CYBSP_BT_GPIO4_PIN 0U
-#define CYBSP_BT_GPIO4_NUM 0U
-#define CYBSP_BT_GPIO4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_BT_GPIO4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_12_pin_0_HSIOM
-	#define ioss_0_port_12_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_GPIO4_HSIOM ioss_0_port_12_pin_0_HSIOM
-#define CYBSP_BT_GPIO4_IRQ ioss_interrupts_gpio_12_IRQn
-#define CYBSP_BT_GPIO5_ENABLED 1U
-#define CYBSP_BT_GPIO5_PORT GPIO_PRT12
-#define CYBSP_BT_GPIO5_PIN 1U
-#define CYBSP_BT_GPIO5_NUM 1U
-#define CYBSP_BT_GPIO5_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_BT_GPIO5_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_12_pin_1_HSIOM
-	#define ioss_0_port_12_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_GPIO5_HSIOM ioss_0_port_12_pin_1_HSIOM
-#define CYBSP_BT_GPIO5_IRQ ioss_interrupts_gpio_12_IRQn
-#define CYBSP_BT_GPIO2_ENABLED 1U
-#define CYBSP_BT_GPIO2_PORT GPIO_PRT12
-#define CYBSP_BT_GPIO2_PIN 2U
-#define CYBSP_BT_GPIO2_NUM 2U
-#define CYBSP_BT_GPIO2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_BT_GPIO2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_12_pin_2_HSIOM
-	#define ioss_0_port_12_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_GPIO2_HSIOM ioss_0_port_12_pin_2_HSIOM
-#define CYBSP_BT_GPIO2_IRQ ioss_interrupts_gpio_12_IRQn
-#define CYBSP_BT_GPIO3_ENABLED 1U
-#define CYBSP_BT_GPIO3_PORT GPIO_PRT12
-#define CYBSP_BT_GPIO3_PIN 3U
-#define CYBSP_BT_GPIO3_NUM 3U
-#define CYBSP_BT_GPIO3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_BT_GPIO3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_12_pin_3_HSIOM
-	#define ioss_0_port_12_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_GPIO3_HSIOM ioss_0_port_12_pin_3_HSIOM
-#define CYBSP_BT_GPIO3_IRQ ioss_interrupts_gpio_12_IRQn
-#define CYBSP_ECO_IN_ENABLED 1U
-#define CYBSP_ECO_IN_PORT GPIO_PRT12
-#define CYBSP_ECO_IN_PIN 6U
-#define CYBSP_ECO_IN_NUM 6U
-#define CYBSP_ECO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_ECO_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_12_pin_6_HSIOM
-	#define ioss_0_port_12_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_ECO_IN_HSIOM ioss_0_port_12_pin_6_HSIOM
-#define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_12_IRQn
-#define CYBSP_ECO_OUT_ENABLED 1U
-#define CYBSP_ECO_OUT_PORT GPIO_PRT12
-#define CYBSP_ECO_OUT_PIN 7U
-#define CYBSP_ECO_OUT_NUM 7U
-#define CYBSP_ECO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_ECO_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_12_pin_7_HSIOM
-	#define ioss_0_port_12_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_ECO_OUT_HSIOM ioss_0_port_12_pin_7_HSIOM
-#define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_12_IRQn
-#define CYBSP_DEBUG_UART_RX_ENABLED 1U
-#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT13
-#define CYBSP_DEBUG_UART_RX_PIN 0U
-#define CYBSP_DEBUG_UART_RX_NUM 0U
-#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_13_pin_0_HSIOM
-	#define ioss_0_port_13_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_13_pin_0_HSIOM
-#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_13_IRQn
-#define CYBSP_DEBUG_UART_TX_ENABLED 1U
-#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT13
-#define CYBSP_DEBUG_UART_TX_PIN 1U
-#define CYBSP_DEBUG_UART_TX_NUM 1U
-#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_13_pin_1_HSIOM
-	#define ioss_0_port_13_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_13_pin_1_HSIOM
-#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_13_IRQn
-#define CYBSP_USB_DEV_VBUS_DET_ENABLED 1U
-#define CYBSP_USB_DEV_VBUS_DET_PORT GPIO_PRT13
-#define CYBSP_USB_DEV_VBUS_DET_PIN 4U
-#define CYBSP_USB_DEV_VBUS_DET_NUM 4U
-#define CYBSP_USB_DEV_VBUS_DET_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_USB_DEV_VBUS_DET_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_13_pin_4_HSIOM
-	#define ioss_0_port_13_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_USB_DEV_VBUS_DET_HSIOM ioss_0_port_13_pin_4_HSIOM
-#define CYBSP_USB_DEV_VBUS_DET_IRQ ioss_interrupts_gpio_13_IRQn
-#define CYBSP_USB_HOST_EN_ENABLED 1U
-#define CYBSP_USB_HOST_EN_PORT GPIO_PRT13
-#define CYBSP_USB_HOST_EN_PIN 5U
-#define CYBSP_USB_HOST_EN_NUM 5U
-#define CYBSP_USB_HOST_EN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_USB_HOST_EN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_13_pin_5_HSIOM
-	#define ioss_0_port_13_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_USB_HOST_EN_HSIOM ioss_0_port_13_pin_5_HSIOM
-#define CYBSP_USB_HOST_EN_IRQ ioss_interrupts_gpio_13_IRQn
-#define CYBSP_USB_INT_L_ENABLED 1U
-#define CYBSP_USB_INT_L_PORT GPIO_PRT13
-#define CYBSP_USB_INT_L_PIN 7U
-#define CYBSP_USB_INT_L_NUM 7U
-#define CYBSP_USB_INT_L_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_USB_INT_L_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_13_pin_7_HSIOM
-	#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_USB_INT_L_HSIOM ioss_0_port_13_pin_7_HSIOM
-#define CYBSP_USB_INT_L_IRQ ioss_interrupts_gpio_13_IRQn
-#define CYBSP_USB_DP_ENABLED 1U
-#define CYBSP_USB_DP_PORT GPIO_PRT14
-#define CYBSP_USB_DP_PIN 0U
-#define CYBSP_USB_DP_NUM 0U
-#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_USB_DP_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_14_pin_0_HSIOM
-	#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
-#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
-#define CYBSP_USB_DM_ENABLED 1U
-#define CYBSP_USB_DM_PORT GPIO_PRT14
-#define CYBSP_USB_DM_PIN 1U
-#define CYBSP_USB_DM_NUM 1U
-#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_USB_DM_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_14_pin_1_HSIOM
-	#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
-#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
-#define CYBSP_CSD_TX_ENABLED 1U
-#define CYBSP_CSD_TX_PORT GPIO_PRT1
-#define CYBSP_CSD_TX_PIN 0U
-#define CYBSP_CSD_TX_NUM 0U
-#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_0_HSIOM
-	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_LED_GREEN_ENABLED 1U
-#define CYBSP_LED_GREEN_PORT GPIO_PRT1
-#define CYBSP_LED_GREEN_PIN 1U
-#define CYBSP_LED_GREEN_NUM 1U
-#define CYBSP_LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_LED_GREEN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_1_HSIOM
-	#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
-#define CYBSP_LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_WL_SECI_IN_ENABLED 1U
-#define CYBSP_WL_SECI_IN_PORT GPIO_PRT1
-#define CYBSP_WL_SECI_IN_PIN 2U
-#define CYBSP_WL_SECI_IN_NUM 2U
-#define CYBSP_WL_SECI_IN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_WL_SECI_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_2_HSIOM
-	#define ioss_0_port_1_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WL_SECI_IN_HSIOM ioss_0_port_1_pin_2_HSIOM
-#define CYBSP_WL_SECI_IN_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_WL_FRAM_SYNC_ENABLED 1U
-#define CYBSP_WL_FRAM_SYNC_PORT GPIO_PRT1
-#define CYBSP_WL_FRAM_SYNC_PIN 3U
-#define CYBSP_WL_FRAM_SYNC_NUM 3U
-#define CYBSP_WL_FRAM_SYNC_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_WL_FRAM_SYNC_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_3_HSIOM
-	#define ioss_0_port_1_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WL_FRAM_SYNC_HSIOM ioss_0_port_1_pin_3_HSIOM
-#define CYBSP_WL_FRAM_SYNC_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_WL_PRIORITY_ENABLED 1U
-#define CYBSP_WL_PRIORITY_PORT GPIO_PRT1
-#define CYBSP_WL_PRIORITY_PIN 4U
-#define CYBSP_WL_PRIORITY_NUM 4U
-#define CYBSP_WL_PRIORITY_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_WL_PRIORITY_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_4_HSIOM
-	#define ioss_0_port_1_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WL_PRIORITY_HSIOM ioss_0_port_1_pin_4_HSIOM
-#define CYBSP_WL_PRIORITY_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_WL_SECI_OUT_ENABLED 1U
-#define CYBSP_WL_SECI_OUT_PORT GPIO_PRT1
-#define CYBSP_WL_SECI_OUT_PIN 5U
-#define CYBSP_WL_SECI_OUT_NUM 5U
-#define CYBSP_WL_SECI_OUT_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_WL_SECI_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_5_HSIOM
-	#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WL_SECI_OUT_HSIOM ioss_0_port_1_pin_5_HSIOM
-#define CYBSP_WL_SECI_OUT_IRQ ioss_interrupts_gpio_1_IRQn
-#define CYBSP_WIFI_SDIO_D0_ENABLED 1U
-#define CYBSP_WIFI_SDIO_D0_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_D0_PIN 0U
-#define CYBSP_WIFI_SDIO_D0_NUM 0U
-#define CYBSP_WIFI_SDIO_D0_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_D0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_0_HSIOM
-	#define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_D0_HSIOM ioss_0_port_2_pin_0_HSIOM
-#define CYBSP_WIFI_SDIO_D0_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_D1_ENABLED 1U
-#define CYBSP_WIFI_SDIO_D1_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_D1_PIN 1U
-#define CYBSP_WIFI_SDIO_D1_NUM 1U
-#define CYBSP_WIFI_SDIO_D1_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_D1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_1_HSIOM
-	#define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_D1_HSIOM ioss_0_port_2_pin_1_HSIOM
-#define CYBSP_WIFI_SDIO_D1_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_D2_ENABLED 1U
-#define CYBSP_WIFI_SDIO_D2_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_D2_PIN 2U
-#define CYBSP_WIFI_SDIO_D2_NUM 2U
-#define CYBSP_WIFI_SDIO_D2_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_D2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_2_HSIOM
-	#define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_D2_HSIOM ioss_0_port_2_pin_2_HSIOM
-#define CYBSP_WIFI_SDIO_D2_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_D3_ENABLED 1U
-#define CYBSP_WIFI_SDIO_D3_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_D3_PIN 3U
-#define CYBSP_WIFI_SDIO_D3_NUM 3U
-#define CYBSP_WIFI_SDIO_D3_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_D3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_3_HSIOM
-	#define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_D3_HSIOM ioss_0_port_2_pin_3_HSIOM
-#define CYBSP_WIFI_SDIO_D3_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_CMD_ENABLED 1U
-#define CYBSP_WIFI_SDIO_CMD_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_CMD_PIN 4U
-#define CYBSP_WIFI_SDIO_CMD_NUM 4U
-#define CYBSP_WIFI_SDIO_CMD_DRIVEMODE CY_GPIO_DM_STRONG
-#define CYBSP_WIFI_SDIO_CMD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_4_HSIOM
-	#define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
-#define CYBSP_WIFI_SDIO_CMD_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_SDIO_CLK_ENABLED 1U
-#define CYBSP_WIFI_SDIO_CLK_PORT GPIO_PRT2
-#define CYBSP_WIFI_SDIO_CLK_PIN 5U
-#define CYBSP_WIFI_SDIO_CLK_NUM 5U
-#define CYBSP_WIFI_SDIO_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_WIFI_SDIO_CLK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_5_HSIOM
-	#define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_SDIO_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
-#define CYBSP_WIFI_SDIO_CLK_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_WL_REG_ON_ENABLED 1U
-#define CYBSP_WIFI_WL_REG_ON_PORT GPIO_PRT2
-#define CYBSP_WIFI_WL_REG_ON_PIN 6U
-#define CYBSP_WIFI_WL_REG_ON_NUM 6U
-#define CYBSP_WIFI_WL_REG_ON_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_WIFI_WL_REG_ON_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_2_pin_6_HSIOM
-	#define ioss_0_port_2_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_WL_REG_ON_HSIOM ioss_0_port_2_pin_6_HSIOM
-#define CYBSP_WIFI_WL_REG_ON_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
-#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2
-#define CYBSP_WIFI_HOST_WAKE_PIN 7U
-#define CYBSP_WIFI_HOST_WAKE_NUM 7U
-#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_2_pin_7_HSIOM
-	#define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM
-#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn
-#define CYBSP_BT_UART_RX_ENABLED 1U
-#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
-#define CYBSP_BT_UART_RX_PIN 0U
-#define CYBSP_BT_UART_RX_NUM 0U
-#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_0_HSIOM
-	#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
-#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_TX_ENABLED 1U
-#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
-#define CYBSP_BT_UART_TX_PIN 1U
-#define CYBSP_BT_UART_TX_NUM 1U
-#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_1_HSIOM
-	#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
-#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_RTS_ENABLED 1U
-#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
-#define CYBSP_BT_UART_RTS_PIN 2U
-#define CYBSP_BT_UART_RTS_NUM 2U
-#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_2_HSIOM
-	#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
-#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_UART_CTS_ENABLED 1U
-#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
-#define CYBSP_BT_UART_CTS_PIN 3U
-#define CYBSP_BT_UART_CTS_NUM 3U
-#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_3_HSIOM
-	#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
-#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_REG_ON_ENABLED 1U
-#define CYBSP_BT_REG_ON_PORT GPIO_PRT3
-#define CYBSP_BT_REG_ON_PIN 4U
-#define CYBSP_BT_REG_ON_NUM 4U
-#define CYBSP_BT_REG_ON_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
-#define CYBSP_BT_REG_ON_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_3_pin_4_HSIOM
-	#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_REG_ON_HSIOM ioss_0_port_3_pin_4_HSIOM
-#define CYBSP_BT_REG_ON_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_HOST_WAKE_ENABLED 1U
-#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
-#define CYBSP_BT_HOST_WAKE_PIN 5U
-#define CYBSP_BT_HOST_WAKE_NUM 5U
-#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_3_pin_5_HSIOM
-	#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
-#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
-#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
-#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
-#define CYBSP_BT_DEVICE_WAKE_PIN 0U
-#define CYBSP_BT_DEVICE_WAKE_NUM 0U
-#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_4_pin_0_HSIOM
-	#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
-#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
-#define CYBSP_BT_RST_ENABLED 1U
-#define CYBSP_BT_RST_PORT GPIO_PRT4
-#define CYBSP_BT_RST_PIN 1U
-#define CYBSP_BT_RST_NUM 1U
-#define CYBSP_BT_RST_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_BT_RST_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_4_pin_1_HSIOM
-	#define ioss_0_port_4_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_BT_RST_HSIOM ioss_0_port_4_pin_1_HSIOM
-#define CYBSP_BT_RST_IRQ ioss_interrupts_gpio_4_IRQn
-#define CYBSP_EZI2C_SCL_ENABLED 1U
-#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SCL_PIN 0U
-#define CYBSP_EZI2C_SCL_NUM 0U
-#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_0_HSIOM
-	#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
-#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_EZI2C_SDA_ENABLED 1U
-#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
-#define CYBSP_EZI2C_SDA_PIN 1U
-#define CYBSP_EZI2C_SDA_NUM 1U
-#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_1_HSIOM
-	#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
-#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWO_ENABLED 1U
-#define CYBSP_SWO_PORT GPIO_PRT6
-#define CYBSP_SWO_PIN 4U
-#define CYBSP_SWO_NUM 4U
-#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_SWO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_4_HSIOM
-	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWDIO_ENABLED 1U
-#define CYBSP_SWDIO_PORT GPIO_PRT6
-#define CYBSP_SWDIO_PIN 6U
-#define CYBSP_SWDIO_NUM 6U
-#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SWDIO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_6_HSIOM
-	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_SWCLK_ENABLED 1U
-#define CYBSP_SWCLK_PORT GPIO_PRT6
-#define CYBSP_SWCLK_PIN 7U
-#define CYBSP_SWCLK_NUM 7U
-#define CYBSP_SWCLK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define CYBSP_SWCLK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_7_HSIOM
-	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWCLK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define CYBSP_SWCLK_IRQ ioss_interrupts_gpio_6_IRQn
-#define CYBSP_TRACECLK_ENABLED 1U
-#define CYBSP_TRACECLK_PORT GPIO_PRT7
-#define CYBSP_TRACECLK_PIN 0U
-#define CYBSP_TRACECLK_NUM 0U
-#define CYBSP_TRACECLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_TRACECLK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_0_HSIOM
-	#define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_TRACECLK_HSIOM ioss_0_port_7_pin_0_HSIOM
-#define CYBSP_TRACECLK_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CINTA_ENABLED 1U
-#define CYBSP_CINTA_PORT GPIO_PRT7
-#define CYBSP_CINTA_PIN 1U
-#define CYBSP_CINTA_NUM 1U
-#define CYBSP_CINTA_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINTA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_1_HSIOM
-	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINTA_HSIOM ioss_0_port_7_pin_1_HSIOM
-#define CYBSP_CINTA_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CINTB_ENABLED 1U
-#define CYBSP_CINTB_PORT GPIO_PRT7
-#define CYBSP_CINTB_PIN 2U
-#define CYBSP_CINTB_NUM 2U
-#define CYBSP_CINTB_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINTB_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_2_HSIOM
-	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINTB_HSIOM ioss_0_port_7_pin_2_HSIOM
-#define CYBSP_CINTB_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CMOD_ENABLED 1U
-#define CYBSP_CMOD_PORT GPIO_PRT7
-#define CYBSP_CMOD_PIN 7U
-#define CYBSP_CMOD_NUM 7U
-#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CMOD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_7_HSIOM
-	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
-#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_CSD_BTN0_ENABLED 1U
-#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN0_PIN 1U
-#define CYBSP_CSD_BTN0_NUM 1U
-#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_1_HSIOM
-	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_BTN1_ENABLED 1U
-#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN1_PIN 2U
-#define CYBSP_CSD_BTN1_NUM 2U
-#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_2_HSIOM
-	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
-#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD0_ENABLED 1U
-#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD0_PIN 3U
-#define CYBSP_CSD_SLD0_NUM 3U
-#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_3_HSIOM
-	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD1_ENABLED 1U
-#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD1_PIN 4U
-#define CYBSP_CSD_SLD1_NUM 4U
-#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_4_HSIOM
-	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
-#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD2_ENABLED 1U
-#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD2_PIN 5U
-#define CYBSP_CSD_SLD2_NUM 5U
-#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_5_HSIOM
-	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
-#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD3_ENABLED 1U
-#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD3_PIN 6U
-#define CYBSP_CSD_SLD3_NUM 6U
-#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_6_HSIOM
-	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
-#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CSD_SLD4_ENABLED 1U
-#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD4_PIN 7U
-#define CYBSP_CSD_SLD4_NUM 7U
-#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_7_HSIOM
-	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
-#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_TRACEDATA3_ENABLED 1U
-#define CYBSP_TRACEDATA3_PORT GPIO_PRT9
-#define CYBSP_TRACEDATA3_PIN 0U
-#define CYBSP_TRACEDATA3_NUM 0U
-#define CYBSP_TRACEDATA3_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_TRACEDATA3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_9_pin_0_HSIOM
-	#define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_TRACEDATA3_HSIOM ioss_0_port_9_pin_0_HSIOM
-#define CYBSP_TRACEDATA3_IRQ ioss_interrupts_gpio_9_IRQn
-#define CYBSP_TRACEDATA2_ENABLED 1U
-#define CYBSP_TRACEDATA2_PORT GPIO_PRT9
-#define CYBSP_TRACEDATA2_PIN 1U
-#define CYBSP_TRACEDATA2_NUM 1U
-#define CYBSP_TRACEDATA2_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_TRACEDATA2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_9_pin_1_HSIOM
-	#define ioss_0_port_9_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_TRACEDATA2_HSIOM ioss_0_port_9_pin_1_HSIOM
-#define CYBSP_TRACEDATA2_IRQ ioss_interrupts_gpio_9_IRQn
-#define CYBSP_TRACEDATA1_ENABLED 1U
-#define CYBSP_TRACEDATA1_PORT GPIO_PRT9
-#define CYBSP_TRACEDATA1_PIN 2U
-#define CYBSP_TRACEDATA1_NUM 2U
-#define CYBSP_TRACEDATA1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_TRACEDATA1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_9_pin_2_HSIOM
-	#define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_TRACEDATA1_HSIOM ioss_0_port_9_pin_2_HSIOM
-#define CYBSP_TRACEDATA1_IRQ ioss_interrupts_gpio_9_IRQn
-#define CYBSP_TRACEDATA0_ENABLED 1U
-#define CYBSP_TRACEDATA0_PORT GPIO_PRT9
-#define CYBSP_TRACEDATA0_PIN 3U
-#define CYBSP_TRACEDATA0_NUM 3U
-#define CYBSP_TRACEDATA0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_TRACEDATA0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_9_pin_3_HSIOM
-	#define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_TRACEDATA0_HSIOM ioss_0_port_9_pin_3_HSIOM
-#define CYBSP_TRACEDATA0_IRQ ioss_interrupts_gpio_9_IRQn
-
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SW6_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_ROW6_SPI_MOSI_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_COL8_SPI_MISO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_ROW7_SPI_CLK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_COL7_SPI_CS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BAT_MON_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WL_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WL_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WL_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO4_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO5_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_USB_DEV_VBUS_DET_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_USB_HOST_EN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_USB_INT_L_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_IN_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WL_FRAM_SYNC_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WL_PRIORITY_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_OUT_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_REG_ON_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_BT_RST_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_TRACECLK_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINTA_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CINTB_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA3_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA2_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA1_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA0_config;
-
-void init_cycfg_pins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PINS_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.h
deleted file mode 100644
index 1f4fb5dfcae..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_qspi_memslot.h
-*
-* Description:
-* Provides declarations of the SMIF-driver memory configuration.
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#ifndef CYCFG_QSPI_MEMSLOT_H
-#define CYCFG_QSPI_MEMSLOT_H
-#include "cy_smif_memslot.h"
-
-#define CY_SMIF_DEVICE_NUM 1
-
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
-extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
-
-extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
-
-extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
-extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
-
-extern const cy_stc_smif_block_config_t smifBlockConfig;
-
-
-#endif /*CY_SMIF_MEMCONFIG_H*/
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/qspi_config.cfg
deleted file mode 100644
index a561643dcf1..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/qspi_config.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-set SMIF_BANKS {
-}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PeripheralPins.c
index 8ff59be3cb9..433e728ea3c 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PeripheralPins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PeripheralPins.c
@@ -104,7 +104,9 @@ const PinMap PinMap_I2C_SCL[] = {
     {P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_0_SCB7_I2C_SCL)},
     {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
     {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
+    {P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
     {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
+    {P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
     {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
     {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
     {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
@@ -122,7 +124,9 @@ const PinMap PinMap_I2C_SDA[] = {
     {P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_1_SCB7_I2C_SDA)},
     {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
     {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
+    {P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
     {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
+    {P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
     {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
     {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
     {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
@@ -144,7 +148,9 @@ const PinMap PinMap_SPI_MOSI[] = {
     {P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)},
     {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
     {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
+    {P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
     {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
+    {P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
     {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
     {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
     {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
@@ -162,7 +168,9 @@ const PinMap PinMap_SPI_MISO[] = {
     {P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)},
     {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
     {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
+    {P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
     {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
+    {P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
     {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
     {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
     {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
@@ -179,7 +187,9 @@ const PinMap PinMap_SPI_SCLK[] = {
     {P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)},
     {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
     {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
+    {P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
     {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
+    {P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
     {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
     {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
     {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
@@ -195,7 +205,9 @@ const PinMap PinMap_SPI_SSEL[] = {
     {P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)},
     {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
     {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
+    {P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
     {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
+    {P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
     {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
     {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
     {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
@@ -430,7 +442,6 @@ const PinMap PinMap_ADC[] = {
 #if DEVICE_ANALOGOUT
 const PinMap PinMap_DAC[] = {
     {P9_6,  DAC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
-    {P10_5, DAC_0, CY_GPIO_CFG_CREATE(HSIOM_SEL_AMUXA, CY_GPIO_DM_ANALOG)},  // CTDAC connects to the P10_5 pin through the AMUXA bus
     {NC,    NC,     0}
 };
 #endif // DEVICE_ANALOGIN
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PinNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PinNames.h
index 203722d9e6a..e4794b5c022 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PinNames.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PinNames.h
@@ -20,13 +20,8 @@
 #ifndef MBED_PINNAMES_H
 #define MBED_PINNAMES_H
 
-#include "cmsis.h"
 #include "PinNamesTypes.h"
-#include "PortNames.h"
 #include "cyhal_pin_package.h"
-#include "cyhal_utils.h"
-
-typedef cyhal_gpio_t PinName;
 
 // Generic signal names
 
@@ -43,25 +38,14 @@ typedef cyhal_gpio_t PinName;
 #define UART_RTS P13_2
 #define UART_CTS P13_3
 
-#define BT_UART_RX P3_0
-#define BT_UART_TX P3_1
-#define BT_UART_CTS P3_3
-#define BT_UART_RTS P3_2
-
-#define BT_PIN_POWER P3_4
-#define BT_PIN_HOST_WAKE P4_0
-#define BT_PIN_DEVICE_WAKE P3_5
-#define BT_PIN_DEVICE_RESET P4_1
-
-#define SWITCH2 P0_4
 #define LED1 P0_3
 #define LED2 P1_1
 #define LED3 P10_6
-
 #define LED_RED LED1
-#define LED_BLUE LED3
 #define LED_GREEN LED2
+#define LED_BLUE LED3
 
+#define SWITCH2 P0_4
 #define USER_BUTTON SWITCH2
 #define BUTTON1 USER_BUTTON
 
@@ -85,23 +69,8 @@ typedef cyhal_gpio_t PinName;
 #define STDIO_UART_CTS UART_CTS
 #define STDIO_UART_RTS UART_RTS
 
-#define CY_STDIO_UART_RX STDIO_UART_RX
-#define CY_STDIO_UART_TX STDIO_UART_TX
-#define CY_STDIO_UART_CTS STDIO_UART_CTS
-#define CY_STDIO_UART_RTS STDIO_UART_RTS
-
-#define CY_BT_UART_RX BT_UART_RX
-#define CY_BT_UART_TX BT_UART_TX
-#define CY_BT_UART_CTS BT_UART_CTS
-#define CY_BT_UART_RTS BT_UART_RTS
-
-#define CY_BT_PIN_POWER BT_PIN_POWER
-#define CY_BT_PIN_HOST_WAKE BT_PIN_HOST_WAKE
-#define CY_BT_PIN_DEVICE_WAKE BT_PIN_DEVICE_WAKE
-
 #define USBTX UART_TX
 #define USBRX UART_RX
 
-#define CY_WIFI_HOST_WAKE P2_7
 
 #endif
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c
index 9cab459a4dd..dac8480d91f 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c
@@ -28,13 +28,23 @@
 extern "C" {
 #endif
 
-#ifdef SEMAPHORE
-#include "cyabs_rtos.h"
+#ifdef CY_RTOS_AWARE
 
-#define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL )
-static cy_semaphore_t sdio_transfer_finished_semaphore;
+    #include "cyabs_rtos.h"
+
+    #define NEVER_TIMEOUT ( (uint32_t)0xffffffffUL )
+    static cy_semaphore_t sdio_transfer_finished_semaphore;
+    static bool sema_initialized = false;
 #endif
 
+/* Backup struct used to store and restore non retention UDB registers */
+typedef struct
+{
+    uint32_t CY_SDIO_UDB_WRKMULT_CTL_0;
+    uint32_t CY_SDIO_UDB_WRKMULT_CTL_1;
+    uint32_t CY_SDIO_UDB_WRKMULT_CTL_2;
+    uint32_t CY_SDIO_UDB_WRKMULT_CTL_3;
+} stc_sdio_backup_regs_t;
 
 /*Globals Needed for DMA */
 /*DMA channel structures*/
@@ -61,14 +71,63 @@ static uint8_t crcTable[256];
 static uint32_t yCountRemainder;
 static uint32_t yCounts;
 
+/* Global value for card interrupt */
+static uint8_t pfnCardInt_count = 0;
+
+/*Global structure to store UDB registers */
+static stc_sdio_backup_regs_t regs;
+
 static uint32_t udb_initialized = 0;
 
+cy_stc_syspm_callback_params_t      sdio_pm_callback_params;
+cy_stc_syspm_callback_t             sdio_pm_callback_handler;
+
+/* Deep Sleep Mode API Support */
+static void SDIO_SaveConfig(void);
+static void SDIO_RestoreConfig(void);
+
+/*******************************************************************************
+* Function Name: SDIO_DeepSleepCallback
+****************************************************************************//**
+*
+* Callback executed during Deep Sleep entry/exit
+*
+* \note
+* Saves/Restores SDIO UDB registers
+*******************************************************************************/
+cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode)
+{
+    cy_en_syspm_status_t status = CY_SYSPM_FAIL;
+
+    switch (mode) 
+    {
+        case CY_SYSPM_CHECK_READY:
+        case CY_SYSPM_CHECK_FAIL:
+            status = CY_SYSPM_SUCCESS;
+            break;
+
+        case CY_SYSPM_BEFORE_TRANSITION:
+            SDIO_SaveConfig();
+            status = CY_SYSPM_SUCCESS;
+            break;
+
+        case CY_SYSPM_AFTER_TRANSITION:
+            SDIO_RestoreConfig();
+            status = CY_SYSPM_SUCCESS;
+            break;
+
+        default:
+            break;
+    }
+
+    return status;
+}
 
 /*******************************************************************************
 * Function Name: SDIO_Init
 ****************************************************************************//**
 *
-* Initializes the SDIO hardware, and register the callback
+* Initializes the SDIO hardware
 *
 * \param pfuCb
 * Pointer to structure that holds pointers to callback function
@@ -132,11 +191,6 @@ void SDIO_Init(stc_sdio_irq_cb_t* pfuCb)
     SDIO_SetSdClkFrequency(400000);
     SDIO_EnableIntClock();
     SDIO_EnableSdClk();
-
-     /*Initalize the semaphore*/
-#ifdef SEMAPHORE
-    cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 1 );
-#endif
 }
 
 
@@ -560,41 +614,49 @@ void SDIO_InitDataTransfer(stc_sdio_data_config_t *pstcDataConfig)
 *******************************************************************************/
 en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
 {
-    /*Store the command and data configurations*/
+    /* Store the command and data configurations*/
     stc_sdio_cmd_config_t   stcCmdConfig;
     stc_sdio_data_config_t  stcDataConfig;
 
-#ifdef SEMAPHORE
-    en_sdio_result_t result;
-#endif
-
-    /*variable used for holding timeout value*/
-#ifndef SEMAPHORE
-    uint32_t    u32Timeout = 0;
-#endif
-
-#ifndef SEMAPHORE_CMD
     uint32_t u32CmdTimeout = 0;
-#endif
 
     /*Returns from various function calls*/
     en_sdio_result_t enRet = Error;
     en_sdio_result_t enRetTmp = Ok;
 
-    /*Hold value of if these checks are needed*/
+    /* Hold value of if these checks are needed */
     uint8_t             bCmdIndexCheck;
     uint8_t             bCmdCrcCheck;
     static uint8_t      u8responseBuf[6];
 
-    /*Clear statuses*/
+    /* Clear statuses */
     gstcInternalData.stcEvents.u8CmdComplete = 0;
     gstcInternalData.stcEvents.u8TransComplete = 0;
     gstcInternalData.stcEvents.u8CRCError = 0;
 
-    /*Setup the command configuration*/
+    /* Setup the command configuration */
     stcCmdConfig.u8CmdIndex = (uint8_t)pstcCmd->u32CmdIdx;
     stcCmdConfig.u32Argument =  pstcCmd->u32Arg;
 
+#ifdef CY_RTOS_AWARE
+
+    cy_rslt_t result;
+
+    /* Initialize the semaphore. This is not done in init because init is called
+    * in interrupt thread. cy_rtos_init_semaphore call is prohibited in 
+    * interrupt thread.
+    */
+    if(!sema_initialized)
+    {
+        cy_rtos_init_semaphore( &sdio_transfer_finished_semaphore, 1, 0 );
+        sema_initialized = true;
+    }
+#else
+
+    /* Variable used for holding timeout value */
+    uint32_t    u32Timeout = 0;
+#endif
+
     /*Determine the type of response and if we need to do any checks*/
     /*Command 0 and 8 have no response, so don't wait for one*/
     if (pstcCmd->u32CmdIdx == 0 || pstcCmd->u32CmdIdx == 8)
@@ -694,30 +756,41 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
                             SDIO_CONTROL_REG |= SDIO_CTRL_ENABLE_WRITE;
                         }
 
-#ifndef SEMAPHORE
-                        /*Wait for the transfer to finish*/
+                    #ifdef CY_RTOS_AWARE
+                        /* Wait for the transfer to finish.
+                        *  Acquire semaphore and wait until it will be released 
+                        *  in SDIO_IRQ:
+                        *  1. sdio_transfer_finished_semaphore count is equal to 
+                        *     zero. cy_rtos_get_semaphore waits until semaphore 
+                        *     count is increased by cy_rtos_set_semaphore() in 
+                        *     SDIO_IRQ.
+                        *  2. The cy_rtos_set_semaphore() increases 
+                        *     sdio_transfer_finished_semaphore count.
+                        *  3. The cy_rtos_get_semaphore() function decreases 
+                        *     sdio_transfer_finished_semaphore back to zero 
+                        *     and exit. Or timeout occurs
+                        */
+                        result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false );
+
+                        enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone);
+
+                        if (result != CY_RSLT_SUCCESS)
+                    #else
+                         /* Wait for the transfer to finish */
                         do
                         {
-
                             u32Timeout++;
                             enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone);
 
                         } while (!((enRetTmp == Ok) || (enRetTmp == DataCrcError) || (u32Timeout >= SDIO_DAT_TIMEOUT)));
 
-                        /*if it was a read it is possible there is still extra data hanging out, trigger the
-                          DMA again. This can result in extra data being transfered so the read buffer should be
-                          3 bytes bigger than needed*/
-                        if (pstcCmd->bRead == true)
+                        if (u32Timeout == SDIO_DAT_TIMEOUT)
+                    #endif
                         {
-                            Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2);
+                            enRet |= DataTimeout;
                         }
 
-                        if (u32Timeout == SDIO_DAT_TIMEOUT)
-#else
-                         result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false );
-                         enRetTmp = SDIO_CheckForEvent(SdCmdEventTransferDone);
-
-                         /* if it was a read it is possible there is still extra data hanging out, trigger the
+                        /* if it was a read it is possible there is still extra data hanging out, trigger the
                            DMA again. This can result in extra data being transfered so the read buffer should be
                            3 bytes bigger than needed*/
                         if (pstcCmd->bRead == true)
@@ -725,12 +798,6 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
                             Cy_TrigMux_SwTrigger((uint32_t)SDIO_HOST_Read_DMA_DW__TR_IN, 2);
                         }
 
-                        if (result != Ok)
-#endif
-                        {
-                            enRet |= DataTimeout;
-                        }
-
                         if (enRetTmp == DataCrcError)
                         {
                             enRet |= DataCrcError;
@@ -741,9 +808,8 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd)
         } /*No Response Required, thus no CMD53*/
     } /*CMD Passed*/
 
-
-#ifndef SEMAPHORE
-     u32Timeout = 0;
+#ifndef CY_RTOS_AWARE
+    u32Timeout = 0;
 #endif
 
     /*If there were no errors then indicate transfer was okay*/
@@ -1161,63 +1227,72 @@ void SDIO_IRQ(void)
 {
     uint8_t u8Status;
 
-    /*first read the status register*/
+    /* First read the status register */
     u8Status = SDIO_STATUS_REG;
 
-    /*Check card interrupt*/
+    /* Check card interrupt */
     if (u8Status & SDIO_STS_CARD_INT )
     {
+        pfnCardInt_count++;
+    }
+    
+    /* Execute card interrupt callback if neccesary */
+    if (0 != pfnCardInt_count)
+    {        
         if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb)
         {
-              gstcInternalData.pstcCallBacks.pfnCardIntCb();
+            gstcInternalData.pstcCallBacks.pfnCardIntCb();
         }
+        pfnCardInt_count--;
     }
 
-    /*If the command is complete set the flag*/
+    /* If the command is complete set the flag */
     if (u8Status & SDIO_STS_CMD_DONE)
     {
         gstcInternalData.stcEvents.u8CmdComplete++;
     }
 
-    /*Check if a write is complete*/
+    /* Check if a write is complete */
     if (u8Status & SDIO_STS_WRITE_DONE )
     {
 
-        /*Clear the Write flag and CMD53 flag*/
+        /* Clear the Write flag and CMD53 flag */
         SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_WRITE | SDIO_CTRL_ENABLE_INT);
 
-        /*Check if the CRC status return was bad*/
-        if (u8Status & SDIO_STS_CRC_ERR )
+        /* Check if the CRC status return was bad */
+        if (u8Status & SDIO_STS_CRC_ERR)
         {
-            /*CRC was bad, set the flag*/
+            /* CRC was bad, set the flag */
             gstcInternalData.stcEvents.u8CRCError++;
         }
-        /*set the done flag*/
-#ifdef SEMAPHORE
+        
+        /* Set the done flag */
+
+    #ifdef CY_RTOS_AWARE
         cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true );
-#else
+    #else
         gstcInternalData.stcEvents.u8TransComplete++;
-#endif
+    #endif
     }
 
-    /*Check if a read is complete*/
+    /* Check if a read is complete */
     if (u8Status & SDIO_STS_READ_DONE)
     {
-        /*Clear the read flag*/
+        /* Clear the read flag */
         SDIO_CONTROL_REG &= ~(SDIO_CTRL_ENABLE_READ| SDIO_CTRL_ENABLE_INT);
 
-        /*check the CRC*/
+        /* Check the CRC */
         if (u8Status & SDIO_STS_CRC_ERR)
         {
-            /*CRC was bad, set the flag*/
+            /* CRC was bad, set the flag */
             gstcInternalData.stcEvents.u8CRCError++;
         }
-        /*Okay we're done so set the done flag*/
-#ifdef SEMAPHORE
+        /* Okay we're done so set the done flag */
+    #ifdef CY_RTOS_AWARE
         cy_rtos_set_semaphore( &sdio_transfer_finished_semaphore, true );
-#else
+    #else
         gstcInternalData.stcEvents.u8TransComplete++;
-#endif
+    #endif
     }
 
     NVIC_ClearPendingIRQ((IRQn_Type) SDIO_HOST_sdio_int__INTC_NUMBER);
@@ -1286,7 +1361,6 @@ void SDIO_READ_DMA_IRQ(void)
     yCounts--;
 }
 
-
 void SDIO_WRITE_DMA_IRQ(void)
 {
     /*We shouldn't have to change anything unless it is the last descriptor*/
@@ -1348,6 +1422,46 @@ void SDIO_WRITE_DMA_IRQ(void)
     yCounts--;
 }
 
+void SDIO_Free(void)
+{
+#ifdef CY_RTOS_AWARE
+    cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore);
+#endif
+}
+
+/*******************************************************************************
+* Function Name: SDIO_SaveConfig
+********************************************************************************
+*
+* Saves the user configuration of the SDIO UDB non-retention registers. Call the
+* SDIO_SaveConfig() function before the Cy_SysPm_CpuEnterDeepSleep() function.
+*
+*******************************************************************************/
+static void SDIO_SaveConfig(void)
+{
+    regs.CY_SDIO_UDB_WRKMULT_CTL_0 = UDB->WRKMULT.CTL[0];
+    regs.CY_SDIO_UDB_WRKMULT_CTL_1 = UDB->WRKMULT.CTL[1];
+    regs.CY_SDIO_UDB_WRKMULT_CTL_2 = UDB->WRKMULT.CTL[2];
+    regs.CY_SDIO_UDB_WRKMULT_CTL_3 = UDB->WRKMULT.CTL[3];
+}
+
+
+/*******************************************************************************
+* Function Name: SDIO_RestoreConfig
+********************************************************************************
+*
+* Restores the user configuration of the SDIO UDB non-retention registers. Call
+* the SDIO_Wakeup() function after the Cy_SysPm_CpuEnterDeepSleep() function.
+*
+*******************************************************************************/
+static void SDIO_RestoreConfig(void)
+{
+    UDB->WRKMULT.CTL[0] = regs.CY_SDIO_UDB_WRKMULT_CTL_0;
+    UDB->WRKMULT.CTL[1] = regs.CY_SDIO_UDB_WRKMULT_CTL_1;
+    UDB->WRKMULT.CTL[2] = regs.CY_SDIO_UDB_WRKMULT_CTL_2;
+    UDB->WRKMULT.CTL[3] = regs.CY_SDIO_UDB_WRKMULT_CTL_3;
+}
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h
index ceeb41995c4..05fff02eda6 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h
@@ -35,7 +35,6 @@
 
 /**
 * \defgroup group_udb_sdio UDB_SDIO
-* \ingroup group_bsp
 * \{
 *  SDIO - Secure Digital Input Output Is a standard for communicating with various
     external devices such as Wifi and bluetooth devices. 
@@ -272,6 +271,7 @@ void                SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz);
 void                SDIO_Reset(void);
 void                SDIO_EnableChipInt(void);
 void                SDIO_DisableChipInt(void);
+void                SDIO_Free(void);
 
 /*Low Level Functions*/
 void                SDIO_SendCommand(stc_sdio_cmd_config_t *pstcCmdConfig);
@@ -293,6 +293,8 @@ void                SDIO_WRITE_DMA_IRQ(void);
 
 void                SDIO_Crc7Init(void);
 
+cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode);
+
 /** \endcond */
 
 /** \} group_udb_sdio_functions */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_types.h
index 5510cd7d281..24c034007aa 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_types.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_types.h
@@ -3,7 +3,7 @@
 *
 * Description:
 * Provides APIs for interacting with the hardware contained on the Cypress
-* CYW943012P6EVB-01 pioneer kit.
+* CYW943012P6EVB-01 evaluation kit.
 *
 ********************************************************************************
 * \copyright
@@ -23,14 +23,6 @@
 * limitations under the License.
 *******************************************************************************/
 
-/**
-* \addtogroup group_bsp_cyw943012p6evb_01 CYW943012P6EVB-01
-* \ingroup group_bsp
-* \{
-* \defgroup group_bsp_cyw943012p6evb_01_macros Macros
-* \defgroup group_bsp_cyw943012p6evb_01_enums Enumerated Types
-*/
-
 #pragma once
 
 #include "cyhal.h"
@@ -40,10 +32,56 @@ extern "C" {
 #endif
 
 /**
-* \addtogroup group_bsp_cyw943012p6evb_01_macros
+* \addtogroup group_bsp_pins Pin Mappings
 * \{
 */
 
+// Arduino connector namings
+/** Arduino A0 */
+#define CYBSP_A0 P10_0
+/** Arduino A1 */
+#define CYBSP_A1 P10_1
+/** Arduino A2 */
+#define CYBSP_A2 P6_4
+/** Arduino A3 */
+#define CYBSP_A3 P6_5
+/** Arduino A4 */
+#define CYBSP_A4 P10_4
+/** Arduino A5 */
+#define CYBSP_A5 P10_5
+/** Arduino D0 */
+#define CYBSP_D0 P5_0
+/** Arduino D1 */
+#define CYBSP_D1 P5_1
+/** Arduino D2 */
+#define CYBSP_D2 P5_2
+/** Arduino D3 */
+#define CYBSP_D3 P5_3
+/** Arduino D4 */
+#define CYBSP_D4 P5_4
+/** Arduino D5 */
+#define CYBSP_D5 P5_5
+/** Arduino D6 */
+#define CYBSP_D6 P5_6
+/** Arduino D7 */
+#define CYBSP_D7 P5_7
+/** Arduino D8 */
+#define CYBSP_D8 NC
+/** Arduino D9 */
+#define CYBSP_D9 NC
+/** Arduino D10 */
+#define CYBSP_D10 P0_5
+/** Arduino D11 */
+#define CYBSP_D11 P0_2
+/** Arduino D12 */
+#define CYBSP_D12 P0_3
+/** Arduino D13 */
+#define CYBSP_D13 P0_4
+/** Arduino D14 */
+#define CYBSP_D14 P1_0
+/** Arduino D15 */
+#define CYBSP_D15 P1_1
+
 // Generic signal names
 /** Pin: CYBSP_WCO_IN         */
 #define CYBSP_WCO_IN         P0_0
@@ -62,18 +100,25 @@ extern "C" {
 #define CYBSP_WL_SECI_OUT    P1_5
 
 /** Pin: CYBSP_WIFI_SDIO_D0   */
+/* Corresponds to: ioss[0].port[2].pin[0], udb[0] */
 #define CYBSP_WIFI_SDIO_D0   P2_0
 /** Pin: CYBSP_WIFI_SDIO_D1   */
+/* Corresponds to: ioss[0].port[2].pin[1], udb[0] */
 #define CYBSP_WIFI_SDIO_D1   P2_1
 /** Pin: CYBSP_WIFI_SDIO_D2   */
+/* Corresponds to: ioss[0].port[2].pin[2], udb[0] */
 #define CYBSP_WIFI_SDIO_D2   P2_2
 /** Pin: CYBSP_WIFI_SDIO_D3   */
+/* Corresponds to: ioss[0].port[2].pin[3], udb[0] */
 #define CYBSP_WIFI_SDIO_D3   P2_3
 /** Pin: CYBSP_WIFI_SDIO_CMD  */
+/* Corresponds to: ioss[0].port[2].pin[4], udb[0] */
 #define CYBSP_WIFI_SDIO_CMD  P2_4
 /** Pin: CYBSP_WIFI_SDIO_CLK  */
+/* Corresponds to: ioss[0].port[2].pin[5], udb[0] */
 #define CYBSP_WIFI_SDIO_CLK  P2_5
 /** Pin: CYBSP_WIFI_WL_REG_ON */
+/* Corresponds to: ioss[0].port[2].pin[6], udb[0] */
 #define CYBSP_WIFI_WL_REG_ON P2_6
 /** Pin: CYBSP_WIFI_HOST_WAKE */
 #define CYBSP_WIFI_HOST_WAKE P2_7
@@ -90,20 +135,22 @@ extern "C" {
 #define CYBSP_BT_UART_RTS    P3_2
 /** Pin: CYBSP_BT_UART_CTS    */
 #define CYBSP_BT_UART_CTS    P3_3
-/** Pin: CYBSP_BT_REG_ON      */
-#define CYBSP_BT_REG_ON      P3_4
+
+/** Pin: BT Power */
+#define CYBSP_BT_POWER       P3_4
 /** Pin: CYBSP_BT_HOST_WAKE   */
 #define CYBSP_BT_HOST_WAKE   P3_5
-
 /** Pin: CYBSP_BT_DEVICE_WAKE */
 #define CYBSP_BT_DEVICE_WAKE P4_0
 /** Pin: CYBSP_BT_RST         */
 #define CYBSP_BT_RST         P4_1
 
 /** Pin: UART RX */
-#define CYBSP_DEBUG_UART_RX    P5_0
+/* Corresponds to: ioss[0].port[13].pin[0], scb[6] */
+#define CYBSP_DEBUG_UART_RX    P13_0
 /** Pin: UART TX */
-#define CYBSP_DEBUG_UART_TX    P5_1
+/* Corresponds to: ioss[0].port[13].pin[1], scb[6] */
+#define CYBSP_DEBUG_UART_TX    P13_1
 
 /** Pin: CYBSP_I2C_SCL        */
 #define CYBSP_I2C_SCL        P6_0
@@ -193,8 +240,10 @@ extern "C" {
 #define CYBSP_ECO_OUT        P12_7
 
 /** Pin: CYBSP_P6_UART_RX     */
+/* Corresponds to: ioss[0].port[13].pin[0], scb[6] */
 #define CYBSP_P6_UART_RX     P13_0
 /** Pin: CYBSP_P6_UART_TX     */
+/* Corresponds to: ioss[0].port[13].pin[1], scb[6] */
 #define CYBSP_P6_UART_TX     P13_1
 /** Pin: CYBSP_USB_DEV_VBUS_DET */
 #define CYBSP_USB_DEV_VBUS_DET P13_4
@@ -208,25 +257,25 @@ extern "C" {
 /** Pin: CYBSP_USB_DM         */
 #define CYBSP_USB_DM         P14_1
 
-/** \} group_bsp_cyw943012p6evb_01_macros */
+/** \} group_bsp_pins */
 
 /**
-* \addtogroup group_bsp_cyw943012p6evb_01_enums
+* \addtogroup group_bsp_enums Enumerated Types
 * \{
 */
 
 /** Enum defining the different states for the LED. */
 typedef enum
 {
-	CYBSP_LED_STATE_ON        	= 0,
-	CYBSP_LED_STATE_OFF        	= 1,
+    CYBSP_LED_STATE_ON          = 0,
+    CYBSP_LED_STATE_OFF         = 1,
 } cybsp_led_state_t;
 
 /** Enum defining the different states for a button. */
 typedef enum
 {
-	CYBSP_BTN_PRESSED  	      	= 0,
-	CYBSP_BTN_OFF	          	= 1,
+    CYBSP_BTN_PRESSED           = 0,
+    CYBSP_BTN_OFF               = 1,
 } cybsp_btn_state_t;
 
 /** Enum defining the different LED pins on the board. */
@@ -236,8 +285,11 @@ typedef enum
     CYBSP_LED_RGB_GREEN = P1_1,
     CYBSP_LED_RGB_BLUE = P10_6,
 
+    /* Corresponds to: ioss[0].port[0].pin[3] */
     CYBSP_USER_LED1 = CYBSP_LED_RGB_RED,
+    /* Corresponds to: ioss[0].port[1].pin[1] */
     CYBSP_USER_LED2 = CYBSP_LED_RGB_GREEN,
+    /* Corresponds to: ioss[0].port[10].pin[6] */
     CYBSP_USER_LED3 = CYBSP_LED_RGB_BLUE,
     CYBSP_USER_LED = CYBSP_USER_LED1,
 } cybsp_led_t;
@@ -247,14 +299,13 @@ typedef enum
 {
     CYBSP_SW6 = P0_4,
 
+    /* Corresponds to: ioss[0].port[0].pin[4] */
     CYBSP_USER_BTN1 = CYBSP_SW6,
     CYBSP_USER_BTN = CYBSP_USER_BTN1,
 } cybsp_btn_t;
 
-/** \} group_bsp_cyw943012p6evb_01_enums */
+/** \} group_bsp_enums */
 
 #if defined(__cplusplus)
 }
 #endif
-
-/** \} group_bsp_cyw943012p6evb_01 */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
deleted file mode 100644
index 0152835028f..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
+++ /dev/null
@@ -1,310 +0,0 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm0plus.scat
-;* \version 2.50
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2019 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    0x08047600
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation. 
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        .ANY (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0
-    { 
-        * (HEAP) 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
-    {
-        * (STACK)
-    }
-}
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    .cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S
deleted file mode 100644
index 536d029f52a..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S
+++ /dev/null
@@ -1,307 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_psoc6_01_cm0plus.S
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0plus Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-                IF :DEF:__STACK_SIZE
-Stack_Size      EQU     __STACK_SIZE
-                ELSE
-Stack_Size      EQU     0x00000400
-                ENDIF
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-                IF :DEF:__HEAP_SIZE
-Heap_Size       EQU     __HEAP_SIZE
-                ELSE
-Heap_Size       EQU     0x00000400
-                ENDIF
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-
-                DCD     0x0000000D                ; NMI Handler located at ROM code
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External interrupts                           Description
-                DCD     NvicMux0_IRQHandler                   ; CM0+ NVIC Mux input 0 
-                DCD     NvicMux1_IRQHandler                   ; CM0+ NVIC Mux input 1 
-                DCD     NvicMux2_IRQHandler                   ; CM0+ NVIC Mux input 2 
-                DCD     NvicMux3_IRQHandler                   ; CM0+ NVIC Mux input 3 
-                DCD     NvicMux4_IRQHandler                   ; CM0+ NVIC Mux input 4 
-                DCD     NvicMux5_IRQHandler                   ; CM0+ NVIC Mux input 5 
-                DCD     NvicMux6_IRQHandler                   ; CM0+ NVIC Mux input 6 
-                DCD     NvicMux7_IRQHandler                   ; CM0+ NVIC Mux input 7 
-                DCD     NvicMux8_IRQHandler                   ; CM0+ NVIC Mux input 8 
-                DCD     NvicMux9_IRQHandler                   ; CM0+ NVIC Mux input 9 
-                DCD     NvicMux10_IRQHandler                  ; CM0+ NVIC Mux input 10 
-                DCD     NvicMux11_IRQHandler                  ; CM0+ NVIC Mux input 11 
-                DCD     NvicMux12_IRQHandler                  ; CM0+ NVIC Mux input 12 
-                DCD     NvicMux13_IRQHandler                  ; CM0+ NVIC Mux input 13 
-                DCD     NvicMux14_IRQHandler                  ; CM0+ NVIC Mux input 14 
-                DCD     NvicMux15_IRQHandler                  ; CM0+ NVIC Mux input 15 
-                DCD     NvicMux16_IRQHandler                  ; CM0+ NVIC Mux input 16 
-                DCD     NvicMux17_IRQHandler                  ; CM0+ NVIC Mux input 17 
-                DCD     NvicMux18_IRQHandler                  ; CM0+ NVIC Mux input 18 
-                DCD     NvicMux19_IRQHandler                  ; CM0+ NVIC Mux input 19 
-                DCD     NvicMux20_IRQHandler                  ; CM0+ NVIC Mux input 20 
-                DCD     NvicMux21_IRQHandler                  ; CM0+ NVIC Mux input 21 
-                DCD     NvicMux22_IRQHandler                  ; CM0+ NVIC Mux input 22 
-                DCD     NvicMux23_IRQHandler                  ; CM0+ NVIC Mux input 23 
-                DCD     NvicMux24_IRQHandler                  ; CM0+ NVIC Mux input 24 
-                DCD     NvicMux25_IRQHandler                  ; CM0+ NVIC Mux input 25 
-                DCD     NvicMux26_IRQHandler                  ; CM0+ NVIC Mux input 26 
-                DCD     NvicMux27_IRQHandler                  ; CM0+ NVIC Mux input 27 
-                DCD     NvicMux28_IRQHandler                  ; CM0+ NVIC Mux input 28 
-                DCD     NvicMux29_IRQHandler                  ; CM0+ NVIC Mux input 29 
-                DCD     NvicMux30_IRQHandler                  ; CM0+ NVIC Mux input 30 
-                DCD     NvicMux31_IRQHandler                  ; CM0+ NVIC Mux input 31 
-
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-                EXPORT __ramVectors
-                AREA    RESET_RAM, READWRITE, NOINIT
-__ramVectors    SPACE   __Vectors_Size
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Weak function for startup customization
-;
-; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
-; because this function is executed as the first instruction in the ResetHandler.
-; The PDL is also not initialized to use the proper register offsets.
-; The user of this function is responsible for initializing the PDL and resources before using them.
-;
-Cy_OnResetUser  PROC
-                EXPORT  Cy_OnResetUser            [WEAK]
-                BX      LR
-                ENDP
-
-; Reset Handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-
-                ; Define strong function for startup customization
-                BL      Cy_OnResetUser
-
-                ; Copy vectors from ROM to RAM
-                LDR r1, =__Vectors
-                LDR r0, =__ramVectors
-                LDR r2, =__Vectors_Size
-Vectors_Copy
-                LDR r3, [r1]
-                STR r3, [r0]
-                ADDS r0, r0, #4
-                ADDS r1, r1, #4
-                SUBS r2, r2, #1
-                CMP r2, #0
-                BNE Vectors_Copy
-
-                ; Update Vector Table Offset Register. */
-                LDR r0, =__ramVectors
-                LDR r1, =0xE000ED08
-                STR r0, [r1]
-                dsb 0xF
-
-                LDR     R0, =__main
-                BLX     R0
-
-                ; Should never get here
-                B       .
-
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-NMI_Handler         PROC
-                    EXPORT  NMI_Handler               [WEAK]
-                    B       .
-                    ENDP
-
-Cy_SysLib_FaultHandler PROC
-                    EXPORT  Cy_SysLib_FaultHandler    [WEAK]
-                    B       .
-                    ENDP
-
-HardFault_Handler   PROC
-                    EXPORT HardFault_Handler          [WEAK]
-                    movs r0, #4
-                    mov r1, LR
-                    tst r0, r1
-                    beq L_MSP
-                    mrs r0, PSP
-                    bl L_API_call
-L_MSP
-                    mrs r0, MSP
-L_API_call
-                    bl Cy_SysLib_FaultHandler
-                    ENDP
-
-SVC_Handler         PROC
-                    EXPORT  SVC_Handler               [WEAK]
-                    B       .
-                    ENDP
-PendSV_Handler      PROC
-                    EXPORT  PendSV_Handler            [WEAK]
-                    B       .
-                    ENDP
-SysTick_Handler     PROC
-                    EXPORT  SysTick_Handler           [WEAK]
-                    B       .
-                    ENDP
-
-Default_Handler     PROC
-                    EXPORT  Default_Handler                       [WEAK]
-                    EXPORT  NvicMux0_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux1_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux2_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux3_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux4_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux5_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux6_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux7_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux8_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux9_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux10_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux11_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux12_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux13_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux14_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux15_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux16_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux17_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux18_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux19_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux20_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux21_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux22_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux23_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux24_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux25_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux26_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux27_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux28_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux29_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux30_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux31_IRQHandler                  [WEAK]
-
-NvicMux0_IRQHandler
-NvicMux1_IRQHandler
-NvicMux2_IRQHandler
-NvicMux3_IRQHandler
-NvicMux4_IRQHandler
-NvicMux5_IRQHandler
-NvicMux6_IRQHandler
-NvicMux7_IRQHandler
-NvicMux8_IRQHandler
-NvicMux9_IRQHandler
-NvicMux10_IRQHandler
-NvicMux11_IRQHandler
-NvicMux12_IRQHandler
-NvicMux13_IRQHandler
-NvicMux14_IRQHandler
-NvicMux15_IRQHandler
-NvicMux16_IRQHandler
-NvicMux17_IRQHandler
-NvicMux18_IRQHandler
-NvicMux19_IRQHandler
-NvicMux20_IRQHandler
-NvicMux21_IRQHandler
-NvicMux22_IRQHandler
-NvicMux23_IRQHandler
-NvicMux24_IRQHandler
-NvicMux25_IRQHandler
-NvicMux26_IRQHandler
-NvicMux27_IRQHandler
-NvicMux28_IRQHandler
-NvicMux29_IRQHandler
-NvicMux30_IRQHandler
-NvicMux31_IRQHandler
-
-                B       .
-                ENDP
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT __use_two_region_memory
-
-                ALIGN
-
-                ENDIF
-
-                END
-
-
-; [] END OF FILE
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
deleted file mode 100644
index 45285e64c3a..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
+++ /dev/null
@@ -1,468 +0,0 @@
-/***************************************************************************//**
-* \file cy8c6xx7_cm0plus.ld
-* \version 2.50
-*
-* Linker file for the GNU C compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point location is fixed and starts at 0x10000000. The valid
-* application image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-ENTRY(Reset_Handler)
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-/* MBED_APP_START is being  used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_START
-* is equal to MBED_ROM_START
-*/
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-/* MBED_APP_SIZE is being  used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-* is equal to MBED_ROM_SIZE
-*/
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    0x08047600
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-    #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-STACK_SIZE = MBED_BOOT_STACK_SIZE;
-
-/* Force symbol to be entered in the output file as an undefined symbol. Doing
-* this may, for example, trigger linking of additional modules from standard
-* libraries. You may list several symbols for each EXTERN, and you may use
-* EXTERN multiple times. This command has the same effect as the -u command-line
-* option.
-*/
-EXTERN(Reset_Handler)
-
-/* The MEMORY section below describes the location and size of blocks of memory in the target.
-* Use this section to specify the memory regions available for allocation.
-*/
-MEMORY
-{
-    /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
-     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
-     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-     * Using this memory region for other purposes will lead to unexpected behavior.
-     * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
-     * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
-     */
-    ram               (rwx)   : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
-    public_ram        (rw)    : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE
-    flash             (rx)    : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000)
-
-    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
-     * You can assign sections to this memory region for only one of the cores.
-     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-     * Therefore, repurposing this memory region will prevent such middleware from operation.
-     */
-    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
-
-    /* The following regions define device specific memory regions and must not be changed. */
-    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
-    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
-    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
-    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
-    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
-    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
-    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-
-
-SECTIONS
-{
-    .cy_app_header :
-    {
-        KEEP(*(.cy_app_header))
-    } > flash
-
-    .text :
-    {
-        . = ALIGN(4);
-        __Vectors = . ;
-        KEEP(*(.vectors))
-        . = ALIGN(4);
-        __Vectors_End = .;
-        __Vectors_Size = __Vectors_End - __Vectors;
-        __end__ = .;
-
-        . = ALIGN(4);
-        *(.text*)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        /* Read-only code (constants). */
-        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
-
-        KEEP(*(.eh_frame*))
-    } > flash
-
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    __exidx_start = .;
-
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > flash
-    __exidx_end = .;
-
-
-    /* To copy multiple ROM to RAM sections,
-     * uncomment .copy.table section and,
-     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */
-    .copy.table :
-    {
-        . = ALIGN(4);
-        __copy_table_start__ = .;
-
-        /* Copy interrupt vectors from flash to RAM */
-        LONG (__Vectors)                                    /* From */
-        LONG (__ram_vectors_start__)                        /* To   */
-        LONG (__Vectors_End - __Vectors)                    /* Size */
-
-        /* Copy data section to RAM */
-        LONG (__etext)                                      /* From */
-        LONG (__data_start__)                               /* To   */
-        LONG (__data_end__ - __data_start__)                /* Size */
-
-        __copy_table_end__ = .;
-    } > flash
-
-
-    /* To clear multiple BSS sections,
-     * uncomment .zero.table section and,
-     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */
-    .zero.table :
-    {
-        . = ALIGN(4);
-        __zero_table_start__ = .;
-        LONG (__bss_start__)
-        LONG (__bss_end__ - __bss_start__)
-        __zero_table_end__ = .;
-    } > flash
-
-    __etext =  . ;
-
-
-    .ramVectors (NOLOAD) : ALIGN(8)
-    {
-        __ram_vectors_start__ = .;
-        KEEP(*(.ram_vectors))
-        __ram_vectors_end__   = .;
-    } > ram
-
-
-    .data __ram_vectors_end__ : AT (__etext)
-    {
-        __data_start__ = .;
-
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-
-        KEEP(*(.cy_ramfunc*))
-        . = ALIGN(4);
-
-        __data_end__ = .;
-
-    } > ram
-
-
-    /* Place variables in the section that should not be initialized during the
-    *  device startup.
-    */
-    .noinit (NOLOAD) : ALIGN(8)
-    {
-      KEEP(*(.noinit))
-    } > ram
-
-
-    /* The uninitialized global or static variables are placed in this section.
-    *
-    * The NOLOAD attribute tells linker that .bss section does not consume
-    * any space in the image. The NOLOAD attribute changes the .bss type to
-    * NOBITS, and that  makes linker to A) not allocate section in memory, and
-    * A) put information to clear the section with all zeros during application
-    * loading.
-    *
-    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
-    * This  makes linker to A) allocate zeroed section in memory, and B) copy
-    * this section to RAM during application loading.
-    */
-    .bss (NOLOAD):
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram
-
-
-    .heap (NOLOAD):
-    {
-        __HeapBase = .;
-        __end__ = .;
-        end = __end__;
-        KEEP(*(.heap*))
-        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
-        __HeapLimit = .;
-    } > ram
-
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (NOLOAD):
-    {
-        KEEP(*(.stack*))
-    } > ram
-
-
-    /* Public RAM */
-    .cy_sharedmem (NOLOAD):
-    {
-        . = ALIGN(4);
-        KEEP(*(.cy_sharedmem))
-    } > public_ram
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(ram) + LENGTH(ram);
-        __StackLimit = __StackTop - STACK_SIZE;
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-
-
-    /* Emulated EEPROM Flash area */
-    .cy_em_eeprom :
-    {
-        KEEP(*(.cy_em_eeprom))
-    } > em_eeprom
-
-
-    /* Supervisory Flash: User data */
-    .cy_sflash_user_data :
-    {
-        KEEP(*(.cy_sflash_user_data))
-    } > sflash_user_data
-
-
-    /* Supervisory Flash: Normal Access Restrictions (NAR) */
-    .cy_sflash_nar :
-    {
-        KEEP(*(.cy_sflash_nar))
-    } > sflash_nar
-
-
-    /* Supervisory Flash: Public Key */
-    .cy_sflash_public_key :
-    {
-        KEEP(*(.cy_sflash_public_key))
-    } > sflash_public_key
-
-
-    /* Supervisory Flash: Table of Content # 2 */
-    .cy_toc_part2 :
-    {
-        KEEP(*(.cy_toc_part2))
-    } > sflash_toc_2
-
-    
-    /* Supervisory Flash: Table of Content # 2 Copy */
-    .cy_rtoc_part2 :
-    {
-        KEEP(*(.cy_rtoc_part2))
-    } > sflash_rtoc_2
-
-
-    /* Places the code in the Execute in Place (XIP) section. See the smif driver
-    *  documentation for details.
-    */
-    .cy_xip :
-    {
-        KEEP(*(.cy_xip))
-    } > xip
-
-
-    /* eFuse */
-    .cy_efuse :
-    {
-        KEEP(*(.cy_efuse))
-    } > efuse
-
-
-    /* These sections are used for additional metadata (silicon revision,
-    *  Silicon/JTAG ID, etc.) storage.
-    */
-    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
-}
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-__cy_memory_0_start    = 0x10000000;
-__cy_memory_0_length   = 0x00100000;
-__cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-__cy_memory_1_start    = 0x14000000;
-__cy_memory_1_length   = 0x8000;
-__cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-__cy_memory_2_start    = 0x16000000;
-__cy_memory_2_length   = 0x8000;
-__cy_memory_2_row_size = 0x200;
-
-/* XIP */
-__cy_memory_3_start    = 0x18000000;
-__cy_memory_3_length   = 0x08000000;
-__cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-__cy_memory_4_start    = 0x90700000;
-__cy_memory_4_length   = 0x100000;
-__cy_memory_4_row_size = 1;
-
-/* EOF */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S
deleted file mode 100644
index b46556a8a7a..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S
+++ /dev/null
@@ -1,399 +0,0 @@
-/**************************************************************************//**
- * @file     startup_psoc6_01_cm0plus.S
- * @brief    CMSIS Core Device Startup File for
- *           ARMCM0plus Device Series
- * @version  V5.00
- * @date     02. March 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-    /* Address of the NMI handler */
-    #define CY_NMI_HANLDER_ADDR         0x0000000D
-
-    /* The CPU VTOR register */
-    #define CY_CPU_VTOR_ADDR            0xE000ED08
-
-    /* Copy flash vectors and data section to RAM */
-    #define __STARTUP_COPY_MULTIPLE
-
-    /* Clear single BSS section */
-    #define __STARTUP_CLEAR_BSS
-
-    .syntax    unified
-    .arch    armv6-m
-
-    .section .stack
-    .align    3
-#ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
-#else
-    .equ    Stack_Size, 0x00001000
-#endif
-    .globl    __StackTop
-    .globl    __StackLimit
-__StackLimit:
-    .space    Stack_Size
-    .size    __StackLimit, . - __StackLimit
-__StackTop:
-    .size    __StackTop, . - __StackTop
-
-    .section .heap
-    .align    3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0x00000400
-#endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
-__HeapBase:
-    .if    Heap_Size
-    .space    Heap_Size
-    .endif
-    .size    __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size    __HeapLimit, . - __HeapLimit
-
-    .section .vectors
-    .align 2
-    .globl    __Vectors
-__Vectors:
-    .long    __StackTop            /* Top of Stack */
-    .long    Reset_Handler         /* Reset Handler */
-    .long    CY_NMI_HANLDER_ADDR   /* NMI Handler */
-    .long    HardFault_Handler     /* Hard Fault Handler */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    SVC_Handler           /* SVCall Handler */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    PendSV_Handler        /* PendSV Handler */
-    .long    SysTick_Handler       /* SysTick Handler */
-
-     /* External interrupts                             Description */
-    .long    NvicMux0_IRQHandler                     /* CM0+ NVIC Mux input 0 */
-    .long    NvicMux1_IRQHandler                     /* CM0+ NVIC Mux input 1 */
-    .long    NvicMux2_IRQHandler                     /* CM0+ NVIC Mux input 2 */
-    .long    NvicMux3_IRQHandler                     /* CM0+ NVIC Mux input 3 */
-    .long    NvicMux4_IRQHandler                     /* CM0+ NVIC Mux input 4 */
-    .long    NvicMux5_IRQHandler                     /* CM0+ NVIC Mux input 5 */
-    .long    NvicMux6_IRQHandler                     /* CM0+ NVIC Mux input 6 */
-    .long    NvicMux7_IRQHandler                     /* CM0+ NVIC Mux input 7 */
-    .long    NvicMux8_IRQHandler                     /* CM0+ NVIC Mux input 8 */
-    .long    NvicMux9_IRQHandler                     /* CM0+ NVIC Mux input 9 */
-    .long    NvicMux10_IRQHandler                    /* CM0+ NVIC Mux input 10 */
-    .long    NvicMux11_IRQHandler                    /* CM0+ NVIC Mux input 11 */
-    .long    NvicMux12_IRQHandler                    /* CM0+ NVIC Mux input 12 */
-    .long    NvicMux13_IRQHandler                    /* CM0+ NVIC Mux input 13 */
-    .long    NvicMux14_IRQHandler                    /* CM0+ NVIC Mux input 14 */
-    .long    NvicMux15_IRQHandler                    /* CM0+ NVIC Mux input 15 */
-    .long    NvicMux16_IRQHandler                    /* CM0+ NVIC Mux input 16 */
-    .long    NvicMux17_IRQHandler                    /* CM0+ NVIC Mux input 17 */
-    .long    NvicMux18_IRQHandler                    /* CM0+ NVIC Mux input 18 */
-    .long    NvicMux19_IRQHandler                    /* CM0+ NVIC Mux input 19 */
-    .long    NvicMux20_IRQHandler                    /* CM0+ NVIC Mux input 20 */
-    .long    NvicMux21_IRQHandler                    /* CM0+ NVIC Mux input 21 */
-    .long    NvicMux22_IRQHandler                    /* CM0+ NVIC Mux input 22 */
-    .long    NvicMux23_IRQHandler                    /* CM0+ NVIC Mux input 23 */
-    .long    NvicMux24_IRQHandler                    /* CM0+ NVIC Mux input 24 */
-    .long    NvicMux25_IRQHandler                    /* CM0+ NVIC Mux input 25 */
-    .long    NvicMux26_IRQHandler                    /* CM0+ NVIC Mux input 26 */
-    .long    NvicMux27_IRQHandler                    /* CM0+ NVIC Mux input 27 */
-    .long    NvicMux28_IRQHandler                    /* CM0+ NVIC Mux input 28 */
-    .long    NvicMux29_IRQHandler                    /* CM0+ NVIC Mux input 29 */
-    .long    NvicMux30_IRQHandler                    /* CM0+ NVIC Mux input 30 */
-    .long    NvicMux31_IRQHandler                    /* CM0+ NVIC Mux input 31 */
-
-    .size    __Vectors, . - __Vectors
-    .equ    __VectorsSize, . - __Vectors
-
-    .section .ram_vectors
-    .align 2
-    .globl __ramVectors
-__ramVectors:
-    .space  __VectorsSize
-    .size   __ramVectors, . - __ramVectors
-
-
-    .text
-    .thumb
-    .thumb_func
-    .align  2
-
-    /* 
-     * Device startup customization 
-     *
-     * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
-     * because this function is executed as the first instruction in the ResetHandler.
-     * The PDL is also not initialized to use the proper register offsets.
-     * The user of this function is responsible for initializing the PDL and resources before using them.
-     */
-    .weak   Cy_OnResetUser
-    .func   Cy_OnResetUser, Cy_OnResetUser
-    .type   Cy_OnResetUser, %function
-
-Cy_OnResetUser:
-    bx lr
-    .size   Cy_OnResetUser, . - Cy_OnResetUser
-    .endfunc
-
-    /* Reset handler */
-    .weak    Reset_Handler
-    .type    Reset_Handler, %function
-
-Reset_Handler:
-    bl Cy_OnResetUser
-
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r4, =__copy_table_start__
-    ldr    r5, =__copy_table_end__
-
-.L_loop0:
-    cmp    r4, r5
-    bge    .L_loop0_done
-    ldr    r1, [r4]
-    ldr    r2, [r4, #4]
-    ldr    r3, [r4, #8]
-
-.L_loop0_0:
-    subs    r3, #4
-    blt    .L_loop0_0_done
-    ldr    r0, [r1, r3]
-    str    r0, [r2, r3]
-    b    .L_loop0_0
-
-.L_loop0_0_done:
-    adds    r4, #12
-    b    .L_loop0
-
-.L_loop0_done:
-#else
-/*  Single section scheme.
- *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r1, =__etext
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
-
-    subs    r3, r2
-    ble    .L_loop1_done
-
-.L_loop1:
-    subs    r3, #4
-    ldr    r0, [r1,r3]
-    str    r0, [r2,r3]
-    bgt    .L_loop1
-
-.L_loop1_done:
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
- *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
- *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
- */
-    ldr    r3, =__zero_table_start__
-    ldr    r4, =__zero_table_end__
-
-.L_loop2:
-    cmp    r3, r4
-    bge    .L_loop2_done
-    ldr    r1, [r3]
-    ldr    r2, [r3, #4]
-    movs    r0, 0
-
-.L_loop2_0:
-    subs    r2, #4
-    blt    .L_loop2_0_done
-    str    r0, [r1, r2]
-    b    .L_loop2_0
-.L_loop2_0_done:
-
-    adds    r3, #8
-    b    .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
- *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
- *
- *  Both addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r1, =__bss_start__
-    ldr    r2, =__bss_end__
-
-    movs    r0, 0
-
-    subs    r2, r1
-    ble    .L_loop3_done
-
-.L_loop3:
-    subs    r2, #4
-    str    r0, [r1, r2]
-    bgt    .L_loop3
-.L_loop3_done:
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
-    /* Update Vector Table Offset Register. */
-    ldr r0, =__ramVectors
-    ldr r1, =CY_CPU_VTOR_ADDR
-    str r0, [r1]
-    dsb 0xF
-
-    bl  _start
-
-    /* Should never get here */
-    b   .
-
-    .pool
-    .size    Reset_Handler, . - Reset_Handler
-
-    .align    1
-    .thumb_func
-    .weak    Default_Handler
-    .type    Default_Handler, %function
-Default_Handler:
-    b    .
-    .size    Default_Handler, . - Default_Handler
-    .weak    Cy_SysLib_FaultHandler
-    .type    Cy_SysLib_FaultHandler, %function
-
-Cy_SysLib_FaultHandler:
-    b    .
-    .size    Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
-    .type Fault_Handler, %function
-
-Fault_Handler:
-    /* Storing LR content for Creator call stack trace */
-    push {LR}
-    movs r0, #4
-    mov r1, LR
-    tst r0, r1
-    beq .L_MSP
-    mrs r0, PSP
-    b .L_API_call
-.L_MSP:
-    mrs r0, MSP
-.L_API_call:
-    /* Compensation of stack pointer address due to pushing 4 bytes of LR */
-    adds r0, r0, #4
-    bl Cy_SysLib_FaultHandler
-    b   .
-    .size    Fault_Handler, . - Fault_Handler
-
-.macro    def_fault_Handler    fault_handler_name
-    .weak    \fault_handler_name
-    .set    \fault_handler_name, Fault_Handler
-    .endm
-
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-    .macro    def_irq_handler    handler_name
-    .weak    \handler_name
-    .set    \handler_name, Default_Handler
-    .endm
-
-    def_irq_handler    NMI_Handler
-
-    def_fault_Handler  HardFault_Handler
-
-    def_irq_handler    SVC_Handler
-    def_irq_handler    PendSV_Handler
-    def_irq_handler    SysTick_Handler
-
-    def_irq_handler  NvicMux0_IRQHandler                     /* CM0+ NVIC Mux input 0 */
-    def_irq_handler  NvicMux1_IRQHandler                     /* CM0+ NVIC Mux input 1 */
-    def_irq_handler  NvicMux2_IRQHandler                     /* CM0+ NVIC Mux input 2 */
-    def_irq_handler  NvicMux3_IRQHandler                     /* CM0+ NVIC Mux input 3 */
-    def_irq_handler  NvicMux4_IRQHandler                     /* CM0+ NVIC Mux input 4 */
-    def_irq_handler  NvicMux5_IRQHandler                     /* CM0+ NVIC Mux input 5 */
-    def_irq_handler  NvicMux6_IRQHandler                     /* CM0+ NVIC Mux input 6 */
-    def_irq_handler  NvicMux7_IRQHandler                     /* CM0+ NVIC Mux input 7 */
-    def_irq_handler  NvicMux8_IRQHandler                     /* CM0+ NVIC Mux input 8 */
-    def_irq_handler  NvicMux9_IRQHandler                     /* CM0+ NVIC Mux input 9 */
-    def_irq_handler  NvicMux10_IRQHandler                    /* CM0+ NVIC Mux input 10 */
-    def_irq_handler  NvicMux11_IRQHandler                    /* CM0+ NVIC Mux input 11 */
-    def_irq_handler  NvicMux12_IRQHandler                    /* CM0+ NVIC Mux input 12 */
-    def_irq_handler  NvicMux13_IRQHandler                    /* CM0+ NVIC Mux input 13 */
-    def_irq_handler  NvicMux14_IRQHandler                    /* CM0+ NVIC Mux input 14 */
-    def_irq_handler  NvicMux15_IRQHandler                    /* CM0+ NVIC Mux input 15 */
-    def_irq_handler  NvicMux16_IRQHandler                    /* CM0+ NVIC Mux input 16 */
-    def_irq_handler  NvicMux17_IRQHandler                    /* CM0+ NVIC Mux input 17 */
-    def_irq_handler  NvicMux18_IRQHandler                    /* CM0+ NVIC Mux input 18 */
-    def_irq_handler  NvicMux19_IRQHandler                    /* CM0+ NVIC Mux input 19 */
-    def_irq_handler  NvicMux20_IRQHandler                    /* CM0+ NVIC Mux input 20 */
-    def_irq_handler  NvicMux21_IRQHandler                    /* CM0+ NVIC Mux input 21 */
-    def_irq_handler  NvicMux22_IRQHandler                    /* CM0+ NVIC Mux input 22 */
-    def_irq_handler  NvicMux23_IRQHandler                    /* CM0+ NVIC Mux input 23 */
-    def_irq_handler  NvicMux24_IRQHandler                    /* CM0+ NVIC Mux input 24 */
-    def_irq_handler  NvicMux25_IRQHandler                    /* CM0+ NVIC Mux input 25 */
-    def_irq_handler  NvicMux26_IRQHandler                    /* CM0+ NVIC Mux input 26 */
-    def_irq_handler  NvicMux27_IRQHandler                    /* CM0+ NVIC Mux input 27 */
-    def_irq_handler  NvicMux28_IRQHandler                    /* CM0+ NVIC Mux input 28 */
-    def_irq_handler  NvicMux29_IRQHandler                    /* CM0+ NVIC Mux input 29 */
-    def_irq_handler  NvicMux30_IRQHandler                    /* CM0+ NVIC Mux input 30 */
-    def_irq_handler  NvicMux31_IRQHandler                    /* CM0+ NVIC Mux input 31 */
-
-    .end
-
-
-/* [] END OF FILE */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
deleted file mode 100644
index dc77b4ce238..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
+++ /dev/null
@@ -1,287 +0,0 @@
-/***************************************************************************//**
-* \file cy8c6xx7_cm0plus.icf
-* \version 2.50
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-if (!isdefinedsymbol(MBED_ROM_START)) {
-  define symbol MBED_ROM_START = 0x10000000;
-}
-
-/* MBED_APP_START is being  used by the bootloader build script and
- * will be calculate by the system. Without bootloader the MBED_APP_START
- * is equal to MBED_ROM_START
- */
-if (!isdefinedsymbol(MBED_APP_START)) {
-  define symbol MBED_APP_START = MBED_ROM_START;
-}
-
-if (!isdefinedsymbol(MBED_ROM_SIZE)) {
-  define symbol MBED_ROM_SIZE = 0x80000;
-}
-
-/* MBED_APP_SIZE is being  used by the bootloader build script and
- * will be calculate by the system. Without bootloader the MBED_APP_SIZE
- * is equal to MBED_ROM_SIZE
- */
-if (!isdefinedsymbol(MBED_APP_SIZE)) {
-  define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
-}
-
-if (!isdefinedsymbol(MBED_RAM_START)) {
-  define symbol MBED_RAM_START = 0x08000000;
-}
-
-if (!isdefinedsymbol(MBED_RAM_SIZE)) {
-  define symbol MBED_RAM_SIZE = 0x00010000;
-}
-
-if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) {
-  define symbol MBED_PUBLIC_RAM_START = 0x08047600;
-}
-
-if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) {
-  define symbol MBED_PUBLIC_RAM_SIZE = 0x200;
-}
-
-if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
-    define symbol MBED_BOOT_STACK_SIZE = 0x400;
-}
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM0+ core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
-define symbol __ICFEDIT_region_IRAM1_end__   = (MBED_RAM_START + MBED_RAM_SIZE);
-/* Public RAM */
-define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START;
-define symbol __ICFEDIT_region_IRAM2_end__   = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE);
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
-define symbol __ICFEDIT_region_IROM1_end__   = (MBED_APP_START + MBED_APP_SIZE - 0x8000);
-
-/* The following symbols define a 32K flash region used for EEPROM emulation. 
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__   = 0x160007FF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-
-
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
-  define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
-} else {
-  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x400;
-} else {
-  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
-
-define block RAM_DATA {readwrite section .data};
-define block RAM_OTHER {readwrite section * };
-define block RAM_NOINIT {readwrite section .noinit};
-define block RAM_BSS {readwrite section .bss};
-define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};
-define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block RO     {first section .intvec, readonly};
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize  { section .noinit, section .intvec_ram };
-
-
-/*-Placement-*/
-
-/* Flash */
-".cy_app_header" : place at start of IROM1_region  { section .cy_app_header };
-place in          IROM1_region  { block RO };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-".cy_xip" : place at start of EROM1_region  { section .cy_xip };
-
-/* RAM */
-place at start of IRAM1_region  { readwrite section .intvec_ram};
-place in IRAM1_region  { block RAM};
-place in IRAM1_region  { readwrite section .cy_ramfunc };
-place at end   of IRAM1_region  { block HSTACK };
-
-/* Public RAM */
-place at start of IRAM2_region  { section .cy_sharedmem };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep {  section .cy_app_header,
-        section .cy_em_eeprom,
-        section .cy_sflash_user_data,
-        section .cy_sflash_nar,
-        section .cy_sflash_public_key,
-        section .cy_toc_part2,
-        section .cy_rtoc_part2,
-        section .cy_efuse,
-        section .cy_xip,
-        section .cymeta,
-         };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start    = 0x10000000;
-define exported symbol __cy_memory_0_length   = 0x00100000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start    = 0x14000000;
-define exported symbol __cy_memory_1_length   = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start    = 0x16000000;
-define exported symbol __cy_memory_2_length   = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start    = 0x18000000;
-define exported symbol __cy_memory_3_length   = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start    = 0x90700000;
-define exported symbol __cy_memory_4_length   = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S
deleted file mode 100644
index e926966cf7e..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S
+++ /dev/null
@@ -1,413 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_psoc6_01_cm0plus.S
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0plus Device Series
-; * @version  V5.00
-; * @date     08. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-        SECTION .intvec_ram:DATA:NOROOT(2)
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        EXTERN __iar_data_init3
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
-        PUBLIC  __ramVectors
-
-        DATA
-
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     0x0000000D      ; NMI_Handler is defined in ROM code
-        DCD     HardFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
-__vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     0
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External interrupts                           Description
-        DCD     NvicMux0_IRQHandler                   ; CM0+ NVIC Mux input 0
-        DCD     NvicMux1_IRQHandler                   ; CM0+ NVIC Mux input 1
-        DCD     NvicMux2_IRQHandler                   ; CM0+ NVIC Mux input 2
-        DCD     NvicMux3_IRQHandler                   ; CM0+ NVIC Mux input 3
-        DCD     NvicMux4_IRQHandler                   ; CM0+ NVIC Mux input 4
-        DCD     NvicMux5_IRQHandler                   ; CM0+ NVIC Mux input 5
-        DCD     NvicMux6_IRQHandler                   ; CM0+ NVIC Mux input 6
-        DCD     NvicMux7_IRQHandler                   ; CM0+ NVIC Mux input 7
-        DCD     NvicMux8_IRQHandler                   ; CM0+ NVIC Mux input 8
-        DCD     NvicMux9_IRQHandler                   ; CM0+ NVIC Mux input 9
-        DCD     NvicMux10_IRQHandler                  ; CM0+ NVIC Mux input 10
-        DCD     NvicMux11_IRQHandler                  ; CM0+ NVIC Mux input 11
-        DCD     NvicMux12_IRQHandler                  ; CM0+ NVIC Mux input 12
-        DCD     NvicMux13_IRQHandler                  ; CM0+ NVIC Mux input 13
-        DCD     NvicMux14_IRQHandler                  ; CM0+ NVIC Mux input 14
-        DCD     NvicMux15_IRQHandler                  ; CM0+ NVIC Mux input 15
-        DCD     NvicMux16_IRQHandler                  ; CM0+ NVIC Mux input 16
-        DCD     NvicMux17_IRQHandler                  ; CM0+ NVIC Mux input 17
-        DCD     NvicMux18_IRQHandler                  ; CM0+ NVIC Mux input 18
-        DCD     NvicMux19_IRQHandler                  ; CM0+ NVIC Mux input 19
-        DCD     NvicMux20_IRQHandler                  ; CM0+ NVIC Mux input 20
-        DCD     NvicMux21_IRQHandler                  ; CM0+ NVIC Mux input 21
-        DCD     NvicMux22_IRQHandler                  ; CM0+ NVIC Mux input 22
-        DCD     NvicMux23_IRQHandler                  ; CM0+ NVIC Mux input 23
-        DCD     NvicMux24_IRQHandler                  ; CM0+ NVIC Mux input 24
-        DCD     NvicMux25_IRQHandler                  ; CM0+ NVIC Mux input 25
-        DCD     NvicMux26_IRQHandler                  ; CM0+ NVIC Mux input 26
-        DCD     NvicMux27_IRQHandler                  ; CM0+ NVIC Mux input 27
-        DCD     NvicMux28_IRQHandler                  ; CM0+ NVIC Mux input 28
-        DCD     NvicMux29_IRQHandler                  ; CM0+ NVIC Mux input 29
-        DCD     NvicMux30_IRQHandler                  ; CM0+ NVIC Mux input 30
-        DCD     NvicMux31_IRQHandler                  ; CM0+ NVIC Mux input 31
-
-__Vectors_End
-
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
-
-        SECTION .intvec_ram:DATA:REORDER:NOROOT(2)
-__ramVectors
-        DS32     __Vectors_Size
-
-
-        THUMB
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default handlers
-;;
-        PUBWEAK Default_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Default_Handler
-        B Default_Handler
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Weak function for startup customization
-;;
-;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
-;; because this function is executed as the first instruction in the ResetHandler.
-;; The PDL is also not initialized to use the proper register offsets.
-;; The user of this function is responsible for initializing the PDL and resources before using them.
-;;
-        PUBWEAK Cy_OnResetUser
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Cy_OnResetUser
-        BX LR
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Define strong version to return zero for
-;; __iar_program_start to skip data sections
-;; initialization.
-;;
-        PUBLIC __low_level_init
-        SECTION .text:CODE:REORDER:NOROOT(2)
-__low_level_init
-        MOVS R0, #0
-        BX LR
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        ; Define strong function for startup customization
-        LDR     R0, =Cy_OnResetUser
-        BLX     R0
-
-        ; Copy vectors from ROM to RAM
-        LDR r1, =__vector_table
-        LDR r0, =__ramVectors
-        LDR r2, =__Vectors_Size
-intvec_copy
-        LDR r3, [r1]
-        STR r3, [r0]
-        ADDS r0, r0, #4
-        ADDS r1, r1, #4
-        SUBS r2, r2, #1
-        CMP r2, #0
-        BNE intvec_copy
-
-        ; Update Vector Table Offset Register
-        LDR r0, =__ramVectors
-        LDR r1, =0xE000ED08
-        STR r0, [r1]
-        dsb
-
-        LDR     R0, =__iar_program_start
-        BLX     R0
-
-; Should never get here
-Cy_Main_Exited
-        B Cy_Main_Exited
-
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-
-        PUBWEAK Cy_SysLib_FaultHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Cy_SysLib_FaultHandler
-        B Cy_SysLib_FaultHandler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        IMPORT Cy_SysLib_FaultHandler
-        movs r0, #4
-        mov r1, LR
-        tst r0, r1
-        beq L_MSP
-        mrs r0, PSP
-        b L_API_call
-L_MSP
-        mrs r0, MSP
-L_API_call
-        ; Storing LR content for Creator call stack trace
-        push {LR}
-        bl Cy_SysLib_FaultHandler
-
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-
-        ; External interrupts
-        PUBWEAK NvicMux0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux0_IRQHandler
-        B       NvicMux0_IRQHandler
-
-        PUBWEAK NvicMux1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux1_IRQHandler
-        B       NvicMux1_IRQHandler
-
-        PUBWEAK NvicMux2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux2_IRQHandler
-        B       NvicMux2_IRQHandler
-
-        PUBWEAK NvicMux3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux3_IRQHandler
-        B       NvicMux3_IRQHandler
-
-        PUBWEAK NvicMux4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux4_IRQHandler
-        B       NvicMux4_IRQHandler
-
-        PUBWEAK NvicMux5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux5_IRQHandler
-        B       NvicMux5_IRQHandler
-
-        PUBWEAK NvicMux6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux6_IRQHandler
-        B       NvicMux6_IRQHandler
-
-        PUBWEAK NvicMux7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux7_IRQHandler
-        B       NvicMux7_IRQHandler
-
-        PUBWEAK NvicMux8_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux8_IRQHandler
-        B       NvicMux8_IRQHandler
-
-        PUBWEAK NvicMux9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux9_IRQHandler
-        B       NvicMux9_IRQHandler
-
-        PUBWEAK NvicMux10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux10_IRQHandler
-        B       NvicMux10_IRQHandler
-
-        PUBWEAK NvicMux11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux11_IRQHandler
-        B       NvicMux11_IRQHandler
-
-        PUBWEAK NvicMux12_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux12_IRQHandler
-        B       NvicMux12_IRQHandler
-
-        PUBWEAK NvicMux13_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux13_IRQHandler
-        B       NvicMux13_IRQHandler
-
-        PUBWEAK NvicMux14_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux14_IRQHandler
-        B       NvicMux14_IRQHandler
-
-        PUBWEAK NvicMux15_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux15_IRQHandler
-        B       NvicMux15_IRQHandler
-
-        PUBWEAK NvicMux16_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux16_IRQHandler
-        B       NvicMux16_IRQHandler
-
-        PUBWEAK NvicMux17_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux17_IRQHandler
-        B       NvicMux17_IRQHandler
-
-        PUBWEAK NvicMux18_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux18_IRQHandler
-        B       NvicMux18_IRQHandler
-
-        PUBWEAK NvicMux19_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux19_IRQHandler
-        B       NvicMux19_IRQHandler
-
-        PUBWEAK NvicMux20_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux20_IRQHandler
-        B       NvicMux20_IRQHandler
-
-        PUBWEAK NvicMux21_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux21_IRQHandler
-        B       NvicMux21_IRQHandler
-
-        PUBWEAK NvicMux22_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux22_IRQHandler
-        B       NvicMux22_IRQHandler
-
-        PUBWEAK NvicMux23_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux23_IRQHandler
-        B       NvicMux23_IRQHandler
-
-        PUBWEAK NvicMux24_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux24_IRQHandler
-        B       NvicMux24_IRQHandler
-
-        PUBWEAK NvicMux25_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux25_IRQHandler
-        B       NvicMux25_IRQHandler
-
-        PUBWEAK NvicMux26_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux26_IRQHandler
-        B       NvicMux26_IRQHandler
-
-        PUBWEAK NvicMux27_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux27_IRQHandler
-        B       NvicMux27_IRQHandler
-
-        PUBWEAK NvicMux28_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux28_IRQHandler
-        B       NvicMux28_IRQHandler
-
-        PUBWEAK NvicMux29_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux29_IRQHandler
-        B       NvicMux29_IRQHandler
-
-        PUBWEAK NvicMux30_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux30_IRQHandler
-        B       NvicMux30_IRQHandler
-
-        PUBWEAK NvicMux31_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux31_IRQHandler
-        B       NvicMux31_IRQHandler
-
-
-        END
-
-
-; [] END OF FILE
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c
deleted file mode 100644
index 010eac6188e..00000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M0/system_psoc6_cm0plus.c
+++ /dev/null
@@ -1,710 +0,0 @@
-/***************************************************************************//**
-* \file system_psoc6_cm0plus.c
-* \version 2.50
-*
-* The device system-source file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#include <stdbool.h>
-#include "system_psoc6.h"
-#include "cy_device.h"
-#include "cy_device_headers.h"
-#include "cy_syslib.h"
-#include "cy_wdt.h"
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-    #include "cy_ipc_sema.h"
-    #include "cy_ipc_pipe.h"
-    #include "cy_ipc_drv.h"
-
-    #if defined(CY_DEVICE_PSOC6ABLE2)
-        #include "cy_flash.h"
-    #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
-
-#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
-
-
-/*******************************************************************************
-* SystemCoreClockUpdate()
-*******************************************************************************/
-
-/** Default HFClk frequency in Hz */
-#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT       (8000000UL)
-
-/** Default PeriClk frequency in Hz */
-#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT      (4000000UL)
-
-/** Default SlowClk system core frequency in Hz */
-#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT       (4000000UL)
-
-/** IMO frequency in Hz */
-#define CY_CLK_IMO_FREQ_HZ                  (8000000UL)
-
-/** HVILO frequency in Hz */
-#define CY_CLK_HVILO_FREQ_HZ                (32000UL)
-
-/** PILO frequency in Hz */
-#define CY_CLK_PILO_FREQ_HZ                 (32768UL)
-
-/** WCO frequency in Hz */
-#define CY_CLK_WCO_FREQ_HZ                  (32768UL)
-
-/** ALTLF frequency in Hz */
-#define CY_CLK_ALTLF_FREQ_HZ                (32768UL)
-
-
-/**
-* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
-* which is the system clock frequency supplied to the SysTick timer and the
-* processor core clock.
-* This variable implements CMSIS Core global variable.
-* Refer to the [CMSIS documentation]
-* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
-* for more details.
-* This variable can be used by debuggers to query the frequency
-* of the debug timer or to configure the trace clock speed.
-*
-* \attention Compilers must be configured to avoid removing this variable in case
-* the application program is not using it. Debugging systems require the variable
-* to be physically present in memory so that it can be examined to configure the debugger. */
-uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
-
-/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
-uint32_t cy_Hfclk0FreqHz  = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
-
-/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
-uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
-
-/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
-#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
-    uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
-#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
-
-
-/*******************************************************************************
-* SystemInit()
-*******************************************************************************/
-
-/* CLK_FLL_CONFIG default values */
-#define CY_FB_CLK_FLL_CONFIG_VALUE      (0x01000000u)
-#define CY_FB_CLK_FLL_CONFIG2_VALUE     (0x00020001u)
-#define CY_FB_CLK_FLL_CONFIG3_VALUE     (0x00002800u)
-#define CY_FB_CLK_FLL_CONFIG4_VALUE     (0x000000FFu)
-
-
-/*******************************************************************************
-* SystemCoreClockUpdate (void)
-*******************************************************************************/
-
-/* Do not use these definitions directly in your application */
-#define CY_DELAY_MS_OVERFLOW_THRESHOLD  (0x8000u)
-#define CY_DELAY_1K_THRESHOLD           (1000u)
-#define CY_DELAY_1K_MINUS_1_THRESHOLD   (CY_DELAY_1K_THRESHOLD - 1u)
-#define CY_DELAY_1M_THRESHOLD           (1000000u)
-#define CY_DELAY_1M_MINUS_1_THRESHOLD   (CY_DELAY_1M_THRESHOLD - 1u)
-uint32_t cy_delayFreqHz   = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
-
-uint32_t cy_delayFreqKhz  = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
-                            CY_DELAY_1K_THRESHOLD;
-
-uint8_t cy_delayFreqMhz  = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
-                            CY_DELAY_1M_THRESHOLD);
-
-uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
-                            ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
-
-#define CY_ROOT_PATH_SRC_IMO                (0UL)
-#define CY_ROOT_PATH_SRC_EXT                (1UL)
-#if (SRSS_ECO_PRESENT == 1U)
-    #define CY_ROOT_PATH_SRC_ECO            (2UL)
-#endif /* (SRSS_ECO_PRESENT == 1U) */
-#if (SRSS_ALTHF_PRESENT == 1U)
-    #define CY_ROOT_PATH_SRC_ALTHF          (3UL)
-#endif /* (SRSS_ALTHF_PRESENT == 1U) */
-#define CY_ROOT_PATH_SRC_DSI_MUX            (4UL)
-#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO      (16UL)
-#define CY_ROOT_PATH_SRC_DSI_MUX_WCO        (17UL)
-#if (SRSS_ALTLF_PRESENT == 1U)
-    #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF  (18UL)
-#endif /* (SRSS_ALTLF_PRESENT == 1U) */
-#if (SRSS_PILO_PRESENT == 1U)
-    #define CY_ROOT_PATH_SRC_DSI_MUX_PILO   (19UL)
-#endif /* (SRSS_PILO_PRESENT == 1U) */
-
-
-/*******************************************************************************
-* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
-*******************************************************************************/
-#define CY_SYS_CM4_PWR_CTL_KEY_OPEN  (0x05FAUL)
-#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
-#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR  (0x000003FFUL)
-
-
-/*******************************************************************************
-* Function Name: SystemInit
-****************************************************************************//**
-*
-* Initializes the system:
-* - Restores FLL registers to the default state.
-* - Unlocks and disables WDT.
-* - Calls Cy_PDL_Init() function to define the driver library.
-* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
-* - Calls \ref SystemCoreClockUpdate().
-*
-*******************************************************************************/
-void SystemInit(void)
-{
-    Cy_PDL_Init(CY_DEVICE_CFG);
-
-    /* Restore FLL registers to the default state as they are not restored by the ROM code */
-    uint32_t copy = SRSS->CLK_FLL_CONFIG;
-    copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
-    SRSS->CLK_FLL_CONFIG = copy;
-
-    copy = SRSS->CLK_ROOT_SELECT[0u];
-    copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
-    SRSS->CLK_ROOT_SELECT[0u] = copy;
-
-    SRSS->CLK_FLL_CONFIG  = CY_FB_CLK_FLL_CONFIG_VALUE;
-    SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
-    SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
-    SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
-
-    /* Unlock and disable WDT */
-    Cy_WDT_Unlock();
-    Cy_WDT_Disable();
-
-    Cy_SystemInit();
-    SystemCoreClockUpdate();
-
-#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
-    if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
-    {
-        /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
-        IPC_STRUCT7->DATA = 0UL;
-        /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
-        IPC_STRUCT7->RELEASE = 0UL;
-    }
-#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-    /* Allocate and initialize semaphores for the system operations. */
-    CY_SECTION(".cy_sharedmem")
-    static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
-
-    (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
-
-
-    /********************************************************************************
-    *
-    * Initializes the system pipes. The system pipes are used by BLE and Flash.
-    *
-    * If the default startup file is not used, or SystemInit() is not called in your
-    * project, call the following three functions prior to executing any flash or
-    * EmEEPROM write or erase operation:
-    *  -# Cy_IPC_Sema_Init()
-    *  -# Cy_IPC_Pipe_Config()
-    *  -# Cy_IPC_Pipe_Init()
-    *  -# Cy_Flash_Init()
-    *
-    *******************************************************************************/
-
-    /* Create an array of endpoint structures */
-    static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
-
-    Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
-
-    static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
-
-    static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
-    {
-    /* .ep0ConfigData */
-        {
-            /* .ipcNotifierNumber    */  CY_IPC_INTR_CYPIPE_EP0,
-            /* .ipcNotifierPriority  */  CY_SYS_INTR_CYPIPE_PRIOR_EP0,
-            /* .ipcNotifierMuxNumber */  CY_SYS_INTR_CYPIPE_MUX_EP0,
-            /* .epAddress            */  CY_IPC_EP_CYPIPE_CM0_ADDR,
-            /* .epConfig             */  CY_SYS_CYPIPE_CONFIG_EP0
-        },
-    /* .ep1ConfigData */
-        {
-            /* .ipcNotifierNumber    */  CY_IPC_INTR_CYPIPE_EP1,
-            /* .ipcNotifierPriority  */  CY_SYS_INTR_CYPIPE_PRIOR_EP1,
-            /* .ipcNotifierMuxNumber */  0u,
-            /* .epAddress            */  CY_IPC_EP_CYPIPE_CM4_ADDR,
-            /* .epConfig             */  CY_SYS_CYPIPE_CONFIG_EP1
-        },
-    /* .endpointClientsCount     */  CY_SYS_CYPIPE_CLIENT_CNT,
-    /* .endpointsCallbacksArray  */  systemIpcPipeSysCbArray,
-    /* .userPipeIsrHandler       */  &Cy_SysIpcPipeIsrCm0
-    };
-
-    if (cy_device->flashPipeRequired != 0u)
-    {
-        Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
-    }
-
-#if defined(CY_DEVICE_PSOC6ABLE2)
-    Cy_Flash_Init();
-#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
-
-#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SystemInit
-****************************************************************************//**
-*
-* The function is called during device startup. Once project compiled as part of
-* the PSoC Creator project, the Cy_SystemInit() function is generated by the
-* PSoC Creator.
-*
-* The function generated by PSoC Creator performs all of the necessary device
-* configuration based on the design settings.  This includes settings from the
-* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
-* configuration that is necessary.
-*
-*******************************************************************************/
-__WEAK void Cy_SystemInit(void)
-{
-     /* Empty weak function. The actual implementation to be in the PSoC Creator
-      * generated strong function.
-     */
-}
-
-
-/*******************************************************************************
-* Function Name: SystemCoreClockUpdate
-****************************************************************************//**
-*
-* Gets core clock frequency and updates \ref SystemCoreClock, \ref
-* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
-*
-* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
-* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
-*
-*******************************************************************************/
-void SystemCoreClockUpdate (void)
-{
-    uint32_t srcFreqHz;
-    uint32_t pathFreqHz;
-    uint32_t slowClkDiv;
-    uint32_t periClkDiv;
-    uint32_t rootPath;
-    uint32_t srcClk;
-
-    /* Get root path clock for the high-frequency clock # 0 */
-    rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
-
-    /* Get source of the root path clock */
-    srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
-
-    /* Get frequency of the source */
-    switch (srcClk)
-    {
-    case CY_ROOT_PATH_SRC_IMO:
-        srcFreqHz = CY_CLK_IMO_FREQ_HZ;
-    break;
-
-    case CY_ROOT_PATH_SRC_EXT:
-        srcFreqHz = CY_CLK_EXT_FREQ_HZ;
-    break;
-
-    #if (SRSS_ECO_PRESENT == 1U)
-        case CY_ROOT_PATH_SRC_ECO:
-            srcFreqHz = CY_CLK_ECO_FREQ_HZ;
-        break;
-    #endif /* (SRSS_ECO_PRESENT == 1U) */
-
-#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
-    case CY_ROOT_PATH_SRC_ALTHF:
-        srcFreqHz = cy_BleEcoClockFreqHz;
-    break;
-#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
-
-    case CY_ROOT_PATH_SRC_DSI_MUX:
-    {
-        uint32_t dsi_src;
-        dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX,  SRSS->CLK_DSI_SELECT[rootPath]);
-        switch (dsi_src)
-        {
-        case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
-            srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
-        break;
-
-        case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
-            srcFreqHz = CY_CLK_WCO_FREQ_HZ;
-        break;
-
-        #if (SRSS_ALTLF_PRESENT == 1U)
-            case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
-                srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
-            break;
-        #endif /* (SRSS_ALTLF_PRESENT == 1U) */
-
-        #if (SRSS_PILO_PRESENT == 1U)
-            case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
-                srcFreqHz = CY_CLK_PILO_FREQ_HZ;
-            break;
-        #endif /* (SRSS_PILO_PRESENT == 1U) */
-
-        default:
-            srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
-        break;
-        }
-    }
-    break;
-
-    default:
-        srcFreqHz = CY_CLK_EXT_FREQ_HZ;
-    break;
-    }
-
-    if (rootPath == 0UL)
-    {
-        /* FLL */
-        bool fllLocked       = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
-        bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
-        bool fllOutputAuto   = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
-                                (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
-        if ((fllOutputAuto && fllLocked) || fllOutputOutput)
-        {
-            uint32_t fllMult;
-            uint32_t refDiv;
-            uint32_t outputDiv;
-
-            fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
-            refDiv  = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
-            outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
-
-            pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
-        }
-        else
-        {
-            pathFreqHz = srcFreqHz;
-        }
-    }
-    else if ((rootPath == 1UL) || (rootPath == 2UL))
-    {
-        /* PLL */
-        bool pllLocked       = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED,     SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
-        bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
-        bool pllOutputAuto   = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
-                                (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
-        if ((pllOutputAuto && pllLocked) || pllOutputOutput)
-        {
-            uint32_t feedbackDiv;
-            uint32_t referenceDiv;
-            uint32_t outputDiv;
-
-            feedbackDiv  = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV,  SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
-            referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
-            outputDiv    = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV,    SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
-
-            pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
-
-        }
-        else
-        {
-            pathFreqHz = srcFreqHz;
-        }
-    }
-    else
-    {
-        /* Direct */
-        pathFreqHz = srcFreqHz;
-    }
-
-    /* Get frequency after hf_clk pre-divider */
-    pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
-    cy_Hfclk0FreqHz = pathFreqHz;
-
-    /* Slow Clock Divider */
-    slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL);
-
-    /* Peripheral Clock Divider */
-    periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
-
-    pathFreqHz = pathFreqHz / periClkDiv;
-    cy_PeriClkFreqHz = pathFreqHz;
-    pathFreqHz = pathFreqHz / slowClkDiv;
-    SystemCoreClock = pathFreqHz;
-
-    /* Sets clock frequency for Delay API */
-    cy_delayFreqHz = SystemCoreClock;
-    cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
-    cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
-    cy_delay32kMs   = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
-}
-
-
-#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
-/*******************************************************************************
-* Function Name: Cy_SysGetCM4Status
-****************************************************************************//**
-*
-* Returns the Cortex-M4 core power mode.
-*
-* \return \ref group_system_config_cm4_status_macro
-*
-*******************************************************************************/
-uint32_t Cy_SysGetCM4Status(void)
-{
-    uint32_t regValue;
-
-    /* Get current power mode */
-    regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
-
-    return (regValue);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysEnableCM4
-****************************************************************************//**
-*
-* Sets vector table base address and enables the Cortex-M4 core.
-*
-* \note If the CPU is already enabled, it is reset and then enabled.
-*
-* \param vectorTableOffset The offset of the vector table base address from
-* memory address 0x00000000. The offset should be multiple to 1024 bytes.
-*
-*******************************************************************************/
-void Cy_SysEnableCM4(uint32_t vectorTableOffset)
-{
-    uint32_t regValue;
-    uint32_t interruptState;
-    uint32_t cpuState;
-
-    CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    cpuState = Cy_SysGetCM4Status();
-    if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
-    {
-        Cy_SysResetCM4();
-    }
-
-    CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_ENABLED;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
-    {
-        /* Wait for the power mode to take effect */
-    }
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysDisableCM4
-****************************************************************************//**
-*
-* Disables the Cortex-M4 core and waits for the mode to take the effect.
-*
-* \warning Do not call the function while the Cortex-M4 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
-* CPU.
-*
-*******************************************************************************/
-void Cy_SysDisableCM4(void)
-{
-    uint32_t interruptState;
-    uint32_t regValue;
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_DISABLED;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
-    {
-        /* Wait for the power mode to take effect */
-    }
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysRetainCM4
-****************************************************************************//**
-*
-* Retains the Cortex-M4 core and exists without waiting for the mode to take
-* effect.
-*
-* \note The retained mode can be entered only from the enabled mode.
-*
-* \warning Do not call the function while the Cortex-M4 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
-*
-*******************************************************************************/
-void Cy_SysRetainCM4(void)
-{
-    uint32_t interruptState;
-    uint32_t regValue;
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_RETAINED;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysResetCM4
-****************************************************************************//**
-*
-* Resets the Cortex-M4 core and waits for the mode to take the effect.
-*
-* \note The reset mode can not be entered from the retained mode.
-*
-* \warning Do not call the function while the Cortex-M4 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
-*
-*******************************************************************************/
-void Cy_SysResetCM4(void)
-{
-    uint32_t interruptState;
-    uint32_t regValue;
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_RESET;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
-    {
-        /* Wait for the power mode to take effect */
-    }
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-/*******************************************************************************
-* Function Name: Cy_SysIpcPipeIsrCm0
-****************************************************************************//**
-*
-* This is the interrupt service routine for the system pipe.
-*
-*******************************************************************************/
-void Cy_SysIpcPipeIsrCm0(void)
-{
-    Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR);
-}
-#endif
-
-
-/*******************************************************************************
-* Function Name: Cy_MemorySymbols
-****************************************************************************//**
-*
-* The intention of the function is to declare boundaries of the memories for the
-* MDK compilers. For the rest of the supported compilers, this is done using
-* linker configuration files. The following symbols used by the cymcuelftool.
-*
-*******************************************************************************/
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
-__asm void Cy_MemorySymbols(void)
-{
-    /* Flash */
-    EXPORT __cy_memory_0_start
-    EXPORT __cy_memory_0_length
-    EXPORT __cy_memory_0_row_size
-
-    /* Working Flash */
-    EXPORT __cy_memory_1_start
-    EXPORT __cy_memory_1_length
-    EXPORT __cy_memory_1_row_size
-
-    /* Supervisory Flash */
-    EXPORT __cy_memory_2_start
-    EXPORT __cy_memory_2_length
-    EXPORT __cy_memory_2_row_size
-
-    /* XIP */
-    EXPORT __cy_memory_3_start
-    EXPORT __cy_memory_3_length
-    EXPORT __cy_memory_3_row_size
-
-    /* eFuse */
-    EXPORT __cy_memory_4_start
-    EXPORT __cy_memory_4_length
-    EXPORT __cy_memory_4_row_size
-
-    /* Flash */
-__cy_memory_0_start     EQU __cpp(CY_FLASH_BASE)
-__cy_memory_0_length    EQU __cpp(CY_FLASH_SIZE)
-__cy_memory_0_row_size  EQU 0x200
-
-    /* Flash region for EEPROM emulation */
-__cy_memory_1_start     EQU __cpp(CY_EM_EEPROM_BASE)
-__cy_memory_1_length    EQU __cpp(CY_EM_EEPROM_SIZE)
-__cy_memory_1_row_size  EQU 0x200
-
-    /* Supervisory Flash */
-__cy_memory_2_start     EQU __cpp(CY_SFLASH_BASE)
-__cy_memory_2_length    EQU __cpp(CY_SFLASH_SIZE)
-__cy_memory_2_row_size  EQU 0x200
-
-    /* XIP */
-__cy_memory_3_start     EQU __cpp(CY_XIP_BASE)
-__cy_memory_3_length    EQU __cpp(CY_XIP_SIZE)
-__cy_memory_3_row_size  EQU 0x200
-
-    /* eFuse */
-__cy_memory_4_start     EQU __cpp(0x90700000)
-__cy_memory_4_length    EQU __cpp(0x100000)
-__cy_memory_4_row_size  EQU __cpp(1)
-}
-#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
-
-
-/* [] END OF FILE */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
similarity index 94%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
index a23e6e13f61..32e78ff05af 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
@@ -3,7 +3,7 @@
 ; to pass a scatter file through a C preprocessor.
 
 ;*******************************************************************************
-;* \file cy8c6xx7_cm4_dual.scat
+;* \file cy8c6xx7_cm4_dual.sct
 ;* \version 2.50
 ;*
 ;* Linker file for the ARMCC.
@@ -78,6 +78,7 @@
   #define MBED_BOOT_STACK_SIZE 0x400
 #endif
 
+; Size of the stack section at the end of CM4 SRAM
 #define STACK_SIZE MBED_BOOT_STACK_SIZE
 
 ; The defines below describe the location and size of blocks of memory in the target.
@@ -96,6 +97,9 @@
 #define FLASH_START             MBED_APP_START
 #define FLASH_SIZE              MBED_APP_SIZE
 
+; Size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
 ; The following defines describe a 32K flash region used for EEPROM emulation.
 ; This region can also be used as the general purpose flash.
 ; You can assign sections to this memory region for only one of the cores.
@@ -133,17 +137,9 @@
 #define EFUSE_START             0x90700000
 #define EFUSE_SIZE              0x100000
 
-; Size and start address of the Cortex-M0+ application image
-#define FLASH_CM0P_SIZE         0x2000
-#define FLASH_CM0P_START        FLASH_START
-
-; Size and start address of the Cortex-M4 application image
-#define FLASH_CM4_SIZE          (FLASH_SIZE - FLASH_CM0P_SIZE)
-#define FLASH_CM4_START         (FLASH_CM0P_START + FLASH_CM0P_SIZE)
-
 
-; Cortex-M0+ application image
-LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
 {
     .cy_m0p_image +0 FLASH_CM0P_SIZE
     {
@@ -151,8 +147,8 @@ LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
     }
 }
 
-; Cortex-M4 application image
-LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
 {
     ER_FLASH_VECTORS +0
     {
@@ -173,7 +169,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
     RW_RAM_DATA +0
     {
         * (.cy_ramfunc)
-        .ANY (+RW, +ZI)
+        * (+RW, +ZI)
     }
 
     ; Place variables in the section that should not be initialized during the
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
similarity index 96%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
index 0cfd336d6ec..a2e3f35a65e 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
@@ -76,8 +76,12 @@ ENTRY(Reset_Handler)
     #define MBED_BOOT_STACK_SIZE 0x400
 #endif
 
+/* Size of the stack section at the end of CM4 SRAM */
 STACK_SIZE = MBED_BOOT_STACK_SIZE;
 
+/* Size of the Cortex-M0+ application image at the start of FLASH */
+FLASH_CM0P_SIZE  = 0x2000;
+
 /* Force symbol to be entered in the output file as an undefined symbol. Doing
 * this may, for example, trigger linking of additional modules from standard
 * libraries. You may list several symbols for each EXTERN, and you may use
@@ -118,13 +122,6 @@ MEMORY
     efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
 }
 
-/* Size and start address of the Cortex-M0+ application image */
-FLASH_CM0P_SIZE  = 0x2000;
-FLASH_CM0P_START = ORIGIN(flash);
-/* Size and start address of the Cortex-M4 application image */
-FLASH_CM4_SIZE   = LENGTH(flash) - FLASH_CM0P_SIZE;
-FLASH_CM4_START  = FLASH_CM0P_START + FLASH_CM0P_SIZE;
-
 /* Library configurations */
 GROUP(libgcc.a libc.a libm.a libnosys.a)
 
@@ -164,8 +161,8 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
 
 SECTIONS
 {
-     /* Cortex-M0+ application image */
-    .cy_m0p_image FLASH_CM0P_START :
+     /* Cortex-M0+ application flash image area */
+    .cy_m0p_image ORIGIN(flash) :
     {
         . = ALIGN(4);
         __cy_m0p_code_start = . ;
@@ -173,8 +170,11 @@ SECTIONS
         __cy_m0p_code_end = . ;
     } > flash
 
-    /* Cortex-M4 application image */
-    .text FLASH_CM4_START :
+    /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
+    ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
+
+    /* Cortex-M4 application flash area */
+    .text ORIGIN(flash) + FLASH_CM0P_SIZE :
     {
         . = ALIGN(4);
         __Vectors = . ;
@@ -290,7 +290,6 @@ SECTIONS
         KEEP(*(.init_array))
         PROVIDE_HIDDEN (__init_array_end = .);
 
-
         . = ALIGN(4);
         /* finit data */
         PROVIDE_HIDDEN (__fini_array_start = .);
@@ -351,7 +350,7 @@ SECTIONS
         __HeapLimit = .;
     } > ram
 
-    
+
     /* Set stack top to end of RAM, and stack limit move down by
      * size of stack_dummy section */
     __StackTop = ORIGIN(ram) + LENGTH(ram);
@@ -404,7 +403,7 @@ SECTIONS
         KEEP(*(.cy_toc_part2))
     } > sflash_toc_2
 
-    
+
     /* Supervisory Flash: Table of Content # 2 Copy */
     .cy_rtoc_part2 :
     {
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
similarity index 98%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
index 1fd2e3e5783..1f3e2aa9ef5 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
@@ -156,7 +156,7 @@ if (!isdefinedsymbol(__STACK_SIZE)) {
 
 /* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
 if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x400;
+    define symbol __ICFEDIT_size_heap__ = 0x0400;
 } else {
   define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
 }
@@ -198,8 +198,10 @@ do not initialize  { section .noinit, section .intvec_ram };
 /* Flash - Cortex-M0+ application image */
 place at start of IROM1_region  { block CM0P_RO };
 
-/* Flash - Cortex-M4 application image */
+/* Flash - Cortex-M4 application */
 place in          IROM1_region  { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
 ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
 
 /* Emulated EEPROM Flash area */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
similarity index 99%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
index 75747c4face..f4ca47b4579 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TARGET_MCU_PSOC6_M4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
@@ -310,10 +310,6 @@ intvec_copy
         STR r0, [r1]
         dsb
 
-        ; Enable the FPU if used
-        LDR     R0, =Cy_SystemInitFpuEnable
-        BLX     R0
-
         ; Initialize data sections
         LDR     R0, =__iar_data_init3
         BLX     R0
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/system_psoc6_cm4.c
similarity index 100%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TARGET_MCU_PSOC6_M4/system_psoc6_cm4.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/system_psoc6_cm4.c
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c
index 69c69a94a0d..5c39f782e0d 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c
@@ -22,6 +22,7 @@
 #include "cybsp_api_core.h"
 #include "mbed_power_mgmt.h"
 #include "rtos_idle.h"
+#include "us_ticker_api.h"
 
 #if defined(COMPONENT_SPM_MAILBOX)
 void mailbox_init(void);
@@ -83,6 +84,11 @@ void mbed_sdk_init(void)
 #if !defined(TARGET_PSA)
     /* Set up the device based on configurator selections */
     cybsp_init();
+    /*
+     * Init the us Ticker here to avoid imposing on the limited stack space of the idle thread.
+     * This also allows the first call to sleep to occur faster.
+     */
+    us_ticker_init();
 #endif
 
     /* Enable global interrupts (disabled in CM4 startup assembly) */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c
index 62e8ce5046d..251e4208919 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c
@@ -110,7 +110,8 @@ const cy_stc_gpio_pin_config_t pin_clk_config =
 static cyhal_sdio_irq_handler_t cyhal_sdio_callback = NULL;
 static cyhal_sdio_t *cyhal_sdio_config_struct = NULL;
 static void *cyhal_sdio_callback_args = NULL;
-
+static bool deep_sleep_pending = false;
+static bool op_pending = false;
 
 /*******************************************************************************
 *       Dispatcher Interrupt Callbacks Service Routine
@@ -128,6 +129,98 @@ static void cyhal_sdio_interrupts_dispatcher_IRQHandler(void)
 *       Internal functions
 *******************************************************************************/
 static void cyhal_free_pins(cyhal_sdio_t *obj);
+static cy_en_syspm_status_t cyhal_sdio_ds_callback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
+
+/******************************************************************************
+*  Parameter structure for Deep Sleep callback function
+******************************************************************************/
+static cy_stc_syspm_callback_params_t cyhal_sdio_pm_callback_params =
+{
+    NULL,
+    NULL
+};
+
+/******************************************************************************
+*       Deep Sleep callback
+******************************************************************************/
+static cy_stc_syspm_callback_t cyhal_sdio_pm_callback =
+{
+    &cyhal_sdio_ds_callback,
+    CY_SYSPM_DEEPSLEEP,
+    0U,
+    &cyhal_sdio_pm_callback_params,
+    NULL,
+    NULL,
+    CYHAL_SDIO_DS_CB_ORDER
+};
+
+/* Internal deep sleep callback, which does following:
+*  1. Save/restore not retained configuration registers in the Deep Sleep
+*  2. Execute registered callback with CYHAL_SDIO_GOING_DOWN event, before
+*     entering into Deep Sleep
+*  3. Execute registered callback with CYHAL_SDIO_COMING_UP event, after
+*     exit from Deep Sleep
+* */
+cy_en_syspm_status_t cyhal_sdio_ds_callback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode)
+{
+    cy_en_syspm_status_t retVal = SDIO_DeepSleepCallback(callbackParams, mode);
+
+    if (retVal == CY_SYSPM_SUCCESS)
+    {
+        switch (mode)
+        {
+            case CY_SYSPM_CHECK_READY:
+            {
+                /* Check if transfer is pending */
+                if (!op_pending)
+                {
+                    /* Execute callback to indicate that interface is going down */
+                    if ((cyhal_sdio_callback != NULL) && (0U != (cyhal_sdio_config_struct->events & (uint32_t) CYHAL_SDIO_GOING_DOWN)))
+                    {
+                        (void)(cyhal_sdio_callback)(cyhal_sdio_callback_args, CYHAL_SDIO_GOING_DOWN);
+                    }
+
+                    /* Indicate Deep Sleep entering */
+                    deep_sleep_pending = true;
+                }
+                else
+                {
+                    retVal = CY_SYSPM_FAIL;
+                }
+                break;
+            }
+
+            case CY_SYSPM_BEFORE_TRANSITION:
+            {
+                /* Nothing to do in this mode */
+                break;
+            }
+
+            case CY_SYSPM_AFTER_TRANSITION:
+            case CY_SYSPM_CHECK_FAIL:
+            {
+                /* Execute this only if check ready case was executed */
+                if (deep_sleep_pending)
+                {
+                    /* Execute callback to indicate that interface is coming up */
+                    if ((cyhal_sdio_callback != NULL) && (0U != (cyhal_sdio_config_struct->events & (uint32_t) CYHAL_SDIO_COMING_UP)))
+                    {
+                        (void)(cyhal_sdio_callback)(cyhal_sdio_callback_args, CYHAL_SDIO_COMING_UP);
+                    }
+
+                    /* Indicate Deep Sleep exit */
+                    deep_sleep_pending = false;
+                }
+                break;
+            }
+
+            default:
+                break;
+        }
+    }
+
+    return retVal;
+}
 
 static void cyhal_free_pins(cyhal_sdio_t *obj)
 {
@@ -380,6 +473,15 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk,
             obj->irq_cause = 0u;
 
             retVal = cyhal_hwmgr_set_configured(udbRsc.type, udbRsc.block_num, udbRsc.channel_num);
+
+            /* Register SDIO Deep Sleep Callback */
+            if (retVal == CY_RSLT_SUCCESS)
+            {
+                if (!Cy_SysPm_RegisterCallback(&cyhal_sdio_pm_callback))
+                {
+                    retVal = CY_RSLT_TYPE_ERROR;
+                }
+            }
         }
     }
 
@@ -398,6 +500,10 @@ void cyhal_sdio_free(cyhal_sdio_t *obj)
     cyhal_free_pins(obj);
     cyhal_free_clocks(obj);
     cyhal_free_dmas(obj);
+
+    SDIO_Free();
+    /* Unregister SDIO Deep Sleep Callback */
+    (void)Cy_SysPm_UnregisterCallback(&cyhal_sdio_pm_callback);
 }
 
 cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config)
@@ -428,35 +534,53 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio
     {
         return CYHAL_SDIO_RSLT_ERR_BAD_PARAM;
     }
-    
+
     uint32_t cmdResponse;
     stc_sdio_cmd_t cmd;
     en_sdio_result_t status;
-    cy_rslt_t retVal = CY_RSLT_SUCCESS;
+    cy_rslt_t retVal = CYHAL_SDIO_RSLT_CANCELED;
 
-    if (response != NULL)
+    /* Check other pending operations */
+    if (!op_pending)
     {
-        *response = 0;
-    }
+        /* Indicate pending operation to prevent entering into Deep Sleep */
+        op_pending = true;
 
-    cmd.u32CmdIdx = (uint32_t) command;
-    cmd.u32Arg = argument;
-    cmd.pu32Response = &cmdResponse;
-    cmd.pu8Data = NULL;              /* Not used */
-    cmd.bRead = (direction != CYHAL_READ) ? false : true;
-    cmd.u16BlockCnt = 0U;            /* Not used */
-    cmd.u16BlockSize = 0U;           /* Not used */
+        if (response != NULL)
+        {
+            *response = 0;
+        }
 
-    status = SDIO_SendCommandAndWait(&cmd);
+        cmd.u32CmdIdx = (uint32_t) command;
+        cmd.u32Arg = argument;
+        cmd.pu32Response = &cmdResponse;
+        cmd.pu8Data = NULL;              /* Not used */
+        cmd.bRead = (direction != CYHAL_READ) ? false : true;
+        cmd.u16BlockCnt = 0U;            /* Not used */
+        cmd.u16BlockSize = 0U;           /* Not used */
 
-    if (Ok != status)
-    {
-        retVal = CYHAL_SDIO_RSLT_ERR_FUNC_RET(status);
-    }
+        /* Send command only if there is no attempts to enter into Deep Sleep */
+        if (!deep_sleep_pending)
+        {
+            status = SDIO_SendCommandAndWait(&cmd);
 
-    if (response != NULL)
-    {
-        *response = cmdResponse;
+            if (Ok != status)
+            {
+                retVal = CYHAL_SDIO_RSLT_ERR_FUNC_RET(status);
+            }
+            else
+            {
+                retVal = CY_RSLT_SUCCESS;
+            }
+
+            if (response != NULL)
+            {
+                *response = cmdResponse;
+            }
+        }
+
+        /*  Indicate finished operation */
+        op_pending = false;
     }
 
     return retVal;
@@ -465,48 +589,66 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio
 cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length, uint32_t* response)
 {
     CY_ASSERT(NULL != obj);
+    cy_rslt_t retVal = CYHAL_SDIO_RSLT_CANCELED;
 
-    stc_sdio_cmd_t cmd;
-    en_sdio_result_t status;
-    uint32_t cmdResponse;
-    cy_rslt_t retVal = CY_RSLT_SUCCESS;
-
-    if (response != NULL)
+    /* Check other pending operations */
+    if (!op_pending)
     {
-        *response = 0;
-    }
+        /* Indicate pending operation to prevent entering into Deep Sleep */
+        op_pending = true;
+        stc_sdio_cmd_t cmd;
+        en_sdio_result_t status;
+        uint32_t cmdResponse;
 
-    cmd.u32CmdIdx = (uint32_t) CYHAL_SDIO_CMD_IO_RW_EXTENDED;
-    cmd.u32Arg = argument;
-    cmd.pu32Response = &cmdResponse;
+        if (response != NULL)
+        {
+            *response = 0;
+        }
 
-    /* Note that this implementation uses 8b address */
-    cmd.pu8Data = (uint8_t *) data;
-    cmd.bRead = (direction != CYHAL_READ) ? false : true;
+        cmd.u32CmdIdx = (uint32_t) CYHAL_SDIO_CMD_IO_RW_EXTENDED;
+        cmd.u32Arg = argument;
+        cmd.pu32Response = &cmdResponse;
 
-    if (length >= obj->block_size)
-    {
-        cmd.u16BlockCnt = (uint16_t) ((length + obj->block_size - 1)/obj->block_size);
-        cmd.u16BlockSize = obj->block_size;
-    }
-    else
-    {
-        /* Data will be sent as one packet */
-        cmd.u16BlockCnt = CY_HAL_SDIO_1B;
-        cmd.u16BlockSize = length;
-    }
+        /* Note that this implementation uses 8b address */
+        cmd.pu8Data = (uint8_t *) data;
+        cmd.bRead = (direction != CYHAL_READ) ? false : true;
 
-    status = SDIO_SendCommandAndWait(&cmd);
+        if (length >= obj->block_size)
+        {
+            cmd.u16BlockCnt = (uint16_t) ((length + obj->block_size - 1)/obj->block_size);
+            cmd.u16BlockSize = obj->block_size;
+        }
+        else
+        {
+            /* Data will be sent as one packet */
+            cmd.u16BlockCnt = CY_HAL_SDIO_1B;
+            cmd.u16BlockSize = length;
+        }
 
-    if (Ok != status)
-    {
-        retVal = CYHAL_SDIO_RSLT_ERR_FUNC_RET(status);
-    }
+        /* Start transfer only if there is no attempts to enter into Deep Sleep */
+        if (!deep_sleep_pending)
+        {
+            status = SDIO_SendCommandAndWait(&cmd);
 
-    if (response != NULL)
-    {
-        *response = cmdResponse;
+            if (Ok != status)
+            {
+                retVal = CYHAL_SDIO_RSLT_ERR_FUNC_RET(status);
+            }
+            else
+            {
+                retVal = CY_RSLT_SUCCESS;
+            }
+
+            if (response != NULL)
+            {
+                *response = cmdResponse;
+            }
+        }
+
+        /*  Indicate finished transfer */
+        op_pending = false;
     }
+
     return retVal;
 }
 
diff --git a/targets/targets.json b/targets/targets.json
index 10fbf87c80e..b1caaa827de 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -8544,7 +8544,7 @@
     },
     "MCU_PSOC6_M4": {
         "inherits": ["MCU_PSOC6"],
-        "components_add": ["FLASHIAP"],
+        "components_add": ["FLASHIAP", "BSP_DESIGN_MODUS"],
         "macros_add": ["MCU_PSOC6_M4"],
         "public": false
     },