MCUXpresso Kinetis SPI drive: Add a delay between CS assertion and first sclk edge #11309
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…rst sclk edge 1. FPGA test shield requires at least half sclk period delay between CS assertion and first sclk edge 2. Update Kinetis SPI drivers to match what is already done for K64F Signed-off-by: Mahesh Mahadevan <[email protected]>
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@mmahadevan108, thank you for your changes. |
0xc0170
approved these changes
Aug 26, 2019
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CI started |
Test run: FAILEDSummary: 2 of 11 test jobs failed Failed test jobs:
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CI started |
Test run: SUCCESSSummary: 11 of 11 test jobs passed |
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