diff --git a/hal/targets.json b/hal/targets.json
index 5f0b2217473..5b4796eea41 100644
--- a/hal/targets.json
+++ b/hal/targets.json
@@ -1536,6 +1536,7 @@
     "TY51822R3": {
         "inherits": ["MCU_NRF51_32K_UNIFIED"],
         "macros_add": ["TARGET_NRF_32MHZ_XTAL"],
+        "progen": {"target": "ty51822r3"},
         "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
         "detect_code": ["1019"],
         "release_versions": ["2", "5"]
diff --git a/tools/export/gcc_arm_ty51822r3.tmpl b/tools/export/gcc_arm_ty51822r3.tmpl
new file mode 100644
index 00000000000..fc63674cddf
--- /dev/null
+++ b/tools/export/gcc_arm_ty51822r3.tmpl
@@ -0,0 +1,18 @@
+{% extends "gcc_arm_common.tmpl" %}
+
+{% block target_all %}
+all: $(PROJECT).bin $(PROJECT)-combined.hex size
+{% endblock %}
+
+{% block additional_variables %}
+SOFTDEVICE = {% for f in hex_files %}{{f}} {% endfor %}
+{% endblock %}
+
+{% block additional_executables %}
+SREC_CAT = srec_cat
+{% endblock %}
+
+{% block additional_targets %}
+$(PROJECT)-combined.hex: $(PROJECT).hex
+	$(SREC_CAT) $(SOFTDEVICE) -intel $(PROJECT).hex -intel -o $(PROJECT)-combined.hex -intel --line-length=44
+{% endblock %}
diff --git a/tools/export/gccarm.py b/tools/export/gccarm.py
index 1e44bbd17ef..d1e955a8b65 100644
--- a/tools/export/gccarm.py
+++ b/tools/export/gccarm.py
@@ -58,6 +58,7 @@ class GccArm(Exporter):
         'ARCH_PRO',
         'NRF51822',
         'HRM1017',
+        'TY51822R3',
         'RBLAB_NRF51822',
         'RBLAB_BLENANO',
         'LPC2368',